diff --git a/data/registers/timer_l0.json b/data/registers/timer_l0.json index af9bdae..c1ad67d 100644 --- a/data/registers/timer_l0.json +++ b/data/registers/timer_l0.json @@ -304,12 +304,6 @@ "description": "DMA address for full transfer", "byte_offset": 76, "fieldset": "DMAR_GP16" - }, - { - "name": "ECR", - "description": "encoder control register", - "byte_offset": 88, - "fieldset": "ECR_GP16" } ] }, @@ -917,56 +911,6 @@ } ] }, - "fieldset/ECR_GP16": { - "description": "encoder control register", - "fields": [ - { - "name": "IE", - "description": "Index enable", - "bit_offset": 0, - "bit_size": 1 - }, - { - "name": "IDIR", - "description": "Index direction", - "bit_offset": 1, - "bit_size": 2, - "enum": "IDIR" - }, - { - "name": "IBLK", - "description": "Index blanking", - "bit_offset": 3, - "bit_size": 2, - "enum": "IBLK" - }, - { - "name": "FIDX", - "description": "First index", - "bit_offset": 5, - "bit_size": 1, - "enum": "FIDX" - }, - { - "name": "IPOS", - "description": "Index positioning", - "bit_offset": 6, - "bit_size": 2 - }, - { - "name": "PW", - "description": "Pulse width", - "bit_offset": 16, - "bit_size": 8 - }, - { - "name": "PWPRSC", - "description": "Pulse width prescaler", - "bit_offset": 24, - "bit_size": 2 - } - ] - }, "fieldset/EGR_1CH": { "extends": "EGR_CORE", "description": "event generation register", @@ -1421,21 +1365,6 @@ } ] }, - "enum/FIDX": { - "bit_size": 1, - "variants": [ - { - "name": "AlwaysActive", - "description": "Index is always active", - "value": 0 - }, - { - "name": "FirstOnly", - "description": "the first Index only resets the counter", - "value": 1 - } - ] - }, "enum/FilterValue": { "bit_size": 4, "variants": [ @@ -1521,46 +1450,6 @@ } ] }, - "enum/IBLK": { - "bit_size": 2, - "variants": [ - { - "name": "AlwaysActive", - "description": "Index always active", - "value": 0 - }, - { - "name": "CC3P", - "description": "Index disabled when tim_ti3 input is active, as per CC3P bitfield", - "value": 1 - }, - { - "name": "CC4P", - "description": "Index disabled when tim_ti4 input is active, as per CC4P bitfield", - "value": 2 - } - ] - }, - "enum/IDIR": { - "bit_size": 2, - "variants": [ - { - "name": "Both", - "description": "Index resets the counter whatever the direction", - "value": 0 - }, - { - "name": "Up", - "description": "Index resets the counter when up-counting only", - "value": 1 - }, - { - "name": "Down", - "description": "Index resets the counter when down-counting only", - "value": 2 - } - ] - }, "enum/MMS": { "bit_size": 3, "variants": [ diff --git a/data/registers/timer_v1.json b/data/registers/timer_v1.json index df002e6..f41eeff 100644 --- a/data/registers/timer_v1.json +++ b/data/registers/timer_v1.json @@ -614,12 +614,6 @@ "byte_offset": 76, "fieldset": "DMAR_GP16" }, - { - "name": "ECR", - "description": "encoder control register", - "byte_offset": 88, - "fieldset": "ECR_GP16" - }, { "name": "AF1", "description": "alternate function register 1", @@ -1875,56 +1869,6 @@ } ] }, - "fieldset/ECR_GP16": { - "description": "encoder control register", - "fields": [ - { - "name": "IE", - "description": "Index enable", - "bit_offset": 0, - "bit_size": 1 - }, - { - "name": "IDIR", - "description": "Index direction", - "bit_offset": 1, - "bit_size": 2, - "enum": "IDIR" - }, - { - "name": "IBLK", - "description": "Index blanking", - "bit_offset": 3, - "bit_size": 2, - "enum": "IBLK" - }, - { - "name": "FIDX", - "description": "First index", - "bit_offset": 5, - "bit_size": 1, - "enum": "FIDX" - }, - { - "name": "IPOS", - "description": "Index positioning", - "bit_offset": 6, - "bit_size": 2 - }, - { - "name": "PW", - "description": "Pulse width", - "bit_offset": 16, - "bit_size": 8 - }, - { - "name": "PWPRSC", - "description": "Pulse width prescaler", - "bit_offset": 24, - "bit_size": 2 - } - ] - }, "fieldset/EGR_1CH": { "extends": "EGR_CORE", "description": "event generation register", @@ -2679,21 +2623,6 @@ } ] }, - "enum/FIDX": { - "bit_size": 1, - "variants": [ - { - "name": "AlwaysActive", - "description": "Index is always active", - "value": 0 - }, - { - "name": "FirstOnly", - "description": "the first Index only resets the counter", - "value": 1 - } - ] - }, "enum/FilterValue": { "bit_size": 4, "variants": [ @@ -2794,46 +2723,6 @@ } ] }, - "enum/IBLK": { - "bit_size": 2, - "variants": [ - { - "name": "AlwaysActive", - "description": "Index always active", - "value": 0 - }, - { - "name": "CC3P", - "description": "Index disabled when tim_ti3 input is active, as per CC3P bitfield", - "value": 1 - }, - { - "name": "CC4P", - "description": "Index disabled when tim_ti4 input is active, as per CC4P bitfield", - "value": 2 - } - ] - }, - "enum/IDIR": { - "bit_size": 2, - "variants": [ - { - "name": "Both", - "description": "Index resets the counter whatever the direction", - "value": 0 - }, - { - "name": "Up", - "description": "Index resets the counter when up-counting only", - "value": 1 - }, - { - "name": "Down", - "description": "Index resets the counter when down-counting only", - "value": 2 - } - ] - }, "enum/LOCK": { "bit_size": 2, "variants": [