diff --git a/data/chips/STM32H503CB.json b/data/chips/STM32H503CB.json index b00bf98..170cda8 100644 --- a/data/chips/STM32H503CB.json +++ b/data/chips/STM32H503CB.json @@ -1187,6 +1187,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_0crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H503EB.json b/data/chips/STM32H503EB.json index 0604b7a..61b6bca 100644 --- a/data/chips/STM32H503EB.json +++ b/data/chips/STM32H503EB.json @@ -1075,6 +1075,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_0crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H503KB.json b/data/chips/STM32H503KB.json index 5ad20b2..2060702 100644 --- a/data/chips/STM32H503KB.json +++ b/data/chips/STM32H503KB.json @@ -1124,6 +1124,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_0crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H503RB.json b/data/chips/STM32H503RB.json index 1a30fb5..4dcb253 100644 --- a/data/chips/STM32H503RB.json +++ b/data/chips/STM32H503RB.json @@ -1337,6 +1337,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_0crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index 223b0f2..33b75fc 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -2583,6 +2583,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index 1605bbc..0497e5b 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -2594,6 +2594,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index bf3e024..01e3344 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -2612,6 +2612,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index fba53fa..389c3d3 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -2623,6 +2623,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index 77b21ea..a99ec0d 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -1694,6 +1694,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index 392df12..18240f5 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -1705,6 +1705,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index 06978ca..18cf99e 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -2119,6 +2119,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index bc8ccdb..5ec1841 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -2130,6 +2130,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index 255658f..d4c7c1a 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -2393,6 +2393,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index 95786b1..d56ce9e 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -2404,6 +2404,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index 0fa2c31..42c92d9 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -2856,6 +2856,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index 71c503e..83427de 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -2886,6 +2886,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 700769e..ff4d3c1 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -2890,6 +2890,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index 52db8cb..801644c 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -2909,6 +2909,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index 00cd25b..1027995 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -2073,6 +2073,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index b974f21..7126e5f 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -1912,6 +1912,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index 05780f0..d4e180c 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -1923,6 +1923,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index dcf98a3..c377696 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -2342,6 +2342,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index 99e76f9..1f11029 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -2367,6 +2367,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index 995b203..d14e667 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -2641,6 +2641,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index e8acda2..ef4c63c 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -2681,6 +2681,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 35cd9b8..cb71442 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -2940,6 +2940,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index dae2cff..a95a678 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -2963,6 +2963,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index 2a257f1..b46649f 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -2127,6 +2127,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index 3d7d5f7..7462570 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -1977,6 +1977,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index 88a0b96..9701419 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -2421,6 +2421,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index 4bc2888..974d973 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -2735,6 +2735,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L552CC.json b/data/chips/STM32L552CC.json index d72b327..0d84653 100644 --- a/data/chips/STM32L552CC.json +++ b/data/chips/STM32L552CC.json @@ -1419,6 +1419,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L552CE.json b/data/chips/STM32L552CE.json index 7ac364c..73b4975 100644 --- a/data/chips/STM32L552CE.json +++ b/data/chips/STM32L552CE.json @@ -1427,6 +1427,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L552ME.json b/data/chips/STM32L552ME.json index 88c1dee..cb2daed 100644 --- a/data/chips/STM32L552ME.json +++ b/data/chips/STM32L552ME.json @@ -1488,6 +1488,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L552QC.json b/data/chips/STM32L552QC.json index a0a9027..4f10661 100644 --- a/data/chips/STM32L552QC.json +++ b/data/chips/STM32L552QC.json @@ -1958,6 +1958,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L552QE.json b/data/chips/STM32L552QE.json index e6db8d8..576be69 100644 --- a/data/chips/STM32L552QE.json +++ b/data/chips/STM32L552QE.json @@ -1966,6 +1966,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L552RC.json b/data/chips/STM32L552RC.json index 3616ca0..bb7157e 100644 --- a/data/chips/STM32L552RC.json +++ b/data/chips/STM32L552RC.json @@ -1481,6 +1481,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L552RE.json b/data/chips/STM32L552RE.json index 76ae26b..5b5f0bb 100644 --- a/data/chips/STM32L552RE.json +++ b/data/chips/STM32L552RE.json @@ -1489,6 +1489,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L552VC.json b/data/chips/STM32L552VC.json index f06651e..29cc99f 100644 --- a/data/chips/STM32L552VC.json +++ b/data/chips/STM32L552VC.json @@ -1783,6 +1783,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L552VE.json b/data/chips/STM32L552VE.json index b8980d1..1b2aad6 100644 --- a/data/chips/STM32L552VE.json +++ b/data/chips/STM32L552VE.json @@ -1787,6 +1787,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L552ZC.json b/data/chips/STM32L552ZC.json index c29bac0..20716e7 100644 --- a/data/chips/STM32L552ZC.json +++ b/data/chips/STM32L552ZC.json @@ -1958,6 +1958,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L552ZE.json b/data/chips/STM32L552ZE.json index e50b790..ca18550 100644 --- a/data/chips/STM32L552ZE.json +++ b/data/chips/STM32L552ZE.json @@ -1962,6 +1962,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index aff4647..37e2670 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -1466,6 +1466,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index 3c21f3c..67eccd6 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -1527,6 +1527,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index c36a96b..5a7615f 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -2005,6 +2005,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index e825ed9..1304422 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -1528,6 +1528,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index 56cdd63..adfb6a9 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -1826,6 +1826,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index 0074271..8682ed7 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -2001,6 +2001,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index d8d6c9c..c4ced88 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -1263,7 +1263,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index 86ae220..078d32d 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -1263,7 +1263,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index cb11ed4..d556dbb 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -1263,7 +1263,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index 4f3f8db..9c4e96b 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -1279,7 +1279,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index 0657dac..7a82b9d 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -1236,7 +1236,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index d8965ff..3b2e7ad 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -1236,7 +1236,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index f0095a6..66f8c69 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -1339,7 +1339,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index b68dfc2..db1524e 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -1339,7 +1339,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index da76e50..f51b8a4 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -1339,7 +1339,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index a7a1771..7741808 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -1572,7 +1572,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index acf4288..4f45a30 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -1572,7 +1572,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index 94a7de4..b9a386e 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -1302,7 +1302,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index 9241f2e..45e4ab6 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -1318,7 +1318,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index a952533..6a57f0a 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -1275,7 +1275,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index d7c8363..9e2887a 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -1378,7 +1378,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index 08d75e7..7b720e5 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -1611,7 +1611,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575AG.json b/data/chips/STM32U575AG.json index c29a883..4ea7693 100644 --- a/data/chips/STM32U575AG.json +++ b/data/chips/STM32U575AG.json @@ -2661,7 +2661,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575AI.json b/data/chips/STM32U575AI.json index dd4ae73..3b182a2 100644 --- a/data/chips/STM32U575AI.json +++ b/data/chips/STM32U575AI.json @@ -2661,7 +2661,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575CG.json b/data/chips/STM32U575CG.json index 2050d0f..e72597b 100644 --- a/data/chips/STM32U575CG.json +++ b/data/chips/STM32U575CG.json @@ -1732,7 +1732,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575CI.json b/data/chips/STM32U575CI.json index d9520e6..4aa55b6 100644 --- a/data/chips/STM32U575CI.json +++ b/data/chips/STM32U575CI.json @@ -1732,7 +1732,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575OG.json b/data/chips/STM32U575OG.json index 438bd5f..fc58a26 100644 --- a/data/chips/STM32U575OG.json +++ b/data/chips/STM32U575OG.json @@ -2117,7 +2117,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575OI.json b/data/chips/STM32U575OI.json index 671a5a1..4d490af 100644 --- a/data/chips/STM32U575OI.json +++ b/data/chips/STM32U575OI.json @@ -2117,7 +2117,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575QG.json b/data/chips/STM32U575QG.json index e393fe3..f5aeaaa 100644 --- a/data/chips/STM32U575QG.json +++ b/data/chips/STM32U575QG.json @@ -2511,7 +2511,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575QI.json b/data/chips/STM32U575QI.json index 2e95c36..49632ac 100644 --- a/data/chips/STM32U575QI.json +++ b/data/chips/STM32U575QI.json @@ -2511,7 +2511,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575RG.json b/data/chips/STM32U575RG.json index 5164a27..8c9d759 100644 --- a/data/chips/STM32U575RG.json +++ b/data/chips/STM32U575RG.json @@ -1931,7 +1931,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575RI.json b/data/chips/STM32U575RI.json index 5bbb6d0..a0a7331 100644 --- a/data/chips/STM32U575RI.json +++ b/data/chips/STM32U575RI.json @@ -1931,7 +1931,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575VG.json b/data/chips/STM32U575VG.json index a3a3863..f46fdd1 100644 --- a/data/chips/STM32U575VG.json +++ b/data/chips/STM32U575VG.json @@ -2310,7 +2310,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575VI.json b/data/chips/STM32U575VI.json index ed7de05..1c3131f 100644 --- a/data/chips/STM32U575VI.json +++ b/data/chips/STM32U575VI.json @@ -2310,7 +2310,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575ZG.json b/data/chips/STM32U575ZG.json index f47c336..893924a 100644 --- a/data/chips/STM32U575ZG.json +++ b/data/chips/STM32U575ZG.json @@ -2531,7 +2531,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U575ZI.json b/data/chips/STM32U575ZI.json index 9030e3d..9bdfba3 100644 --- a/data/chips/STM32U575ZI.json +++ b/data/chips/STM32U575ZI.json @@ -2531,7 +2531,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index 64d5f58..37e6128 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -2706,7 +2706,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index 6ba9af0..f79ed4a 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -1777,7 +1777,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index a44a637..8c7cda2 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -2162,7 +2162,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index ba15b7f..65f6c26 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -2556,7 +2556,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index 2cf0640..8da6b5c 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -1976,7 +1976,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index 3fbed38..264ac2b 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -2355,7 +2355,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index 33c1b58..426e72e 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -2576,7 +2576,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index 2f53ffd..25b7b6b 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -2559,7 +2559,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index 56a3207..5bb6cbd 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -2559,7 +2559,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index 06837cb..42f061d 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -2394,7 +2394,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index b5b7842..22ba592 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -2394,7 +2394,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index 5b34aa1..df859a1 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -1677,7 +1677,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index 8968d87..189571a 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -1677,7 +1677,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index 16cf3a4..f6e8a72 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -2173,7 +2173,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index 90a7bbe..437ed25 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -2173,7 +2173,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index eaa8dd4..6b2d5be 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -2418,7 +2418,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index 7f76302..8ac2f41 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -2418,7 +2418,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index dad4e19..543c5d9 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -2764,7 +2764,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index ac4f255..188c1ae 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -2789,7 +2789,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index 8c5eef0..2feb9e1 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -2789,7 +2789,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index 984f281..df4a8ae 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -2184,7 +2184,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index 90bc57a..d1bcde4 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -2245,7 +2245,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index 5830f76..5fef0e1 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -2486,7 +2486,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index 499497c..1a07a6a 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -2486,7 +2486,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index 50b9697..13673cc 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -2598,7 +2598,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index 973c6d4..2e96b15 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -2433,7 +2433,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index f8b27e6..9724f21 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -1716,7 +1716,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index c6420b1..f68469e 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -2212,7 +2212,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 2b6ea56..1748af7 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -2457,7 +2457,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 3352a27..c1857e2 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -2803,7 +2803,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index 708c0aa..4c8b956 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -2828,7 +2828,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 272db78..a87ddff 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -2223,7 +2223,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index e9481a9..8f6ac4d 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -2525,7 +2525,7 @@ "address": 1073939456, "registers": { "kind": "icache", - "version": "v1", + "version": "v1_3crr", "block": "ICACHE" }, "interrupts": [ diff --git a/data/chips/STM32WBA52CE.json b/data/chips/STM32WBA52CE.json index e58e919..caf7e4a 100644 --- a/data/chips/STM32WBA52CE.json +++ b/data/chips/STM32WBA52CE.json @@ -637,6 +637,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32WBA52CG.json b/data/chips/STM32WBA52CG.json index cefbfc8..a836122 100644 --- a/data/chips/STM32WBA52CG.json +++ b/data/chips/STM32WBA52CG.json @@ -637,6 +637,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32WBA52KE.json b/data/chips/STM32WBA52KE.json index dfce3e3..f212b10 100644 --- a/data/chips/STM32WBA52KE.json +++ b/data/chips/STM32WBA52KE.json @@ -613,6 +613,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32WBA52KG.json b/data/chips/STM32WBA52KG.json index 4160904..956bf24 100644 --- a/data/chips/STM32WBA52KG.json +++ b/data/chips/STM32WBA52KG.json @@ -613,6 +613,11 @@ { "name": "ICACHE", "address": 1073939456, + "registers": { + "kind": "icache", + "version": "v1_4crr", + "block": "ICACHE" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/registers/icache_v1_0crr.json b/data/registers/icache_v1_0crr.json new file mode 100644 index 0000000..275290b --- /dev/null +++ b/data/registers/icache_v1_0crr.json @@ -0,0 +1,177 @@ +{ + "block/ICACHE": { + "description": "Instruction Cache Control Registers.", + "items": [ + { + "name": "CR", + "description": "ICACHE control register.", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "SR", + "description": "ICACHE status register.", + "byte_offset": 4, + "access": "Read", + "fieldset": "SR" + }, + { + "name": "IER", + "description": "ICACHE interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "FCR", + "description": "ICACHE flag clear register.", + "byte_offset": 12, + "access": "Write", + "fieldset": "FCR" + }, + { + "name": "HMONR", + "description": "ICACHE hit monitor register.", + "byte_offset": 16, + "access": "Read" + }, + { + "name": "MMONR", + "description": "ICACHE miss monitor register.", + "byte_offset": 20, + "access": "Read", + "fieldset": "MMONR" + } + ] + }, + "fieldset/CR": { + "description": "ICACHE control register.", + "fields": [ + { + "name": "EN", + "description": "EN.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CACHEINV", + "description": "Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "WAYSEL", + "description": "This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0).", + "bit_offset": 2, + "bit_size": 1, + "enum": "WAYSEL" + }, + { + "name": "HITMEN", + "description": "Hit monitor enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "MISSMEN", + "description": "Miss monitor enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "HITMRST", + "description": "Hit monitor reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "MISSMRST", + "description": "Miss monitor reset.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/FCR": { + "description": "ICACHE flag clear register.", + "fields": [ + { + "name": "CBSYENDF", + "description": "Clear busy end flag.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CERRF", + "description": "Clear ERRF flag in SR.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "ICACHE interrupt enable register.", + "fields": [ + { + "name": "BSYENDIE", + "description": "Interrupt enable on busy end.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ERRIE", + "description": "Error interrupt on cache error.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/MMONR": { + "description": "ICACHE miss monitor register.", + "fields": [ + { + "name": "MISSMON", + "description": "Miss monitor register.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/SR": { + "description": "ICACHE status register.", + "fields": [ + { + "name": "BUSYF", + "description": "cache busy executing a full invalidate CACHEINV operation.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BSYENDF", + "description": "full invalidate CACHEINV operation finished.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ERRF", + "description": "an error occurred during the operation.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "enum/WAYSEL": { + "bit_size": 1, + "variants": [ + { + "name": "DirectMapped", + "description": "direct mapped cache (1-way cache)", + "value": 0 + }, + { + "name": "NWaySetAssociative", + "description": "n-way set associative cache (reset value)", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/icache_v1.json b/data/registers/icache_v1_3crr.json similarity index 80% rename from data/registers/icache_v1.json rename to data/registers/icache_v1_3crr.json index 1914c8d..ea430fe 100644 --- a/data/registers/icache_v1.json +++ b/data/registers/icache_v1_3crr.json @@ -1,15 +1,4 @@ { - "block/CRR": { - "description": "ICACHE region configuration register.", - "items": [ - { - "name": "CRRX", - "description": "ICACHE control register.", - "byte_offset": 0, - "fieldset": "CRRX" - } - ] - }, "block/ICACHE": { "description": "Instruction Cache Control Registers.", "items": [ @@ -43,8 +32,7 @@ "name": "HMONR", "description": "ICACHE hit monitor register.", "byte_offset": 16, - "access": "Read", - "fieldset": "HMONR" + "access": "Read" }, { "name": "MMONR", @@ -61,7 +49,7 @@ "stride": 4 }, "byte_offset": 32, - "block": "CRR" + "fieldset": "CRR" } ] }, @@ -78,8 +66,7 @@ "name": "CACHEINV", "description": "Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect.", "bit_offset": 1, - "bit_size": 1, - "enum": "CACHEINV" + "bit_size": 1 }, { "name": "WAYSEL", @@ -104,19 +91,17 @@ "name": "HITMRST", "description": "Hit monitor reset.", "bit_offset": 18, - "bit_size": 1, - "enum": "HITMRST" + "bit_size": 1 }, { "name": "MISSMRST", "description": "Miss monitor reset.", "bit_offset": 19, - "bit_size": 1, - "enum": "MISSMRST" + "bit_size": 1 } ] }, - "fieldset/CRRX": { + "fieldset/CRR": { "description": "ICACHE region configuration register.", "fields": [ { @@ -177,17 +162,6 @@ } ] }, - "fieldset/HMONR": { - "description": "ICACHE hit monitor register.", - "fields": [ - { - "name": "HITMON", - "description": "Hit monitor register.", - "bit_offset": 0, - "bit_size": 32 - } - ] - }, "fieldset/IER": { "description": "ICACHE interrupt enable register.", "fields": [ @@ -239,16 +213,6 @@ } ] }, - "enum/CACHEINV": { - "bit_size": 1, - "variants": [ - { - "name": "Invalidate", - "description": "Invalidate entire cache", - "value": 1 - } - ] - }, "enum/HBURST": { "bit_size": 1, "variants": [ @@ -262,26 +226,6 @@ } ] }, - "enum/HITMRST": { - "bit_size": 1, - "variants": [ - { - "name": "Reset", - "description": "Reset cache hit monitor", - "value": 1 - } - ] - }, - "enum/MISSMRST": { - "bit_size": 1, - "variants": [ - { - "name": "Reset", - "description": "Reset cache miss monitor", - "value": 1 - } - ] - }, "enum/MSTSEL": { "bit_size": 1, "variants": [ @@ -299,31 +243,31 @@ "bit_size": 3, "variants": [ { - "name": "TwoMegabytes", + "name": "MegaBytes2", "value": 1 }, { - "name": "FourMegabytes", + "name": "MegaBytes4", "value": 2 }, { - "name": "EightMegabytes", + "name": "MegaBytes8", "value": 3 }, { - "name": "SixteenMegabytes", + "name": "MegaBytes16", "value": 4 }, { - "name": "ThirtyTwoMegabytes", + "name": "MegaBytes32", "value": 5 }, { - "name": "SixtyFourMegabytes", + "name": "MegaBytes64", "value": 6 }, { - "name": "OneTwentyEightMegabytes", + "name": "MegaBytes128", "value": 7 } ] diff --git a/data/registers/icache_v1_4crr.json b/data/registers/icache_v1_4crr.json new file mode 100644 index 0000000..b21be6f --- /dev/null +++ b/data/registers/icache_v1_4crr.json @@ -0,0 +1,290 @@ +{ + "block/ICACHE": { + "description": "Instruction Cache Control Registers.", + "items": [ + { + "name": "CR", + "description": "ICACHE control register.", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "SR", + "description": "ICACHE status register.", + "byte_offset": 4, + "access": "Read", + "fieldset": "SR" + }, + { + "name": "IER", + "description": "ICACHE interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "FCR", + "description": "ICACHE flag clear register.", + "byte_offset": 12, + "access": "Write", + "fieldset": "FCR" + }, + { + "name": "HMONR", + "description": "ICACHE hit monitor register.", + "byte_offset": 16, + "access": "Read" + }, + { + "name": "MMONR", + "description": "ICACHE miss monitor register.", + "byte_offset": 20, + "access": "Read", + "fieldset": "MMONR" + }, + { + "name": "CRR", + "description": "Cluster CRR%s, container region configuration registers.", + "array": { + "len": 4, + "stride": 4 + }, + "byte_offset": 32, + "fieldset": "CRR" + } + ] + }, + "fieldset/CR": { + "description": "ICACHE control register.", + "fields": [ + { + "name": "EN", + "description": "EN.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CACHEINV", + "description": "Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "WAYSEL", + "description": "This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0).", + "bit_offset": 2, + "bit_size": 1, + "enum": "WAYSEL" + }, + { + "name": "HITMEN", + "description": "Hit monitor enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "MISSMEN", + "description": "Miss monitor enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "HITMRST", + "description": "Hit monitor reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "MISSMRST", + "description": "Miss monitor reset.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/CRR": { + "description": "ICACHE region configuration register.", + "fields": [ + { + "name": "BASEADDR", + "description": "base address for region.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "RSIZE", + "description": "size for region.", + "bit_offset": 9, + "bit_size": 3, + "enum": "RSIZE" + }, + { + "name": "REN", + "description": "enable for region.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "REMAPADDR", + "description": "remapped address for region.", + "bit_offset": 16, + "bit_size": 11 + }, + { + "name": "MSTSEL", + "description": "AHB cache master selection for region.", + "bit_offset": 28, + "bit_size": 1, + "enum": "MSTSEL" + }, + { + "name": "HBURST", + "description": "output burst type for region.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HBURST" + } + ] + }, + "fieldset/FCR": { + "description": "ICACHE flag clear register.", + "fields": [ + { + "name": "CBSYENDF", + "description": "Clear busy end flag.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CERRF", + "description": "Clear ERRF flag in SR.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "ICACHE interrupt enable register.", + "fields": [ + { + "name": "BSYENDIE", + "description": "Interrupt enable on busy end.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ERRIE", + "description": "Error interrupt on cache error.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/MMONR": { + "description": "ICACHE miss monitor register.", + "fields": [ + { + "name": "MISSMON", + "description": "Miss monitor register.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/SR": { + "description": "ICACHE status register.", + "fields": [ + { + "name": "BUSYF", + "description": "cache busy executing a full invalidate CACHEINV operation.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BSYENDF", + "description": "full invalidate CACHEINV operation finished.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ERRF", + "description": "an error occurred during the operation.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "enum/HBURST": { + "bit_size": 1, + "variants": [ + { + "name": "Wrap", + "value": 0 + }, + { + "name": "Increment", + "value": 1 + } + ] + }, + "enum/MSTSEL": { + "bit_size": 1, + "variants": [ + { + "name": "Master1Selected", + "value": 0 + }, + { + "name": "Master2Selected", + "value": 1 + } + ] + }, + "enum/RSIZE": { + "bit_size": 3, + "variants": [ + { + "name": "MegaBytes2", + "value": 1 + }, + { + "name": "MegaBytes4", + "value": 2 + }, + { + "name": "MegaBytes8", + "value": 3 + }, + { + "name": "MegaBytes16", + "value": 4 + }, + { + "name": "MegaBytes32", + "value": 5 + }, + { + "name": "MegaBytes64", + "value": 6 + }, + { + "name": "MegaBytes128", + "value": 7 + } + ] + }, + "enum/WAYSEL": { + "bit_size": 1, + "variants": [ + { + "name": "DirectMapped", + "description": "direct mapped cache (1-way cache)", + "value": 0 + }, + { + "name": "NWaySetAssociative", + "description": "n-way set associative cache (reset value)", + "value": 1 + } + ] + } +} \ No newline at end of file