block/LEDC: description: LED Control PWM (Pulse Width Modulation). items: - name: HSCH0_CONF0 byte_offset: 0 fieldset: HSCH_CONF0 - name: HSCH0_HPOINT byte_offset: 4 fieldset: HSCH_HPOINT - name: HSCH0_DUTY byte_offset: 8 fieldset: HSCH_DUTY - name: HSCH0_CONF1 byte_offset: 12 fieldset: HSCH_CONF1 - name: HSCH0_DUTY_R byte_offset: 16 fieldset: HSCH_DUTY_R - name: HSCH1_CONF0 byte_offset: 20 fieldset: HSCH_CONF0 - name: HSCH1_HPOINT byte_offset: 24 fieldset: HSCH_HPOINT - name: HSCH1_DUTY byte_offset: 28 fieldset: HSCH_DUTY - name: HSCH1_CONF1 byte_offset: 32 fieldset: HSCH_CONF1 - name: HSCH1_DUTY_R byte_offset: 36 fieldset: HSCH_DUTY_R - name: HSCH2_CONF0 byte_offset: 40 fieldset: HSCH_CONF0 - name: HSCH2_HPOINT byte_offset: 44 fieldset: HSCH_HPOINT - name: HSCH2_DUTY byte_offset: 48 fieldset: HSCH_DUTY - name: HSCH2_CONF1 byte_offset: 52 fieldset: HSCH_CONF1 - name: HSCH2_DUTY_R byte_offset: 56 fieldset: HSCH_DUTY_R - name: HSCH3_CONF0 byte_offset: 60 fieldset: HSCH_CONF0 - name: HSCH3_HPOINT byte_offset: 64 fieldset: HSCH_HPOINT - name: HSCH3_DUTY byte_offset: 68 fieldset: HSCH_DUTY - name: HSCH3_CONF1 byte_offset: 72 fieldset: HSCH_CONF1 - name: HSCH3_DUTY_R byte_offset: 76 fieldset: HSCH_DUTY_R - name: HSCH4_CONF0 byte_offset: 80 fieldset: HSCH_CONF0 - name: HSCH4_HPOINT byte_offset: 84 fieldset: HSCH_HPOINT - name: HSCH4_DUTY byte_offset: 88 fieldset: HSCH_DUTY - name: HSCH4_CONF1 byte_offset: 92 fieldset: HSCH_CONF1 - name: HSCH4_DUTY_R byte_offset: 96 fieldset: HSCH_DUTY_R - name: HSCH5_CONF0 byte_offset: 100 fieldset: HSCH_CONF0 - name: HSCH5_HPOINT byte_offset: 104 fieldset: HSCH_HPOINT - name: HSCH5_DUTY byte_offset: 108 fieldset: HSCH_DUTY - name: HSCH5_CONF1 byte_offset: 112 fieldset: HSCH_CONF1 - name: HSCH5_DUTY_R byte_offset: 116 fieldset: HSCH_DUTY_R - name: HSCH6_CONF0 byte_offset: 120 fieldset: HSCH_CONF0 - name: HSCH6_HPOINT byte_offset: 124 fieldset: HSCH_HPOINT - name: HSCH6_DUTY byte_offset: 128 fieldset: HSCH_DUTY - name: HSCH6_CONF1 byte_offset: 132 fieldset: HSCH_CONF1 - name: HSCH6_DUTY_R byte_offset: 136 fieldset: HSCH_DUTY_R - name: HSCH7_CONF0 byte_offset: 140 fieldset: HSCH_CONF0 - name: HSCH7_HPOINT byte_offset: 144 fieldset: HSCH_HPOINT - name: HSCH7_DUTY byte_offset: 148 fieldset: HSCH_DUTY - name: HSCH7_CONF1 byte_offset: 152 fieldset: HSCH_CONF1 - name: HSCH7_DUTY_R byte_offset: 156 fieldset: HSCH_DUTY_R - name: LSCH0_CONF0 byte_offset: 160 fieldset: LSCH_CONF0 - name: LSCH0_HPOINT byte_offset: 164 fieldset: LSCH_HPOINT - name: LSCH0_DUTY byte_offset: 168 fieldset: LSCH_DUTY - name: LSCH0_CONF1 byte_offset: 172 fieldset: LSCH_CONF1 - name: LSCH0_DUTY_R byte_offset: 176 fieldset: LSCH_DUTY_R - name: LSCH1_CONF0 byte_offset: 180 fieldset: LSCH_CONF0 - name: LSCH1_HPOINT byte_offset: 184 fieldset: LSCH_HPOINT - name: LSCH1_DUTY byte_offset: 188 fieldset: LSCH_DUTY - name: LSCH1_CONF1 byte_offset: 192 fieldset: LSCH_CONF1 - name: LSCH1_DUTY_R byte_offset: 196 fieldset: LSCH_DUTY_R - name: LSCH2_CONF0 byte_offset: 200 fieldset: LSCH_CONF0 - name: LSCH2_HPOINT byte_offset: 204 fieldset: LSCH_HPOINT - name: LSCH2_DUTY byte_offset: 208 fieldset: LSCH_DUTY - name: LSCH2_CONF1 byte_offset: 212 fieldset: LSCH_CONF1 - name: LSCH2_DUTY_R byte_offset: 216 fieldset: LSCH_DUTY_R - name: LSCH3_CONF0 byte_offset: 220 fieldset: LSCH_CONF0 - name: LSCH3_HPOINT byte_offset: 224 fieldset: LSCH_HPOINT - name: LSCH3_DUTY byte_offset: 228 fieldset: LSCH_DUTY - name: LSCH3_CONF1 byte_offset: 232 fieldset: LSCH_CONF1 - name: LSCH3_DUTY_R byte_offset: 236 fieldset: LSCH_DUTY_R - name: LSCH4_CONF0 byte_offset: 240 fieldset: LSCH_CONF0 - name: LSCH4_HPOINT byte_offset: 244 fieldset: LSCH_HPOINT - name: LSCH4_DUTY byte_offset: 248 fieldset: LSCH_DUTY - name: LSCH4_CONF1 byte_offset: 252 fieldset: LSCH_CONF1 - name: LSCH4_DUTY_R byte_offset: 256 fieldset: LSCH_DUTY_R - name: LSCH5_CONF0 byte_offset: 260 fieldset: LSCH_CONF0 - name: LSCH5_HPOINT byte_offset: 264 fieldset: LSCH_HPOINT - name: LSCH5_DUTY byte_offset: 268 fieldset: LSCH_DUTY - name: LSCH5_CONF1 byte_offset: 272 fieldset: LSCH_CONF1 - name: LSCH5_DUTY_R byte_offset: 276 fieldset: LSCH_DUTY_R - name: LSCH6_CONF0 byte_offset: 280 fieldset: LSCH_CONF0 - name: LSCH6_HPOINT byte_offset: 284 fieldset: LSCH_HPOINT - name: LSCH6_DUTY byte_offset: 288 fieldset: LSCH_DUTY - name: LSCH6_CONF1 byte_offset: 292 fieldset: LSCH_CONF1 - name: LSCH6_DUTY_R byte_offset: 296 fieldset: LSCH_DUTY_R - name: LSCH7_CONF0 byte_offset: 300 fieldset: LSCH_CONF0 - name: LSCH7_HPOINT byte_offset: 304 fieldset: LSCH_HPOINT - name: LSCH7_DUTY byte_offset: 308 fieldset: LSCH_DUTY - name: LSCH7_CONF1 byte_offset: 312 fieldset: LSCH_CONF1 - name: LSCH7_DUTY_R byte_offset: 316 fieldset: LSCH_DUTY_R - name: HSTIMER0_CONF byte_offset: 320 fieldset: HSTIMER_CONF - name: HSTIMER0_VALUE byte_offset: 324 fieldset: HSTIMER_VALUE - name: HSTIMER1_CONF byte_offset: 328 fieldset: HSTIMER_CONF - name: HSTIMER1_VALUE byte_offset: 332 fieldset: HSTIMER_VALUE - name: HSTIMER2_CONF byte_offset: 336 fieldset: HSTIMER_CONF - name: HSTIMER2_VALUE byte_offset: 340 fieldset: HSTIMER_VALUE - name: HSTIMER3_CONF byte_offset: 344 fieldset: HSTIMER_CONF - name: HSTIMER3_VALUE byte_offset: 348 fieldset: HSTIMER_VALUE - name: LSTIMER0_CONF byte_offset: 352 fieldset: LSTIMER_CONF - name: LSTIMER0_VALUE byte_offset: 356 fieldset: LSTIMER_VALUE - name: LSTIMER1_CONF byte_offset: 360 fieldset: LSTIMER_CONF - name: LSTIMER1_VALUE byte_offset: 364 fieldset: LSTIMER_VALUE - name: LSTIMER2_CONF byte_offset: 368 fieldset: LSTIMER_CONF - name: LSTIMER2_VALUE byte_offset: 372 fieldset: LSTIMER_VALUE - name: LSTIMER3_CONF byte_offset: 376 fieldset: LSTIMER_CONF - name: LSTIMER3_VALUE byte_offset: 380 fieldset: LSTIMER_VALUE - name: INT_RAW byte_offset: 384 fieldset: INT_RAW - name: INT_ST byte_offset: 388 fieldset: INT_ST - name: INT_ENA byte_offset: 392 fieldset: INT_ENA - name: INT_CLR byte_offset: 396 fieldset: INT_CLR - name: CONF byte_offset: 400 fieldset: CONF - name: DATE byte_offset: 508 fieldset: DATE fieldset/CONF: fields: - name: APB_CLK_SEL description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz. bit_offset: 0 bit_size: 1 fieldset/DATE: fields: - name: DATE description: This register represents the version. bit_offset: 0 bit_size: 32 fieldset/HSCH_CONF0: fields: - name: TIMER_SEL description: 'There are four high speed timers the two bits are used to select one of them for high speed channel0. 2''b00: seletc hstimer0. 2''b01: select hstimer1. 2''b10: select hstimer2. 2''b11: select hstimer3.' bit_offset: 0 bit_size: 2 - name: SIG_OUT_EN description: This is the output enable control bit for high speed channel0. bit_offset: 2 bit_size: 1 - name: IDLE_LV description: This bit is used to control the output value when high speed channel0 is off. bit_offset: 3 bit_size: 1 fieldset/HSCH_CONF1: fields: - name: DUTY_SCALE description: This register controls the increase or decrease step scale for high speed channel0. bit_offset: 0 bit_size: 10 - name: DUTY_CYCLE description: This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel0. bit_offset: 10 bit_size: 10 - name: DUTY_NUM description: This register is used to control the num of increased or decreased times for high speed channel0. bit_offset: 20 bit_size: 10 - name: DUTY_INC description: This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel0. bit_offset: 30 bit_size: 1 - name: DUTY_START description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware. bit_offset: 31 bit_size: 1 fieldset/HSCH_DUTY: fields: - name: DUTY description: This register represents the current duty of the output signal for high speed channel0. bit_offset: 0 bit_size: 25 fieldset/HSCH_DUTY_R: fields: - name: DUTY_R description: This register represents the current duty cycle of the output signal for high-speed channel %s. bit_offset: 0 bit_size: 25 fieldset/HSCH_HPOINT: fields: - name: HPOINT description: The output value changes to high when htimerx(x=[0 3]) selected by high speed channel0 has reached reg_hpoint_hsch0[19:0]. bit_offset: 0 bit_size: 20 fieldset/HSTIMER_CONF: fields: - name: DUTY_RES description: This register controls the range of the counter in high speed timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20. bit_offset: 0 bit_size: 5 - name: DIV_NUM description: This register is used to configure parameter for divider in high speed timer0 the least significant eight bits represent the decimal part. bit_offset: 5 bit_size: 18 - name: PAUSE description: This bit is used to pause the counter in high speed timer0. bit_offset: 23 bit_size: 1 - name: RST description: This bit is used to reset high speed timer0 the counter will be 0 after reset. bit_offset: 24 bit_size: 1 - name: TICK_SEL description: This bit is used to choose apb_clk or ref_tick for high speed timer0. 1'b1:apb_clk 0:ref_tick. bit_offset: 25 bit_size: 1 fieldset/HSTIMER_VALUE: fields: - name: CNT description: software can read this register to get the current counter value in high speed timer0. bit_offset: 0 bit_size: 20 fieldset/INT_CLR: fields: - name: HSTIMER0_OVF_INT_CLR description: Set this bit to clear high speed channel0 counter overflow interrupt. bit_offset: 0 bit_size: 1 - name: HSTIMER1_OVF_INT_CLR description: Set this bit to clear high speed channel1 counter overflow interrupt. bit_offset: 1 bit_size: 1 - name: HSTIMER2_OVF_INT_CLR description: Set this bit to clear high speed channel2 counter overflow interrupt. bit_offset: 2 bit_size: 1 - name: HSTIMER3_OVF_INT_CLR description: Set this bit to clear high speed channel3 counter overflow interrupt. bit_offset: 3 bit_size: 1 - name: LSTIMER0_OVF_INT_CLR description: Set this bit to clear low speed channel0 counter overflow interrupt. bit_offset: 4 bit_size: 1 - name: LSTIMER1_OVF_INT_CLR description: Set this bit to clear low speed channel1 counter overflow interrupt. bit_offset: 5 bit_size: 1 - name: LSTIMER2_OVF_INT_CLR description: Set this bit to clear low speed channel2 counter overflow interrupt. bit_offset: 6 bit_size: 1 - name: LSTIMER3_OVF_INT_CLR description: Set this bit to clear low speed channel3 counter overflow interrupt. bit_offset: 7 bit_size: 1 - name: DUTY_CHNG_END_HSCH0_INT_CLR description: Set this bit to clear high speed channel 0 duty change done interrupt. bit_offset: 8 bit_size: 1 - name: DUTY_CHNG_END_HSCH1_INT_CLR description: Set this bit to clear high speed channel 1 duty change done interrupt. bit_offset: 9 bit_size: 1 - name: DUTY_CHNG_END_HSCH2_INT_CLR description: Set this bit to clear high speed channel 2 duty change done interrupt. bit_offset: 10 bit_size: 1 - name: DUTY_CHNG_END_HSCH3_INT_CLR description: Set this bit to clear high speed channel 3 duty change done interrupt. bit_offset: 11 bit_size: 1 - name: DUTY_CHNG_END_HSCH4_INT_CLR description: Set this bit to clear high speed channel 4 duty change done interrupt. bit_offset: 12 bit_size: 1 - name: DUTY_CHNG_END_HSCH5_INT_CLR description: Set this bit to clear high speed channel 5 duty change done interrupt. bit_offset: 13 bit_size: 1 - name: DUTY_CHNG_END_HSCH6_INT_CLR description: Set this bit to clear high speed channel 6 duty change done interrupt. bit_offset: 14 bit_size: 1 - name: DUTY_CHNG_END_HSCH7_INT_CLR description: Set this bit to clear high speed channel 7 duty change done interrupt. bit_offset: 15 bit_size: 1 - name: DUTY_CHNG_END_LSCH0_INT_CLR description: Set this bit to clear low speed channel 0 duty change done interrupt. bit_offset: 16 bit_size: 1 - name: DUTY_CHNG_END_LSCH1_INT_CLR description: Set this bit to clear low speed channel 1 duty change done interrupt. bit_offset: 17 bit_size: 1 - name: DUTY_CHNG_END_LSCH2_INT_CLR description: Set this bit to clear low speed channel 2 duty change done interrupt. bit_offset: 18 bit_size: 1 - name: DUTY_CHNG_END_LSCH3_INT_CLR description: Set this bit to clear low speed channel 3 duty change done interrupt. bit_offset: 19 bit_size: 1 - name: DUTY_CHNG_END_LSCH4_INT_CLR description: Set this bit to clear low speed channel 4 duty change done interrupt. bit_offset: 20 bit_size: 1 - name: DUTY_CHNG_END_LSCH5_INT_CLR description: Set this bit to clear low speed channel 5 duty change done interrupt. bit_offset: 21 bit_size: 1 - name: DUTY_CHNG_END_LSCH6_INT_CLR description: Set this bit to clear low speed channel 6 duty change done interrupt. bit_offset: 22 bit_size: 1 - name: DUTY_CHNG_END_LSCH7_INT_CLR description: Set this bit to clear low speed channel 7 duty change done interrupt. bit_offset: 23 bit_size: 1 fieldset/INT_ENA: fields: - name: HSTIMER0_OVF_INT_ENA description: The interrupt enable bit for high speed channel0 counter overflow interrupt. bit_offset: 0 bit_size: 1 - name: HSTIMER1_OVF_INT_ENA description: The interrupt enable bit for high speed channel1 counter overflow interrupt. bit_offset: 1 bit_size: 1 - name: HSTIMER2_OVF_INT_ENA description: The interrupt enable bit for high speed channel2 counter overflow interrupt. bit_offset: 2 bit_size: 1 - name: HSTIMER3_OVF_INT_ENA description: The interrupt enable bit for high speed channel3 counter overflow interrupt. bit_offset: 3 bit_size: 1 - name: LSTIMER0_OVF_INT_ENA description: The interrupt enable bit for low speed channel0 counter overflow interrupt. bit_offset: 4 bit_size: 1 - name: LSTIMER1_OVF_INT_ENA description: The interrupt enable bit for low speed channel1 counter overflow interrupt. bit_offset: 5 bit_size: 1 - name: LSTIMER2_OVF_INT_ENA description: The interrupt enable bit for low speed channel2 counter overflow interrupt. bit_offset: 6 bit_size: 1 - name: LSTIMER3_OVF_INT_ENA description: The interrupt enable bit for low speed channel3 counter overflow interrupt. bit_offset: 7 bit_size: 1 - name: DUTY_CHNG_END_HSCH0_INT_ENA description: The interrupt enable bit for high speed channel 0 duty change done interrupt. bit_offset: 8 bit_size: 1 - name: DUTY_CHNG_END_HSCH1_INT_ENA description: The interrupt enable bit for high speed channel 1 duty change done interrupt. bit_offset: 9 bit_size: 1 - name: DUTY_CHNG_END_HSCH2_INT_ENA description: The interrupt enable bit for high speed channel 2 duty change done interrupt. bit_offset: 10 bit_size: 1 - name: DUTY_CHNG_END_HSCH3_INT_ENA description: The interrupt enable bit for high speed channel 3 duty change done interrupt. bit_offset: 11 bit_size: 1 - name: DUTY_CHNG_END_HSCH4_INT_ENA description: The interrupt enable bit for high speed channel 4 duty change done interrupt. bit_offset: 12 bit_size: 1 - name: DUTY_CHNG_END_HSCH5_INT_ENA description: The interrupt enable bit for high speed channel 5 duty change done interrupt. bit_offset: 13 bit_size: 1 - name: DUTY_CHNG_END_HSCH6_INT_ENA description: The interrupt enable bit for high speed channel 6 duty change done interrupt. bit_offset: 14 bit_size: 1 - name: DUTY_CHNG_END_HSCH7_INT_ENA description: The interrupt enable bit for high speed channel 7 duty change done interrupt. bit_offset: 15 bit_size: 1 - name: DUTY_CHNG_END_LSCH0_INT_ENA description: The interrupt enable bit for low speed channel 0 duty change done interrupt. bit_offset: 16 bit_size: 1 - name: DUTY_CHNG_END_LSCH1_INT_ENA description: The interrupt enable bit for low speed channel 1 duty change done interrupt. bit_offset: 17 bit_size: 1 - name: DUTY_CHNG_END_LSCH2_INT_ENA description: The interrupt enable bit for low speed channel 2 duty change done interrupt. bit_offset: 18 bit_size: 1 - name: DUTY_CHNG_END_LSCH3_INT_ENA description: The interrupt enable bit for low speed channel 3 duty change done interrupt. bit_offset: 19 bit_size: 1 - name: DUTY_CHNG_END_LSCH4_INT_ENA description: The interrupt enable bit for low speed channel 4 duty change done interrupt. bit_offset: 20 bit_size: 1 - name: DUTY_CHNG_END_LSCH5_INT_ENA description: The interrupt enable bit for low speed channel 5 duty change done interrupt. bit_offset: 21 bit_size: 1 - name: DUTY_CHNG_END_LSCH6_INT_ENA description: The interrupt enable bit for low speed channel 6 duty change done interrupt. bit_offset: 22 bit_size: 1 - name: DUTY_CHNG_END_LSCH7_INT_ENA description: The interrupt enable bit for low speed channel 7 duty change done interrupt. bit_offset: 23 bit_size: 1 fieldset/INT_RAW: fields: - name: HSTIMER0_OVF_INT_RAW description: The interrupt raw bit for high speed channel0 counter overflow. bit_offset: 0 bit_size: 1 - name: HSTIMER1_OVF_INT_RAW description: The interrupt raw bit for high speed channel1 counter overflow. bit_offset: 1 bit_size: 1 - name: HSTIMER2_OVF_INT_RAW description: The interrupt raw bit for high speed channel2 counter overflow. bit_offset: 2 bit_size: 1 - name: HSTIMER3_OVF_INT_RAW description: The interrupt raw bit for high speed channel3 counter overflow. bit_offset: 3 bit_size: 1 - name: LSTIMER0_OVF_INT_RAW description: The interrupt raw bit for low speed channel0 counter overflow. bit_offset: 4 bit_size: 1 - name: LSTIMER1_OVF_INT_RAW description: The interrupt raw bit for low speed channel1 counter overflow. bit_offset: 5 bit_size: 1 - name: LSTIMER2_OVF_INT_RAW description: The interrupt raw bit for low speed channel2 counter overflow. bit_offset: 6 bit_size: 1 - name: LSTIMER3_OVF_INT_RAW description: The interrupt raw bit for low speed channel3 counter overflow. bit_offset: 7 bit_size: 1 - name: DUTY_CHNG_END_HSCH0_INT_RAW description: The interrupt raw bit for high speed channel 0 duty change done. bit_offset: 8 bit_size: 1 - name: DUTY_CHNG_END_HSCH1_INT_RAW description: The interrupt raw bit for high speed channel 1 duty change done. bit_offset: 9 bit_size: 1 - name: DUTY_CHNG_END_HSCH2_INT_RAW description: The interrupt raw bit for high speed channel 2 duty change done. bit_offset: 10 bit_size: 1 - name: DUTY_CHNG_END_HSCH3_INT_RAW description: The interrupt raw bit for high speed channel 3 duty change done. bit_offset: 11 bit_size: 1 - name: DUTY_CHNG_END_HSCH4_INT_RAW description: The interrupt raw bit for high speed channel 4 duty change done. bit_offset: 12 bit_size: 1 - name: DUTY_CHNG_END_HSCH5_INT_RAW description: The interrupt raw bit for high speed channel 5 duty change done. bit_offset: 13 bit_size: 1 - name: DUTY_CHNG_END_HSCH6_INT_RAW description: The interrupt raw bit for high speed channel 6 duty change done. bit_offset: 14 bit_size: 1 - name: DUTY_CHNG_END_HSCH7_INT_RAW description: The interrupt raw bit for high speed channel 7 duty change done. bit_offset: 15 bit_size: 1 - name: DUTY_CHNG_END_LSCH0_INT_RAW description: The interrupt raw bit for low speed channel 0 duty change done. bit_offset: 16 bit_size: 1 - name: DUTY_CHNG_END_LSCH1_INT_RAW description: The interrupt raw bit for low speed channel 1 duty change done. bit_offset: 17 bit_size: 1 - name: DUTY_CHNG_END_LSCH2_INT_RAW description: The interrupt raw bit for low speed channel 2 duty change done. bit_offset: 18 bit_size: 1 - name: DUTY_CHNG_END_LSCH3_INT_RAW description: The interrupt raw bit for low speed channel 3 duty change done. bit_offset: 19 bit_size: 1 - name: DUTY_CHNG_END_LSCH4_INT_RAW description: The interrupt raw bit for low speed channel 4 duty change done. bit_offset: 20 bit_size: 1 - name: DUTY_CHNG_END_LSCH5_INT_RAW description: The interrupt raw bit for low speed channel 5 duty change done. bit_offset: 21 bit_size: 1 - name: DUTY_CHNG_END_LSCH6_INT_RAW description: The interrupt raw bit for low speed channel 6 duty change done. bit_offset: 22 bit_size: 1 - name: DUTY_CHNG_END_LSCH7_INT_RAW description: The interrupt raw bit for low speed channel 7 duty change done. bit_offset: 23 bit_size: 1 fieldset/INT_ST: fields: - name: HSTIMER0_OVF_INT_ST description: The interrupt status bit for high speed channel0 counter overflow event. bit_offset: 0 bit_size: 1 - name: HSTIMER1_OVF_INT_ST description: The interrupt status bit for high speed channel1 counter overflow event. bit_offset: 1 bit_size: 1 - name: HSTIMER2_OVF_INT_ST description: The interrupt status bit for high speed channel2 counter overflow event. bit_offset: 2 bit_size: 1 - name: HSTIMER3_OVF_INT_ST description: The interrupt status bit for high speed channel3 counter overflow event. bit_offset: 3 bit_size: 1 - name: LSTIMER0_OVF_INT_ST description: The interrupt status bit for low speed channel0 counter overflow event. bit_offset: 4 bit_size: 1 - name: LSTIMER1_OVF_INT_ST description: The interrupt status bit for low speed channel1 counter overflow event. bit_offset: 5 bit_size: 1 - name: LSTIMER2_OVF_INT_ST description: The interrupt status bit for low speed channel2 counter overflow event. bit_offset: 6 bit_size: 1 - name: LSTIMER3_OVF_INT_ST description: The interrupt status bit for low speed channel3 counter overflow event. bit_offset: 7 bit_size: 1 - name: DUTY_CHNG_END_HSCH0_INT_ST description: The interrupt status bit for high speed channel 0 duty change done event. bit_offset: 8 bit_size: 1 - name: DUTY_CHNG_END_HSCH1_INT_ST description: The interrupt status bit for high speed channel 1 duty change done event. bit_offset: 9 bit_size: 1 - name: DUTY_CHNG_END_HSCH2_INT_ST description: The interrupt status bit for high speed channel 2 duty change done event. bit_offset: 10 bit_size: 1 - name: DUTY_CHNG_END_HSCH3_INT_ST description: The interrupt status bit for high speed channel 3 duty change done event. bit_offset: 11 bit_size: 1 - name: DUTY_CHNG_END_HSCH4_INT_ST description: The interrupt status bit for high speed channel 4 duty change done event. bit_offset: 12 bit_size: 1 - name: DUTY_CHNG_END_HSCH5_INT_ST description: The interrupt status bit for high speed channel 5 duty change done event. bit_offset: 13 bit_size: 1 - name: DUTY_CHNG_END_HSCH6_INT_ST description: The interrupt status bit for high speed channel 6 duty change done event. bit_offset: 14 bit_size: 1 - name: DUTY_CHNG_END_HSCH7_INT_ST description: The interrupt status bit for high speed channel 7 duty change done event. bit_offset: 15 bit_size: 1 - name: DUTY_CHNG_END_LSCH0_INT_ST description: The interrupt status bit for low speed channel 0 duty change done event. bit_offset: 16 bit_size: 1 - name: DUTY_CHNG_END_LSCH1_INT_ST description: The interrupt status bit for low speed channel 1 duty change done event. bit_offset: 17 bit_size: 1 - name: DUTY_CHNG_END_LSCH2_INT_ST description: The interrupt status bit for low speed channel 2 duty change done event. bit_offset: 18 bit_size: 1 - name: DUTY_CHNG_END_LSCH3_INT_ST description: The interrupt status bit for low speed channel 3 duty change done event. bit_offset: 19 bit_size: 1 - name: DUTY_CHNG_END_LSCH4_INT_ST description: The interrupt status bit for low speed channel 4 duty change done event. bit_offset: 20 bit_size: 1 - name: DUTY_CHNG_END_LSCH5_INT_ST description: The interrupt status bit for low speed channel 5 duty change done event. bit_offset: 21 bit_size: 1 - name: DUTY_CHNG_END_LSCH6_INT_ST description: The interrupt status bit for low speed channel 6 duty change done event. bit_offset: 22 bit_size: 1 - name: DUTY_CHNG_END_LSCH7_INT_ST description: The interrupt status bit for low speed channel 7 duty change done event. bit_offset: 23 bit_size: 1 fieldset/LSCH_CONF0: fields: - name: TIMER_SEL description: 'There are four low speed timers the two bits are used to select one of them for low speed channel0. 2''b00: seletc lstimer0. 2''b01: select lstimer1. 2''b10: select lstimer2. 2''b11: select lstimer3.' bit_offset: 0 bit_size: 2 - name: SIG_OUT_EN description: This is the output enable control bit for low speed channel0. bit_offset: 2 bit_size: 1 - name: IDLE_LV description: This bit is used to control the output value when low speed channel0 is off. bit_offset: 3 bit_size: 1 - name: PARA_UP description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel0. bit_offset: 4 bit_size: 1 fieldset/LSCH_CONF1: fields: - name: DUTY_SCALE description: This register controls the increase or decrease step scale for low speed channel0. bit_offset: 0 bit_size: 10 - name: DUTY_CYCLE description: This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel0. bit_offset: 10 bit_size: 10 - name: DUTY_NUM description: This register is used to control the num of increased or decreased times for low speed channel6. bit_offset: 20 bit_size: 10 - name: DUTY_INC description: This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6. bit_offset: 30 bit_size: 1 - name: DUTY_START description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware. bit_offset: 31 bit_size: 1 fieldset/LSCH_DUTY: fields: - name: DUTY description: This register represents the current duty of the output signal for low speed channel0. bit_offset: 0 bit_size: 25 fieldset/LSCH_DUTY_R: fields: - name: DUTY_R description: This register represents the current duty cycle of the output signal for low-speed channel %s. bit_offset: 0 bit_size: 25 fieldset/LSCH_HPOINT: fields: - name: HPOINT description: The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel0 has reached reg_hpoint_lsch0[19:0]. bit_offset: 0 bit_size: 20 fieldset/LSTIMER_CONF: fields: - name: DUTY_RES description: This register controls the range of the counter in low speed timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20. bit_offset: 0 bit_size: 5 - name: DIV_NUM description: This register is used to configure parameter for divider in low speed timer0 the least significant eight bits represent the decimal part. bit_offset: 5 bit_size: 18 - name: PAUSE description: This bit is used to pause the counter in low speed timer0. bit_offset: 23 bit_size: 1 - name: RST description: This bit is used to reset low speed timer0 the counter will be 0 after reset. bit_offset: 24 bit_size: 1 - name: TICK_SEL description: This bit is used to choose slow_clk or ref_tick for low speed timer0. 1'b1:slow_clk 0:ref_tick. bit_offset: 25 bit_size: 1 - name: PARA_UP description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim. bit_offset: 26 bit_size: 1 fieldset/LSTIMER_VALUE: fields: - name: CNT description: software can read this register to get the current counter value in low speed timer0. bit_offset: 0 bit_size: 20