diff --git a/base/MK22F25612/ADC0.yaml b/head/MK22F25612/ADC0.yaml index d14f3d3..008aa78 100644 --- a/base/MK22F25612/ADC0.yaml +++ b/head/MK22F25612/ADC0.yaml @@ -1,13 +1,14 @@ block/ADC0: description: Analog-to-Digital Converter. items: - - name: SC1 + - name: SC1A description: ADC Status and Control Registers 1. - array: - len: 2 - stride: 4 byte_offset: 0 fieldset: SC1 + - name: SC1B + description: ADC Status and Control Registers 1. + byte_offset: 4 + fieldset: SC1 - name: CFG1 description: ADC Configuration Register 1. byte_offset: 8 @@ -16,21 +17,24 @@ block/ADC0: description: ADC Configuration Register 2. byte_offset: 12 fieldset: CFG2 - - name: R + - name: RA description: ADC Data Result Register. - array: - len: 2 - stride: 4 byte_offset: 16 access: Read fieldset: R - - name: CV + - name: RB + description: ADC Data Result Register. + byte_offset: 20 + access: Read + fieldset: R + - name: CV1 description: Compare Value Registers. - array: - len: 2 - stride: 4 byte_offset: 24 fieldset: CV + - name: CV2 + description: Compare Value Registers. + byte_offset: 28 + fieldset: CV - name: SC2 description: Status and Control Register 2. byte_offset: 32 diff --git a/base/MK22F25612/ADC1.yaml b/head/MK22F25612/ADC1.yaml index 7450243..39961f4 100644 --- a/base/MK22F25612/ADC1.yaml +++ b/head/MK22F25612/ADC1.yaml @@ -1,13 +1,14 @@ block/ADC1: description: Analog-to-Digital Converter. items: - - name: SC1 + - name: SC1A description: ADC Status and Control Registers 1. - array: - len: 2 - stride: 4 byte_offset: 0 fieldset: SC1 + - name: SC1B + description: ADC Status and Control Registers 1. + byte_offset: 4 + fieldset: SC1 - name: CFG1 description: ADC Configuration Register 1. byte_offset: 8 @@ -16,21 +17,24 @@ block/ADC1: description: ADC Configuration Register 2. byte_offset: 12 fieldset: CFG2 - - name: R + - name: RA description: ADC Data Result Register. - array: - len: 2 - stride: 4 byte_offset: 16 access: Read fieldset: R - - name: CV + - name: RB + description: ADC Data Result Register. + byte_offset: 20 + access: Read + fieldset: R + - name: CV1 description: Compare Value Registers. - array: - len: 2 - stride: 4 byte_offset: 24 fieldset: CV + - name: CV2 + description: Compare Value Registers. + byte_offset: 28 + fieldset: CV - name: SC2 description: Status and Control Register 2. byte_offset: 32 diff --git a/base/MK22F25612/DAC0.yaml b/head/MK22F25612/DAC0.yaml index 2e7b8bf..664b5fd 100644 --- a/base/MK22F25612/DAC0.yaml +++ b/head/MK22F25612/DAC0.yaml @@ -1,22 +1,166 @@ block/DAC0: description: 12-Bit Digital-to-Analog Converter. items: - - name: DATL + - name: DAT0L description: DAC Data Low Register. - array: - len: 16 - stride: 2 byte_offset: 0 bit_size: 8 fieldset: DATL - - name: DATH + - name: DAT0H description: DAC Data High Register. - array: - len: 16 - stride: 2 byte_offset: 1 bit_size: 8 fieldset: DATH + - name: DAT1L + description: DAC Data Low Register. + byte_offset: 2 + bit_size: 8 + fieldset: DATL + - name: DAT1H + description: DAC Data High Register. + byte_offset: 3 + bit_size: 8 + fieldset: DATH + - name: DAT2L + description: DAC Data Low Register. + byte_offset: 4 + bit_size: 8 + fieldset: DATL + - name: DAT2H + description: DAC Data High Register. + byte_offset: 5 + bit_size: 8 + fieldset: DATH + - name: DAT3L + description: DAC Data Low Register. + byte_offset: 6 + bit_size: 8 + fieldset: DATL + - name: DAT3H + description: DAC Data High Register. + byte_offset: 7 + bit_size: 8 + fieldset: DATH + - name: DAT4L + description: DAC Data Low Register. + byte_offset: 8 + bit_size: 8 + fieldset: DATL + - name: DAT4H + description: DAC Data High Register. + byte_offset: 9 + bit_size: 8 + fieldset: DATH + - name: DAT5L + description: DAC Data Low Register. + byte_offset: 10 + bit_size: 8 + fieldset: DATL + - name: DAT5H + description: DAC Data High Register. + byte_offset: 11 + bit_size: 8 + fieldset: DATH + - name: DAT6L + description: DAC Data Low Register. + byte_offset: 12 + bit_size: 8 + fieldset: DATL + - name: DAT6H + description: DAC Data High Register. + byte_offset: 13 + bit_size: 8 + fieldset: DATH + - name: DAT7L + description: DAC Data Low Register. + byte_offset: 14 + bit_size: 8 + fieldset: DATL + - name: DAT7H + description: DAC Data High Register. + byte_offset: 15 + bit_size: 8 + fieldset: DATH + - name: DAT8L + description: DAC Data Low Register. + byte_offset: 16 + bit_size: 8 + fieldset: DATL + - name: DAT8H + description: DAC Data High Register. + byte_offset: 17 + bit_size: 8 + fieldset: DATH + - name: DAT9L + description: DAC Data Low Register. + byte_offset: 18 + bit_size: 8 + fieldset: DATL + - name: DAT9H + description: DAC Data High Register. + byte_offset: 19 + bit_size: 8 + fieldset: DATH + - name: DAT10L + description: DAC Data Low Register. + byte_offset: 20 + bit_size: 8 + fieldset: DATL + - name: DAT10H + description: DAC Data High Register. + byte_offset: 21 + bit_size: 8 + fieldset: DATH + - name: DAT11L + description: DAC Data Low Register. + byte_offset: 22 + bit_size: 8 + fieldset: DATL + - name: DAT11H + description: DAC Data High Register. + byte_offset: 23 + bit_size: 8 + fieldset: DATH + - name: DAT12L + description: DAC Data Low Register. + byte_offset: 24 + bit_size: 8 + fieldset: DATL + - name: DAT12H + description: DAC Data High Register. + byte_offset: 25 + bit_size: 8 + fieldset: DATH + - name: DAT13L + description: DAC Data Low Register. + byte_offset: 26 + bit_size: 8 + fieldset: DATL + - name: DAT13H + description: DAC Data High Register. + byte_offset: 27 + bit_size: 8 + fieldset: DATH + - name: DAT14L + description: DAC Data Low Register. + byte_offset: 28 + bit_size: 8 + fieldset: DATL + - name: DAT14H + description: DAC Data High Register. + byte_offset: 29 + bit_size: 8 + fieldset: DATH + - name: DAT15L + description: DAC Data Low Register. + byte_offset: 30 + bit_size: 8 + fieldset: DATL + - name: DAT15H + description: DAC Data High Register. + byte_offset: 31 + bit_size: 8 + fieldset: DATH - name: SR description: DAC Status Register. byte_offset: 32 diff --git a/base/MK22F25612/DMA.yaml b/head/MK22F25612/DMA.yaml index ced2ca2..34ee72f 100644 --- a/base/MK22F25612/DMA.yaml +++ b/head/MK22F25612/DMA.yaml @@ -83,127 +83,1174 @@ block/DMA: description: Enable Asynchronous Request in Stop Register. byte_offset: 68 fieldset: EARS - - name: DCHPRI + - name: DCHPRI3 description: Channel n Priority Register. - array: - len: 16 - stride: 1 byte_offset: 256 bit_size: 8 fieldset: DCHPRI - - name: TCD_SADDR + - name: DCHPRI2 + description: Channel n Priority Register. + byte_offset: 257 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI1 + description: Channel n Priority Register. + byte_offset: 258 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI0 + description: Channel n Priority Register. + byte_offset: 259 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI7 + description: Channel n Priority Register. + byte_offset: 260 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI6 + description: Channel n Priority Register. + byte_offset: 261 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI5 + description: Channel n Priority Register. + byte_offset: 262 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI4 + description: Channel n Priority Register. + byte_offset: 263 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI11 + description: Channel n Priority Register. + byte_offset: 264 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI10 + description: Channel n Priority Register. + byte_offset: 265 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI9 + description: Channel n Priority Register. + byte_offset: 266 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI8 + description: Channel n Priority Register. + byte_offset: 267 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI15 + description: Channel n Priority Register. + byte_offset: 268 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI14 + description: Channel n Priority Register. + byte_offset: 269 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI13 + description: Channel n Priority Register. + byte_offset: 270 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI12 + description: Channel n Priority Register. + byte_offset: 271 + bit_size: 8 + fieldset: DCHPRI + - name: TCD0_SADDR description: TCD Source Address. - array: - len: 16 - stride: 32 byte_offset: 4096 fieldset: TCD_SADDR - - name: TCD_SOFF + - name: TCD0_SOFF description: TCD Signed Source Address Offset. - array: - len: 16 - stride: 32 byte_offset: 4100 bit_size: 16 fieldset: TCD_SOFF - - name: TCD_ATTR + - name: TCD0_ATTR description: TCD Transfer Attributes. - array: - len: 16 - stride: 32 byte_offset: 4102 bit_size: 16 fieldset: TCD_ATTR - - name: TCD_NBYTES_MLNO + - name: TCD0_NBYTES_MLNO description: TCD Minor Byte Count (Minor Loop Disabled). - array: - len: 16 - stride: 32 byte_offset: 4104 fieldset: TCD_NBYTES_MLNO - - name: TCD_NBYTES_MLOFFNO + - name: TCD0_NBYTES_MLOFFNO description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). - array: - len: 16 - stride: 32 byte_offset: 4104 fieldset: TCD_NBYTES_MLOFFNO - - name: TCD_NBYTES_MLOFFYES + - name: TCD0_NBYTES_MLOFFYES description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). - array: - len: 16 - stride: 32 byte_offset: 4104 fieldset: TCD_NBYTES_MLOFFYES - - name: TCD_SLAST + - name: TCD0_SLAST description: TCD Last Source Address Adjustment. - array: - len: 16 - stride: 32 byte_offset: 4108 fieldset: TCD_SLAST - - name: TCD_DADDR + - name: TCD0_DADDR description: TCD Destination Address. - array: - len: 16 - stride: 32 byte_offset: 4112 fieldset: TCD_DADDR - - name: TCD_DOFF + - name: TCD0_DOFF description: TCD Signed Destination Address Offset. - array: - len: 16 - stride: 32 byte_offset: 4116 bit_size: 16 fieldset: TCD_DOFF - - name: TCD_CITER_ELINKNO + - name: TCD0_CITER_ELINKNO description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). - array: - len: 16 - stride: 32 byte_offset: 4118 bit_size: 16 fieldset: TCD_CITER_ELINKNO - - name: TCD_CITER_ELINKYES + - name: TCD0_CITER_ELINKYES description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). - array: - len: 16 - stride: 32 byte_offset: 4118 bit_size: 16 fieldset: TCD_CITER_ELINKYES - - name: TCD_DLASTSGA + - name: TCD0_DLASTSGA description: TCD Last Destination Address Adjustment/Scatter Gather Address. - array: - len: 16 - stride: 32 byte_offset: 4120 fieldset: TCD_DLASTSGA - - name: TCD_CSR + - name: TCD0_CSR description: TCD Control and Status. - array: - len: 16 - stride: 32 byte_offset: 4124 bit_size: 16 fieldset: TCD_CSR - - name: TCD_BITER_ELINKNO + - name: TCD0_BITER_ELINKNO description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). - array: - len: 16 - stride: 32 byte_offset: 4126 bit_size: 16 fieldset: TCD_BITER_ELINKNO - - name: TCD_BITER_ELINKYES + - name: TCD0_BITER_ELINKYES description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). - array: - len: 16 - stride: 32 byte_offset: 4126 bit_size: 16 fieldset: TCD_BITER_ELINKYES + - name: TCD1_SADDR + description: TCD Source Address. + byte_offset: 4128 + fieldset: TCD_SADDR + - name: TCD1_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4132 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD1_ATTR + description: TCD Transfer Attributes. + byte_offset: 4134 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD1_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4136 + fieldset: TCD_NBYTES_MLNO + - name: TCD1_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4136 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD1_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4136 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD1_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4140 + fieldset: TCD_SLAST + - name: TCD1_DADDR + description: TCD Destination Address. + byte_offset: 4144 + fieldset: TCD_DADDR + - name: TCD1_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4148 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD1_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4150 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD1_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4150 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD1_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4152 + fieldset: TCD_DLASTSGA + - name: TCD1_CSR + description: TCD Control and Status. + byte_offset: 4156 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD1_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4158 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD1_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4158 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD2_SADDR + description: TCD Source Address. + byte_offset: 4160 + fieldset: TCD_SADDR + - name: TCD2_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4164 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD2_ATTR + description: TCD Transfer Attributes. + byte_offset: 4166 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD2_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4168 + fieldset: TCD_NBYTES_MLNO + - name: TCD2_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4168 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD2_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4168 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD2_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4172 + fieldset: TCD_SLAST + - name: TCD2_DADDR + description: TCD Destination Address. + byte_offset: 4176 + fieldset: TCD_DADDR + - name: TCD2_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4180 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD2_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4182 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD2_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4182 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD2_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4184 + fieldset: TCD_DLASTSGA + - name: TCD2_CSR + description: TCD Control and Status. + byte_offset: 4188 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD2_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4190 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD2_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4190 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD3_SADDR + description: TCD Source Address. + byte_offset: 4192 + fieldset: TCD_SADDR + - name: TCD3_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4196 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD3_ATTR + description: TCD Transfer Attributes. + byte_offset: 4198 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD3_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4200 + fieldset: TCD_NBYTES_MLNO + - name: TCD3_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4200 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD3_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4200 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD3_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4204 + fieldset: TCD_SLAST + - name: TCD3_DADDR + description: TCD Destination Address. + byte_offset: 4208 + fieldset: TCD_DADDR + - name: TCD3_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4212 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD3_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4214 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD3_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4214 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD3_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4216 + fieldset: TCD_DLASTSGA + - name: TCD3_CSR + description: TCD Control and Status. + byte_offset: 4220 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD3_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4222 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD3_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4222 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD4_SADDR + description: TCD Source Address. + byte_offset: 4224 + fieldset: TCD_SADDR + - name: TCD4_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4228 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD4_ATTR + description: TCD Transfer Attributes. + byte_offset: 4230 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD4_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4232 + fieldset: TCD_NBYTES_MLNO + - name: TCD4_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4232 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD4_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4232 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD4_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4236 + fieldset: TCD_SLAST + - name: TCD4_DADDR + description: TCD Destination Address. + byte_offset: 4240 + fieldset: TCD_DADDR + - name: TCD4_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4244 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD4_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4246 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD4_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4246 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD4_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4248 + fieldset: TCD_DLASTSGA + - name: TCD4_CSR + description: TCD Control and Status. + byte_offset: 4252 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD4_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4254 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD4_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4254 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD5_SADDR + description: TCD Source Address. + byte_offset: 4256 + fieldset: TCD_SADDR + - name: TCD5_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4260 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD5_ATTR + description: TCD Transfer Attributes. + byte_offset: 4262 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD5_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4264 + fieldset: TCD_NBYTES_MLNO + - name: TCD5_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4264 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD5_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4264 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD5_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4268 + fieldset: TCD_SLAST + - name: TCD5_DADDR + description: TCD Destination Address. + byte_offset: 4272 + fieldset: TCD_DADDR + - name: TCD5_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4276 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD5_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4278 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD5_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4278 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD5_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4280 + fieldset: TCD_DLASTSGA + - name: TCD5_CSR + description: TCD Control and Status. + byte_offset: 4284 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD5_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4286 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD5_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4286 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD6_SADDR + description: TCD Source Address. + byte_offset: 4288 + fieldset: TCD_SADDR + - name: TCD6_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4292 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD6_ATTR + description: TCD Transfer Attributes. + byte_offset: 4294 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD6_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4296 + fieldset: TCD_NBYTES_MLNO + - name: TCD6_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4296 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD6_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4296 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD6_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4300 + fieldset: TCD_SLAST + - name: TCD6_DADDR + description: TCD Destination Address. + byte_offset: 4304 + fieldset: TCD_DADDR + - name: TCD6_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4308 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD6_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4310 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD6_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4310 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD6_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4312 + fieldset: TCD_DLASTSGA + - name: TCD6_CSR + description: TCD Control and Status. + byte_offset: 4316 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD6_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4318 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD6_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4318 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD7_SADDR + description: TCD Source Address. + byte_offset: 4320 + fieldset: TCD_SADDR + - name: TCD7_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4324 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD7_ATTR + description: TCD Transfer Attributes. + byte_offset: 4326 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD7_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4328 + fieldset: TCD_NBYTES_MLNO + - name: TCD7_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4328 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD7_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4328 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD7_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4332 + fieldset: TCD_SLAST + - name: TCD7_DADDR + description: TCD Destination Address. + byte_offset: 4336 + fieldset: TCD_DADDR + - name: TCD7_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4340 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD7_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4342 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD7_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4342 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD7_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4344 + fieldset: TCD_DLASTSGA + - name: TCD7_CSR + description: TCD Control and Status. + byte_offset: 4348 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD7_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4350 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD7_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4350 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD8_SADDR + description: TCD Source Address. + byte_offset: 4352 + fieldset: TCD_SADDR + - name: TCD8_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4356 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD8_ATTR + description: TCD Transfer Attributes. + byte_offset: 4358 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD8_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4360 + fieldset: TCD_NBYTES_MLNO + - name: TCD8_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4360 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD8_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4360 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD8_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4364 + fieldset: TCD_SLAST + - name: TCD8_DADDR + description: TCD Destination Address. + byte_offset: 4368 + fieldset: TCD_DADDR + - name: TCD8_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4372 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD8_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4374 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD8_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4374 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD8_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4376 + fieldset: TCD_DLASTSGA + - name: TCD8_CSR + description: TCD Control and Status. + byte_offset: 4380 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD8_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4382 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD8_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4382 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD9_SADDR + description: TCD Source Address. + byte_offset: 4384 + fieldset: TCD_SADDR + - name: TCD9_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4388 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD9_ATTR + description: TCD Transfer Attributes. + byte_offset: 4390 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD9_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4392 + fieldset: TCD_NBYTES_MLNO + - name: TCD9_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4392 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD9_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4392 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD9_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4396 + fieldset: TCD_SLAST + - name: TCD9_DADDR + description: TCD Destination Address. + byte_offset: 4400 + fieldset: TCD_DADDR + - name: TCD9_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4404 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD9_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4406 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD9_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4406 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD9_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4408 + fieldset: TCD_DLASTSGA + - name: TCD9_CSR + description: TCD Control and Status. + byte_offset: 4412 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD9_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4414 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD9_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4414 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD10_SADDR + description: TCD Source Address. + byte_offset: 4416 + fieldset: TCD_SADDR + - name: TCD10_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4420 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD10_ATTR + description: TCD Transfer Attributes. + byte_offset: 4422 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD10_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4424 + fieldset: TCD_NBYTES_MLNO + - name: TCD10_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4424 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD10_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4424 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD10_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4428 + fieldset: TCD_SLAST + - name: TCD10_DADDR + description: TCD Destination Address. + byte_offset: 4432 + fieldset: TCD_DADDR + - name: TCD10_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4436 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD10_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4438 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD10_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4438 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD10_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4440 + fieldset: TCD_DLASTSGA + - name: TCD10_CSR + description: TCD Control and Status. + byte_offset: 4444 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD10_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4446 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD10_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4446 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD11_SADDR + description: TCD Source Address. + byte_offset: 4448 + fieldset: TCD_SADDR + - name: TCD11_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4452 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD11_ATTR + description: TCD Transfer Attributes. + byte_offset: 4454 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD11_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4456 + fieldset: TCD_NBYTES_MLNO + - name: TCD11_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4456 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD11_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4456 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD11_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4460 + fieldset: TCD_SLAST + - name: TCD11_DADDR + description: TCD Destination Address. + byte_offset: 4464 + fieldset: TCD_DADDR + - name: TCD11_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4468 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD11_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4470 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD11_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4470 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD11_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4472 + fieldset: TCD_DLASTSGA + - name: TCD11_CSR + description: TCD Control and Status. + byte_offset: 4476 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD11_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4478 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD11_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4478 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD12_SADDR + description: TCD Source Address. + byte_offset: 4480 + fieldset: TCD_SADDR + - name: TCD12_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4484 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD12_ATTR + description: TCD Transfer Attributes. + byte_offset: 4486 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD12_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4488 + fieldset: TCD_NBYTES_MLNO + - name: TCD12_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4488 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD12_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4488 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD12_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4492 + fieldset: TCD_SLAST + - name: TCD12_DADDR + description: TCD Destination Address. + byte_offset: 4496 + fieldset: TCD_DADDR + - name: TCD12_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4500 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD12_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4502 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD12_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4502 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD12_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4504 + fieldset: TCD_DLASTSGA + - name: TCD12_CSR + description: TCD Control and Status. + byte_offset: 4508 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD12_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4510 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD12_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4510 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD13_SADDR + description: TCD Source Address. + byte_offset: 4512 + fieldset: TCD_SADDR + - name: TCD13_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4516 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD13_ATTR + description: TCD Transfer Attributes. + byte_offset: 4518 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD13_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4520 + fieldset: TCD_NBYTES_MLNO + - name: TCD13_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4520 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD13_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4520 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD13_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4524 + fieldset: TCD_SLAST + - name: TCD13_DADDR + description: TCD Destination Address. + byte_offset: 4528 + fieldset: TCD_DADDR + - name: TCD13_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4532 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD13_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4534 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD13_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4534 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD13_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4536 + fieldset: TCD_DLASTSGA + - name: TCD13_CSR + description: TCD Control and Status. + byte_offset: 4540 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD13_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4542 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD13_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4542 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD14_SADDR + description: TCD Source Address. + byte_offset: 4544 + fieldset: TCD_SADDR + - name: TCD14_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4548 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD14_ATTR + description: TCD Transfer Attributes. + byte_offset: 4550 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD14_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4552 + fieldset: TCD_NBYTES_MLNO + - name: TCD14_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4552 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD14_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4552 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD14_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4556 + fieldset: TCD_SLAST + - name: TCD14_DADDR + description: TCD Destination Address. + byte_offset: 4560 + fieldset: TCD_DADDR + - name: TCD14_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4564 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD14_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4566 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD14_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4566 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD14_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4568 + fieldset: TCD_DLASTSGA + - name: TCD14_CSR + description: TCD Control and Status. + byte_offset: 4572 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD14_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4574 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD14_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4574 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD15_SADDR + description: TCD Source Address. + byte_offset: 4576 + fieldset: TCD_SADDR + - name: TCD15_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4580 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD15_ATTR + description: TCD Transfer Attributes. + byte_offset: 4582 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD15_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Disabled). + byte_offset: 4584 + fieldset: TCD_NBYTES_MLNO + - name: TCD15_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled). + byte_offset: 4584 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD15_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled). + byte_offset: 4584 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD15_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4588 + fieldset: TCD_SLAST + - name: TCD15_DADDR + description: TCD Destination Address. + byte_offset: 4592 + fieldset: TCD_DADDR + - name: TCD15_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4596 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD15_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4598 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD15_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4598 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD15_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4600 + fieldset: TCD_DLASTSGA + - name: TCD15_CSR + description: TCD Control and Status. + byte_offset: 4604 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD15_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4606 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD15_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4606 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES fieldset/CDNE: description: Clear DONE Status Bit Register. bit_size: 8 diff --git a/base/MK22F25612/DMAMUX.yaml b/head/MK22F25612/DMAMUX.yaml index ce79608..2a6218a 100644 --- a/base/MK22F25612/DMAMUX.yaml +++ b/head/MK22F25612/DMAMUX.yaml @@ -1,14 +1,86 @@ block/DMAMUX: description: DMA channel multiplexor. items: - - name: CHCFG + - name: CHCFG0 description: Channel Configuration register. - array: - len: 16 - stride: 1 byte_offset: 0 bit_size: 8 fieldset: CHCFG + - name: CHCFG1 + description: Channel Configuration register. + byte_offset: 1 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG2 + description: Channel Configuration register. + byte_offset: 2 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG3 + description: Channel Configuration register. + byte_offset: 3 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG4 + description: Channel Configuration register. + byte_offset: 4 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG5 + description: Channel Configuration register. + byte_offset: 5 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG6 + description: Channel Configuration register. + byte_offset: 6 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG7 + description: Channel Configuration register. + byte_offset: 7 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG8 + description: Channel Configuration register. + byte_offset: 8 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG9 + description: Channel Configuration register. + byte_offset: 9 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG10 + description: Channel Configuration register. + byte_offset: 10 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG11 + description: Channel Configuration register. + byte_offset: 11 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG12 + description: Channel Configuration register. + byte_offset: 12 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG13 + description: Channel Configuration register. + byte_offset: 13 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG14 + description: Channel Configuration register. + byte_offset: 14 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG15 + description: Channel Configuration register. + byte_offset: 15 + bit_size: 8 + fieldset: CHCFG fieldset/CHCFG: description: Channel Configuration register. bit_size: 8 diff --git a/base/MK22F25612/FMC.yaml b/head/MK22F25612/FMC.yaml index e487f18..5d7727b 100644 --- a/base/MK22F25612/FMC.yaml +++ b/head/MK22F25612/FMC.yaml @@ -13,90 +13,390 @@ block/FMC: description: Flash Bank 1 Control Register. byte_offset: 8 fieldset: PFB1CR - - name: TAGVDW0S + - name: TAGVDW0S0 description: Cache Tag Storage. - array: - len: 8 - stride: 4 byte_offset: 256 fieldset: TAGVDW0S - - name: TAGVDW1S + - name: TAGVDW0S1 + description: Cache Tag Storage. + byte_offset: 260 + fieldset: TAGVDW0S + - name: TAGVDW0S2 + description: Cache Tag Storage. + byte_offset: 264 + fieldset: TAGVDW0S + - name: TAGVDW0S3 + description: Cache Tag Storage. + byte_offset: 268 + fieldset: TAGVDW0S + - name: TAGVDW0S4 + description: Cache Tag Storage. + byte_offset: 272 + fieldset: TAGVDW0S + - name: TAGVDW0S5 + description: Cache Tag Storage. + byte_offset: 276 + fieldset: TAGVDW0S + - name: TAGVDW0S6 + description: Cache Tag Storage. + byte_offset: 280 + fieldset: TAGVDW0S + - name: TAGVDW0S7 + description: Cache Tag Storage. + byte_offset: 284 + fieldset: TAGVDW0S + - name: TAGVDW1S0 description: Cache Tag Storage. - array: - len: 8 - stride: 4 byte_offset: 288 fieldset: TAGVDW1S - - name: TAGVDW2S + - name: TAGVDW1S1 + description: Cache Tag Storage. + byte_offset: 292 + fieldset: TAGVDW1S + - name: TAGVDW1S2 + description: Cache Tag Storage. + byte_offset: 296 + fieldset: TAGVDW1S + - name: TAGVDW1S3 + description: Cache Tag Storage. + byte_offset: 300 + fieldset: TAGVDW1S + - name: TAGVDW1S4 + description: Cache Tag Storage. + byte_offset: 304 + fieldset: TAGVDW1S + - name: TAGVDW1S5 + description: Cache Tag Storage. + byte_offset: 308 + fieldset: TAGVDW1S + - name: TAGVDW1S6 + description: Cache Tag Storage. + byte_offset: 312 + fieldset: TAGVDW1S + - name: TAGVDW1S7 + description: Cache Tag Storage. + byte_offset: 316 + fieldset: TAGVDW1S + - name: TAGVDW2S0 description: Cache Tag Storage. - array: - len: 8 - stride: 4 byte_offset: 320 fieldset: TAGVDW2S - - name: TAGVDW3S + - name: TAGVDW2S1 + description: Cache Tag Storage. + byte_offset: 324 + fieldset: TAGVDW2S + - name: TAGVDW2S2 + description: Cache Tag Storage. + byte_offset: 328 + fieldset: TAGVDW2S + - name: TAGVDW2S3 + description: Cache Tag Storage. + byte_offset: 332 + fieldset: TAGVDW2S + - name: TAGVDW2S4 + description: Cache Tag Storage. + byte_offset: 336 + fieldset: TAGVDW2S + - name: TAGVDW2S5 + description: Cache Tag Storage. + byte_offset: 340 + fieldset: TAGVDW2S + - name: TAGVDW2S6 + description: Cache Tag Storage. + byte_offset: 344 + fieldset: TAGVDW2S + - name: TAGVDW2S7 + description: Cache Tag Storage. + byte_offset: 348 + fieldset: TAGVDW2S + - name: TAGVDW3S0 description: Cache Tag Storage. - array: - len: 8 - stride: 4 byte_offset: 352 fieldset: TAGVDW3S - - name: DATAW0SU + - name: TAGVDW3S1 + description: Cache Tag Storage. + byte_offset: 356 + fieldset: TAGVDW3S + - name: TAGVDW3S2 + description: Cache Tag Storage. + byte_offset: 360 + fieldset: TAGVDW3S + - name: TAGVDW3S3 + description: Cache Tag Storage. + byte_offset: 364 + fieldset: TAGVDW3S + - name: TAGVDW3S4 + description: Cache Tag Storage. + byte_offset: 368 + fieldset: TAGVDW3S + - name: TAGVDW3S5 + description: Cache Tag Storage. + byte_offset: 372 + fieldset: TAGVDW3S + - name: TAGVDW3S6 + description: Cache Tag Storage. + byte_offset: 376 + fieldset: TAGVDW3S + - name: TAGVDW3S7 + description: Cache Tag Storage. + byte_offset: 380 + fieldset: TAGVDW3S + - name: DATAW0S0U description: Cache Data Storage (upper word). - array: - len: 8 - stride: 8 byte_offset: 512 fieldset: DATAW0SU - - name: DATAW0SL + - name: DATAW0S0L description: Cache Data Storage (lower word). - array: - len: 8 - stride: 8 byte_offset: 516 fieldset: DATAW0SL - - name: DATAW1SU + - name: DATAW0S1U + description: Cache Data Storage (upper word). + byte_offset: 520 + fieldset: DATAW0SU + - name: DATAW0S1L + description: Cache Data Storage (lower word). + byte_offset: 524 + fieldset: DATAW0SL + - name: DATAW0S2U + description: Cache Data Storage (upper word). + byte_offset: 528 + fieldset: DATAW0SU + - name: DATAW0S2L + description: Cache Data Storage (lower word). + byte_offset: 532 + fieldset: DATAW0SL + - name: DATAW0S3U + description: Cache Data Storage (upper word). + byte_offset: 536 + fieldset: DATAW0SU + - name: DATAW0S3L + description: Cache Data Storage (lower word). + byte_offset: 540 + fieldset: DATAW0SL + - name: DATAW0S4U + description: Cache Data Storage (upper word). + byte_offset: 544 + fieldset: DATAW0SU + - name: DATAW0S4L + description: Cache Data Storage (lower word). + byte_offset: 548 + fieldset: DATAW0SL + - name: DATAW0S5U + description: Cache Data Storage (upper word). + byte_offset: 552 + fieldset: DATAW0SU + - name: DATAW0S5L + description: Cache Data Storage (lower word). + byte_offset: 556 + fieldset: DATAW0SL + - name: DATAW0S6U + description: Cache Data Storage (upper word). + byte_offset: 560 + fieldset: DATAW0SU + - name: DATAW0S6L + description: Cache Data Storage (lower word). + byte_offset: 564 + fieldset: DATAW0SL + - name: DATAW0S7U + description: Cache Data Storage (upper word). + byte_offset: 568 + fieldset: DATAW0SU + - name: DATAW0S7L + description: Cache Data Storage (lower word). + byte_offset: 572 + fieldset: DATAW0SL + - name: DATAW1S0U description: Cache Data Storage (upper word). - array: - len: 8 - stride: 8 byte_offset: 576 fieldset: DATAW1SU - - name: DATAW1SL + - name: DATAW1S0L description: Cache Data Storage (lower word). - array: - len: 8 - stride: 8 byte_offset: 580 fieldset: DATAW1SL - - name: DATAW2SU + - name: DATAW1S1U + description: Cache Data Storage (upper word). + byte_offset: 584 + fieldset: DATAW1SU + - name: DATAW1S1L + description: Cache Data Storage (lower word). + byte_offset: 588 + fieldset: DATAW1SL + - name: DATAW1S2U + description: Cache Data Storage (upper word). + byte_offset: 592 + fieldset: DATAW1SU + - name: DATAW1S2L + description: Cache Data Storage (lower word). + byte_offset: 596 + fieldset: DATAW1SL + - name: DATAW1S3U + description: Cache Data Storage (upper word). + byte_offset: 600 + fieldset: DATAW1SU + - name: DATAW1S3L + description: Cache Data Storage (lower word). + byte_offset: 604 + fieldset: DATAW1SL + - name: DATAW1S4U + description: Cache Data Storage (upper word). + byte_offset: 608 + fieldset: DATAW1SU + - name: DATAW1S4L + description: Cache Data Storage (lower word). + byte_offset: 612 + fieldset: DATAW1SL + - name: DATAW1S5U + description: Cache Data Storage (upper word). + byte_offset: 616 + fieldset: DATAW1SU + - name: DATAW1S5L + description: Cache Data Storage (lower word). + byte_offset: 620 + fieldset: DATAW1SL + - name: DATAW1S6U + description: Cache Data Storage (upper word). + byte_offset: 624 + fieldset: DATAW1SU + - name: DATAW1S6L + description: Cache Data Storage (lower word). + byte_offset: 628 + fieldset: DATAW1SL + - name: DATAW1S7U + description: Cache Data Storage (upper word). + byte_offset: 632 + fieldset: DATAW1SU + - name: DATAW1S7L + description: Cache Data Storage (lower word). + byte_offset: 636 + fieldset: DATAW1SL + - name: DATAW2S0U description: Cache Data Storage (upper word). - array: - len: 8 - stride: 8 byte_offset: 640 fieldset: DATAW2SU - - name: DATAW2SL + - name: DATAW2S0L description: Cache Data Storage (lower word). - array: - len: 8 - stride: 8 byte_offset: 644 fieldset: DATAW2SL - - name: DATAW3SU + - name: DATAW2S1U + description: Cache Data Storage (upper word). + byte_offset: 648 + fieldset: DATAW2SU + - name: DATAW2S1L + description: Cache Data Storage (lower word). + byte_offset: 652 + fieldset: DATAW2SL + - name: DATAW2S2U + description: Cache Data Storage (upper word). + byte_offset: 656 + fieldset: DATAW2SU + - name: DATAW2S2L + description: Cache Data Storage (lower word). + byte_offset: 660 + fieldset: DATAW2SL + - name: DATAW2S3U + description: Cache Data Storage (upper word). + byte_offset: 664 + fieldset: DATAW2SU + - name: DATAW2S3L + description: Cache Data Storage (lower word). + byte_offset: 668 + fieldset: DATAW2SL + - name: DATAW2S4U + description: Cache Data Storage (upper word). + byte_offset: 672 + fieldset: DATAW2SU + - name: DATAW2S4L + description: Cache Data Storage (lower word). + byte_offset: 676 + fieldset: DATAW2SL + - name: DATAW2S5U + description: Cache Data Storage (upper word). + byte_offset: 680 + fieldset: DATAW2SU + - name: DATAW2S5L + description: Cache Data Storage (lower word). + byte_offset: 684 + fieldset: DATAW2SL + - name: DATAW2S6U + description: Cache Data Storage (upper word). + byte_offset: 688 + fieldset: DATAW2SU + - name: DATAW2S6L + description: Cache Data Storage (lower word). + byte_offset: 692 + fieldset: DATAW2SL + - name: DATAW2S7U + description: Cache Data Storage (upper word). + byte_offset: 696 + fieldset: DATAW2SU + - name: DATAW2S7L + description: Cache Data Storage (lower word). + byte_offset: 700 + fieldset: DATAW2SL + - name: DATAW3S0U description: Cache Data Storage (upper word). - array: - len: 8 - stride: 8 byte_offset: 704 fieldset: DATAW3SU - - name: DATAW3SL + - name: DATAW3S0L description: Cache Data Storage (lower word). - array: - len: 8 - stride: 8 byte_offset: 708 fieldset: DATAW3SL + - name: DATAW3S1U + description: Cache Data Storage (upper word). + byte_offset: 712 + fieldset: DATAW3SU + - name: DATAW3S1L + description: Cache Data Storage (lower word). + byte_offset: 716 + fieldset: DATAW3SL + - name: DATAW3S2U + description: Cache Data Storage (upper word). + byte_offset: 720 + fieldset: DATAW3SU + - name: DATAW3S2L + description: Cache Data Storage (lower word). + byte_offset: 724 + fieldset: DATAW3SL + - name: DATAW3S3U + description: Cache Data Storage (upper word). + byte_offset: 728 + fieldset: DATAW3SU + - name: DATAW3S3L + description: Cache Data Storage (lower word). + byte_offset: 732 + fieldset: DATAW3SL + - name: DATAW3S4U + description: Cache Data Storage (upper word). + byte_offset: 736 + fieldset: DATAW3SU + - name: DATAW3S4L + description: Cache Data Storage (lower word). + byte_offset: 740 + fieldset: DATAW3SL + - name: DATAW3S5U + description: Cache Data Storage (upper word). + byte_offset: 744 + fieldset: DATAW3SU + - name: DATAW3S5L + description: Cache Data Storage (lower word). + byte_offset: 748 + fieldset: DATAW3SL + - name: DATAW3S6U + description: Cache Data Storage (upper word). + byte_offset: 752 + fieldset: DATAW3SU + - name: DATAW3S6L + description: Cache Data Storage (lower word). + byte_offset: 756 + fieldset: DATAW3SL + - name: DATAW3S7U + description: Cache Data Storage (upper word). + byte_offset: 760 + fieldset: DATAW3SU + - name: DATAW3S7L + description: Cache Data Storage (lower word). + byte_offset: 764 + fieldset: DATAW3SL fieldset/DATAW0SL: description: Cache Data Storage (lower word). fields: diff --git a/base/MK22F25612/FTFA.yaml b/head/MK22F25612/FTFA.yaml index 2fc5a44..11b1f30 100644 --- a/base/MK22F25612/FTFA.yaml +++ b/head/MK22F25612/FTFA.yaml @@ -23,40 +23,182 @@ block/FTFA: access: Read bit_size: 8 fieldset: FOPT - - name: FCCOB + - name: FCCOB3 description: Flash Common Command Object Registers. - array: - len: 12 - stride: 1 byte_offset: 4 bit_size: 8 fieldset: FCCOB - - name: FPROT + - name: FCCOB2 + description: Flash Common Command Object Registers. + byte_offset: 5 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB1 + description: Flash Common Command Object Registers. + byte_offset: 6 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB0 + description: Flash Common Command Object Registers. + byte_offset: 7 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB7 + description: Flash Common Command Object Registers. + byte_offset: 8 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB6 + description: Flash Common Command Object Registers. + byte_offset: 9 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB5 + description: Flash Common Command Object Registers. + byte_offset: 10 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB4 + description: Flash Common Command Object Registers. + byte_offset: 11 + bit_size: 8 + fieldset: FCCOB + - name: FCCOBB + description: Flash Common Command Object Registers. + byte_offset: 12 + bit_size: 8 + fieldset: FCCOB + - name: FCCOBA + description: Flash Common Command Object Registers. + byte_offset: 13 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB9 + description: Flash Common Command Object Registers. + byte_offset: 14 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB8 + description: Flash Common Command Object Registers. + byte_offset: 15 + bit_size: 8 + fieldset: FCCOB + - name: FPROT3 description: Program Flash Protection Registers. - array: - len: 4 - stride: 1 byte_offset: 16 bit_size: 8 fieldset: FPROT - - name: XACC + - name: FPROT2 + description: Program Flash Protection Registers. + byte_offset: 17 + bit_size: 8 + fieldset: FPROT + - name: FPROT1 + description: Program Flash Protection Registers. + byte_offset: 18 + bit_size: 8 + fieldset: FPROT + - name: FPROT0 + description: Program Flash Protection Registers. + byte_offset: 19 + bit_size: 8 + fieldset: FPROT + - name: XACCH3 description: Execute-only Access Registers. - array: - len: 8 - stride: 1 byte_offset: 24 access: Read bit_size: 8 fieldset: XACC - - name: SACC + - name: XACCH2 + description: Execute-only Access Registers. + byte_offset: 25 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCH1 + description: Execute-only Access Registers. + byte_offset: 26 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCH0 + description: Execute-only Access Registers. + byte_offset: 27 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCL3 + description: Execute-only Access Registers. + byte_offset: 28 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCL2 + description: Execute-only Access Registers. + byte_offset: 29 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCL1 + description: Execute-only Access Registers. + byte_offset: 30 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCL0 + description: Execute-only Access Registers. + byte_offset: 31 + access: Read + bit_size: 8 + fieldset: XACC + - name: SACCH3 description: Supervisor-only Access Registers. - array: - len: 8 - stride: 1 byte_offset: 32 access: Read bit_size: 8 fieldset: SACC + - name: SACCH2 + description: Supervisor-only Access Registers. + byte_offset: 33 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCH1 + description: Supervisor-only Access Registers. + byte_offset: 34 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCH0 + description: Supervisor-only Access Registers. + byte_offset: 35 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCL3 + description: Supervisor-only Access Registers. + byte_offset: 36 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCL2 + description: Supervisor-only Access Registers. + byte_offset: 37 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCL1 + description: Supervisor-only Access Registers. + byte_offset: 38 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCL0 + description: Supervisor-only Access Registers. + byte_offset: 39 + access: Read + bit_size: 8 + fieldset: SACC - name: FACSS description: Flash Access Segment Size Register. byte_offset: 40 diff --git a/base/MK22F25612/FTM0.yaml b/head/MK22F25612/FTM0.yaml index 6c0e242..d14e6d2 100644 --- a/base/MK22F25612/FTM0.yaml +++ b/head/MK22F25612/FTM0.yaml @@ -13,20 +13,70 @@ block/FTM0: description: Modulo. byte_offset: 8 fieldset: MOD - - name: CSC + - name: C0SC description: Channel (n) Status And Control. - array: - len: 8 - stride: 8 byte_offset: 12 fieldset: CSC - - name: CV + - name: C0V description: Channel (n) Value. - array: - len: 8 - stride: 8 byte_offset: 16 fieldset: CV + - name: C1SC + description: Channel (n) Status And Control. + byte_offset: 20 + fieldset: CSC + - name: C1V + description: Channel (n) Value. + byte_offset: 24 + fieldset: CV + - name: C2SC + description: Channel (n) Status And Control. + byte_offset: 28 + fieldset: CSC + - name: C2V + description: Channel (n) Value. + byte_offset: 32 + fieldset: CV + - name: C3SC + description: Channel (n) Status And Control. + byte_offset: 36 + fieldset: CSC + - name: C3V + description: Channel (n) Value. + byte_offset: 40 + fieldset: CV + - name: C4SC + description: Channel (n) Status And Control. + byte_offset: 44 + fieldset: CSC + - name: C4V + description: Channel (n) Value. + byte_offset: 48 + fieldset: CV + - name: C5SC + description: Channel (n) Status And Control. + byte_offset: 52 + fieldset: CSC + - name: C5V + description: Channel (n) Value. + byte_offset: 56 + fieldset: CV + - name: C6SC + description: Channel (n) Status And Control. + byte_offset: 60 + fieldset: CSC + - name: C6V + description: Channel (n) Value. + byte_offset: 64 + fieldset: CV + - name: C7SC + description: Channel (n) Status And Control. + byte_offset: 68 + fieldset: CSC + - name: C7V + description: Channel (n) Value. + byte_offset: 72 + fieldset: CV - name: CNTIN description: Counter Initial Value. byte_offset: 76 diff --git a/base/MK22F25612/FTM1.yaml b/head/MK22F25612/FTM1.yaml index ae99099..3c23fa3 100644 --- a/base/MK22F25612/FTM1.yaml +++ b/head/MK22F25612/FTM1.yaml @@ -13,20 +13,22 @@ block/FTM1: description: Modulo. byte_offset: 8 fieldset: MOD - - name: CSC + - name: C0SC description: Channel (n) Status And Control. - array: - len: 2 - stride: 8 byte_offset: 12 fieldset: CSC - - name: CV + - name: C0V description: Channel (n) Value. - array: - len: 2 - stride: 8 byte_offset: 16 fieldset: CV + - name: C1SC + description: Channel (n) Status And Control. + byte_offset: 20 + fieldset: CSC + - name: C1V + description: Channel (n) Value. + byte_offset: 24 + fieldset: CV - name: CNTIN description: Counter Initial Value. byte_offset: 76 diff --git a/base/MK22F25612/FTM2.yaml b/head/MK22F25612/FTM2.yaml index f90afa3..5a32ea0 100644 --- a/base/MK22F25612/FTM2.yaml +++ b/head/MK22F25612/FTM2.yaml @@ -13,20 +13,22 @@ block/FTM2: description: Modulo. byte_offset: 8 fieldset: MOD - - name: CSC + - name: C0SC description: Channel (n) Status And Control. - array: - len: 2 - stride: 8 byte_offset: 12 fieldset: CSC - - name: CV + - name: C0V description: Channel (n) Value. - array: - len: 2 - stride: 8 byte_offset: 16 fieldset: CV + - name: C1SC + description: Channel (n) Status And Control. + byte_offset: 20 + fieldset: CSC + - name: C1V + description: Channel (n) Value. + byte_offset: 24 + fieldset: CV - name: CNTIN description: Counter Initial Value. byte_offset: 76 diff --git a/base/MK22F25612/PDB0.yaml b/head/MK22F25612/PDB0.yaml index 79d0da3..387b1de 100644 --- a/base/MK22F25612/PDB0.yaml +++ b/head/MK22F25612/PDB0.yaml @@ -18,34 +18,38 @@ block/PDB0: description: Interrupt Delay register. byte_offset: 12 fieldset: IDLY - - name: CHC1 + - name: CH0C1 description: Channel n Control register 1. - array: - len: 2 - stride: 40 byte_offset: 16 fieldset: CHC1 - - name: CHS + - name: CH0S description: Channel n Status register. - array: - len: 2 - stride: 40 byte_offset: 20 fieldset: CHS - - name: CHDLY0 + - name: CH0DLY0 description: Channel n Delay 0 register. - array: - len: 2 - stride: 40 byte_offset: 24 fieldset: CHDLY0 - - name: CHDLY1 + - name: CH0DLY1 description: Channel n Delay 1 register. - array: - len: 2 - stride: 40 byte_offset: 28 fieldset: CHDLY1 + - name: CH1C1 + description: Channel n Control register 1. + byte_offset: 56 + fieldset: CHC1 + - name: CH1S + description: Channel n Status register. + byte_offset: 60 + fieldset: CHS + - name: CH1DLY0 + description: Channel n Delay 0 register. + byte_offset: 64 + fieldset: CHDLY0 + - name: CH1DLY1 + description: Channel n Delay 1 register. + byte_offset: 68 + fieldset: CHDLY1 - name: DACINTC description: DAC Interval Trigger n Control register. byte_offset: 336 @@ -58,13 +62,14 @@ block/PDB0: description: Pulse-Out n Enable register. byte_offset: 400 fieldset: POEN - - name: PODLY + - name: PO0DLY description: Pulse-Out n Delay register. - array: - len: 2 - stride: 4 byte_offset: 404 fieldset: PODLY + - name: PO1DLY + description: Pulse-Out n Delay register. + byte_offset: 408 + fieldset: PODLY fieldset/CHC1: description: Channel n Control register 1. fields: diff --git a/base/MK22F25612/PIT.yaml b/head/MK22F25612/PIT.yaml index d81e5d1..baf70f8 100644 --- a/base/MK22F25612/PIT.yaml +++ b/head/MK22F25612/PIT.yaml @@ -5,35 +5,74 @@ block/PIT: description: PIT Module Control Register. byte_offset: 0 fieldset: MCR - - name: LDVAL + - name: LDVAL0 description: Timer Load Value Register. - array: - len: 4 - stride: 16 byte_offset: 256 fieldset: LDVAL - - name: CVAL + - name: CVAL0 description: Current Timer Value Register. - array: - len: 4 - stride: 16 byte_offset: 260 access: Read fieldset: CVAL - - name: TCTRL + - name: TCTRL0 description: Timer Control Register. - array: - len: 4 - stride: 16 byte_offset: 264 fieldset: TCTRL - - name: TFLG + - name: TFLG0 description: Timer Flag Register. - array: - len: 4 - stride: 16 byte_offset: 268 fieldset: TFLG + - name: LDVAL1 + description: Timer Load Value Register. + byte_offset: 272 + fieldset: LDVAL + - name: CVAL1 + description: Current Timer Value Register. + byte_offset: 276 + access: Read + fieldset: CVAL + - name: TCTRL1 + description: Timer Control Register. + byte_offset: 280 + fieldset: TCTRL + - name: TFLG1 + description: Timer Flag Register. + byte_offset: 284 + fieldset: TFLG + - name: LDVAL2 + description: Timer Load Value Register. + byte_offset: 288 + fieldset: LDVAL + - name: CVAL2 + description: Current Timer Value Register. + byte_offset: 292 + access: Read + fieldset: CVAL + - name: TCTRL2 + description: Timer Control Register. + byte_offset: 296 + fieldset: TCTRL + - name: TFLG2 + description: Timer Flag Register. + byte_offset: 300 + fieldset: TFLG + - name: LDVAL3 + description: Timer Load Value Register. + byte_offset: 304 + fieldset: LDVAL + - name: CVAL3 + description: Current Timer Value Register. + byte_offset: 308 + access: Read + fieldset: CVAL + - name: TCTRL3 + description: Timer Control Register. + byte_offset: 312 + fieldset: TCTRL + - name: TFLG3 + description: Timer Flag Register. + byte_offset: 316 + fieldset: TFLG fieldset/CVAL: description: Current Timer Value Register. fields: diff --git a/base/MK22F25612/RFSYS.yaml b/head/MK22F25612/RFSYS.yaml index 4041816..7a4484b 100644 --- a/base/MK22F25612/RFSYS.yaml +++ b/head/MK22F25612/RFSYS.yaml @@ -1,13 +1,38 @@ block/RFSYS: description: System register file. items: - - name: REG + - name: REG0 description: Register file register. - array: - len: 8 - stride: 4 byte_offset: 0 fieldset: REG + - name: REG1 + description: Register file register. + byte_offset: 4 + fieldset: REG + - name: REG2 + description: Register file register. + byte_offset: 8 + fieldset: REG + - name: REG3 + description: Register file register. + byte_offset: 12 + fieldset: REG + - name: REG4 + description: Register file register. + byte_offset: 16 + fieldset: REG + - name: REG5 + description: Register file register. + byte_offset: 20 + fieldset: REG + - name: REG6 + description: Register file register. + byte_offset: 24 + fieldset: REG + - name: REG7 + description: Register file register. + byte_offset: 28 + fieldset: REG fieldset/REG: description: Register file register. fields: diff --git a/base/MK22F25612/RFVBAT.yaml b/head/MK22F25612/RFVBAT.yaml index 7029309..3159c94 100644 --- a/base/MK22F25612/RFVBAT.yaml +++ b/head/MK22F25612/RFVBAT.yaml @@ -1,13 +1,38 @@ block/RFVBAT: description: VBAT register file. items: - - name: REG + - name: REG0 description: VBAT register file register. - array: - len: 8 - stride: 4 byte_offset: 0 fieldset: REG + - name: REG1 + description: VBAT register file register. + byte_offset: 4 + fieldset: REG + - name: REG2 + description: VBAT register file register. + byte_offset: 8 + fieldset: REG + - name: REG3 + description: VBAT register file register. + byte_offset: 12 + fieldset: REG + - name: REG4 + description: VBAT register file register. + byte_offset: 16 + fieldset: REG + - name: REG5 + description: VBAT register file register. + byte_offset: 20 + fieldset: REG + - name: REG6 + description: VBAT register file register. + byte_offset: 24 + fieldset: REG + - name: REG7 + description: VBAT register file register. + byte_offset: 28 + fieldset: REG fieldset/REG: description: VBAT register file register. fields: diff --git a/base/MK22F25612/SPI0.yaml b/head/MK22F25612/SPI0.yaml index fb0c8fb..643c78c 100644 --- a/base/MK22F25612/SPI0.yaml +++ b/head/MK22F25612/SPI0.yaml @@ -9,17 +9,18 @@ block/SPI0: description: Transfer Count Register. byte_offset: 8 fieldset: TCR - - name: CTAR + - name: CTAR0 description: Clock and Transfer Attributes Register (In Master Mode). - array: - len: 2 - stride: 4 byte_offset: 12 fieldset: CTAR - name: CTAR_SLAVE description: Clock and Transfer Attributes Register (In Slave Mode). byte_offset: 12 fieldset: CTAR_SLAVE + - name: CTAR1 + description: Clock and Transfer Attributes Register (In Master Mode). + byte_offset: 16 + fieldset: CTAR - name: SR description: Status Register. byte_offset: 44 @@ -41,22 +42,46 @@ block/SPI0: byte_offset: 56 access: Read fieldset: POPR - - name: TXFR + - name: TXFR0 description: Transmit FIFO Registers. - array: - len: 4 - stride: 4 byte_offset: 60 access: Read fieldset: TXFR - - name: RXFR + - name: TXFR1 + description: Transmit FIFO Registers. + byte_offset: 64 + access: Read + fieldset: TXFR + - name: TXFR2 + description: Transmit FIFO Registers. + byte_offset: 68 + access: Read + fieldset: TXFR + - name: TXFR3 + description: Transmit FIFO Registers. + byte_offset: 72 + access: Read + fieldset: TXFR + - name: RXFR0 description: Receive FIFO Registers. - array: - len: 4 - stride: 4 byte_offset: 124 access: Read fieldset: RXFR + - name: RXFR1 + description: Receive FIFO Registers. + byte_offset: 128 + access: Read + fieldset: RXFR + - name: RXFR2 + description: Receive FIFO Registers. + byte_offset: 132 + access: Read + fieldset: RXFR + - name: RXFR3 + description: Receive FIFO Registers. + byte_offset: 136 + access: Read + fieldset: RXFR fieldset/CTAR: description: Clock and Transfer Attributes Register (In Master Mode). fields: diff --git a/base/MK22F25612/SPI1.yaml b/head/MK22F25612/SPI1.yaml index ccb572b..7959eed 100644 --- a/base/MK22F25612/SPI1.yaml +++ b/head/MK22F25612/SPI1.yaml @@ -9,17 +9,18 @@ block/SPI1: description: Transfer Count Register. byte_offset: 8 fieldset: TCR - - name: CTAR + - name: CTAR0 description: Clock and Transfer Attributes Register (In Master Mode). - array: - len: 2 - stride: 4 byte_offset: 12 fieldset: CTAR - name: CTAR_SLAVE description: Clock and Transfer Attributes Register (In Slave Mode). byte_offset: 12 fieldset: CTAR_SLAVE + - name: CTAR1 + description: Clock and Transfer Attributes Register (In Master Mode). + byte_offset: 16 + fieldset: CTAR - name: SR description: Status Register. byte_offset: 44 @@ -41,22 +42,46 @@ block/SPI1: byte_offset: 56 access: Read fieldset: POPR - - name: TXFR + - name: TXFR0 description: Transmit FIFO Registers. - array: - len: 4 - stride: 4 byte_offset: 60 access: Read fieldset: TXFR - - name: RXFR + - name: TXFR1 + description: Transmit FIFO Registers. + byte_offset: 64 + access: Read + fieldset: TXFR + - name: TXFR2 + description: Transmit FIFO Registers. + byte_offset: 68 + access: Read + fieldset: TXFR + - name: TXFR3 + description: Transmit FIFO Registers. + byte_offset: 72 + access: Read + fieldset: TXFR + - name: RXFR0 description: Receive FIFO Registers. - array: - len: 4 - stride: 4 byte_offset: 124 access: Read fieldset: RXFR + - name: RXFR1 + description: Receive FIFO Registers. + byte_offset: 128 + access: Read + fieldset: RXFR + - name: RXFR2 + description: Receive FIFO Registers. + byte_offset: 132 + access: Read + fieldset: RXFR + - name: RXFR3 + description: Receive FIFO Registers. + byte_offset: 136 + access: Read + fieldset: RXFR fieldset/CTAR: description: Clock and Transfer Attributes Register (In Master Mode). fields: diff --git a/base/MK22F25612/USB0.yaml b/head/MK22F25612/USB0.yaml index 4394d5a..e3bdd75 100644 --- a/base/MK22F25612/USB0.yaml +++ b/head/MK22F25612/USB0.yaml @@ -116,14 +116,86 @@ block/USB0: byte_offset: 180 bit_size: 8 fieldset: BDTPAGE3 - - name: ENDPT + - name: ENDPT0 description: Endpoint Control register. - array: - len: 16 - stride: 4 byte_offset: 192 bit_size: 8 fieldset: ENDPT + - name: ENDPT1 + description: Endpoint Control register. + byte_offset: 196 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT2 + description: Endpoint Control register. + byte_offset: 200 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT3 + description: Endpoint Control register. + byte_offset: 204 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT4 + description: Endpoint Control register. + byte_offset: 208 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT5 + description: Endpoint Control register. + byte_offset: 212 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT6 + description: Endpoint Control register. + byte_offset: 216 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT7 + description: Endpoint Control register. + byte_offset: 220 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT8 + description: Endpoint Control register. + byte_offset: 224 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT9 + description: Endpoint Control register. + byte_offset: 228 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT10 + description: Endpoint Control register. + byte_offset: 232 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT11 + description: Endpoint Control register. + byte_offset: 236 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT12 + description: Endpoint Control register. + byte_offset: 240 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT13 + description: Endpoint Control register. + byte_offset: 244 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT14 + description: Endpoint Control register. + byte_offset: 248 + bit_size: 8 + fieldset: ENDPT + - name: ENDPT15 + description: Endpoint Control register. + byte_offset: 252 + bit_size: 8 + fieldset: ENDPT - name: USBCTRL description: USB Control register. byte_offset: 256 diff --git a/base/MKL17Z644/ADC0.yaml b/head/MKL17Z644/ADC0.yaml index 4e465c4..e870082 100644 --- a/base/MKL17Z644/ADC0.yaml +++ b/head/MKL17Z644/ADC0.yaml @@ -1,13 +1,14 @@ block/ADC0: description: Analog-to-Digital Converter. items: - - name: SC1 + - name: SC1A description: ADC Status and Control Registers 1. - array: - len: 2 - stride: 4 byte_offset: 0 fieldset: SC1 + - name: SC1B + description: ADC Status and Control Registers 1. + byte_offset: 4 + fieldset: SC1 - name: CFG1 description: ADC Configuration Register 1. byte_offset: 8 @@ -16,21 +17,24 @@ block/ADC0: description: ADC Configuration Register 2. byte_offset: 12 fieldset: CFG2 - - name: R + - name: RA description: ADC Data Result Register. - array: - len: 2 - stride: 4 byte_offset: 16 access: Read fieldset: R - - name: CV + - name: RB + description: ADC Data Result Register. + byte_offset: 20 + access: Read + fieldset: R + - name: CV1 description: Compare Value Registers. - array: - len: 2 - stride: 4 byte_offset: 24 fieldset: CV + - name: CV2 + description: Compare Value Registers. + byte_offset: 28 + fieldset: CV - name: SC2 description: Status and Control Register 2. byte_offset: 32 diff --git a/base/MKL17Z644/DMAMUX0.yaml b/head/MKL17Z644/DMAMUX0.yaml index b094884..b05380c 100644 --- a/base/MKL17Z644/DMAMUX0.yaml +++ b/head/MKL17Z644/DMAMUX0.yaml @@ -1,14 +1,26 @@ block/DMAMUX0: description: DMA channel multiplexor. items: - - name: CHCFG + - name: CHCFG0 description: Channel Configuration register. - array: - len: 4 - stride: 1 byte_offset: 0 bit_size: 8 fieldset: CHCFG + - name: CHCFG1 + description: Channel Configuration register. + byte_offset: 1 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG2 + description: Channel Configuration register. + byte_offset: 2 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG3 + description: Channel Configuration register. + byte_offset: 3 + bit_size: 8 + fieldset: CHCFG fieldset/CHCFG: description: Channel Configuration register. bit_size: 8 diff --git a/base/MKL17Z644/FLEXIO.yaml b/head/MKL17Z644/FLEXIO.yaml index 535471b..1b43102 100644 --- a/base/MKL17Z644/FLEXIO.yaml +++ b/head/MKL17Z644/FLEXIO.yaml @@ -43,69 +43,150 @@ block/FLEXIO: description: Shifter Status DMA Enable. byte_offset: 48 fieldset: SHIFTSDEN - - name: SHIFTCTL + - name: SHIFTCTL0 description: Shifter Control N Register. - array: - len: 4 - stride: 4 byte_offset: 128 fieldset: SHIFTCTL - - name: SHIFTCFG + - name: SHIFTCTL1 + description: Shifter Control N Register. + byte_offset: 132 + fieldset: SHIFTCTL + - name: SHIFTCTL2 + description: Shifter Control N Register. + byte_offset: 136 + fieldset: SHIFTCTL + - name: SHIFTCTL3 + description: Shifter Control N Register. + byte_offset: 140 + fieldset: SHIFTCTL + - name: SHIFTCFG0 description: Shifter Configuration N Register. - array: - len: 4 - stride: 4 byte_offset: 256 fieldset: SHIFTCFG - - name: SHIFTBUF + - name: SHIFTCFG1 + description: Shifter Configuration N Register. + byte_offset: 260 + fieldset: SHIFTCFG + - name: SHIFTCFG2 + description: Shifter Configuration N Register. + byte_offset: 264 + fieldset: SHIFTCFG + - name: SHIFTCFG3 + description: Shifter Configuration N Register. + byte_offset: 268 + fieldset: SHIFTCFG + - name: SHIFTBUF0 description: Shifter Buffer N Register. - array: - len: 4 - stride: 4 byte_offset: 512 fieldset: SHIFTBUF - - name: SHIFTBUFBIS + - name: SHIFTBUF1 + description: Shifter Buffer N Register. + byte_offset: 516 + fieldset: SHIFTBUF + - name: SHIFTBUF2 + description: Shifter Buffer N Register. + byte_offset: 520 + fieldset: SHIFTBUF + - name: SHIFTBUF3 + description: Shifter Buffer N Register. + byte_offset: 524 + fieldset: SHIFTBUF + - name: SHIFTBUFBIS0 description: Shifter Buffer N Bit Swapped Register. - array: - len: 4 - stride: 4 byte_offset: 640 fieldset: SHIFTBUFBIS - - name: SHIFTBUFBYS + - name: SHIFTBUFBIS1 + description: Shifter Buffer N Bit Swapped Register. + byte_offset: 644 + fieldset: SHIFTBUFBIS + - name: SHIFTBUFBIS2 + description: Shifter Buffer N Bit Swapped Register. + byte_offset: 648 + fieldset: SHIFTBUFBIS + - name: SHIFTBUFBIS3 + description: Shifter Buffer N Bit Swapped Register. + byte_offset: 652 + fieldset: SHIFTBUFBIS + - name: SHIFTBUFBYS0 description: Shifter Buffer N Byte Swapped Register. - array: - len: 4 - stride: 4 byte_offset: 768 fieldset: SHIFTBUFBYS - - name: SHIFTBUFBBS + - name: SHIFTBUFBYS1 + description: Shifter Buffer N Byte Swapped Register. + byte_offset: 772 + fieldset: SHIFTBUFBYS + - name: SHIFTBUFBYS2 + description: Shifter Buffer N Byte Swapped Register. + byte_offset: 776 + fieldset: SHIFTBUFBYS + - name: SHIFTBUFBYS3 + description: Shifter Buffer N Byte Swapped Register. + byte_offset: 780 + fieldset: SHIFTBUFBYS + - name: SHIFTBUFBBS0 description: Shifter Buffer N Bit Byte Swapped Register. - array: - len: 4 - stride: 4 byte_offset: 896 fieldset: SHIFTBUFBBS - - name: TIMCTL + - name: SHIFTBUFBBS1 + description: Shifter Buffer N Bit Byte Swapped Register. + byte_offset: 900 + fieldset: SHIFTBUFBBS + - name: SHIFTBUFBBS2 + description: Shifter Buffer N Bit Byte Swapped Register. + byte_offset: 904 + fieldset: SHIFTBUFBBS + - name: SHIFTBUFBBS3 + description: Shifter Buffer N Bit Byte Swapped Register. + byte_offset: 908 + fieldset: SHIFTBUFBBS + - name: TIMCTL0 description: Timer Control N Register. - array: - len: 4 - stride: 4 byte_offset: 1024 fieldset: TIMCTL - - name: TIMCFG + - name: TIMCTL1 + description: Timer Control N Register. + byte_offset: 1028 + fieldset: TIMCTL + - name: TIMCTL2 + description: Timer Control N Register. + byte_offset: 1032 + fieldset: TIMCTL + - name: TIMCTL3 + description: Timer Control N Register. + byte_offset: 1036 + fieldset: TIMCTL + - name: TIMCFG0 description: Timer Configuration N Register. - array: - len: 4 - stride: 4 byte_offset: 1152 fieldset: TIMCFG - - name: TIMCMP + - name: TIMCFG1 + description: Timer Configuration N Register. + byte_offset: 1156 + fieldset: TIMCFG + - name: TIMCFG2 + description: Timer Configuration N Register. + byte_offset: 1160 + fieldset: TIMCFG + - name: TIMCFG3 + description: Timer Configuration N Register. + byte_offset: 1164 + fieldset: TIMCFG + - name: TIMCMP0 description: Timer Compare N Register. - array: - len: 4 - stride: 4 byte_offset: 1280 fieldset: TIMCMP + - name: TIMCMP1 + description: Timer Compare N Register. + byte_offset: 1284 + fieldset: TIMCMP + - name: TIMCMP2 + description: Timer Compare N Register. + byte_offset: 1288 + fieldset: TIMCMP + - name: TIMCMP3 + description: Timer Compare N Register. + byte_offset: 1292 + fieldset: TIMCMP fieldset/CTRL: description: FlexIO Control Register. fields: diff --git a/base/MKL17Z644/FTFA.yaml b/head/MKL17Z644/FTFA.yaml index 2fb206d..8c06479 100644 --- a/base/MKL17Z644/FTFA.yaml +++ b/head/MKL17Z644/FTFA.yaml @@ -23,22 +23,86 @@ block/FTFA: access: Read bit_size: 8 fieldset: FOPT - - name: FCCOB + - name: FCCOB3 description: Flash Common Command Object Registers. - array: - len: 12 - stride: 1 byte_offset: 4 bit_size: 8 fieldset: FCCOB - - name: FPROT + - name: FCCOB2 + description: Flash Common Command Object Registers. + byte_offset: 5 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB1 + description: Flash Common Command Object Registers. + byte_offset: 6 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB0 + description: Flash Common Command Object Registers. + byte_offset: 7 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB7 + description: Flash Common Command Object Registers. + byte_offset: 8 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB6 + description: Flash Common Command Object Registers. + byte_offset: 9 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB5 + description: Flash Common Command Object Registers. + byte_offset: 10 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB4 + description: Flash Common Command Object Registers. + byte_offset: 11 + bit_size: 8 + fieldset: FCCOB + - name: FCCOBB + description: Flash Common Command Object Registers. + byte_offset: 12 + bit_size: 8 + fieldset: FCCOB + - name: FCCOBA + description: Flash Common Command Object Registers. + byte_offset: 13 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB9 + description: Flash Common Command Object Registers. + byte_offset: 14 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB8 + description: Flash Common Command Object Registers. + byte_offset: 15 + bit_size: 8 + fieldset: FCCOB + - name: FPROT3 description: Program Flash Protection Registers. - array: - len: 4 - stride: 1 byte_offset: 16 bit_size: 8 fieldset: FPROT + - name: FPROT2 + description: Program Flash Protection Registers. + byte_offset: 17 + bit_size: 8 + fieldset: FPROT + - name: FPROT1 + description: Program Flash Protection Registers. + byte_offset: 18 + bit_size: 8 + fieldset: FPROT + - name: FPROT0 + description: Program Flash Protection Registers. + byte_offset: 19 + bit_size: 8 + fieldset: FPROT fieldset/FCCOB: description: Flash Common Command Object Registers. bit_size: 8 diff --git a/base/MKL17Z644/MTB.yaml b/head/MKL17Z644/MTB.yaml index 6467743..c67d5e8 100644 --- a/base/MKL17Z644/MTB.yaml +++ b/head/MKL17Z644/MTB.yaml @@ -63,22 +63,66 @@ block/MTB: byte_offset: 4044 access: Read fieldset: DEVICETYPID - - name: PERIPHID + - name: PERIPHID4 description: Peripheral ID Register. - array: - len: 8 - stride: 4 byte_offset: 4048 access: Read fieldset: PERIPHID - - name: COMPID + - name: PERIPHID5 + description: Peripheral ID Register. + byte_offset: 4052 + access: Read + fieldset: PERIPHID + - name: PERIPHID6 + description: Peripheral ID Register. + byte_offset: 4056 + access: Read + fieldset: PERIPHID + - name: PERIPHID7 + description: Peripheral ID Register. + byte_offset: 4060 + access: Read + fieldset: PERIPHID + - name: PERIPHID0 + description: Peripheral ID Register. + byte_offset: 4064 + access: Read + fieldset: PERIPHID + - name: PERIPHID1 + description: Peripheral ID Register. + byte_offset: 4068 + access: Read + fieldset: PERIPHID + - name: PERIPHID2 + description: Peripheral ID Register. + byte_offset: 4072 + access: Read + fieldset: PERIPHID + - name: PERIPHID3 + description: Peripheral ID Register. + byte_offset: 4076 + access: Read + fieldset: PERIPHID + - name: COMPID0 description: Component ID Register. - array: - len: 4 - stride: 4 byte_offset: 4080 access: Read fieldset: COMPID + - name: COMPID1 + description: Component ID Register. + byte_offset: 4084 + access: Read + fieldset: COMPID + - name: COMPID2 + description: Component ID Register. + byte_offset: 4088 + access: Read + fieldset: COMPID + - name: COMPID3 + description: Component ID Register. + byte_offset: 4092 + access: Read + fieldset: COMPID fieldset/AUTHSTAT: description: Authentication Status Register. fields: diff --git a/base/MKL17Z644/MTBDWT.yaml b/head/MKL17Z644/MTBDWT.yaml index 6f023a1..e6e462e 100644 --- a/base/MKL17Z644/MTBDWT.yaml +++ b/head/MKL17Z644/MTBDWT.yaml @@ -6,24 +6,26 @@ block/MTBDWT: byte_offset: 0 access: Read fieldset: CTRL - - name: COMP + - name: COMP0 description: MTB_DWT Comparator Register. - array: - len: 2 - stride: 16 byte_offset: 32 fieldset: COMP - - name: MASK + - name: MASK0 description: MTB_DWT Comparator Mask Register. - array: - len: 2 - stride: 16 byte_offset: 36 fieldset: MASK - name: FCT0 description: MTB_DWT Comparator Function Register 0. byte_offset: 40 fieldset: FCT0 + - name: COMP1 + description: MTB_DWT Comparator Register. + byte_offset: 48 + fieldset: COMP + - name: MASK1 + description: MTB_DWT Comparator Mask Register. + byte_offset: 52 + fieldset: MASK - name: FCT1 description: MTB_DWT Comparator Function Register 1. byte_offset: 56 @@ -42,22 +44,66 @@ block/MTBDWT: byte_offset: 4044 access: Read fieldset: DEVICETYPID - - name: PERIPHID + - name: PERIPHID4 description: Peripheral ID Register. - array: - len: 8 - stride: 4 byte_offset: 4048 access: Read fieldset: PERIPHID - - name: COMPID + - name: PERIPHID5 + description: Peripheral ID Register. + byte_offset: 4052 + access: Read + fieldset: PERIPHID + - name: PERIPHID6 + description: Peripheral ID Register. + byte_offset: 4056 + access: Read + fieldset: PERIPHID + - name: PERIPHID7 + description: Peripheral ID Register. + byte_offset: 4060 + access: Read + fieldset: PERIPHID + - name: PERIPHID0 + description: Peripheral ID Register. + byte_offset: 4064 + access: Read + fieldset: PERIPHID + - name: PERIPHID1 + description: Peripheral ID Register. + byte_offset: 4068 + access: Read + fieldset: PERIPHID + - name: PERIPHID2 + description: Peripheral ID Register. + byte_offset: 4072 + access: Read + fieldset: PERIPHID + - name: PERIPHID3 + description: Peripheral ID Register. + byte_offset: 4076 + access: Read + fieldset: PERIPHID + - name: COMPID0 description: Component ID Register. - array: - len: 4 - stride: 4 byte_offset: 4080 access: Read fieldset: COMPID + - name: COMPID1 + description: Component ID Register. + byte_offset: 4084 + access: Read + fieldset: COMPID + - name: COMPID2 + description: Component ID Register. + byte_offset: 4088 + access: Read + fieldset: COMPID + - name: COMPID3 + description: Component ID Register. + byte_offset: 4092 + access: Read + fieldset: COMPID fieldset/COMP: description: MTB_DWT Comparator Register. fields: diff --git a/base/MKL17Z644/PIT.yaml b/head/MKL17Z644/PIT.yaml index 83cd531..f6904d2 100644 --- a/base/MKL17Z644/PIT.yaml +++ b/head/MKL17Z644/PIT.yaml @@ -15,35 +15,40 @@ block/PIT: byte_offset: 228 access: Read fieldset: LTMR64L - - name: LDVAL + - name: LDVAL0 description: Timer Load Value Register. - array: - len: 2 - stride: 16 byte_offset: 256 fieldset: LDVAL - - name: CVAL + - name: CVAL0 description: Current Timer Value Register. - array: - len: 2 - stride: 16 byte_offset: 260 access: Read fieldset: CVAL - - name: TCTRL + - name: TCTRL0 description: Timer Control Register. - array: - len: 2 - stride: 16 byte_offset: 264 fieldset: TCTRL - - name: TFLG + - name: TFLG0 description: Timer Flag Register. - array: - len: 2 - stride: 16 byte_offset: 268 fieldset: TFLG + - name: LDVAL1 + description: Timer Load Value Register. + byte_offset: 272 + fieldset: LDVAL + - name: CVAL1 + description: Current Timer Value Register. + byte_offset: 276 + access: Read + fieldset: CVAL + - name: TCTRL1 + description: Timer Control Register. + byte_offset: 280 + fieldset: TCTRL + - name: TFLG1 + description: Timer Flag Register. + byte_offset: 284 + fieldset: TFLG fieldset/CVAL: description: Current Timer Value Register. fields: diff --git a/base/MKL17Z644/RFSYS.yaml b/head/MKL17Z644/RFSYS.yaml index 4041816..7a4484b 100644 --- a/base/MKL17Z644/RFSYS.yaml +++ b/head/MKL17Z644/RFSYS.yaml @@ -1,13 +1,38 @@ block/RFSYS: description: System register file. items: - - name: REG + - name: REG0 description: Register file register. - array: - len: 8 - stride: 4 byte_offset: 0 fieldset: REG + - name: REG1 + description: Register file register. + byte_offset: 4 + fieldset: REG + - name: REG2 + description: Register file register. + byte_offset: 8 + fieldset: REG + - name: REG3 + description: Register file register. + byte_offset: 12 + fieldset: REG + - name: REG4 + description: Register file register. + byte_offset: 16 + fieldset: REG + - name: REG5 + description: Register file register. + byte_offset: 20 + fieldset: REG + - name: REG6 + description: Register file register. + byte_offset: 24 + fieldset: REG + - name: REG7 + description: Register file register. + byte_offset: 28 + fieldset: REG fieldset/REG: description: Register file register. fields: diff --git a/base/MKL17Z644/ROM.yaml b/head/MKL17Z644/ROM.yaml index 6da2ff9..deda379 100644 --- a/base/MKL17Z644/ROM.yaml +++ b/head/MKL17Z644/ROM.yaml @@ -1,14 +1,21 @@ block/ROM: description: System ROM. items: - - name: ENTRY + - name: ENTRY0 description: Entry. - array: - len: 3 - stride: 4 byte_offset: 0 access: Read fieldset: ENTRY + - name: ENTRY1 + description: Entry. + byte_offset: 4 + access: Read + fieldset: ENTRY + - name: ENTRY2 + description: Entry. + byte_offset: 8 + access: Read + fieldset: ENTRY - name: TABLEMARK description: End of Table Marker Register. byte_offset: 12 @@ -19,22 +26,66 @@ block/ROM: byte_offset: 4044 access: Read fieldset: SYSACCESS - - name: PERIPHID + - name: PERIPHID4 description: Peripheral ID Register. - array: - len: 8 - stride: 4 byte_offset: 4048 access: Read fieldset: PERIPHID - - name: COMPID + - name: PERIPHID5 + description: Peripheral ID Register. + byte_offset: 4052 + access: Read + fieldset: PERIPHID + - name: PERIPHID6 + description: Peripheral ID Register. + byte_offset: 4056 + access: Read + fieldset: PERIPHID + - name: PERIPHID7 + description: Peripheral ID Register. + byte_offset: 4060 + access: Read + fieldset: PERIPHID + - name: PERIPHID0 + description: Peripheral ID Register. + byte_offset: 4064 + access: Read + fieldset: PERIPHID + - name: PERIPHID1 + description: Peripheral ID Register. + byte_offset: 4068 + access: Read + fieldset: PERIPHID + - name: PERIPHID2 + description: Peripheral ID Register. + byte_offset: 4072 + access: Read + fieldset: PERIPHID + - name: PERIPHID3 + description: Peripheral ID Register. + byte_offset: 4076 + access: Read + fieldset: PERIPHID + - name: COMPID0 description: Component ID Register. - array: - len: 4 - stride: 4 byte_offset: 4080 access: Read fieldset: COMPID + - name: COMPID1 + description: Component ID Register. + byte_offset: 4084 + access: Read + fieldset: COMPID + - name: COMPID2 + description: Component ID Register. + byte_offset: 4088 + access: Read + fieldset: COMPID + - name: COMPID3 + description: Component ID Register. + byte_offset: 4092 + access: Read + fieldset: COMPID fieldset/COMPID: description: Component ID Register. fields: diff --git a/base/MKL17Z644/TPM0.yaml b/head/MKL17Z644/TPM0.yaml index a0d7c81..e83f72a 100644 --- a/base/MKL17Z644/TPM0.yaml +++ b/head/MKL17Z644/TPM0.yaml @@ -13,20 +13,54 @@ block/TPM0: description: Modulo. byte_offset: 8 fieldset: MOD - - name: CSC + - name: C0SC description: Channel (n) Status and Control. - array: - len: 6 - stride: 8 byte_offset: 12 fieldset: CSC - - name: CV + - name: C0V description: Channel (n) Value. - array: - len: 6 - stride: 8 byte_offset: 16 fieldset: CV + - name: C1SC + description: Channel (n) Status and Control. + byte_offset: 20 + fieldset: CSC + - name: C1V + description: Channel (n) Value. + byte_offset: 24 + fieldset: CV + - name: C2SC + description: Channel (n) Status and Control. + byte_offset: 28 + fieldset: CSC + - name: C2V + description: Channel (n) Value. + byte_offset: 32 + fieldset: CV + - name: C3SC + description: Channel (n) Status and Control. + byte_offset: 36 + fieldset: CSC + - name: C3V + description: Channel (n) Value. + byte_offset: 40 + fieldset: CV + - name: C4SC + description: Channel (n) Status and Control. + byte_offset: 44 + fieldset: CSC + - name: C4V + description: Channel (n) Value. + byte_offset: 48 + fieldset: CV + - name: C5SC + description: Channel (n) Status and Control. + byte_offset: 52 + fieldset: CSC + - name: C5V + description: Channel (n) Value. + byte_offset: 56 + fieldset: CV - name: STATUS description: Capture and Compare Status. byte_offset: 80 diff --git a/base/MKL17Z644/TPM1.yaml b/head/MKL17Z644/TPM1.yaml index 9c763de..d5212a1 100644 --- a/base/MKL17Z644/TPM1.yaml +++ b/head/MKL17Z644/TPM1.yaml @@ -13,20 +13,22 @@ block/TPM1: description: Modulo. byte_offset: 8 fieldset: MOD - - name: CSC + - name: C0SC description: Channel (n) Status and Control. - array: - len: 2 - stride: 8 byte_offset: 12 fieldset: CSC - - name: CV + - name: C0V description: Channel (n) Value. - array: - len: 2 - stride: 8 byte_offset: 16 fieldset: CV + - name: C1SC + description: Channel (n) Status and Control. + byte_offset: 20 + fieldset: CSC + - name: C1V + description: Channel (n) Value. + byte_offset: 24 + fieldset: CV - name: STATUS description: Capture and Compare Status. byte_offset: 80 diff --git a/base/MKL17Z644/TPM2.yaml b/head/MKL17Z644/TPM2.yaml index 6ebb768..517b444 100644 --- a/base/MKL17Z644/TPM2.yaml +++ b/head/MKL17Z644/TPM2.yaml @@ -13,20 +13,22 @@ block/TPM2: description: Modulo. byte_offset: 8 fieldset: MOD - - name: CSC + - name: C0SC description: Channel (n) Status and Control. - array: - len: 2 - stride: 8 byte_offset: 12 fieldset: CSC - - name: CV + - name: C0V description: Channel (n) Value. - array: - len: 2 - stride: 8 byte_offset: 16 fieldset: CV + - name: C1SC + description: Channel (n) Status and Control. + byte_offset: 20 + fieldset: CSC + - name: C1V + description: Channel (n) Value. + byte_offset: 24 + fieldset: CV - name: STATUS description: Capture and Compare Status. byte_offset: 80 diff --git a/base/MKW41Z4/ADC0.yaml b/head/MKW41Z4/ADC0.yaml index f810147..d911bc5 100644 --- a/base/MKW41Z4/ADC0.yaml +++ b/head/MKW41Z4/ADC0.yaml @@ -1,13 +1,14 @@ block/ADC0: description: Analog-to-Digital Converter. items: - - name: SC1 + - name: SC1A description: ADC Status and Control Registers 1. - array: - len: 2 - stride: 4 byte_offset: 0 fieldset: SC1 + - name: SC1B + description: ADC Status and Control Registers 1. + byte_offset: 4 + fieldset: SC1 - name: CFG1 description: ADC Configuration Register 1. byte_offset: 8 @@ -16,21 +17,24 @@ block/ADC0: description: ADC Configuration Register 2. byte_offset: 12 fieldset: CFG2 - - name: R + - name: RA description: ADC Data Result Register. - array: - len: 2 - stride: 4 byte_offset: 16 access: Read fieldset: R - - name: CV + - name: RB + description: ADC Data Result Register. + byte_offset: 20 + access: Read + fieldset: R + - name: CV1 description: Compare Value Registers. - array: - len: 2 - stride: 4 byte_offset: 24 fieldset: CV + - name: CV2 + description: Compare Value Registers. + byte_offset: 28 + fieldset: CV - name: SC2 description: Status and Control Register 2. byte_offset: 32 diff --git a/base/MKW41Z4/DAC0.yaml b/head/MKW41Z4/DAC0.yaml index 8ff9c09..c0d9be1 100644 --- a/base/MKW41Z4/DAC0.yaml +++ b/head/MKW41Z4/DAC0.yaml @@ -1,22 +1,26 @@ block/DAC0: description: 12-Bit Digital-to-Analog Converter. items: - - name: DATL + - name: DAT0L description: DAC Data Low Register. - array: - len: 2 - stride: 2 byte_offset: 0 bit_size: 8 fieldset: DATL - - name: DATH + - name: DAT0H description: DAC Data High Register. - array: - len: 2 - stride: 2 byte_offset: 1 bit_size: 8 fieldset: DATH + - name: DAT1L + description: DAC Data Low Register. + byte_offset: 2 + bit_size: 8 + fieldset: DATL + - name: DAT1H + description: DAC Data High Register. + byte_offset: 3 + bit_size: 8 + fieldset: DATH - name: SR description: DAC Status Register. byte_offset: 32 diff --git a/base/MKW41Z4/DMA.yaml b/head/MKW41Z4/DMA.yaml index 66954da..1dd688a 100644 --- a/base/MKW41Z4/DMA.yaml +++ b/head/MKW41Z4/DMA.yaml @@ -83,127 +83,298 @@ block/DMA: description: Enable Asynchronous Request in Stop Register. byte_offset: 68 fieldset: EARS - - name: DCHPRI + - name: DCHPRI3 description: Channel n Priority Register. - array: - len: 4 - stride: 1 byte_offset: 256 bit_size: 8 fieldset: DCHPRI - - name: TCD_SADDR + - name: DCHPRI2 + description: Channel n Priority Register. + byte_offset: 257 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI1 + description: Channel n Priority Register. + byte_offset: 258 + bit_size: 8 + fieldset: DCHPRI + - name: DCHPRI0 + description: Channel n Priority Register. + byte_offset: 259 + bit_size: 8 + fieldset: DCHPRI + - name: TCD0_SADDR description: TCD Source Address. - array: - len: 4 - stride: 32 byte_offset: 4096 fieldset: TCD_SADDR - - name: TCD_SOFF + - name: TCD0_SOFF description: TCD Signed Source Address Offset. - array: - len: 4 - stride: 32 byte_offset: 4100 bit_size: 16 fieldset: TCD_SOFF - - name: TCD_ATTR + - name: TCD0_ATTR description: TCD Transfer Attributes. - array: - len: 4 - stride: 32 byte_offset: 4102 bit_size: 16 fieldset: TCD_ATTR - - name: TCD_NBYTES_MLNO + - name: TCD0_NBYTES_MLNO description: TCD Minor Byte Count (Minor Loop Mapping Disabled). - array: - len: 4 - stride: 32 byte_offset: 4104 fieldset: TCD_NBYTES_MLNO - - name: TCD_NBYTES_MLOFFNO + - name: TCD0_NBYTES_MLOFFNO description: TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled). - array: - len: 4 - stride: 32 byte_offset: 4104 fieldset: TCD_NBYTES_MLOFFNO - - name: TCD_NBYTES_MLOFFYES + - name: TCD0_NBYTES_MLOFFYES description: TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled). - array: - len: 4 - stride: 32 byte_offset: 4104 fieldset: TCD_NBYTES_MLOFFYES - - name: TCD_SLAST + - name: TCD0_SLAST description: TCD Last Source Address Adjustment. - array: - len: 4 - stride: 32 byte_offset: 4108 fieldset: TCD_SLAST - - name: TCD_DADDR + - name: TCD0_DADDR description: TCD Destination Address. - array: - len: 4 - stride: 32 byte_offset: 4112 fieldset: TCD_DADDR - - name: TCD_DOFF + - name: TCD0_DOFF description: TCD Signed Destination Address Offset. - array: - len: 4 - stride: 32 byte_offset: 4116 bit_size: 16 fieldset: TCD_DOFF - - name: TCD_CITER_ELINKNO + - name: TCD0_CITER_ELINKNO description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). - array: - len: 4 - stride: 32 byte_offset: 4118 bit_size: 16 fieldset: TCD_CITER_ELINKNO - - name: TCD_CITER_ELINKYES + - name: TCD0_CITER_ELINKYES description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). - array: - len: 4 - stride: 32 byte_offset: 4118 bit_size: 16 fieldset: TCD_CITER_ELINKYES - - name: TCD_DLASTSGA + - name: TCD0_DLASTSGA description: TCD Last Destination Address Adjustment/Scatter Gather Address. - array: - len: 4 - stride: 32 byte_offset: 4120 fieldset: TCD_DLASTSGA - - name: TCD_CSR + - name: TCD0_CSR description: TCD Control and Status. - array: - len: 4 - stride: 32 byte_offset: 4124 bit_size: 16 fieldset: TCD_CSR - - name: TCD_BITER_ELINKNO + - name: TCD0_BITER_ELINKNO description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). - array: - len: 4 - stride: 32 byte_offset: 4126 bit_size: 16 fieldset: TCD_BITER_ELINKNO - - name: TCD_BITER_ELINKYES + - name: TCD0_BITER_ELINKYES description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). - array: - len: 4 - stride: 32 byte_offset: 4126 bit_size: 16 fieldset: TCD_BITER_ELINKYES + - name: TCD1_SADDR + description: TCD Source Address. + byte_offset: 4128 + fieldset: TCD_SADDR + - name: TCD1_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4132 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD1_ATTR + description: TCD Transfer Attributes. + byte_offset: 4134 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD1_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Mapping Disabled). + byte_offset: 4136 + fieldset: TCD_NBYTES_MLNO + - name: TCD1_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled). + byte_offset: 4136 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD1_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled). + byte_offset: 4136 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD1_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4140 + fieldset: TCD_SLAST + - name: TCD1_DADDR + description: TCD Destination Address. + byte_offset: 4144 + fieldset: TCD_DADDR + - name: TCD1_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4148 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD1_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4150 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD1_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4150 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD1_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4152 + fieldset: TCD_DLASTSGA + - name: TCD1_CSR + description: TCD Control and Status. + byte_offset: 4156 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD1_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4158 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD1_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4158 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD2_SADDR + description: TCD Source Address. + byte_offset: 4160 + fieldset: TCD_SADDR + - name: TCD2_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4164 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD2_ATTR + description: TCD Transfer Attributes. + byte_offset: 4166 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD2_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Mapping Disabled). + byte_offset: 4168 + fieldset: TCD_NBYTES_MLNO + - name: TCD2_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled). + byte_offset: 4168 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD2_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled). + byte_offset: 4168 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD2_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4172 + fieldset: TCD_SLAST + - name: TCD2_DADDR + description: TCD Destination Address. + byte_offset: 4176 + fieldset: TCD_DADDR + - name: TCD2_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4180 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD2_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4182 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD2_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4182 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD2_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4184 + fieldset: TCD_DLASTSGA + - name: TCD2_CSR + description: TCD Control and Status. + byte_offset: 4188 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD2_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4190 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD2_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4190 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES + - name: TCD3_SADDR + description: TCD Source Address. + byte_offset: 4192 + fieldset: TCD_SADDR + - name: TCD3_SOFF + description: TCD Signed Source Address Offset. + byte_offset: 4196 + bit_size: 16 + fieldset: TCD_SOFF + - name: TCD3_ATTR + description: TCD Transfer Attributes. + byte_offset: 4198 + bit_size: 16 + fieldset: TCD_ATTR + - name: TCD3_NBYTES_MLNO + description: TCD Minor Byte Count (Minor Loop Mapping Disabled). + byte_offset: 4200 + fieldset: TCD_NBYTES_MLNO + - name: TCD3_NBYTES_MLOFFNO + description: TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled). + byte_offset: 4200 + fieldset: TCD_NBYTES_MLOFFNO + - name: TCD3_NBYTES_MLOFFYES + description: TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled). + byte_offset: 4200 + fieldset: TCD_NBYTES_MLOFFYES + - name: TCD3_SLAST + description: TCD Last Source Address Adjustment. + byte_offset: 4204 + fieldset: TCD_SLAST + - name: TCD3_DADDR + description: TCD Destination Address. + byte_offset: 4208 + fieldset: TCD_DADDR + - name: TCD3_DOFF + description: TCD Signed Destination Address Offset. + byte_offset: 4212 + bit_size: 16 + fieldset: TCD_DOFF + - name: TCD3_CITER_ELINKNO + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4214 + bit_size: 16 + fieldset: TCD_CITER_ELINKNO + - name: TCD3_CITER_ELINKYES + description: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4214 + bit_size: 16 + fieldset: TCD_CITER_ELINKYES + - name: TCD3_DLASTSGA + description: TCD Last Destination Address Adjustment/Scatter Gather Address. + byte_offset: 4216 + fieldset: TCD_DLASTSGA + - name: TCD3_CSR + description: TCD Control and Status. + byte_offset: 4220 + bit_size: 16 + fieldset: TCD_CSR + - name: TCD3_BITER_ELINKNO + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled). + byte_offset: 4222 + bit_size: 16 + fieldset: TCD_BITER_ELINKNO + - name: TCD3_BITER_ELINKYES + description: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled). + byte_offset: 4222 + bit_size: 16 + fieldset: TCD_BITER_ELINKYES fieldset/CDNE: description: Clear DONE Status Bit Register. bit_size: 8 diff --git a/base/MKW41Z4/DMAMUX0.yaml b/head/MKW41Z4/DMAMUX0.yaml index ea064f6..b369bbc 100644 --- a/base/MKW41Z4/DMAMUX0.yaml +++ b/head/MKW41Z4/DMAMUX0.yaml @@ -1,14 +1,26 @@ block/DMAMUX0: description: DMA channel multiplexor. items: - - name: CHCFG + - name: CHCFG0 description: Channel Configuration register. - array: - len: 4 - stride: 1 byte_offset: 0 bit_size: 8 fieldset: CHCFG + - name: CHCFG1 + description: Channel Configuration register. + byte_offset: 1 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG2 + description: Channel Configuration register. + byte_offset: 2 + bit_size: 8 + fieldset: CHCFG + - name: CHCFG3 + description: Channel Configuration register. + byte_offset: 3 + bit_size: 8 + fieldset: CHCFG fieldset/CHCFG: description: Channel Configuration register. bit_size: 8 diff --git a/base/MKW41Z4/FTFA.yaml b/head/MKW41Z4/FTFA.yaml index f3b597e..a67a437 100644 --- a/base/MKW41Z4/FTFA.yaml +++ b/head/MKW41Z4/FTFA.yaml @@ -23,40 +23,182 @@ block/FTFA: access: Read bit_size: 8 fieldset: FOPT - - name: FCCOB + - name: FCCOB3 description: Flash Common Command Object Registers. - array: - len: 12 - stride: 1 byte_offset: 4 bit_size: 8 fieldset: FCCOB - - name: FPROT + - name: FCCOB2 + description: Flash Common Command Object Registers. + byte_offset: 5 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB1 + description: Flash Common Command Object Registers. + byte_offset: 6 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB0 + description: Flash Common Command Object Registers. + byte_offset: 7 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB7 + description: Flash Common Command Object Registers. + byte_offset: 8 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB6 + description: Flash Common Command Object Registers. + byte_offset: 9 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB5 + description: Flash Common Command Object Registers. + byte_offset: 10 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB4 + description: Flash Common Command Object Registers. + byte_offset: 11 + bit_size: 8 + fieldset: FCCOB + - name: FCCOBB + description: Flash Common Command Object Registers. + byte_offset: 12 + bit_size: 8 + fieldset: FCCOB + - name: FCCOBA + description: Flash Common Command Object Registers. + byte_offset: 13 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB9 + description: Flash Common Command Object Registers. + byte_offset: 14 + bit_size: 8 + fieldset: FCCOB + - name: FCCOB8 + description: Flash Common Command Object Registers. + byte_offset: 15 + bit_size: 8 + fieldset: FCCOB + - name: FPROT3 description: Program Flash Protection Registers. - array: - len: 4 - stride: 1 byte_offset: 16 bit_size: 8 fieldset: FPROT - - name: XACC + - name: FPROT2 + description: Program Flash Protection Registers. + byte_offset: 17 + bit_size: 8 + fieldset: FPROT + - name: FPROT1 + description: Program Flash Protection Registers. + byte_offset: 18 + bit_size: 8 + fieldset: FPROT + - name: FPROT0 + description: Program Flash Protection Registers. + byte_offset: 19 + bit_size: 8 + fieldset: FPROT + - name: XACCH3 description: Execute-only Access Registers. - array: - len: 8 - stride: 1 byte_offset: 24 access: Read bit_size: 8 fieldset: XACC - - name: SACC + - name: XACCH2 + description: Execute-only Access Registers. + byte_offset: 25 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCH1 + description: Execute-only Access Registers. + byte_offset: 26 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCH0 + description: Execute-only Access Registers. + byte_offset: 27 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCL3 + description: Execute-only Access Registers. + byte_offset: 28 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCL2 + description: Execute-only Access Registers. + byte_offset: 29 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCL1 + description: Execute-only Access Registers. + byte_offset: 30 + access: Read + bit_size: 8 + fieldset: XACC + - name: XACCL0 + description: Execute-only Access Registers. + byte_offset: 31 + access: Read + bit_size: 8 + fieldset: XACC + - name: SACCH3 description: Supervisor-only Access Registers. - array: - len: 8 - stride: 1 byte_offset: 32 access: Read bit_size: 8 fieldset: SACC + - name: SACCH2 + description: Supervisor-only Access Registers. + byte_offset: 33 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCH1 + description: Supervisor-only Access Registers. + byte_offset: 34 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCH0 + description: Supervisor-only Access Registers. + byte_offset: 35 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCL3 + description: Supervisor-only Access Registers. + byte_offset: 36 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCL2 + description: Supervisor-only Access Registers. + byte_offset: 37 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCL1 + description: Supervisor-only Access Registers. + byte_offset: 38 + access: Read + bit_size: 8 + fieldset: SACC + - name: SACCL0 + description: Supervisor-only Access Registers. + byte_offset: 39 + access: Read + bit_size: 8 + fieldset: SACC - name: FACSS description: Flash Access Segment Size Register. byte_offset: 40 diff --git a/base/MKW41Z4/MTB.yaml b/head/MKW41Z4/MTB.yaml index 6467743..c67d5e8 100644 --- a/base/MKW41Z4/MTB.yaml +++ b/head/MKW41Z4/MTB.yaml @@ -63,22 +63,66 @@ block/MTB: byte_offset: 4044 access: Read fieldset: DEVICETYPID - - name: PERIPHID + - name: PERIPHID4 description: Peripheral ID Register. - array: - len: 8 - stride: 4 byte_offset: 4048 access: Read fieldset: PERIPHID - - name: COMPID + - name: PERIPHID5 + description: Peripheral ID Register. + byte_offset: 4052 + access: Read + fieldset: PERIPHID + - name: PERIPHID6 + description: Peripheral ID Register. + byte_offset: 4056 + access: Read + fieldset: PERIPHID + - name: PERIPHID7 + description: Peripheral ID Register. + byte_offset: 4060 + access: Read + fieldset: PERIPHID + - name: PERIPHID0 + description: Peripheral ID Register. + byte_offset: 4064 + access: Read + fieldset: PERIPHID + - name: PERIPHID1 + description: Peripheral ID Register. + byte_offset: 4068 + access: Read + fieldset: PERIPHID + - name: PERIPHID2 + description: Peripheral ID Register. + byte_offset: 4072 + access: Read + fieldset: PERIPHID + - name: PERIPHID3 + description: Peripheral ID Register. + byte_offset: 4076 + access: Read + fieldset: PERIPHID + - name: COMPID0 description: Component ID Register. - array: - len: 4 - stride: 4 byte_offset: 4080 access: Read fieldset: COMPID + - name: COMPID1 + description: Component ID Register. + byte_offset: 4084 + access: Read + fieldset: COMPID + - name: COMPID2 + description: Component ID Register. + byte_offset: 4088 + access: Read + fieldset: COMPID + - name: COMPID3 + description: Component ID Register. + byte_offset: 4092 + access: Read + fieldset: COMPID fieldset/AUTHSTAT: description: Authentication Status Register. fields: diff --git a/base/MKW41Z4/MTBDWT.yaml b/head/MKW41Z4/MTBDWT.yaml index 6f023a1..e6e462e 100644 --- a/base/MKW41Z4/MTBDWT.yaml +++ b/head/MKW41Z4/MTBDWT.yaml @@ -6,24 +6,26 @@ block/MTBDWT: byte_offset: 0 access: Read fieldset: CTRL - - name: COMP + - name: COMP0 description: MTB_DWT Comparator Register. - array: - len: 2 - stride: 16 byte_offset: 32 fieldset: COMP - - name: MASK + - name: MASK0 description: MTB_DWT Comparator Mask Register. - array: - len: 2 - stride: 16 byte_offset: 36 fieldset: MASK - name: FCT0 description: MTB_DWT Comparator Function Register 0. byte_offset: 40 fieldset: FCT0 + - name: COMP1 + description: MTB_DWT Comparator Register. + byte_offset: 48 + fieldset: COMP + - name: MASK1 + description: MTB_DWT Comparator Mask Register. + byte_offset: 52 + fieldset: MASK - name: FCT1 description: MTB_DWT Comparator Function Register 1. byte_offset: 56 @@ -42,22 +44,66 @@ block/MTBDWT: byte_offset: 4044 access: Read fieldset: DEVICETYPID - - name: PERIPHID + - name: PERIPHID4 description: Peripheral ID Register. - array: - len: 8 - stride: 4 byte_offset: 4048 access: Read fieldset: PERIPHID - - name: COMPID + - name: PERIPHID5 + description: Peripheral ID Register. + byte_offset: 4052 + access: Read + fieldset: PERIPHID + - name: PERIPHID6 + description: Peripheral ID Register. + byte_offset: 4056 + access: Read + fieldset: PERIPHID + - name: PERIPHID7 + description: Peripheral ID Register. + byte_offset: 4060 + access: Read + fieldset: PERIPHID + - name: PERIPHID0 + description: Peripheral ID Register. + byte_offset: 4064 + access: Read + fieldset: PERIPHID + - name: PERIPHID1 + description: Peripheral ID Register. + byte_offset: 4068 + access: Read + fieldset: PERIPHID + - name: PERIPHID2 + description: Peripheral ID Register. + byte_offset: 4072 + access: Read + fieldset: PERIPHID + - name: PERIPHID3 + description: Peripheral ID Register. + byte_offset: 4076 + access: Read + fieldset: PERIPHID + - name: COMPID0 description: Component ID Register. - array: - len: 4 - stride: 4 byte_offset: 4080 access: Read fieldset: COMPID + - name: COMPID1 + description: Component ID Register. + byte_offset: 4084 + access: Read + fieldset: COMPID + - name: COMPID2 + description: Component ID Register. + byte_offset: 4088 + access: Read + fieldset: COMPID + - name: COMPID3 + description: Component ID Register. + byte_offset: 4092 + access: Read + fieldset: COMPID fieldset/COMP: description: MTB_DWT Comparator Register. fields: diff --git a/base/MKW41Z4/PIT.yaml b/head/MKW41Z4/PIT.yaml index 83cd531..f6904d2 100644 --- a/base/MKW41Z4/PIT.yaml +++ b/head/MKW41Z4/PIT.yaml @@ -15,35 +15,40 @@ block/PIT: byte_offset: 228 access: Read fieldset: LTMR64L - - name: LDVAL + - name: LDVAL0 description: Timer Load Value Register. - array: - len: 2 - stride: 16 byte_offset: 256 fieldset: LDVAL - - name: CVAL + - name: CVAL0 description: Current Timer Value Register. - array: - len: 2 - stride: 16 byte_offset: 260 access: Read fieldset: CVAL - - name: TCTRL + - name: TCTRL0 description: Timer Control Register. - array: - len: 2 - stride: 16 byte_offset: 264 fieldset: TCTRL - - name: TFLG + - name: TFLG0 description: Timer Flag Register. - array: - len: 2 - stride: 16 byte_offset: 268 fieldset: TFLG + - name: LDVAL1 + description: Timer Load Value Register. + byte_offset: 272 + fieldset: LDVAL + - name: CVAL1 + description: Current Timer Value Register. + byte_offset: 276 + access: Read + fieldset: CVAL + - name: TCTRL1 + description: Timer Control Register. + byte_offset: 280 + fieldset: TCTRL + - name: TFLG1 + description: Timer Flag Register. + byte_offset: 284 + fieldset: TFLG fieldset/CVAL: description: Current Timer Value Register. fields: diff --git a/base/MKW41Z4/RFSYS.yaml b/head/MKW41Z4/RFSYS.yaml index 4041816..7a4484b 100644 --- a/base/MKW41Z4/RFSYS.yaml +++ b/head/MKW41Z4/RFSYS.yaml @@ -1,13 +1,38 @@ block/RFSYS: description: System register file. items: - - name: REG + - name: REG0 description: Register file register. - array: - len: 8 - stride: 4 byte_offset: 0 fieldset: REG + - name: REG1 + description: Register file register. + byte_offset: 4 + fieldset: REG + - name: REG2 + description: Register file register. + byte_offset: 8 + fieldset: REG + - name: REG3 + description: Register file register. + byte_offset: 12 + fieldset: REG + - name: REG4 + description: Register file register. + byte_offset: 16 + fieldset: REG + - name: REG5 + description: Register file register. + byte_offset: 20 + fieldset: REG + - name: REG6 + description: Register file register. + byte_offset: 24 + fieldset: REG + - name: REG7 + description: Register file register. + byte_offset: 28 + fieldset: REG fieldset/REG: description: Register file register. fields: diff --git a/base/MKW41Z4/ROM.yaml b/head/MKW41Z4/ROM.yaml index 6da2ff9..deda379 100644 --- a/base/MKW41Z4/ROM.yaml +++ b/head/MKW41Z4/ROM.yaml @@ -1,14 +1,21 @@ block/ROM: description: System ROM. items: - - name: ENTRY + - name: ENTRY0 description: Entry. - array: - len: 3 - stride: 4 byte_offset: 0 access: Read fieldset: ENTRY + - name: ENTRY1 + description: Entry. + byte_offset: 4 + access: Read + fieldset: ENTRY + - name: ENTRY2 + description: Entry. + byte_offset: 8 + access: Read + fieldset: ENTRY - name: TABLEMARK description: End of Table Marker Register. byte_offset: 12 @@ -19,22 +26,66 @@ block/ROM: byte_offset: 4044 access: Read fieldset: SYSACCESS - - name: PERIPHID + - name: PERIPHID4 description: Peripheral ID Register. - array: - len: 8 - stride: 4 byte_offset: 4048 access: Read fieldset: PERIPHID - - name: COMPID + - name: PERIPHID5 + description: Peripheral ID Register. + byte_offset: 4052 + access: Read + fieldset: PERIPHID + - name: PERIPHID6 + description: Peripheral ID Register. + byte_offset: 4056 + access: Read + fieldset: PERIPHID + - name: PERIPHID7 + description: Peripheral ID Register. + byte_offset: 4060 + access: Read + fieldset: PERIPHID + - name: PERIPHID0 + description: Peripheral ID Register. + byte_offset: 4064 + access: Read + fieldset: PERIPHID + - name: PERIPHID1 + description: Peripheral ID Register. + byte_offset: 4068 + access: Read + fieldset: PERIPHID + - name: PERIPHID2 + description: Peripheral ID Register. + byte_offset: 4072 + access: Read + fieldset: PERIPHID + - name: PERIPHID3 + description: Peripheral ID Register. + byte_offset: 4076 + access: Read + fieldset: PERIPHID + - name: COMPID0 description: Component ID Register. - array: - len: 4 - stride: 4 byte_offset: 4080 access: Read fieldset: COMPID + - name: COMPID1 + description: Component ID Register. + byte_offset: 4084 + access: Read + fieldset: COMPID + - name: COMPID2 + description: Component ID Register. + byte_offset: 4088 + access: Read + fieldset: COMPID + - name: COMPID3 + description: Component ID Register. + byte_offset: 4092 + access: Read + fieldset: COMPID fieldset/COMPID: description: Component ID Register. fields: diff --git a/base/MKW41Z4/SPI0.yaml b/head/MKW41Z4/SPI0.yaml index afeb903..1f483a1 100644 --- a/base/MKW41Z4/SPI0.yaml +++ b/head/MKW41Z4/SPI0.yaml @@ -9,17 +9,18 @@ block/SPI0: description: Transfer Count Register. byte_offset: 8 fieldset: TCR - - name: CTAR + - name: CTAR0 description: Clock and Transfer Attributes Register (In Master Mode). - array: - len: 2 - stride: 4 byte_offset: 12 fieldset: CTAR - name: CTAR_SLAVE description: Clock and Transfer Attributes Register (In Slave Mode). byte_offset: 12 fieldset: CTAR_SLAVE + - name: CTAR1 + description: Clock and Transfer Attributes Register (In Master Mode). + byte_offset: 16 + fieldset: CTAR - name: SR description: Status Register. byte_offset: 44 @@ -41,22 +42,46 @@ block/SPI0: byte_offset: 56 access: Read fieldset: POPR - - name: TXFR + - name: TXFR0 description: Transmit FIFO Registers. - array: - len: 4 - stride: 4 byte_offset: 60 access: Read fieldset: TXFR - - name: RXFR + - name: TXFR1 + description: Transmit FIFO Registers. + byte_offset: 64 + access: Read + fieldset: TXFR + - name: TXFR2 + description: Transmit FIFO Registers. + byte_offset: 68 + access: Read + fieldset: TXFR + - name: TXFR3 + description: Transmit FIFO Registers. + byte_offset: 72 + access: Read + fieldset: TXFR + - name: RXFR0 description: Receive FIFO Registers. - array: - len: 4 - stride: 4 byte_offset: 124 access: Read fieldset: RXFR + - name: RXFR1 + description: Receive FIFO Registers. + byte_offset: 128 + access: Read + fieldset: RXFR + - name: RXFR2 + description: Receive FIFO Registers. + byte_offset: 132 + access: Read + fieldset: RXFR + - name: RXFR3 + description: Receive FIFO Registers. + byte_offset: 136 + access: Read + fieldset: RXFR fieldset/CTAR: description: Clock and Transfer Attributes Register (In Master Mode). fields: diff --git a/base/MKW41Z4/SPI1.yaml b/head/MKW41Z4/SPI1.yaml index 28c341f..502e58d 100644 --- a/base/MKW41Z4/SPI1.yaml +++ b/head/MKW41Z4/SPI1.yaml @@ -9,17 +9,18 @@ block/SPI1: description: Transfer Count Register. byte_offset: 8 fieldset: TCR - - name: CTAR + - name: CTAR0 description: Clock and Transfer Attributes Register (In Master Mode). - array: - len: 2 - stride: 4 byte_offset: 12 fieldset: CTAR - name: CTAR_SLAVE description: Clock and Transfer Attributes Register (In Slave Mode). byte_offset: 12 fieldset: CTAR_SLAVE + - name: CTAR1 + description: Clock and Transfer Attributes Register (In Master Mode). + byte_offset: 16 + fieldset: CTAR - name: SR description: Status Register. byte_offset: 44 @@ -41,22 +42,46 @@ block/SPI1: byte_offset: 56 access: Read fieldset: POPR - - name: TXFR + - name: TXFR0 description: Transmit FIFO Registers. - array: - len: 4 - stride: 4 byte_offset: 60 access: Read fieldset: TXFR - - name: RXFR + - name: TXFR1 + description: Transmit FIFO Registers. + byte_offset: 64 + access: Read + fieldset: TXFR + - name: TXFR2 + description: Transmit FIFO Registers. + byte_offset: 68 + access: Read + fieldset: TXFR + - name: TXFR3 + description: Transmit FIFO Registers. + byte_offset: 72 + access: Read + fieldset: TXFR + - name: RXFR0 description: Receive FIFO Registers. - array: - len: 4 - stride: 4 byte_offset: 124 access: Read fieldset: RXFR + - name: RXFR1 + description: Receive FIFO Registers. + byte_offset: 128 + access: Read + fieldset: RXFR + - name: RXFR2 + description: Receive FIFO Registers. + byte_offset: 132 + access: Read + fieldset: RXFR + - name: RXFR3 + description: Receive FIFO Registers. + byte_offset: 136 + access: Read + fieldset: RXFR fieldset/CTAR: description: Clock and Transfer Attributes Register (In Master Mode). fields: diff --git a/base/MKW41Z4/TPM0.yaml b/head/MKW41Z4/TPM0.yaml index 407b928..3330aa0 100644 --- a/base/MKW41Z4/TPM0.yaml +++ b/head/MKW41Z4/TPM0.yaml @@ -13,20 +13,38 @@ block/TPM0: description: Modulo. byte_offset: 8 fieldset: MOD - - name: CSC + - name: C0SC description: Channel (n) Status and Control. - array: - len: 4 - stride: 8 byte_offset: 12 fieldset: CSC - - name: CV + - name: C0V description: Channel (n) Value. - array: - len: 4 - stride: 8 byte_offset: 16 fieldset: CV + - name: C1SC + description: Channel (n) Status and Control. + byte_offset: 20 + fieldset: CSC + - name: C1V + description: Channel (n) Value. + byte_offset: 24 + fieldset: CV + - name: C2SC + description: Channel (n) Status and Control. + byte_offset: 28 + fieldset: CSC + - name: C2V + description: Channel (n) Value. + byte_offset: 32 + fieldset: CV + - name: C3SC + description: Channel (n) Status and Control. + byte_offset: 36 + fieldset: CSC + - name: C3V + description: Channel (n) Value. + byte_offset: 40 + fieldset: CV - name: STATUS description: Capture and Compare Status. byte_offset: 80 diff --git a/base/MKW41Z4/TPM1.yaml b/head/MKW41Z4/TPM1.yaml index 9112b67..ed67fa0 100644 --- a/base/MKW41Z4/TPM1.yaml +++ b/head/MKW41Z4/TPM1.yaml @@ -13,20 +13,22 @@ block/TPM1: description: Modulo. byte_offset: 8 fieldset: MOD - - name: CSC + - name: C0SC description: Channel (n) Status and Control. - array: - len: 2 - stride: 8 byte_offset: 12 fieldset: CSC - - name: CV + - name: C0V description: Channel (n) Value. - array: - len: 2 - stride: 8 byte_offset: 16 fieldset: CV + - name: C1SC + description: Channel (n) Status and Control. + byte_offset: 20 + fieldset: CSC + - name: C1V + description: Channel (n) Value. + byte_offset: 24 + fieldset: CV - name: STATUS description: Capture and Compare Status. byte_offset: 80 diff --git a/base/MKW41Z4/TPM2.yaml b/head/MKW41Z4/TPM2.yaml index 470846a..3855dcb 100644 --- a/base/MKW41Z4/TPM2.yaml +++ b/head/MKW41Z4/TPM2.yaml @@ -13,20 +13,22 @@ block/TPM2: description: Modulo. byte_offset: 8 fieldset: MOD - - name: CSC + - name: C0SC description: Channel (n) Status and Control. - array: - len: 2 - stride: 8 byte_offset: 12 fieldset: CSC - - name: CV + - name: C0V description: Channel (n) Value. - array: - len: 2 - stride: 8 byte_offset: 16 fieldset: CV + - name: C1SC + description: Channel (n) Status and Control. + byte_offset: 20 + fieldset: CSC + - name: C1V + description: Channel (n) Value. + byte_offset: 24 + fieldset: CV - name: STATUS description: Capture and Compare Status. byte_offset: 80 diff --git a/base/STM32C011/ADC.yaml b/head/STM32C011/ADC.yaml index d04d261..8a8cd25 100644 --- a/base/STM32C011/ADC.yaml +++ b/head/STM32C011/ADC.yaml @@ -79,13 +79,120 @@ fieldset/AWD1TR: fieldset/AWD2CR: description: ADC Analog Watchdog 2 Configuration register. fields: - - name: AWD2CH + - name: AWD2CH0 description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 0 bit_size: 1 - array: - len: 23 - stride: 1 + enum: AWD2CH + - name: AWD2CH1 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 1 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH2 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 2 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH3 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 3 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH4 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 4 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH5 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 5 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH6 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 6 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH7 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 7 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH8 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 8 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH9 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 9 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH10 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 10 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH11 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 11 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH12 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 12 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH13 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 13 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH14 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 14 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH15 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 15 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH16 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 16 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH17 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 17 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH18 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 18 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH19 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 19 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH20 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 20 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH21 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 21 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH22 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' + bit_offset: 22 + bit_size: 1 enum: AWD2CH fieldset/AWD2TR: description: ADC watchdog threshold register. @@ -101,13 +208,120 @@ fieldset/AWD2TR: fieldset/AWD3CR: description: ADC Analog Watchdog 3 Configuration register. fields: - - name: AWD3CH + - name: AWD3CH0 description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' bit_offset: 0 bit_size: 1 - array: - len: 23 - stride: 1 + enum: AWD3CH + - name: AWD3CH1 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 1 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH2 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 2 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH3 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 3 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH4 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 4 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH5 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 5 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH6 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 6 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH7 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 7 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH8 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 8 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH9 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 9 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH10 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 10 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH11 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 11 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH12 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 12 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH13 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 13 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH14 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 14 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH15 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 15 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH16 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 16 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH17 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 17 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH18 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 18 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH19 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 19 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH20 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 20 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH21 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 21 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH22 + description: 'Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).' + bit_offset: 22 + bit_size: 1 enum: AWD3CH fieldset/AWD3TR: description: ADC watchdog threshold register. @@ -263,24 +477,163 @@ fieldset/CFGR2: fieldset/CHSELR0: description: ADC channel selection register [alternate]. fields: - - name: CHSEL + - name: CHSEL0 description: Channel-%s selection. bit_offset: 0 bit_size: 1 - array: - len: 23 - stride: 1 + enum: CHSEL + - name: CHSEL1 + description: Channel-%s selection. + bit_offset: 1 + bit_size: 1 + enum: CHSEL + - name: CHSEL2 + description: Channel-%s selection. + bit_offset: 2 + bit_size: 1 + enum: CHSEL + - name: CHSEL3 + description: Channel-%s selection. + bit_offset: 3 + bit_size: 1 + enum: CHSEL + - name: CHSEL4 + description: Channel-%s selection. + bit_offset: 4 + bit_size: 1 + enum: CHSEL + - name: CHSEL5 + description: Channel-%s selection. + bit_offset: 5 + bit_size: 1 + enum: CHSEL + - name: CHSEL6 + description: Channel-%s selection. + bit_offset: 6 + bit_size: 1 + enum: CHSEL + - name: CHSEL7 + description: Channel-%s selection. + bit_offset: 7 + bit_size: 1 + enum: CHSEL + - name: CHSEL8 + description: Channel-%s selection. + bit_offset: 8 + bit_size: 1 + enum: CHSEL + - name: CHSEL9 + description: Channel-%s selection. + bit_offset: 9 + bit_size: 1 + enum: CHSEL + - name: CHSEL10 + description: Channel-%s selection. + bit_offset: 10 + bit_size: 1 + enum: CHSEL + - name: CHSEL11 + description: Channel-%s selection. + bit_offset: 11 + bit_size: 1 + enum: CHSEL + - name: CHSEL12 + description: Channel-%s selection. + bit_offset: 12 + bit_size: 1 + enum: CHSEL + - name: CHSEL13 + description: Channel-%s selection. + bit_offset: 13 + bit_size: 1 + enum: CHSEL + - name: CHSEL14 + description: Channel-%s selection. + bit_offset: 14 + bit_size: 1 + enum: CHSEL + - name: CHSEL15 + description: Channel-%s selection. + bit_offset: 15 + bit_size: 1 + enum: CHSEL + - name: CHSEL16 + description: Channel-%s selection. + bit_offset: 16 + bit_size: 1 + enum: CHSEL + - name: CHSEL17 + description: Channel-%s selection. + bit_offset: 17 + bit_size: 1 + enum: CHSEL + - name: CHSEL18 + description: Channel-%s selection. + bit_offset: 18 + bit_size: 1 + enum: CHSEL + - name: CHSEL19 + description: Channel-%s selection. + bit_offset: 19 + bit_size: 1 + enum: CHSEL + - name: CHSEL20 + description: Channel-%s selection. + bit_offset: 20 + bit_size: 1 + enum: CHSEL + - name: CHSEL21 + description: Channel-%s selection. + bit_offset: 21 + bit_size: 1 + enum: CHSEL + - name: CHSEL22 + description: Channel-%s selection. + bit_offset: 22 + bit_size: 1 enum: CHSEL fieldset/CHSELR1: description: ADC channel selection register [alternate]. fields: - - name: SQ + - name: SQ1 description: '%s conversion of the sequence.' bit_offset: 0 bit_size: 4 - array: - len: 8 - stride: 4 + enum: SQ + - name: SQ2 + description: '%s conversion of the sequence.' + bit_offset: 4 + bit_size: 4 + enum: SQ + - name: SQ3 + description: '%s conversion of the sequence.' + bit_offset: 8 + bit_size: 4 + enum: SQ + - name: SQ4 + description: '%s conversion of the sequence.' + bit_offset: 12 + bit_size: 4 + enum: SQ + - name: SQ5 + description: '%s conversion of the sequence.' + bit_offset: 16 + bit_size: 4 + enum: SQ + - name: SQ6 + description: '%s conversion of the sequence.' + bit_offset: 20 + bit_size: 4 + enum: SQ + - name: SQ7 + description: '%s conversion of the sequence.' + bit_offset: 24 + bit_size: 4 + enum: SQ + - name: SQ8 + description: '%s conversion of the sequence.' + bit_offset: 28 + bit_size: 4 enum: SQ fieldset/CR: description: ADC control register. @@ -350,13 +703,20 @@ fieldset/IER: bit_offset: 4 bit_size: 1 enum: OVRIE - - name: AWDIE + - name: AWD1IE description: Analog watchdog %s interrupt enable. bit_offset: 7 bit_size: 1 - array: - len: 3 - stride: 1 + enum: AWDIE + - name: AWD2IE + description: Analog watchdog %s interrupt enable. + bit_offset: 8 + bit_size: 1 + enum: AWDIE + - name: AWD3IE + description: Analog watchdog %s interrupt enable. + bit_offset: 9 + bit_size: 1 enum: AWDIE - name: EOCALIE description: 'End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).' @@ -396,13 +756,20 @@ fieldset/ISR: bit_offset: 4 bit_size: 1 enum: OVR - - name: AWD + - name: AWD1 description: Analog watchdog %s flag. bit_offset: 7 bit_size: 1 - array: - len: 3 - stride: 1 + enum: AWD + - name: AWD2 + description: Analog watchdog %s flag. + bit_offset: 8 + bit_size: 1 + enum: AWD + - name: AWD3 + description: Analog watchdog %s flag. + bit_offset: 9 + bit_size: 1 enum: AWD - name: EOCAL description: End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it. @@ -417,21 +784,130 @@ fieldset/ISR: fieldset/SMPR: description: ADC sampling time register. fields: - - name: SMP + - name: SMP1 description: Sampling time selection %s. bit_offset: 0 bit_size: 3 - array: - len: 2 - stride: 4 enum: SMP - - name: SMPSEL + - name: SMP2 + description: Sampling time selection %s. + bit_offset: 4 + bit_size: 3 + enum: SMP + - name: SMPSEL0 description: Channel-%s sampling time selection. bit_offset: 8 bit_size: 1 - array: - len: 23 - stride: 1 + enum: SMPSEL + - name: SMPSEL1 + description: Channel-%s sampling time selection. + bit_offset: 9 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL2 + description: Channel-%s sampling time selection. + bit_offset: 10 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL3 + description: Channel-%s sampling time selection. + bit_offset: 11 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL4 + description: Channel-%s sampling time selection. + bit_offset: 12 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL5 + description: Channel-%s sampling time selection. + bit_offset: 13 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL6 + description: Channel-%s sampling time selection. + bit_offset: 14 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL7 + description: Channel-%s sampling time selection. + bit_offset: 15 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL8 + description: Channel-%s sampling time selection. + bit_offset: 16 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL9 + description: Channel-%s sampling time selection. + bit_offset: 17 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL10 + description: Channel-%s sampling time selection. + bit_offset: 18 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL11 + description: Channel-%s sampling time selection. + bit_offset: 19 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL12 + description: Channel-%s sampling time selection. + bit_offset: 20 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL13 + description: Channel-%s sampling time selection. + bit_offset: 21 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL14 + description: Channel-%s sampling time selection. + bit_offset: 22 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL15 + description: Channel-%s sampling time selection. + bit_offset: 23 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL16 + description: Channel-%s sampling time selection. + bit_offset: 24 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL17 + description: Channel-%s sampling time selection. + bit_offset: 25 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL18 + description: Channel-%s sampling time selection. + bit_offset: 26 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL19 + description: Channel-%s sampling time selection. + bit_offset: 27 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL20 + description: Channel-%s sampling time selection. + bit_offset: 28 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL21 + description: Channel-%s sampling time selection. + bit_offset: 29 + bit_size: 1 + enum: SMPSEL + - name: SMPSEL22 + description: Channel-%s sampling time selection. + bit_offset: 30 + bit_size: 1 enum: SMPSEL enum/ADCAL: bit_size: 1 diff --git a/base/STM32C011/DMA.yaml b/head/STM32C011/DMA.yaml index 77a5699..eaafabd 100644 --- a/base/STM32C011/DMA.yaml +++ b/head/STM32C011/DMA.yaml @@ -1,22 +1,60 @@ -block/CH: +block/CH1: description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' items: - name: CR description: DMA channel 1 configuration register. byte_offset: 0 - fieldset: CR + fieldset: CH1_CR - name: NDTR description: DMA channel 1 number of data to transfer register. byte_offset: 4 - fieldset: NDTR + fieldset: CH1_NDTR - name: PAR description: DMA channel 1 peripheral address register. byte_offset: 8 - fieldset: PAR + fieldset: CH1_PAR - name: MAR description: DMA channel 1 memory address register. byte_offset: 12 - fieldset: MAR + fieldset: CH1_MAR +block/CH2: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: DMA channel 1 configuration register. + byte_offset: 0 + fieldset: CH2_CR + - name: NDTR + description: DMA channel 1 number of data to transfer register. + byte_offset: 4 + fieldset: CH2_NDTR + - name: PAR + description: DMA channel 1 peripheral address register. + byte_offset: 8 + fieldset: CH2_PAR + - name: MAR + description: DMA channel 1 memory address register. + byte_offset: 12 + fieldset: CH2_MAR +block/CH3: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: DMA channel 1 configuration register. + byte_offset: 0 + fieldset: CH3_CR + - name: NDTR + description: DMA channel 1 number of data to transfer register. + byte_offset: 4 + fieldset: CH3_NDTR + - name: PAR + description: DMA channel 1 peripheral address register. + byte_offset: 8 + fieldset: CH3_PAR + - name: MAR + description: DMA channel 1 memory address register. + byte_offset: 12 + fieldset: CH3_MAR block/DMA: description: DMA controller. items: @@ -28,201 +66,532 @@ block/DMA: description: DMA interrupt flag clear register. byte_offset: 4 fieldset: IFCR - - name: CH + - name: CH1 description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' - array: - len: 3 - stride: 20 byte_offset: 8 - block: CH -fieldset/CR: + block: CH1 + - name: CH2 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 28 + block: CH2 + - name: CH3 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 48 + block: CH3 +fieldset/CH1_CR: + description: DMA channel 1 configuration register. + fields: + - name: EN + description: 'channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.' + bit_offset: 0 + bit_size: 1 + enum: CH1_CR_EN + - name: TCIE + description: 'transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 1 + bit_size: 1 + enum: CH1_CR_TCIE + - name: HTIE + description: 'half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 2 + bit_size: 1 + enum: CH1_CR_HTIE + - name: TEIE + description: 'transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 3 + bit_size: 1 + enum: CH1_CR_TEIE + - name: DIR + description: 'data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 4 + bit_size: 1 + enum: CH1_CR_DIR + - name: CIRC + description: 'circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 5 + bit_size: 1 + enum: CH1_CR_CIRC + - name: PINC + description: 'peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 6 + bit_size: 1 + enum: CH1_CR_PINC + - name: MINC + description: 'memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 7 + bit_size: 1 + enum: CH1_CR_MINC + - name: PSIZE + description: 'peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 8 + bit_size: 2 + enum: CH1_CR_PSIZE + - name: MSIZE + description: 'memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 10 + bit_size: 2 + enum: CH1_CR_MSIZE + - name: PL + description: 'priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 12 + bit_size: 2 + enum: CH1_CR_PL + - name: MEM2MEM + description: 'memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 14 + bit_size: 1 + enum: CH1_CR_MEM2MEM +fieldset/CH1_MAR: + description: DMA channel 1 memory address register. + fields: + - name: MA + description: 'peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 0 + bit_size: 32 +fieldset/CH1_NDTR: + description: DMA channel 1 number of data to transfer register. + fields: + - name: NDT + description: 'number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 0 + bit_size: 16 +fieldset/CH1_PAR: + description: DMA channel 1 peripheral address register. + fields: + - name: PA + description: 'peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 0 + bit_size: 32 +fieldset/CH2_CR: + description: DMA channel 1 configuration register. + fields: + - name: EN + description: 'channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.' + bit_offset: 0 + bit_size: 1 + enum: CH2_CR_EN + - name: TCIE + description: 'transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 1 + bit_size: 1 + enum: CH2_CR_TCIE + - name: HTIE + description: 'half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 2 + bit_size: 1 + enum: CH2_CR_HTIE + - name: TEIE + description: 'transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 3 + bit_size: 1 + enum: CH2_CR_TEIE + - name: DIR + description: 'data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 4 + bit_size: 1 + enum: CH2_CR_DIR + - name: CIRC + description: 'circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 5 + bit_size: 1 + enum: CH2_CR_CIRC + - name: PINC + description: 'peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 6 + bit_size: 1 + enum: CH2_CR_PINC + - name: MINC + description: 'memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 7 + bit_size: 1 + enum: CH2_CR_MINC + - name: PSIZE + description: 'peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 8 + bit_size: 2 + enum: CH2_CR_PSIZE + - name: MSIZE + description: 'memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 10 + bit_size: 2 + enum: CH2_CR_MSIZE + - name: PL + description: 'priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 12 + bit_size: 2 + enum: CH2_CR_PL + - name: MEM2MEM + description: 'memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 14 + bit_size: 1 + enum: CH2_CR_MEM2MEM +fieldset/CH2_MAR: + description: DMA channel 1 memory address register. + fields: + - name: MA + description: 'peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 0 + bit_size: 32 +fieldset/CH2_NDTR: + description: DMA channel 1 number of data to transfer register. + fields: + - name: NDT + description: 'number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 0 + bit_size: 16 +fieldset/CH2_PAR: + description: DMA channel 1 peripheral address register. + fields: + - name: PA + description: 'peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 0 + bit_size: 32 +fieldset/CH3_CR: description: DMA channel 1 configuration register. fields: - name: EN description: 'channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of the DMA_IFCR register). Note: this bit is set and cleared by software.' bit_offset: 0 bit_size: 1 - enum: EN + enum: CH3_CR_EN - name: TCIE description: 'transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' bit_offset: 1 bit_size: 1 - enum: TCIE + enum: CH3_CR_TCIE - name: HTIE description: 'half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' bit_offset: 2 bit_size: 1 - enum: HTIE + enum: CH3_CR_HTIE - name: TEIE description: 'transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' bit_offset: 3 bit_size: 1 - enum: TEIE + enum: CH3_CR_TEIE - name: DIR description: 'data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' bit_offset: 4 bit_size: 1 - enum: DIR + enum: CH3_CR_DIR - name: CIRC description: 'circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' bit_offset: 5 bit_size: 1 - enum: CIRC + enum: CH3_CR_CIRC - name: PINC description: 'peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' bit_offset: 6 bit_size: 1 - enum: PINC + enum: CH3_CR_PINC - name: MINC description: 'memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' bit_offset: 7 bit_size: 1 - enum: MINC + enum: CH3_CR_MINC - name: PSIZE description: 'peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' bit_offset: 8 bit_size: 2 - enum: PSIZE + enum: CH3_CR_PSIZE - name: MSIZE description: 'memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' bit_offset: 10 bit_size: 2 - enum: MSIZE + enum: CH3_CR_MSIZE - name: PL description: 'priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' bit_offset: 12 bit_size: 2 - enum: PL + enum: CH3_CR_PL - name: MEM2MEM description: 'memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' bit_offset: 14 bit_size: 1 - enum: MEM2MEM + enum: CH3_CR_MEM2MEM +fieldset/CH3_MAR: + description: DMA channel 1 memory address register. + fields: + - name: MA + description: 'peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 0 + bit_size: 32 +fieldset/CH3_NDTR: + description: DMA channel 1 number of data to transfer register. + fields: + - name: NDT + description: 'number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' + bit_offset: 0 + bit_size: 16 +fieldset/CH3_PAR: + description: DMA channel 1 peripheral address register. + fields: + - name: PA + description: 'peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' + bit_offset: 0 + bit_size: 32 fieldset/IFCR: description: DMA interrupt flag clear register. fields: - - name: CGIF + - name: CGIF1 description: Channel %s Global interrupt clear. bit_offset: 0 bit_size: 1 - array: - len: 3 - stride: 4 enum: CGIF - - name: CTCIF + - name: CTCIF1 description: Channel %s Transfer Complete clear. bit_offset: 1 bit_size: 1 - array: - len: 3 - stride: 4 enum: CTCIF - - name: CHTIF + - name: CHTIF1 description: Channel %s Half Transfer clear. bit_offset: 2 bit_size: 1 - array: - len: 3 - stride: 4 enum: CHTIF - - name: CTEIF + - name: CTEIF1 description: Channel %s Transfer Error clear. bit_offset: 3 bit_size: 1 - array: - len: 3 - stride: 4 + enum: CTEIF + - name: CGIF2 + description: Channel %s Global interrupt clear. + bit_offset: 4 + bit_size: 1 + enum: CGIF + - name: CTCIF2 + description: Channel %s Transfer Complete clear. + bit_offset: 5 + bit_size: 1 + enum: CTCIF + - name: CHTIF2 + description: Channel %s Half Transfer clear. + bit_offset: 6 + bit_size: 1 + enum: CHTIF + - name: CTEIF2 + description: Channel %s Transfer Error clear. + bit_offset: 7 + bit_size: 1 + enum: CTEIF + - name: CGIF3 + description: Channel %s Global interrupt clear. + bit_offset: 8 + bit_size: 1 + enum: CGIF + - name: CTCIF3 + description: Channel %s Transfer Complete clear. + bit_offset: 9 + bit_size: 1 + enum: CTCIF + - name: CHTIF3 + description: Channel %s Half Transfer clear. + bit_offset: 10 + bit_size: 1 + enum: CHTIF + - name: CTEIF3 + description: Channel %s Transfer Error clear. + bit_offset: 11 + bit_size: 1 enum: CTEIF fieldset/ISR: description: DMA interrupt status register. fields: - - name: GIF + - name: GIF1 description: Channel %s Global interrupt flag. bit_offset: 0 bit_size: 1 - array: - len: 3 - stride: 4 enum: GIF - - name: TCIF + - name: TCIF1 description: Channel %s Transfer Complete flag. bit_offset: 1 bit_size: 1 - array: - len: 3 - stride: 4 enum: TCIF - - name: HTIF + - name: HTIF1 description: Channel %s Half Transfer Complete flag. bit_offset: 2 bit_size: 1 - array: - len: 3 - stride: 4 enum: HTIF - - name: TEIF + - name: TEIF1 description: Channel %s Transfer Error flag. bit_offset: 3 bit_size: 1 - array: - len: 3 - stride: 4 enum: TEIF -fieldset/MAR: - description: DMA channel 1 memory address register. - fields: - - name: MA - description: 'peripheral address It contains the base address of the memory from/to which the data will be read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory source address if DIR = 1 and the memory destination address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral source address DIR = 1 and the peripheral destination address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' - bit_offset: 0 - bit_size: 32 -fieldset/NDTR: - description: DMA channel 1 number of data to transfer register. - fields: - - name: NDT - description: 'number of data to transfer (0 to 216 - 1) This field is updated by hardware when the channel is enabled: It is decremented after each single DMA read followed by write transfer, indicating the remaining amount of data items to transfer. It is kept at zero when the programmed amount of data to transfer is reached, if the channel is not in circular mode (CIRC = 0 in the DMA_CCRx register). It is reloaded automatically by the previously programmed value, when the transfer is complete, if the channel is in circular mode (CIRC = 1). If this field is zero, no transfer can be served whatever the channel status (enabled or not). Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1).' - bit_offset: 0 - bit_size: 16 -fieldset/PAR: - description: DMA channel 1 peripheral address register. - fields: - - name: PA - description: 'peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this register identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this register identifies the peripheral destination address DIR = 1 and the peripheral source address if DIR = 0. Note: this register is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1).' - bit_offset: 0 - bit_size: 32 + - name: GIF2 + description: Channel %s Global interrupt flag. + bit_offset: 4 + bit_size: 1 + enum: GIF + - name: TCIF2 + description: Channel %s Transfer Complete flag. + bit_offset: 5 + bit_size: 1 + enum: TCIF + - name: HTIF2 + description: Channel %s Half Transfer Complete flag. + bit_offset: 6 + bit_size: 1 + enum: HTIF + - name: TEIF2 + description: Channel %s Transfer Error flag. + bit_offset: 7 + bit_size: 1 + enum: TEIF + - name: GIF3 + description: Channel %s Global interrupt flag. + bit_offset: 8 + bit_size: 1 + enum: GIF + - name: TCIF3 + description: Channel %s Transfer Complete flag. + bit_offset: 9 + bit_size: 1 + enum: TCIF + - name: HTIF3 + description: Channel %s Half Transfer Complete flag. + bit_offset: 10 + bit_size: 1 + enum: HTIF + - name: TEIF3 + description: Channel %s Transfer Error flag. + bit_offset: 11 + bit_size: 1 + enum: TEIF enum/CGIF: bit_size: 1 variants: - - name: Clear - description: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register. + - name: Clear + description: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register. + value: 1 +enum/CH1_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH1_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH1_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH1_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. value: 1 -enum/CHTIF: +enum/CH1_CR_MEM2MEM: bit_size: 1 variants: - - name: Clear - description: Clears the HTIF flag in the ISR register. + - name: Disabled + description: Memory to memory mode disabled. + value: 0 + - name: Enabled + description: Memory to memory mode enabled. value: 1 -enum/CIRC: +enum/CH1_CR_MINC: bit_size: 1 variants: - name: Disabled - description: Circular buffer disabled. + description: Increment mode disabled. value: 0 - name: Enabled - description: Circular buffer enabled. + description: Increment mode enabled. value: 1 -enum/CTCIF: +enum/CH1_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH1_CR_PINC: bit_size: 1 variants: - - name: Clear - description: Clears the TCIF flag in the ISR register. + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. value: 1 -enum/CTEIF: +enum/CH1_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH1_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH1_CR_TCIE: bit_size: 1 variants: - - name: Clear - description: Clears the TEIF flag in the ISR register. + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH1_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH2_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. value: 1 -enum/DIR: +enum/CH2_CR_DIR: bit_size: 1 variants: - name: FromPeripheral @@ -231,7 +600,7 @@ enum/DIR: - name: FromMemory description: Read from memory. value: 1 -enum/EN: +enum/CH2_CR_EN: bit_size: 1 variants: - name: Disabled @@ -240,34 +609,136 @@ enum/EN: - name: Enabled description: Channel enabled. value: 1 -enum/GIF: +enum/CH2_CR_HTIE: bit_size: 1 variants: - - name: NoEvent - description: No transfer error, half event, complete event. + - name: Disabled + description: Half Transfer interrupt disabled. value: 0 - - name: Event - description: A transfer error, half event or complete event has occured. + - name: Enabled + description: Half Transfer interrupt enabled. value: 1 -enum/HTIE: +enum/CH2_CR_MEM2MEM: bit_size: 1 variants: - name: Disabled - description: Half Transfer interrupt disabled. + description: Memory to memory mode disabled. value: 0 - name: Enabled - description: Half Transfer interrupt enabled. + description: Memory to memory mode enabled. value: 1 -enum/HTIF: +enum/CH2_CR_MINC: bit_size: 1 variants: - - name: NotHalf - description: No half transfer event. + - name: Disabled + description: Increment mode disabled. value: 0 - - name: Half - description: A half transfer event has occured. + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH2_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH2_CR_PINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH2_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH2_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH2_CR_TCIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH2_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH3_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH3_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH3_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH3_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. value: 1 -enum/MEM2MEM: +enum/CH3_CR_MEM2MEM: bit_size: 1 variants: - name: Disabled @@ -276,7 +747,7 @@ enum/MEM2MEM: - name: Enabled description: Memory to memory mode enabled. value: 1 -enum/MINC: +enum/CH3_CR_MINC: bit_size: 1 variants: - name: Disabled @@ -285,7 +756,7 @@ enum/MINC: - name: Enabled description: Increment mode enabled. value: 1 -enum/MSIZE: +enum/CH3_CR_MSIZE: bit_size: 2 variants: - name: Bits8 @@ -297,7 +768,7 @@ enum/MSIZE: - name: Bits32 description: 32-bit size. value: 2 -enum/PINC: +enum/CH3_CR_PINC: bit_size: 1 variants: - name: Disabled @@ -306,7 +777,7 @@ enum/PINC: - name: Enabled description: Increment mode enabled. value: 1 -enum/PL: +enum/CH3_CR_PL: bit_size: 2 variants: - name: Low @@ -321,7 +792,7 @@ enum/PL: - name: VeryHigh description: Very high priority. value: 3 -enum/PSIZE: +enum/CH3_CR_PSIZE: bit_size: 2 variants: - name: Bits8 @@ -333,7 +804,7 @@ enum/PSIZE: - name: Bits32 description: 32-bit size. value: 2 -enum/TCIE: +enum/CH3_CR_TCIE: bit_size: 1 variants: - name: Disabled @@ -342,6 +813,51 @@ enum/TCIE: - name: Enabled description: Transfer Complete interrupt enabled. value: 1 +enum/CH3_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CHTIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the HTIF flag in the ISR register. + value: 1 +enum/CTCIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the TCIF flag in the ISR register. + value: 1 +enum/CTEIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the TEIF flag in the ISR register. + value: 1 +enum/GIF: + bit_size: 1 + variants: + - name: NoEvent + description: No transfer error, half event, complete event. + value: 0 + - name: Event + description: A transfer error, half event or complete event has occured. + value: 1 +enum/HTIF: + bit_size: 1 + variants: + - name: NotHalf + description: No half transfer event. + value: 0 + - name: Half + description: A half transfer event has occured. + value: 1 enum/TCIF: bit_size: 1 variants: @@ -351,15 +867,6 @@ enum/TCIF: - name: Complete description: A transfer complete event has occured. value: 1 -enum/TEIE: - bit_size: 1 - variants: - - name: Disabled - description: Transfer Error interrupt disabled. - value: 0 - - name: Enabled - description: Transfer Error interrupt enabled. - value: 1 enum/TEIF: bit_size: 1 variants: diff --git a/base/STM32C011/DMAMUX.yaml b/head/STM32C011/DMAMUX.yaml index 27eeb06..91ab7ee 100644 --- a/base/STM32C011/DMAMUX.yaml +++ b/head/STM32C011/DMAMUX.yaml @@ -1,13 +1,18 @@ block/DMAMUX: description: DMAMUX register block. items: - - name: CCR + - name: CCR0 description: DMA Multiplexer Channel %s Control register. - array: - len: 3 - stride: 4 byte_offset: 0 fieldset: CCR + - name: CCR1 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 4 + fieldset: CCR + - name: CCR2 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 8 + fieldset: CCR - name: CSR description: DMAMUX request line multiplexer interrupt channel status register. byte_offset: 128 @@ -16,13 +21,22 @@ block/DMAMUX: description: DMAMUX request line multiplexer interrupt clear flag register. byte_offset: 132 fieldset: CFR - - name: RGCR + - name: RGCR0 description: DMAMUX request generator channel %s configuration register. - array: - len: 4 - stride: 4 byte_offset: 256 fieldset: RGCR + - name: RGCR1 + description: DMAMUX request generator channel %s configuration register. + byte_offset: 260 + fieldset: RGCR + - name: RGCR2 + description: DMAMUX request generator channel %s configuration register. + byte_offset: 264 + fieldset: RGCR + - name: RGCR3 + description: DMAMUX request generator channel %s configuration register. + byte_offset: 268 + fieldset: RGCR - name: RGSR description: DMAMUX request generator interrupt status register. byte_offset: 320 @@ -69,35 +83,61 @@ fieldset/CCR: fieldset/CFR: description: DMAMUX request line multiplexer interrupt clear flag register. fields: - - name: CSOF + - name: CSOF0 description: Synchronization Clear Overrun Flag %s. bit_offset: 0 bit_size: 1 - array: - len: 3 - stride: 1 + enum: CSOF + - name: CSOF1 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 1 + bit_size: 1 + enum: CSOF + - name: CSOF2 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 2 + bit_size: 1 enum: CSOF fieldset/CSR: description: DMAMUX request line multiplexer interrupt channel status register. fields: - - name: SOF + - name: SOF0 description: Synchronization Overrun Flag %s. bit_offset: 0 bit_size: 1 - array: - len: 3 - stride: 1 + enum: SOF + - name: SOF1 + description: Synchronization Overrun Flag %s. + bit_offset: 1 + bit_size: 1 + enum: SOF + - name: SOF2 + description: Synchronization Overrun Flag %s. + bit_offset: 2 + bit_size: 1 enum: SOF fieldset/RGCFR: description: DMAMUX request generator interrupt clear flag register. fields: - - name: COF + - name: COF0 description: Generator Clear Overrun Flag %s. bit_offset: 0 bit_size: 1 - array: - len: 4 - stride: 1 + enum: COF + - name: COF1 + description: Generator Clear Overrun Flag %s. + bit_offset: 1 + bit_size: 1 + enum: COF + - name: COF2 + description: Generator Clear Overrun Flag %s. + bit_offset: 2 + bit_size: 1 + enum: COF + - name: COF3 + description: Generator Clear Overrun Flag %s. + bit_offset: 3 + bit_size: 1 enum: COF fieldset/RGCR: description: DMAMUX request generator channel %s configuration register. @@ -128,13 +168,25 @@ fieldset/RGCR: fieldset/RGSR: description: DMAMUX request generator interrupt status register. fields: - - name: OF + - name: OF0 description: Generator Overrun Flag %s. bit_offset: 0 bit_size: 1 - array: - len: 4 - stride: 1 + enum: OF + - name: OF1 + description: Generator Overrun Flag %s. + bit_offset: 1 + bit_size: 1 + enum: OF + - name: OF2 + description: Generator Overrun Flag %s. + bit_offset: 2 + bit_size: 1 + enum: OF + - name: OF3 + description: Generator Overrun Flag %s. + bit_offset: 3 + bit_size: 1 enum: OF enum/COF: bit_size: 1 diff --git a/base/STM32C011/GPIOA.yaml b/head/STM32C011/GPIOA.yaml index df88ad5..4430db3 100644 --- a/base/STM32C011/GPIOA.yaml +++ b/head/STM32C011/GPIOA.yaml @@ -51,65 +51,457 @@ fieldset/AFRH: fieldset/AFRL: description: GPIO alternate function low register. fields: - - name: AFSEL + - name: AFSEL0 description: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os. bit_offset: 0 bit_size: 4 - array: - len: 8 - stride: 4 + enum: AFSEL + - name: AFSEL1 + description: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os. + bit_offset: 4 + bit_size: 4 + enum: AFSEL + - name: AFSEL2 + description: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os. + bit_offset: 8 + bit_size: 4 + enum: AFSEL + - name: AFSEL3 + description: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os. + bit_offset: 12 + bit_size: 4 + enum: AFSEL + - name: AFSEL4 + description: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os. + bit_offset: 16 + bit_size: 4 + enum: AFSEL + - name: AFSEL5 + description: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os. + bit_offset: 20 + bit_size: 4 + enum: AFSEL + - name: AFSEL6 + description: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os. + bit_offset: 24 + bit_size: 4 + enum: AFSEL + - name: AFSEL7 + description: Alternate function selection for port x pin y (y = 0 to 7) These bits are written by software to configure alternate function I/Os. + bit_offset: 28 + bit_size: 4 enum: AFSEL fieldset/BRR: description: GPIO port bit reset register. fields: - - name: BR + - name: BR0 description: Port x reset pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: BRR_BR + - name: BR1 + description: Port x reset pin %s. + bit_offset: 1 + bit_size: 1 + enum: BRR_BR + - name: BR2 + description: Port x reset pin %s. + bit_offset: 2 + bit_size: 1 + enum: BRR_BR + - name: BR3 + description: Port x reset pin %s. + bit_offset: 3 + bit_size: 1 + enum: BRR_BR + - name: BR4 + description: Port x reset pin %s. + bit_offset: 4 + bit_size: 1 + enum: BRR_BR + - name: BR5 + description: Port x reset pin %s. + bit_offset: 5 + bit_size: 1 + enum: BRR_BR + - name: BR6 + description: Port x reset pin %s. + bit_offset: 6 + bit_size: 1 + enum: BRR_BR + - name: BR7 + description: Port x reset pin %s. + bit_offset: 7 + bit_size: 1 + enum: BRR_BR + - name: BR8 + description: Port x reset pin %s. + bit_offset: 8 + bit_size: 1 + enum: BRR_BR + - name: BR9 + description: Port x reset pin %s. + bit_offset: 9 + bit_size: 1 + enum: BRR_BR + - name: BR10 + description: Port x reset pin %s. + bit_offset: 10 + bit_size: 1 + enum: BRR_BR + - name: BR11 + description: Port x reset pin %s. + bit_offset: 11 + bit_size: 1 + enum: BRR_BR + - name: BR12 + description: Port x reset pin %s. + bit_offset: 12 + bit_size: 1 + enum: BRR_BR + - name: BR13 + description: Port x reset pin %s. + bit_offset: 13 + bit_size: 1 + enum: BRR_BR + - name: BR14 + description: Port x reset pin %s. + bit_offset: 14 + bit_size: 1 + enum: BRR_BR + - name: BR15 + description: Port x reset pin %s. + bit_offset: 15 + bit_size: 1 enum: BRR_BR fieldset/BSRR: description: GPIO port bit set/reset register. fields: - - name: BS + - name: BS0 description: Port x set pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 enum: BS - - name: BR + - name: BS1 + description: Port x set pin %s. + bit_offset: 1 + bit_size: 1 + enum: BS + - name: BS2 + description: Port x set pin %s. + bit_offset: 2 + bit_size: 1 + enum: BS + - name: BS3 + description: Port x set pin %s. + bit_offset: 3 + bit_size: 1 + enum: BS + - name: BS4 + description: Port x set pin %s. + bit_offset: 4 + bit_size: 1 + enum: BS + - name: BS5 + description: Port x set pin %s. + bit_offset: 5 + bit_size: 1 + enum: BS + - name: BS6 + description: Port x set pin %s. + bit_offset: 6 + bit_size: 1 + enum: BS + - name: BS7 + description: Port x set pin %s. + bit_offset: 7 + bit_size: 1 + enum: BS + - name: BS8 + description: Port x set pin %s. + bit_offset: 8 + bit_size: 1 + enum: BS + - name: BS9 + description: Port x set pin %s. + bit_offset: 9 + bit_size: 1 + enum: BS + - name: BS10 + description: Port x set pin %s. + bit_offset: 10 + bit_size: 1 + enum: BS + - name: BS11 + description: Port x set pin %s. + bit_offset: 11 + bit_size: 1 + enum: BS + - name: BS12 + description: Port x set pin %s. + bit_offset: 12 + bit_size: 1 + enum: BS + - name: BS13 + description: Port x set pin %s. + bit_offset: 13 + bit_size: 1 + enum: BS + - name: BS14 + description: Port x set pin %s. + bit_offset: 14 + bit_size: 1 + enum: BS + - name: BS15 + description: Port x set pin %s. + bit_offset: 15 + bit_size: 1 + enum: BS + - name: BR0 description: Port x reset pin %s. bit_offset: 16 bit_size: 1 - array: - len: 16 - stride: 1 + enum: BSRR_BR + - name: BR1 + description: Port x reset pin %s. + bit_offset: 17 + bit_size: 1 + enum: BSRR_BR + - name: BR2 + description: Port x reset pin %s. + bit_offset: 18 + bit_size: 1 + enum: BSRR_BR + - name: BR3 + description: Port x reset pin %s. + bit_offset: 19 + bit_size: 1 + enum: BSRR_BR + - name: BR4 + description: Port x reset pin %s. + bit_offset: 20 + bit_size: 1 + enum: BSRR_BR + - name: BR5 + description: Port x reset pin %s. + bit_offset: 21 + bit_size: 1 + enum: BSRR_BR + - name: BR6 + description: Port x reset pin %s. + bit_offset: 22 + bit_size: 1 + enum: BSRR_BR + - name: BR7 + description: Port x reset pin %s. + bit_offset: 23 + bit_size: 1 + enum: BSRR_BR + - name: BR8 + description: Port x reset pin %s. + bit_offset: 24 + bit_size: 1 + enum: BSRR_BR + - name: BR9 + description: Port x reset pin %s. + bit_offset: 25 + bit_size: 1 + enum: BSRR_BR + - name: BR10 + description: Port x reset pin %s. + bit_offset: 26 + bit_size: 1 + enum: BSRR_BR + - name: BR11 + description: Port x reset pin %s. + bit_offset: 27 + bit_size: 1 + enum: BSRR_BR + - name: BR12 + description: Port x reset pin %s. + bit_offset: 28 + bit_size: 1 + enum: BSRR_BR + - name: BR13 + description: Port x reset pin %s. + bit_offset: 29 + bit_size: 1 + enum: BSRR_BR + - name: BR14 + description: Port x reset pin %s. + bit_offset: 30 + bit_size: 1 + enum: BSRR_BR + - name: BR15 + description: Port x reset pin %s. + bit_offset: 31 + bit_size: 1 enum: BSRR_BR fieldset/IDR: description: GPIO port input data register. fields: - - name: ID + - name: ID0 description: Port input data pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: ID + - name: ID1 + description: Port input data pin %s. + bit_offset: 1 + bit_size: 1 + enum: ID + - name: ID2 + description: Port input data pin %s. + bit_offset: 2 + bit_size: 1 + enum: ID + - name: ID3 + description: Port input data pin %s. + bit_offset: 3 + bit_size: 1 + enum: ID + - name: ID4 + description: Port input data pin %s. + bit_offset: 4 + bit_size: 1 + enum: ID + - name: ID5 + description: Port input data pin %s. + bit_offset: 5 + bit_size: 1 + enum: ID + - name: ID6 + description: Port input data pin %s. + bit_offset: 6 + bit_size: 1 + enum: ID + - name: ID7 + description: Port input data pin %s. + bit_offset: 7 + bit_size: 1 + enum: ID + - name: ID8 + description: Port input data pin %s. + bit_offset: 8 + bit_size: 1 + enum: ID + - name: ID9 + description: Port input data pin %s. + bit_offset: 9 + bit_size: 1 + enum: ID + - name: ID10 + description: Port input data pin %s. + bit_offset: 10 + bit_size: 1 + enum: ID + - name: ID11 + description: Port input data pin %s. + bit_offset: 11 + bit_size: 1 + enum: ID + - name: ID12 + description: Port input data pin %s. + bit_offset: 12 + bit_size: 1 + enum: ID + - name: ID13 + description: Port input data pin %s. + bit_offset: 13 + bit_size: 1 + enum: ID + - name: ID14 + description: Port input data pin %s. + bit_offset: 14 + bit_size: 1 + enum: ID + - name: ID15 + description: Port input data pin %s. + bit_offset: 15 + bit_size: 1 enum: ID fieldset/LCKR: description: GPIO port configuration lock register. fields: - - name: LCK + - name: LCK0 description: Port x lock pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: LCK + - name: LCK1 + description: Port x lock pin %s. + bit_offset: 1 + bit_size: 1 + enum: LCK + - name: LCK2 + description: Port x lock pin %s. + bit_offset: 2 + bit_size: 1 + enum: LCK + - name: LCK3 + description: Port x lock pin %s. + bit_offset: 3 + bit_size: 1 + enum: LCK + - name: LCK4 + description: Port x lock pin %s. + bit_offset: 4 + bit_size: 1 + enum: LCK + - name: LCK5 + description: Port x lock pin %s. + bit_offset: 5 + bit_size: 1 + enum: LCK + - name: LCK6 + description: Port x lock pin %s. + bit_offset: 6 + bit_size: 1 + enum: LCK + - name: LCK7 + description: Port x lock pin %s. + bit_offset: 7 + bit_size: 1 + enum: LCK + - name: LCK8 + description: Port x lock pin %s. + bit_offset: 8 + bit_size: 1 + enum: LCK + - name: LCK9 + description: Port x lock pin %s. + bit_offset: 9 + bit_size: 1 + enum: LCK + - name: LCK10 + description: Port x lock pin %s. + bit_offset: 10 + bit_size: 1 + enum: LCK + - name: LCK11 + description: Port x lock pin %s. + bit_offset: 11 + bit_size: 1 + enum: LCK + - name: LCK12 + description: Port x lock pin %s. + bit_offset: 12 + bit_size: 1 + enum: LCK + - name: LCK13 + description: Port x lock pin %s. + bit_offset: 13 + bit_size: 1 + enum: LCK + - name: LCK14 + description: Port x lock pin %s. + bit_offset: 14 + bit_size: 1 + enum: LCK + - name: LCK15 + description: Port x lock pin %s. + bit_offset: 15 + bit_size: 1 enum: LCK - name: LCKK description: 'Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset.' @@ -119,57 +511,417 @@ fieldset/LCKR: fieldset/MODER: description: GPIO port mode register. fields: - - name: MODE + - name: MODE0 description: Port x configuration pin %s. bit_offset: 0 bit_size: 2 - array: - len: 16 - stride: 2 + enum: MODE + - name: MODE1 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 2 + enum: MODE + - name: MODE2 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 2 + enum: MODE + - name: MODE3 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 2 + enum: MODE + - name: MODE4 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 2 + enum: MODE + - name: MODE5 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 2 + enum: MODE + - name: MODE6 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 2 + enum: MODE + - name: MODE7 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 2 + enum: MODE + - name: MODE8 + description: Port x configuration pin %s. + bit_offset: 16 + bit_size: 2 + enum: MODE + - name: MODE9 + description: Port x configuration pin %s. + bit_offset: 18 + bit_size: 2 + enum: MODE + - name: MODE10 + description: Port x configuration pin %s. + bit_offset: 20 + bit_size: 2 + enum: MODE + - name: MODE11 + description: Port x configuration pin %s. + bit_offset: 22 + bit_size: 2 + enum: MODE + - name: MODE12 + description: Port x configuration pin %s. + bit_offset: 24 + bit_size: 2 + enum: MODE + - name: MODE13 + description: Port x configuration pin %s. + bit_offset: 26 + bit_size: 2 + enum: MODE + - name: MODE14 + description: Port x configuration pin %s. + bit_offset: 28 + bit_size: 2 + enum: MODE + - name: MODE15 + description: Port x configuration pin %s. + bit_offset: 30 + bit_size: 2 enum: MODE fieldset/ODR: description: GPIO port output data register. fields: - - name: OD + - name: OD0 description: Port output data pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: OD + - name: OD1 + description: Port output data pin %s. + bit_offset: 1 + bit_size: 1 + enum: OD + - name: OD2 + description: Port output data pin %s. + bit_offset: 2 + bit_size: 1 + enum: OD + - name: OD3 + description: Port output data pin %s. + bit_offset: 3 + bit_size: 1 + enum: OD + - name: OD4 + description: Port output data pin %s. + bit_offset: 4 + bit_size: 1 + enum: OD + - name: OD5 + description: Port output data pin %s. + bit_offset: 5 + bit_size: 1 + enum: OD + - name: OD6 + description: Port output data pin %s. + bit_offset: 6 + bit_size: 1 + enum: OD + - name: OD7 + description: Port output data pin %s. + bit_offset: 7 + bit_size: 1 + enum: OD + - name: OD8 + description: Port output data pin %s. + bit_offset: 8 + bit_size: 1 + enum: OD + - name: OD9 + description: Port output data pin %s. + bit_offset: 9 + bit_size: 1 + enum: OD + - name: OD10 + description: Port output data pin %s. + bit_offset: 10 + bit_size: 1 + enum: OD + - name: OD11 + description: Port output data pin %s. + bit_offset: 11 + bit_size: 1 + enum: OD + - name: OD12 + description: Port output data pin %s. + bit_offset: 12 + bit_size: 1 + enum: OD + - name: OD13 + description: Port output data pin %s. + bit_offset: 13 + bit_size: 1 + enum: OD + - name: OD14 + description: Port output data pin %s. + bit_offset: 14 + bit_size: 1 + enum: OD + - name: OD15 + description: Port output data pin %s. + bit_offset: 15 + bit_size: 1 enum: OD fieldset/OSPEEDR: description: GPIO port output speed register. fields: - - name: OSPEED + - name: OSPEED0 description: Port x configuration pin %s. bit_offset: 0 bit_size: 2 - array: - len: 16 - stride: 2 + enum: OSPEED + - name: OSPEED1 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 2 + enum: OSPEED + - name: OSPEED2 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 2 + enum: OSPEED + - name: OSPEED3 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 2 + enum: OSPEED + - name: OSPEED4 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 2 + enum: OSPEED + - name: OSPEED5 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 2 + enum: OSPEED + - name: OSPEED6 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 2 + enum: OSPEED + - name: OSPEED7 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 2 + enum: OSPEED + - name: OSPEED8 + description: Port x configuration pin %s. + bit_offset: 16 + bit_size: 2 + enum: OSPEED + - name: OSPEED9 + description: Port x configuration pin %s. + bit_offset: 18 + bit_size: 2 + enum: OSPEED + - name: OSPEED10 + description: Port x configuration pin %s. + bit_offset: 20 + bit_size: 2 + enum: OSPEED + - name: OSPEED11 + description: Port x configuration pin %s. + bit_offset: 22 + bit_size: 2 + enum: OSPEED + - name: OSPEED12 + description: Port x configuration pin %s. + bit_offset: 24 + bit_size: 2 + enum: OSPEED + - name: OSPEED13 + description: Port x configuration pin %s. + bit_offset: 26 + bit_size: 2 + enum: OSPEED + - name: OSPEED14 + description: Port x configuration pin %s. + bit_offset: 28 + bit_size: 2 + enum: OSPEED + - name: OSPEED15 + description: Port x configuration pin %s. + bit_offset: 30 + bit_size: 2 enum: OSPEED fieldset/OTYPER: description: GPIO port output type register. fields: - - name: OT + - name: OT0 description: Port x configuration pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: OT + - name: OT1 + description: Port x configuration pin %s. + bit_offset: 1 + bit_size: 1 + enum: OT + - name: OT2 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 1 + enum: OT + - name: OT3 + description: Port x configuration pin %s. + bit_offset: 3 + bit_size: 1 + enum: OT + - name: OT4 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 1 + enum: OT + - name: OT5 + description: Port x configuration pin %s. + bit_offset: 5 + bit_size: 1 + enum: OT + - name: OT6 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 1 + enum: OT + - name: OT7 + description: Port x configuration pin %s. + bit_offset: 7 + bit_size: 1 + enum: OT + - name: OT8 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 1 + enum: OT + - name: OT9 + description: Port x configuration pin %s. + bit_offset: 9 + bit_size: 1 + enum: OT + - name: OT10 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 1 + enum: OT + - name: OT11 + description: Port x configuration pin %s. + bit_offset: 11 + bit_size: 1 + enum: OT + - name: OT12 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 1 + enum: OT + - name: OT13 + description: Port x configuration pin %s. + bit_offset: 13 + bit_size: 1 + enum: OT + - name: OT14 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 1 + enum: OT + - name: OT15 + description: Port x configuration pin %s. + bit_offset: 15 + bit_size: 1 enum: OT fieldset/PUPDR: description: GPIO port pull-up/pull-down register. fields: - - name: PUPD + - name: PUPD0 description: Port x configuration pin %s. bit_offset: 0 bit_size: 2 - array: - len: 16 - stride: 2 + enum: PUPD + - name: PUPD1 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 2 + enum: PUPD + - name: PUPD2 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 2 + enum: PUPD + - name: PUPD3 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 2 + enum: PUPD + - name: PUPD4 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 2 + enum: PUPD + - name: PUPD5 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 2 + enum: PUPD + - name: PUPD6 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 2 + enum: PUPD + - name: PUPD7 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 2 + enum: PUPD + - name: PUPD8 + description: Port x configuration pin %s. + bit_offset: 16 + bit_size: 2 + enum: PUPD + - name: PUPD9 + description: Port x configuration pin %s. + bit_offset: 18 + bit_size: 2 + enum: PUPD + - name: PUPD10 + description: Port x configuration pin %s. + bit_offset: 20 + bit_size: 2 + enum: PUPD + - name: PUPD11 + description: Port x configuration pin %s. + bit_offset: 22 + bit_size: 2 + enum: PUPD + - name: PUPD12 + description: Port x configuration pin %s. + bit_offset: 24 + bit_size: 2 + enum: PUPD + - name: PUPD13 + description: Port x configuration pin %s. + bit_offset: 26 + bit_size: 2 + enum: PUPD + - name: PUPD14 + description: Port x configuration pin %s. + bit_offset: 28 + bit_size: 2 + enum: PUPD + - name: PUPD15 + description: Port x configuration pin %s. + bit_offset: 30 + bit_size: 2 enum: PUPD enum/AFSEL: bit_size: 4 diff --git a/base/STM32C011/TIM1.yaml b/head/STM32C011/TIM1.yaml index fa1fa32..af43ef4 100644 --- a/base/STM32C011/TIM1.yaml +++ b/head/STM32C011/TIM1.yaml @@ -72,14 +72,26 @@ block/TIM1: byte_offset: 48 bit_size: 16 fieldset: RCR - - name: CCR + - name: CCR1 description: capture/compare register. - array: - len: 4 - stride: 4 byte_offset: 52 bit_size: 16 fieldset: CCR + - name: CCR2 + description: capture/compare register. + byte_offset: 56 + bit_size: 16 + fieldset: CCR + - name: CCR3 + description: capture/compare register. + byte_offset: 60 + bit_size: 16 + fieldset: CCR + - name: CCR4 + description: capture/compare register. + byte_offset: 64 + bit_size: 16 + fieldset: CCR - name: BDTR description: TIM1 break and dead-time register. byte_offset: 68 @@ -231,38 +243,101 @@ fieldset/BDTR: fieldset/CCER: description: TIM1 capture/compare enable register. fields: - - name: CCE + - name: CC1E description: Capture/Compare %s output enable. bit_offset: 0 bit_size: 1 - array: - len: 6 - stride: 4 enum: CCE - - name: CCP + - name: CC1P description: Capture/Compare %s output Polarity. bit_offset: 1 bit_size: 1 - array: - len: 6 - stride: 4 enum: CCP - - name: CCNE + - name: CC1NE description: Capture/Compare %s complementary output enable. bit_offset: 2 bit_size: 1 - array: - len: 3 - stride: 4 enum: CCNE - - name: CCNP + - name: CC1NP description: Capture/Compare %s output Polarity. bit_offset: 3 bit_size: 1 - array: - len: 4 - stride: 4 enum: CCNP + - name: CC2E + description: Capture/Compare %s output enable. + bit_offset: 4 + bit_size: 1 + enum: CCE + - name: CC2P + description: Capture/Compare %s output Polarity. + bit_offset: 5 + bit_size: 1 + enum: CCP + - name: CC2NE + description: Capture/Compare %s complementary output enable. + bit_offset: 6 + bit_size: 1 + enum: CCNE + - name: CC2NP + description: Capture/Compare %s output Polarity. + bit_offset: 7 + bit_size: 1 + enum: CCNP + - name: CC3E + description: Capture/Compare %s output enable. + bit_offset: 8 + bit_size: 1 + enum: CCE + - name: CC3P + description: Capture/Compare %s output Polarity. + bit_offset: 9 + bit_size: 1 + enum: CCP + - name: CC3NE + description: Capture/Compare %s complementary output enable. + bit_offset: 10 + bit_size: 1 + enum: CCNE + - name: CC3NP + description: Capture/Compare %s output Polarity. + bit_offset: 11 + bit_size: 1 + enum: CCNP + - name: CC4E + description: Capture/Compare %s output enable. + bit_offset: 12 + bit_size: 1 + enum: CCE + - name: CC4P + description: Capture/Compare %s output Polarity. + bit_offset: 13 + bit_size: 1 + enum: CCP + - name: CC4NP + description: Capture/Compare %s output Polarity. + bit_offset: 15 + bit_size: 1 + enum: CCNP + - name: CC5E + description: Capture/Compare %s output enable. + bit_offset: 16 + bit_size: 1 + enum: CCE + - name: CC5P + description: Capture/Compare %s output Polarity. + bit_offset: 17 + bit_size: 1 + enum: CCP + - name: CC6E + description: Capture/Compare %s output enable. + bit_offset: 20 + bit_size: 1 + enum: CCE + - name: CC6P + description: Capture/Compare %s output Polarity. + bit_offset: 21 + bit_size: 1 + enum: CCP fieldset/CCMR1_Input: description: TIM1 capture/compare mode register 1 [alternate]. fields: @@ -271,77 +346,93 @@ fieldset/CCMR1_Input: bit_offset: 0 bit_size: 2 enum: CC1S - - name: ICPSC + - name: IC1PSC description: Input capture %s prescaler. bit_offset: 2 bit_size: 2 - array: - len: 2 - stride: 8 enum: ICPSC - - name: ICF + - name: IC1F description: Input capture %s filter. bit_offset: 4 bit_size: 4 - array: - len: 2 - stride: 8 enum: ICF - name: CC2S description: 'Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).' bit_offset: 8 bit_size: 2 enum: CC2S + - name: IC2PSC + description: Input capture %s prescaler. + bit_offset: 10 + bit_size: 2 + enum: ICPSC + - name: IC2F + description: Input capture %s filter. + bit_offset: 12 + bit_size: 4 + enum: ICF fieldset/CCMR1_Output: description: TIM1 capture/compare mode register 1 [alternate]. fields: - - name: CCS + - name: CC1S description: Capture/Compare %s selection. bit_offset: 0 bit_size: 2 - array: - len: 2 - stride: 8 enum: CCS - - name: OCFE + - name: OC1FE description: Output compare %s fast enable. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCFE - - name: OCPE + - name: OC1PE description: Output compare %s preload enable. bit_offset: 3 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCPE - - name: OCM + - name: OC1M description: Output compare %s mode. bit_offset: 4 bit_size: 3 - array: - len: 2 - stride: 8 enum: OCM - - name: OCCE + - name: OC1CE description: Output compare %s clear enable. bit_offset: 7 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCCE - - name: OCM_3 + - name: CC2S + description: Capture/Compare %s selection. + bit_offset: 8 + bit_size: 2 + enum: CCS + - name: OC2FE + description: Output compare %s fast enable. + bit_offset: 10 + bit_size: 1 + enum: OCFE + - name: OC2PE + description: Output compare %s preload enable. + bit_offset: 11 + bit_size: 1 + enum: OCPE + - name: OC2M + description: Output compare %s mode. + bit_offset: 12 + bit_size: 3 + enum: OCM + - name: OC2CE + description: Output compare %s clear enable. + bit_offset: 15 + bit_size: 1 + enum: OCCE + - name: OC1M_3 description: Output compare %s mode, bit 3. bit_offset: 16 bit_size: 1 - array: - len: 2 - stride: 8 + enum: OCM_3 + - name: OC2M_3 + description: Output compare %s mode, bit 3. + bit_offset: 24 + bit_size: 1 enum: OCM_3 fieldset/CCMR2_Input: description: TIM1 capture/compare mode register 2 [alternate]. @@ -491,22 +582,51 @@ fieldset/CR2: bit_offset: 7 bit_size: 1 enum: TI1S - - name: OIS + - name: OIS1 description: Output Idle state (OC%s output). bit_offset: 8 bit_size: 1 - array: - len: 6 - stride: 2 enum: OIS - - name: OISN + - name: OIS1N description: Output Idle state (OC%sN output). bit_offset: 9 bit_size: 1 - array: - len: 3 - stride: 2 enum: OISN + - name: OIS2 + description: Output Idle state (OC%s output). + bit_offset: 10 + bit_size: 1 + enum: OIS + - name: OIS2N + description: Output Idle state (OC%sN output). + bit_offset: 11 + bit_size: 1 + enum: OISN + - name: OIS3 + description: Output Idle state (OC%s output). + bit_offset: 12 + bit_size: 1 + enum: OIS + - name: OIS3N + description: Output Idle state (OC%sN output). + bit_offset: 13 + bit_size: 1 + enum: OISN + - name: OIS4 + description: Output Idle state (OC%s output). + bit_offset: 14 + bit_size: 1 + enum: OIS + - name: OIS5 + description: Output Idle state (OC%s output). + bit_offset: 16 + bit_size: 1 + enum: OIS + - name: OIS6 + description: Output Idle state (OC%s output). + bit_offset: 18 + bit_size: 1 + enum: OIS - name: MMS2 description: 'Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.' bit_offset: 20 @@ -532,13 +652,25 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 enum: UIE - - name: CCIE + - name: CC1IE description: Capture/Compare %s interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIE + - name: CC2IE + description: Capture/Compare %s interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CCIE + - name: CC3IE + description: Capture/Compare %s interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CCIE + - name: CC4IE + description: Capture/Compare %s interrupt enable. + bit_offset: 4 + bit_size: 1 enum: CCIE - name: COMIE description: COM interrupt enable. @@ -560,13 +692,25 @@ fieldset/DIER: bit_offset: 8 bit_size: 1 enum: UDE - - name: CCDE + - name: CC1DE description: Capture/Compare %s DMA request enable. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCDE + - name: CC2DE + description: Capture/Compare %s DMA request enable. + bit_offset: 10 + bit_size: 1 + enum: CCDE + - name: CC3DE + description: Capture/Compare %s DMA request enable. + bit_offset: 11 + bit_size: 1 + enum: CCDE + - name: CC4DE + description: Capture/Compare %s DMA request enable. + bit_offset: 12 + bit_size: 1 enum: CCDE - name: COMDE description: COM DMA request enable. @@ -594,13 +738,25 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 enum: UG - - name: CCG + - name: CC1G description: Capture/compare %s generation. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCG + - name: CC2G + description: Capture/compare %s generation. + bit_offset: 2 + bit_size: 1 + enum: CCG + - name: CC3G + description: Capture/compare %s generation. + bit_offset: 3 + bit_size: 1 + enum: CCG + - name: CC4G + description: Capture/compare %s generation. + bit_offset: 4 + bit_size: 1 enum: CCG - name: COMG description: 'Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output.' @@ -694,13 +850,25 @@ fieldset/SR: bit_offset: 0 bit_size: 1 enum: UIF - - name: CCIF + - name: CC1IF description: Capture/compare %s interrupt flag. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIF + - name: CC2IF + description: Capture/compare %s interrupt flag. + bit_offset: 2 + bit_size: 1 + enum: CCIF + - name: CC3IF + description: Capture/compare %s interrupt flag. + bit_offset: 3 + bit_size: 1 + enum: CCIF + - name: CC4IF + description: Capture/compare %s interrupt flag. + bit_offset: 4 + bit_size: 1 enum: CCIF - name: COMIF description: COM interrupt flag. @@ -722,13 +890,25 @@ fieldset/SR: bit_offset: 8 bit_size: 1 enum: B2IF - - name: CCOF + - name: CC1OF description: Capture/Compare %s overcapture flag. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCOF + - name: CC2OF + description: Capture/Compare %s overcapture flag. + bit_offset: 10 + bit_size: 1 + enum: CCOF + - name: CC3OF + description: Capture/Compare %s overcapture flag. + bit_offset: 11 + bit_size: 1 + enum: CCOF + - name: CC4OF + description: Capture/Compare %s overcapture flag. + bit_offset: 12 + bit_size: 1 enum: CCOF - name: SBIF description: System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation. diff --git a/base/STM32C011/TIM14.yaml b/head/STM32C011/TIM14.yaml index c1d971a..ab0d3ef 100644 --- a/base/STM32C011/TIM14.yaml +++ b/head/STM32C011/TIM14.yaml @@ -53,11 +53,8 @@ block/TIM14: byte_offset: 44 bit_size: 16 fieldset: ARR - - name: CCR + - name: CCR1 description: capture/compare register. - array: - len: 1 - stride: 2 byte_offset: 52 bit_size: 16 fieldset: CCR @@ -78,29 +75,20 @@ fieldset/CCER: description: TIM14 capture/compare enable register. bit_size: 16 fields: - - name: CCE + - name: CC1E description: Capture/Compare %s output enable. bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCE - - name: CCP + - name: CC1P description: Capture/Compare %s output Polarity. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCP - - name: CCNP + - name: CC1NP description: Capture/Compare %s output Polarity. bit_offset: 3 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/CCMR1_Input: description: TIM14 capture/compare mode register 1 [alternate]. fields: @@ -109,64 +97,43 @@ fieldset/CCMR1_Input: bit_offset: 0 bit_size: 2 enum: CC1S - - name: ICPSC + - name: IC1PSC description: Input capture %s prescaler. bit_offset: 2 bit_size: 2 - array: - len: 1 - stride: 0 enum: ICPSC - - name: ICF + - name: IC1F description: Input capture %s filter. bit_offset: 4 bit_size: 4 - array: - len: 1 - stride: 0 enum: ICF fieldset/CCMR1_Output: description: TIM14 capture/compare mode register 1 [alternate]. fields: - - name: CCS + - name: CC1S description: Capture/Compare %s selection. bit_offset: 0 bit_size: 2 - array: - len: 1 - stride: 0 enum: CCS - - name: OCFE + - name: OC1FE description: Output compare %s fast enable. bit_offset: 2 bit_size: 1 - array: - len: 1 - stride: 0 enum: OCFE - - name: OCPE + - name: OC1PE description: Output compare %s preload enable. bit_offset: 3 bit_size: 1 - array: - len: 1 - stride: 0 enum: OCPE - - name: OCM + - name: OC1M description: Output compare %s mode. bit_offset: 4 bit_size: 3 - array: - len: 1 - stride: 0 enum: OCM - - name: OCM_3 + - name: OC1M_3 description: Output compare %s mode, bit 3. bit_offset: 16 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/CCR: description: capture/compare register. bit_size: 16 @@ -241,13 +208,10 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 enum: UIE - - name: CCIE + - name: CC1IE description: Capture/Compare %s interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCIE fieldset/EGR: description: TIM14 event generation register. @@ -258,13 +222,10 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 enum: UG - - name: CCG + - name: CC1G description: Capture/compare %s generation. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCG fieldset/PSC: description: TIM14 prescaler. @@ -283,21 +244,15 @@ fieldset/SR: bit_offset: 0 bit_size: 1 enum: UIF - - name: CCIF + - name: CC1IF description: Capture/compare %s interrupt flag. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCIF - - name: CCOF + - name: CC1OF description: Capture/Compare %s overcapture flag. bit_offset: 9 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCOF fieldset/TISEL: description: TIM14 timer input selection register. diff --git a/base/STM32C011/TIM16.yaml b/head/STM32C011/TIM16.yaml index 2f2accf..438d8f0 100644 --- a/base/STM32C011/TIM16.yaml +++ b/head/STM32C011/TIM16.yaml @@ -63,11 +63,8 @@ block/TIM16: byte_offset: 48 bit_size: 16 fieldset: RCR - - name: CCR + - name: CCR1 description: capture/compare register. - array: - len: 1 - stride: 2 byte_offset: 52 bit_size: 16 fieldset: CCR @@ -170,37 +167,25 @@ fieldset/CCER: description: TIM16 capture/compare enable register. bit_size: 16 fields: - - name: CCE + - name: CC1E description: Capture/Compare %s output enable. bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCE - - name: CCP + - name: CC1P description: Capture/Compare %s output Polarity. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCP - - name: CCNE + - name: CC1NE description: Capture/Compare %s complementary output enable. bit_offset: 2 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCNE - - name: CCNP + - name: CC1NP description: Capture/Compare %s output Polarity. bit_offset: 3 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCNP fieldset/CCMR1_Input: description: TIM16 capture/compare mode register 1 [alternate]. @@ -210,64 +195,43 @@ fieldset/CCMR1_Input: bit_offset: 0 bit_size: 2 enum: CC1S - - name: ICPSC + - name: IC1PSC description: Input capture %s prescaler. bit_offset: 2 bit_size: 2 - array: - len: 1 - stride: 0 enum: ICPSC - - name: ICF + - name: IC1F description: Input capture %s filter. bit_offset: 4 bit_size: 4 - array: - len: 1 - stride: 0 enum: ICF fieldset/CCMR1_Output: description: TIM16 capture/compare mode register 1 [alternate]. fields: - - name: CCS + - name: CC1S description: Capture/Compare %s selection. bit_offset: 0 bit_size: 2 - array: - len: 1 - stride: 0 enum: CCS - - name: OCFE + - name: OC1FE description: Output compare %s fast enable. bit_offset: 2 bit_size: 1 - array: - len: 1 - stride: 0 enum: OCFE - - name: OCPE + - name: OC1PE description: Output compare %s preload enable. bit_offset: 3 bit_size: 1 - array: - len: 1 - stride: 0 enum: OCPE - - name: OCM + - name: OC1M description: Output compare %s mode. bit_offset: 4 bit_size: 3 - array: - len: 1 - stride: 0 enum: OCM - - name: OCM_3 + - name: OC1M_3 description: Output compare %s mode, bit 3. bit_offset: 16 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/CCR: description: capture/compare register. bit_size: 16 @@ -352,21 +316,15 @@ fieldset/CR2: bit_offset: 3 bit_size: 1 enum: CCDS - - name: OIS + - name: OIS1 description: Output Idle state (OC%s output). bit_offset: 8 bit_size: 1 - array: - len: 1 - stride: 0 enum: OIS - - name: OISN + - name: OIS1N description: Output Idle state (OC%sN output). bit_offset: 9 bit_size: 1 - array: - len: 1 - stride: 0 enum: OISN fieldset/DCR: description: TIM16 DMA control register. @@ -389,13 +347,10 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 enum: UIE - - name: CCIE + - name: CC1IE description: Capture/Compare %s interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCIE - name: COMIE description: COM interrupt enable. @@ -412,13 +367,10 @@ fieldset/DIER: bit_offset: 8 bit_size: 1 enum: UDE - - name: CCDE + - name: CC1DE description: Capture/Compare %s DMA request enable. bit_offset: 9 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCDE fieldset/DMAR: description: TIM16 DMA address for full transfer. @@ -437,13 +389,10 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 enum: UG - - name: CCG + - name: CC1G description: Capture/compare %s generation. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCG - name: COMG description: 'Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output.' @@ -480,13 +429,10 @@ fieldset/SR: bit_offset: 0 bit_size: 1 enum: UIF - - name: CCIF + - name: CC1IF description: Capture/compare %s interrupt flag. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCIF - name: COMIF description: COM interrupt flag. @@ -498,13 +444,10 @@ fieldset/SR: bit_offset: 7 bit_size: 1 enum: BIF - - name: CCOF + - name: CC1OF description: Capture/Compare %s overcapture flag. bit_offset: 9 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCOF fieldset/TISEL: description: TIM16 input selection register. diff --git a/base/STM32C011/TIM3.yaml b/head/STM32C011/TIM3.yaml index a30f7f7..8e04cce 100644 --- a/base/STM32C011/TIM3.yaml +++ b/head/STM32C011/TIM3.yaml @@ -70,14 +70,26 @@ block/TIM3: byte_offset: 44 bit_size: 16 fieldset: ARR - - name: CCR + - name: CCR1 description: capture/compare register. - array: - len: 4 - stride: 4 byte_offset: 52 bit_size: 16 fieldset: CCR + - name: CCR2 + description: capture/compare register. + byte_offset: 56 + bit_size: 16 + fieldset: CCR + - name: CCR3 + description: capture/compare register. + byte_offset: 60 + bit_size: 16 + fieldset: CCR + - name: CCR4 + description: capture/compare register. + byte_offset: 64 + bit_size: 16 + fieldset: CCR - name: DCR description: TIM3 DMA control register. byte_offset: 72 @@ -115,29 +127,62 @@ fieldset/CCER: description: TIM3 capture/compare enable register. bit_size: 16 fields: - - name: CCE + - name: CC1E description: Capture/Compare %s output enable. bit_offset: 0 bit_size: 1 - array: - len: 4 - stride: 4 enum: CCE - - name: CCP + - name: CC1P description: Capture/Compare %s output Polarity. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 4 enum: CCP - - name: CCNP + - name: CC1NP description: Capture/Compare %s output Polarity. bit_offset: 3 bit_size: 1 - array: - len: 4 - stride: 4 + - name: CC2E + description: Capture/Compare %s output enable. + bit_offset: 4 + bit_size: 1 + enum: CCE + - name: CC2P + description: Capture/Compare %s output Polarity. + bit_offset: 5 + bit_size: 1 + enum: CCP + - name: CC2NP + description: Capture/Compare %s output Polarity. + bit_offset: 7 + bit_size: 1 + - name: CC3E + description: Capture/Compare %s output enable. + bit_offset: 8 + bit_size: 1 + enum: CCE + - name: CC3P + description: Capture/Compare %s output Polarity. + bit_offset: 9 + bit_size: 1 + enum: CCP + - name: CC3NP + description: Capture/Compare %s output Polarity. + bit_offset: 11 + bit_size: 1 + - name: CC4E + description: Capture/Compare %s output enable. + bit_offset: 12 + bit_size: 1 + enum: CCE + - name: CC4P + description: Capture/Compare %s output Polarity. + bit_offset: 13 + bit_size: 1 + enum: CCP + - name: CC4NP + description: Capture/Compare %s output Polarity. + bit_offset: 15 + bit_size: 1 fieldset/CCMR1_Input: description: TIM3 capture/compare mode register 1 [alternate]. fields: @@ -146,77 +191,93 @@ fieldset/CCMR1_Input: bit_offset: 0 bit_size: 2 enum: CC1S - - name: ICPSC + - name: IC1PSC description: Input capture %s prescaler. bit_offset: 2 bit_size: 2 - array: - len: 2 - stride: 8 enum: ICPSC - - name: ICF + - name: IC1F description: Input capture %s filter. bit_offset: 4 bit_size: 4 - array: - len: 2 - stride: 8 enum: ICF - name: CC2S description: 'Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).' bit_offset: 8 bit_size: 2 enum: CC2S + - name: IC2PSC + description: Input capture %s prescaler. + bit_offset: 10 + bit_size: 2 + enum: ICPSC + - name: IC2F + description: Input capture %s filter. + bit_offset: 12 + bit_size: 4 + enum: ICF fieldset/CCMR1_Output: description: TIM3 capture/compare mode register 1 [alternate]. fields: - - name: CCS + - name: CC1S description: Capture/Compare %s selection. bit_offset: 0 bit_size: 2 - array: - len: 2 - stride: 8 enum: CCS - - name: OCFE + - name: OC1FE description: Output compare %s fast enable. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCFE - - name: OCPE + - name: OC1PE description: Output compare %s preload enable. bit_offset: 3 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCPE - - name: OCM + - name: OC1M description: Output compare %s mode. bit_offset: 4 bit_size: 3 - array: - len: 2 - stride: 8 enum: OCM - - name: OCCE + - name: OC1CE description: Output compare %s clear enable. bit_offset: 7 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCCE - - name: OCM_3 + - name: CC2S + description: Capture/Compare %s selection. + bit_offset: 8 + bit_size: 2 + enum: CCS + - name: OC2FE + description: Output compare %s fast enable. + bit_offset: 10 + bit_size: 1 + enum: OCFE + - name: OC2PE + description: Output compare %s preload enable. + bit_offset: 11 + bit_size: 1 + enum: OCPE + - name: OC2M + description: Output compare %s mode. + bit_offset: 12 + bit_size: 3 + enum: OCM + - name: OC2CE + description: Output compare %s clear enable. + bit_offset: 15 + bit_size: 1 + enum: OCCE + - name: OC1M_3 description: Output compare %s mode, bit 3. bit_offset: 16 bit_size: 1 - array: - len: 2 - stride: 8 + enum: OCM_3 + - name: OC2M_3 + description: Output compare %s mode, bit 3. + bit_offset: 24 + bit_size: 1 enum: OCM_3 fieldset/CCMR2_Input: description: TIM3 capture/compare mode register 2 [alternate]. @@ -348,13 +409,25 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 enum: UIE - - name: CCIE + - name: CC1IE description: Capture/Compare %s interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIE + - name: CC2IE + description: Capture/Compare %s interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CCIE + - name: CC3IE + description: Capture/Compare %s interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CCIE + - name: CC4IE + description: Capture/Compare %s interrupt enable. + bit_offset: 4 + bit_size: 1 enum: CCIE - name: TIE description: Trigger interrupt enable. @@ -366,13 +439,25 @@ fieldset/DIER: bit_offset: 8 bit_size: 1 enum: UDE - - name: CCDE + - name: CC1DE description: Capture/Compare %s DMA request enable. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCDE + - name: CC2DE + description: Capture/Compare %s DMA request enable. + bit_offset: 10 + bit_size: 1 + enum: CCDE + - name: CC3DE + description: Capture/Compare %s DMA request enable. + bit_offset: 11 + bit_size: 1 + enum: CCDE + - name: CC4DE + description: Capture/Compare %s DMA request enable. + bit_offset: 12 + bit_size: 1 enum: CCDE - name: TDE description: Trigger DMA request enable. @@ -396,13 +481,25 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 enum: UG - - name: CCG + - name: CC1G description: Capture/compare %s generation. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCG + - name: CC2G + description: Capture/compare %s generation. + bit_offset: 2 + bit_size: 1 + enum: CCG + - name: CC3G + description: Capture/compare %s generation. + bit_offset: 3 + bit_size: 1 + enum: CCG + - name: CC4G + description: Capture/compare %s generation. + bit_offset: 4 + bit_size: 1 enum: CCG - name: TG description: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. @@ -474,26 +571,50 @@ fieldset/SR: bit_offset: 0 bit_size: 1 enum: UIF - - name: CCIF + - name: CC1IF description: Capture/compare %s interrupt flag. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIF + - name: CC2IF + description: Capture/compare %s interrupt flag. + bit_offset: 2 + bit_size: 1 + enum: CCIF + - name: CC3IF + description: Capture/compare %s interrupt flag. + bit_offset: 3 + bit_size: 1 + enum: CCIF + - name: CC4IF + description: Capture/compare %s interrupt flag. + bit_offset: 4 + bit_size: 1 enum: CCIF - name: TIF description: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. bit_offset: 6 bit_size: 1 enum: TIF - - name: CCOF + - name: CC1OF description: Capture/Compare %s overcapture flag. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCOF + - name: CC2OF + description: Capture/Compare %s overcapture flag. + bit_offset: 10 + bit_size: 1 + enum: CCOF + - name: CC3OF + description: Capture/Compare %s overcapture flag. + bit_offset: 11 + bit_size: 1 + enum: CCOF + - name: CC4OF + description: Capture/Compare %s overcapture flag. + bit_offset: 12 + bit_size: 1 enum: CCOF fieldset/TISEL: description: TIM3 timer input selection register. diff --git a/base/STM32F103/ADC1.yaml b/head/STM32F103/ADC1.yaml index 4e79983..acc84a0 100644 --- a/base/STM32F103/ADC1.yaml +++ b/head/STM32F103/ADC1.yaml @@ -21,13 +21,22 @@ block/ADC1: description: sample time register 2. byte_offset: 16 fieldset: SMPR2 - - name: JOFR + - name: JOFR1 description: injected channel data offset register %s. - array: - len: 4 - stride: 4 byte_offset: 20 fieldset: JOFR + - name: JOFR2 + description: injected channel data offset register %s. + byte_offset: 24 + fieldset: JOFR + - name: JOFR3 + description: injected channel data offset register %s. + byte_offset: 28 + fieldset: JOFR + - name: JOFR4 + description: injected channel data offset register %s. + byte_offset: 32 + fieldset: JOFR - name: HTR description: watchdog higher threshold register. byte_offset: 36 @@ -52,14 +61,26 @@ block/ADC1: description: injected sequence register. byte_offset: 56 fieldset: JSQR - - name: JDR + - name: JDR1 description: injected data register x. - array: - len: 4 - stride: 4 byte_offset: 60 access: Read fieldset: JDR + - name: JDR2 + description: injected data register x. + byte_offset: 64 + access: Read + fieldset: JDR + - name: JDR3 + description: injected data register x. + byte_offset: 68 + access: Read + fieldset: JDR + - name: JDR4 + description: injected data register x. + byte_offset: 72 + access: Read + fieldset: JDR - name: DR description: regular data register. byte_offset: 76 @@ -234,13 +255,22 @@ fieldset/JOFR: fieldset/JSQR: description: injected sequence register. fields: - - name: JSQ + - name: JSQ1 description: '%s conversion in injected sequence.' bit_offset: 0 bit_size: 5 - array: - len: 4 - stride: 5 + - name: JSQ2 + description: '%s conversion in injected sequence.' + bit_offset: 5 + bit_size: 5 + - name: JSQ3 + description: '%s conversion in injected sequence.' + bit_offset: 10 + bit_size: 5 + - name: JSQ4 + description: '%s conversion in injected sequence.' + bit_offset: 15 + bit_size: 5 - name: JL description: Injected sequence length. bit_offset: 20 @@ -255,13 +285,45 @@ fieldset/LTR: fieldset/SMPR1: description: sample time register 1. fields: - - name: SMP + - name: SMP10 description: Channel %s sample time selection. bit_offset: 0 bit_size: 3 - array: - len: 8 - stride: 3 + enum: SMP + - name: SMP11 + description: Channel %s sample time selection. + bit_offset: 3 + bit_size: 3 + enum: SMP + - name: SMP12 + description: Channel %s sample time selection. + bit_offset: 6 + bit_size: 3 + enum: SMP + - name: SMP13 + description: Channel %s sample time selection. + bit_offset: 9 + bit_size: 3 + enum: SMP + - name: SMP14 + description: Channel %s sample time selection. + bit_offset: 12 + bit_size: 3 + enum: SMP + - name: SMP15 + description: Channel %s sample time selection. + bit_offset: 15 + bit_size: 3 + enum: SMP + - name: SMP16 + description: Channel %s sample time selection. + bit_offset: 18 + bit_size: 3 + enum: SMP + - name: SMP17 + description: Channel %s sample time selection. + bit_offset: 21 + bit_size: 3 enum: SMP fieldset/SMPR2: description: sample time register 2. @@ -269,13 +331,22 @@ fieldset/SMPR2: fieldset/SQR1: description: regular sequence register 1. fields: - - name: SQ + - name: SQ13 description: '%s conversion in regular sequence.' bit_offset: 0 bit_size: 5 - array: - len: 4 - stride: 5 + - name: SQ14 + description: '%s conversion in regular sequence.' + bit_offset: 5 + bit_size: 5 + - name: SQ15 + description: '%s conversion in regular sequence.' + bit_offset: 10 + bit_size: 5 + - name: SQ16 + description: '%s conversion in regular sequence.' + bit_offset: 15 + bit_size: 5 - name: L description: Regular channel sequence length. bit_offset: 20 diff --git a/base/STM32F103/BKP.yaml b/head/STM32F103/BKP.yaml index c827a7f..db4f26e 100644 --- a/base/STM32F103/BKP.yaml +++ b/head/STM32F103/BKP.yaml @@ -1,13 +1,46 @@ block/BKP: description: Backup registers. items: - - name: DR + - name: DR1 description: Backup data register (BKP_DR). - array: - len: 10 - stride: 4 byte_offset: 0 fieldset: DR + - name: DR2 + description: Backup data register (BKP_DR). + byte_offset: 4 + fieldset: DR + - name: DR3 + description: Backup data register (BKP_DR). + byte_offset: 8 + fieldset: DR + - name: DR4 + description: Backup data register (BKP_DR). + byte_offset: 12 + fieldset: DR + - name: DR5 + description: Backup data register (BKP_DR). + byte_offset: 16 + fieldset: DR + - name: DR6 + description: Backup data register (BKP_DR). + byte_offset: 20 + fieldset: DR + - name: DR7 + description: Backup data register (BKP_DR). + byte_offset: 24 + fieldset: DR + - name: DR8 + description: Backup data register (BKP_DR). + byte_offset: 28 + fieldset: DR + - name: DR9 + description: Backup data register (BKP_DR). + byte_offset: 32 + fieldset: DR + - name: DR10 + description: Backup data register (BKP_DR). + byte_offset: 36 + fieldset: DR - name: RTCCR description: RTC clock calibration register (BKP_RTCCR). byte_offset: 40 @@ -20,13 +53,134 @@ block/BKP: description: BKP_CSR control/status register (BKP_CSR). byte_offset: 48 fieldset: CSR - - name: BKP_DR + - name: BKP_DR11 description: Backup data register (BKP_DR). - array: - len: 32 - stride: 4 byte_offset: 60 fieldset: BKP_DR + - name: BKP_DR12 + description: Backup data register (BKP_DR). + byte_offset: 64 + fieldset: BKP_DR + - name: BKP_DR13 + description: Backup data register (BKP_DR). + byte_offset: 68 + fieldset: BKP_DR + - name: BKP_DR14 + description: Backup data register (BKP_DR). + byte_offset: 72 + fieldset: BKP_DR + - name: BKP_DR15 + description: Backup data register (BKP_DR). + byte_offset: 76 + fieldset: BKP_DR + - name: BKP_DR16 + description: Backup data register (BKP_DR). + byte_offset: 80 + fieldset: BKP_DR + - name: BKP_DR17 + description: Backup data register (BKP_DR). + byte_offset: 84 + fieldset: BKP_DR + - name: BKP_DR18 + description: Backup data register (BKP_DR). + byte_offset: 88 + fieldset: BKP_DR + - name: BKP_DR19 + description: Backup data register (BKP_DR). + byte_offset: 92 + fieldset: BKP_DR + - name: BKP_DR20 + description: Backup data register (BKP_DR). + byte_offset: 96 + fieldset: BKP_DR + - name: BKP_DR21 + description: Backup data register (BKP_DR). + byte_offset: 100 + fieldset: BKP_DR + - name: BKP_DR22 + description: Backup data register (BKP_DR). + byte_offset: 104 + fieldset: BKP_DR + - name: BKP_DR23 + description: Backup data register (BKP_DR). + byte_offset: 108 + fieldset: BKP_DR + - name: BKP_DR24 + description: Backup data register (BKP_DR). + byte_offset: 112 + fieldset: BKP_DR + - name: BKP_DR25 + description: Backup data register (BKP_DR). + byte_offset: 116 + fieldset: BKP_DR + - name: BKP_DR26 + description: Backup data register (BKP_DR). + byte_offset: 120 + fieldset: BKP_DR + - name: BKP_DR27 + description: Backup data register (BKP_DR). + byte_offset: 124 + fieldset: BKP_DR + - name: BKP_DR28 + description: Backup data register (BKP_DR). + byte_offset: 128 + fieldset: BKP_DR + - name: BKP_DR29 + description: Backup data register (BKP_DR). + byte_offset: 132 + fieldset: BKP_DR + - name: BKP_DR30 + description: Backup data register (BKP_DR). + byte_offset: 136 + fieldset: BKP_DR + - name: BKP_DR31 + description: Backup data register (BKP_DR). + byte_offset: 140 + fieldset: BKP_DR + - name: BKP_DR32 + description: Backup data register (BKP_DR). + byte_offset: 144 + fieldset: BKP_DR + - name: BKP_DR33 + description: Backup data register (BKP_DR). + byte_offset: 148 + fieldset: BKP_DR + - name: BKP_DR34 + description: Backup data register (BKP_DR). + byte_offset: 152 + fieldset: BKP_DR + - name: BKP_DR35 + description: Backup data register (BKP_DR). + byte_offset: 156 + fieldset: BKP_DR + - name: BKP_DR36 + description: Backup data register (BKP_DR). + byte_offset: 160 + fieldset: BKP_DR + - name: BKP_DR37 + description: Backup data register (BKP_DR). + byte_offset: 164 + fieldset: BKP_DR + - name: BKP_DR38 + description: Backup data register (BKP_DR). + byte_offset: 168 + fieldset: BKP_DR + - name: BKP_DR39 + description: Backup data register (BKP_DR). + byte_offset: 172 + fieldset: BKP_DR + - name: BKP_DR40 + description: Backup data register (BKP_DR). + byte_offset: 176 + fieldset: BKP_DR + - name: BKP_DR41 + description: Backup data register (BKP_DR). + byte_offset: 180 + fieldset: BKP_DR + - name: BKP_DR42 + description: Backup data register (BKP_DR). + byte_offset: 184 + fieldset: BKP_DR fieldset/BKP_DR: description: Backup data register (BKP_DR). fields: diff --git a/base/STM32F103/CAN.yaml b/head/STM32F103/CAN.yaml index b1624ab..12007bf 100644 --- a/base/STM32F103/CAN.yaml +++ b/head/STM32F103/CAN.yaml @@ -13,13 +13,14 @@ block/CAN: description: CAN_TSR. byte_offset: 8 fieldset: TSR - - name: RFR + - name: RF0R description: CAN_RF%sR. - array: - len: 2 - stride: 4 byte_offset: 12 fieldset: RFR + - name: RF1R + description: CAN_RF%sR. + byte_offset: 16 + fieldset: RFR - name: IER description: CAN_IER. byte_offset: 20 @@ -32,20 +33,26 @@ block/CAN: description: CAN_BTR. byte_offset: 28 fieldset: BTR - - name: TX + - name: TX0 description: CAN Transmit cluster. - array: - len: 3 - stride: 16 byte_offset: 384 - block: TX - - name: RX + block: TX0 + - name: TX1 + description: CAN Transmit cluster. + byte_offset: 400 + block: TX1 + - name: TX2 + description: CAN Transmit cluster. + byte_offset: 416 + block: TX2 + - name: RX0 description: CAN Receive cluster. - array: - len: 2 - stride: 16 byte_offset: 432 - block: RX + block: RX0 + - name: RX1 + description: CAN Receive cluster. + byte_offset: 448 + block: RX1 - name: FMR description: CAN_FMR. byte_offset: 512 @@ -66,66 +73,319 @@ block/CAN: description: CAN_FA1R. byte_offset: 540 fieldset: FA1R - - name: FB + - name: FB0 description: CAN Filter Bank cluster. - array: - len: 14 - stride: 8 byte_offset: 576 - block: FB -block/FB: + block: FB0 + - name: FB1 + description: CAN Filter Bank cluster. + byte_offset: 584 + block: FB1 + - name: FB2 + description: CAN Filter Bank cluster. + byte_offset: 592 + block: FB2 + - name: FB3 + description: CAN Filter Bank cluster. + byte_offset: 600 + block: FB3 + - name: FB4 + description: CAN Filter Bank cluster. + byte_offset: 608 + block: FB4 + - name: FB5 + description: CAN Filter Bank cluster. + byte_offset: 616 + block: FB5 + - name: FB6 + description: CAN Filter Bank cluster. + byte_offset: 624 + block: FB6 + - name: FB7 + description: CAN Filter Bank cluster. + byte_offset: 632 + block: FB7 + - name: FB8 + description: CAN Filter Bank cluster. + byte_offset: 640 + block: FB8 + - name: FB9 + description: CAN Filter Bank cluster. + byte_offset: 648 + block: FB9 + - name: FB10 + description: CAN Filter Bank cluster. + byte_offset: 656 + block: FB10 + - name: FB11 + description: CAN Filter Bank cluster. + byte_offset: 664 + block: FB11 + - name: FB12 + description: CAN Filter Bank cluster. + byte_offset: 672 + block: FB12 + - name: FB13 + description: CAN Filter Bank cluster. + byte_offset: 680 + block: FB13 +block/FB0: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB0_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB0_FR2 +block/FB1: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB1_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB1_FR2 +block/FB10: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB10_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB10_FR2 +block/FB11: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB11_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB11_FR2 +block/FB12: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB12_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB12_FR2 +block/FB13: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB13_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB13_FR2 +block/FB2: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB2_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB2_FR2 +block/FB3: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB3_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB3_FR2 +block/FB4: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB4_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB4_FR2 +block/FB5: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB5_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB5_FR2 +block/FB6: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB6_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB6_FR2 +block/FB7: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB7_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB7_FR2 +block/FB8: + description: CAN Filter Bank cluster. + items: + - name: FR1 + description: Filter bank x register 1. + byte_offset: 0 + fieldset: FB8_FR1 + - name: FR2 + description: Filter bank x register 2. + byte_offset: 4 + fieldset: FB8_FR2 +block/FB9: description: CAN Filter Bank cluster. items: - name: FR1 description: Filter bank x register 1. byte_offset: 0 - fieldset: FR1 + fieldset: FB9_FR1 - name: FR2 description: Filter bank x register 2. byte_offset: 4 - fieldset: FR2 -block/RX: + fieldset: FB9_FR2 +block/RX0: + description: CAN Receive cluster. + items: + - name: RIR + description: CAN_RI0R. + byte_offset: 0 + access: Read + fieldset: RX0_RIR + - name: RDTR + description: CAN_RDT0R. + byte_offset: 4 + access: Read + fieldset: RX0_RDTR + - name: RDLR + description: CAN_RDL0R. + byte_offset: 8 + access: Read + fieldset: RX0_RDLR + - name: RDHR + description: CAN_RDH0R. + byte_offset: 12 + access: Read + fieldset: RX0_RDHR +block/RX1: description: CAN Receive cluster. items: - name: RIR description: CAN_RI0R. byte_offset: 0 access: Read - fieldset: RIR + fieldset: RX1_RIR - name: RDTR description: CAN_RDT0R. byte_offset: 4 access: Read - fieldset: RDTR + fieldset: RX1_RDTR - name: RDLR description: CAN_RDL0R. byte_offset: 8 access: Read - fieldset: RDLR + fieldset: RX1_RDLR - name: RDHR description: CAN_RDH0R. byte_offset: 12 access: Read - fieldset: RDHR -block/TX: + fieldset: RX1_RDHR +block/TX0: + description: CAN Transmit cluster. + items: + - name: TIR + description: CAN_TI0R. + byte_offset: 0 + fieldset: TX0_TIR + - name: TDTR + description: CAN_TDT0R. + byte_offset: 4 + fieldset: TX0_TDTR + - name: TDLR + description: CAN_TDL0R. + byte_offset: 8 + fieldset: TX0_TDLR + - name: TDHR + description: CAN_TDH0R. + byte_offset: 12 + fieldset: TX0_TDHR +block/TX1: + description: CAN Transmit cluster. + items: + - name: TIR + description: CAN_TI0R. + byte_offset: 0 + fieldset: TX1_TIR + - name: TDTR + description: CAN_TDT0R. + byte_offset: 4 + fieldset: TX1_TDTR + - name: TDLR + description: CAN_TDL0R. + byte_offset: 8 + fieldset: TX1_TDLR + - name: TDHR + description: CAN_TDH0R. + byte_offset: 12 + fieldset: TX1_TDHR +block/TX2: description: CAN Transmit cluster. items: - name: TIR description: CAN_TI0R. byte_offset: 0 - fieldset: TIR + fieldset: TX2_TIR - name: TDTR description: CAN_TDT0R. byte_offset: 4 - fieldset: TDTR + fieldset: TX2_TDTR - name: TDLR description: CAN_TDL0R. byte_offset: 8 - fieldset: TDLR + fieldset: TX2_TDLR - name: TDHR description: CAN_TDH0R. byte_offset: 12 - fieldset: TDHR + fieldset: TX2_TDHR fieldset/BTR: description: CAN_BTR. fields: @@ -186,73 +446,451 @@ fieldset/ESR: fieldset/FA1R: description: CAN_FA1R. fields: - - name: FACT + - name: FACT0 description: Filter active. bit_offset: 0 bit_size: 1 - array: - len: 14 - stride: 1 -fieldset/FFA1R: - description: CAN_FFA1R. + - name: FACT1 + description: Filter active. + bit_offset: 1 + bit_size: 1 + - name: FACT2 + description: Filter active. + bit_offset: 2 + bit_size: 1 + - name: FACT3 + description: Filter active. + bit_offset: 3 + bit_size: 1 + - name: FACT4 + description: Filter active. + bit_offset: 4 + bit_size: 1 + - name: FACT5 + description: Filter active. + bit_offset: 5 + bit_size: 1 + - name: FACT6 + description: Filter active. + bit_offset: 6 + bit_size: 1 + - name: FACT7 + description: Filter active. + bit_offset: 7 + bit_size: 1 + - name: FACT8 + description: Filter active. + bit_offset: 8 + bit_size: 1 + - name: FACT9 + description: Filter active. + bit_offset: 9 + bit_size: 1 + - name: FACT10 + description: Filter active. + bit_offset: 10 + bit_size: 1 + - name: FACT11 + description: Filter active. + bit_offset: 11 + bit_size: 1 + - name: FACT12 + description: Filter active. + bit_offset: 12 + bit_size: 1 + - name: FACT13 + description: Filter active. + bit_offset: 13 + bit_size: 1 +fieldset/FB0_FR1: + description: Filter bank x register 1. fields: - - name: FFA - description: Filter FIFO assignment for filter %s. + - name: FB + description: Filter bits. bit_offset: 0 - bit_size: 1 - array: - len: 14 - stride: 1 -fieldset/FM1R: - description: CAN_FM1R. + bit_size: 32 +fieldset/FB0_FR2: + description: Filter bank x register 2. fields: - - name: FBM - description: Filter mode. + - name: FB + description: Filter bits. bit_offset: 0 - bit_size: 1 - array: - len: 14 - stride: 1 -fieldset/FMR: - description: CAN_FMR. + bit_size: 32 +fieldset/FB10_FR1: + description: Filter bank x register 1. fields: - - name: FINIT - description: FINIT. + - name: FB + description: Filter bits. bit_offset: 0 - bit_size: 1 -fieldset/FR1: + bit_size: 32 +fieldset/FB10_FR2: + description: Filter bank x register 2. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB11_FR1: description: Filter bank x register 1. fields: - name: FB description: Filter bits. bit_offset: 0 bit_size: 32 -fieldset/FR2: +fieldset/FB11_FR2: description: Filter bank x register 2. fields: - name: FB description: Filter bits. bit_offset: 0 bit_size: 32 -fieldset/FS1R: - description: CAN_FS1R. +fieldset/FB12_FR1: + description: Filter bank x register 1. fields: - - name: FSC - description: Filter scale configuration. + - name: FB + description: Filter bits. bit_offset: 0 - bit_size: 1 - array: - len: 14 - stride: 1 -fieldset/IER: - description: CAN_IER. + bit_size: 32 +fieldset/FB12_FR2: + description: Filter bank x register 2. fields: - - name: TMEIE - description: TMEIE. + - name: FB + description: Filter bits. bit_offset: 0 - bit_size: 1 - enum: TMEIE - - name: FMPIE0 + bit_size: 32 +fieldset/FB13_FR1: + description: Filter bank x register 1. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB13_FR2: + description: Filter bank x register 2. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB1_FR1: + description: Filter bank x register 1. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB1_FR2: + description: Filter bank x register 2. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB2_FR1: + description: Filter bank x register 1. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB2_FR2: + description: Filter bank x register 2. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB3_FR1: + description: Filter bank x register 1. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB3_FR2: + description: Filter bank x register 2. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB4_FR1: + description: Filter bank x register 1. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB4_FR2: + description: Filter bank x register 2. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB5_FR1: + description: Filter bank x register 1. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB5_FR2: + description: Filter bank x register 2. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB6_FR1: + description: Filter bank x register 1. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB6_FR2: + description: Filter bank x register 2. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB7_FR1: + description: Filter bank x register 1. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB7_FR2: + description: Filter bank x register 2. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB8_FR1: + description: Filter bank x register 1. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB8_FR2: + description: Filter bank x register 2. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB9_FR1: + description: Filter bank x register 1. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FB9_FR2: + description: Filter bank x register 2. + fields: + - name: FB + description: Filter bits. + bit_offset: 0 + bit_size: 32 +fieldset/FFA1R: + description: CAN_FFA1R. + fields: + - name: FFA0 + description: Filter FIFO assignment for filter %s. + bit_offset: 0 + bit_size: 1 + - name: FFA1 + description: Filter FIFO assignment for filter %s. + bit_offset: 1 + bit_size: 1 + - name: FFA2 + description: Filter FIFO assignment for filter %s. + bit_offset: 2 + bit_size: 1 + - name: FFA3 + description: Filter FIFO assignment for filter %s. + bit_offset: 3 + bit_size: 1 + - name: FFA4 + description: Filter FIFO assignment for filter %s. + bit_offset: 4 + bit_size: 1 + - name: FFA5 + description: Filter FIFO assignment for filter %s. + bit_offset: 5 + bit_size: 1 + - name: FFA6 + description: Filter FIFO assignment for filter %s. + bit_offset: 6 + bit_size: 1 + - name: FFA7 + description: Filter FIFO assignment for filter %s. + bit_offset: 7 + bit_size: 1 + - name: FFA8 + description: Filter FIFO assignment for filter %s. + bit_offset: 8 + bit_size: 1 + - name: FFA9 + description: Filter FIFO assignment for filter %s. + bit_offset: 9 + bit_size: 1 + - name: FFA10 + description: Filter FIFO assignment for filter %s. + bit_offset: 10 + bit_size: 1 + - name: FFA11 + description: Filter FIFO assignment for filter %s. + bit_offset: 11 + bit_size: 1 + - name: FFA12 + description: Filter FIFO assignment for filter %s. + bit_offset: 12 + bit_size: 1 + - name: FFA13 + description: Filter FIFO assignment for filter %s. + bit_offset: 13 + bit_size: 1 +fieldset/FM1R: + description: CAN_FM1R. + fields: + - name: FBM0 + description: Filter mode. + bit_offset: 0 + bit_size: 1 + - name: FBM1 + description: Filter mode. + bit_offset: 1 + bit_size: 1 + - name: FBM2 + description: Filter mode. + bit_offset: 2 + bit_size: 1 + - name: FBM3 + description: Filter mode. + bit_offset: 3 + bit_size: 1 + - name: FBM4 + description: Filter mode. + bit_offset: 4 + bit_size: 1 + - name: FBM5 + description: Filter mode. + bit_offset: 5 + bit_size: 1 + - name: FBM6 + description: Filter mode. + bit_offset: 6 + bit_size: 1 + - name: FBM7 + description: Filter mode. + bit_offset: 7 + bit_size: 1 + - name: FBM8 + description: Filter mode. + bit_offset: 8 + bit_size: 1 + - name: FBM9 + description: Filter mode. + bit_offset: 9 + bit_size: 1 + - name: FBM10 + description: Filter mode. + bit_offset: 10 + bit_size: 1 + - name: FBM11 + description: Filter mode. + bit_offset: 11 + bit_size: 1 + - name: FBM12 + description: Filter mode. + bit_offset: 12 + bit_size: 1 + - name: FBM13 + description: Filter mode. + bit_offset: 13 + bit_size: 1 +fieldset/FMR: + description: CAN_FMR. + fields: + - name: FINIT + description: FINIT. + bit_offset: 0 + bit_size: 1 +fieldset/FS1R: + description: CAN_FS1R. + fields: + - name: FSC0 + description: Filter scale configuration. + bit_offset: 0 + bit_size: 1 + - name: FSC1 + description: Filter scale configuration. + bit_offset: 1 + bit_size: 1 + - name: FSC2 + description: Filter scale configuration. + bit_offset: 2 + bit_size: 1 + - name: FSC3 + description: Filter scale configuration. + bit_offset: 3 + bit_size: 1 + - name: FSC4 + description: Filter scale configuration. + bit_offset: 4 + bit_size: 1 + - name: FSC5 + description: Filter scale configuration. + bit_offset: 5 + bit_size: 1 + - name: FSC6 + description: Filter scale configuration. + bit_offset: 6 + bit_size: 1 + - name: FSC7 + description: Filter scale configuration. + bit_offset: 7 + bit_size: 1 + - name: FSC8 + description: Filter scale configuration. + bit_offset: 8 + bit_size: 1 + - name: FSC9 + description: Filter scale configuration. + bit_offset: 9 + bit_size: 1 + - name: FSC10 + description: Filter scale configuration. + bit_offset: 10 + bit_size: 1 + - name: FSC11 + description: Filter scale configuration. + bit_offset: 11 + bit_size: 1 + - name: FSC12 + description: Filter scale configuration. + bit_offset: 12 + bit_size: 1 + - name: FSC13 + description: Filter scale configuration. + bit_offset: 13 + bit_size: 1 +fieldset/IER: + description: CAN_IER. + fields: + - name: TMEIE + description: TMEIE. + bit_offset: 0 + bit_size: 1 + enum: TMEIE + - name: FMPIE0 description: FMPIE0. bit_offset: 1 bit_size: 1 @@ -360,115 +998,376 @@ fieldset/MCR: description: DBF. bit_offset: 16 bit_size: 1 -fieldset/MSR: - description: CAN_MSR. - fields: - - name: INAK - description: INAK. - bit_offset: 0 +fieldset/MSR: + description: CAN_MSR. + fields: + - name: INAK + description: INAK. + bit_offset: 0 + bit_size: 1 + - name: SLAK + description: SLAK. + bit_offset: 1 + bit_size: 1 + - name: ERRI + description: ERRI. + bit_offset: 2 + bit_size: 1 + - name: WKUI + description: WKUI. + bit_offset: 3 + bit_size: 1 + - name: SLAKI + description: SLAKI. + bit_offset: 4 + bit_size: 1 + - name: TXM + description: TXM. + bit_offset: 8 + bit_size: 1 + - name: RXM + description: RXM. + bit_offset: 9 + bit_size: 1 + - name: SAMP + description: SAMP. + bit_offset: 10 + bit_size: 1 + - name: RX + description: RX. + bit_offset: 11 + bit_size: 1 +fieldset/RFR: + description: CAN_RF%sR. + fields: + - name: FMP + description: FMP0. + bit_offset: 0 + bit_size: 2 + - name: FULL + description: FULL0. + bit_offset: 3 + bit_size: 1 + enum: FULL + - name: FOVR + description: FOVR0. + bit_offset: 4 + bit_size: 1 + enum: FOVR + - name: RFOM + description: RFOM0. + bit_offset: 5 + bit_size: 1 + enum: RFOM +fieldset/RX0_RDHR: + description: CAN_RDH0R. + fields: + - name: DATA4 + description: DATA%s. + bit_offset: 0 + bit_size: 8 + - name: DATA5 + description: DATA%s. + bit_offset: 8 + bit_size: 8 + - name: DATA6 + description: DATA%s. + bit_offset: 16 + bit_size: 8 + - name: DATA7 + description: DATA%s. + bit_offset: 24 + bit_size: 8 +fieldset/RX0_RDLR: + description: CAN_RDL0R. + fields: + - name: DATA0 + description: DATA%s. + bit_offset: 0 + bit_size: 8 + - name: DATA1 + description: DATA%s. + bit_offset: 8 + bit_size: 8 + - name: DATA2 + description: DATA%s. + bit_offset: 16 + bit_size: 8 + - name: DATA3 + description: DATA%s. + bit_offset: 24 + bit_size: 8 +fieldset/RX0_RDTR: + description: CAN_RDT0R. + fields: + - name: DLC + description: DLC. + bit_offset: 0 + bit_size: 4 + - name: FMI + description: FMI. + bit_offset: 8 + bit_size: 8 + - name: TIME + description: TIME. + bit_offset: 16 + bit_size: 16 +fieldset/RX0_RIR: + description: CAN_RI0R. + fields: + - name: RTR + description: RTR. + bit_offset: 1 + bit_size: 1 + enum: RX0_RIR_RTR + - name: IDE + description: IDE. + bit_offset: 2 + bit_size: 1 + enum: RX0_RIR_IDE + - name: EXID + description: EXID. + bit_offset: 3 + bit_size: 18 + - name: STID + description: STID. + bit_offset: 21 + bit_size: 11 +fieldset/RX1_RDHR: + description: CAN_RDH0R. + fields: + - name: DATA4 + description: DATA%s. + bit_offset: 0 + bit_size: 8 + - name: DATA5 + description: DATA%s. + bit_offset: 8 + bit_size: 8 + - name: DATA6 + description: DATA%s. + bit_offset: 16 + bit_size: 8 + - name: DATA7 + description: DATA%s. + bit_offset: 24 + bit_size: 8 +fieldset/RX1_RDLR: + description: CAN_RDL0R. + fields: + - name: DATA0 + description: DATA%s. + bit_offset: 0 + bit_size: 8 + - name: DATA1 + description: DATA%s. + bit_offset: 8 + bit_size: 8 + - name: DATA2 + description: DATA%s. + bit_offset: 16 + bit_size: 8 + - name: DATA3 + description: DATA%s. + bit_offset: 24 + bit_size: 8 +fieldset/RX1_RDTR: + description: CAN_RDT0R. + fields: + - name: DLC + description: DLC. + bit_offset: 0 + bit_size: 4 + - name: FMI + description: FMI. + bit_offset: 8 + bit_size: 8 + - name: TIME + description: TIME. + bit_offset: 16 + bit_size: 16 +fieldset/RX1_RIR: + description: CAN_RI0R. + fields: + - name: RTR + description: RTR. + bit_offset: 1 + bit_size: 1 + enum: RX1_RIR_RTR + - name: IDE + description: IDE. + bit_offset: 2 + bit_size: 1 + enum: RX1_RIR_IDE + - name: EXID + description: EXID. + bit_offset: 3 + bit_size: 18 + - name: STID + description: STID. + bit_offset: 21 + bit_size: 11 +fieldset/TSR: + description: CAN_TSR. + fields: + - name: RQCP0 + description: RQCP%s. + bit_offset: 0 + bit_size: 1 + - name: TXOK0 + description: TXOK%s. + bit_offset: 1 + bit_size: 1 + - name: ALST0 + description: ALST%s. + bit_offset: 2 + bit_size: 1 + - name: TERR0 + description: TERR%s. + bit_offset: 3 + bit_size: 1 + - name: ABRQ0 + description: ABRQ%s. + bit_offset: 7 + bit_size: 1 + - name: RQCP1 + description: RQCP%s. + bit_offset: 8 + bit_size: 1 + - name: TXOK1 + description: TXOK%s. + bit_offset: 9 + bit_size: 1 + - name: ALST1 + description: ALST%s. + bit_offset: 10 + bit_size: 1 + - name: TERR1 + description: TERR%s. + bit_offset: 11 + bit_size: 1 + - name: ABRQ1 + description: ABRQ%s. + bit_offset: 15 + bit_size: 1 + - name: RQCP2 + description: RQCP%s. + bit_offset: 16 + bit_size: 1 + - name: TXOK2 + description: TXOK%s. + bit_offset: 17 bit_size: 1 - - name: SLAK - description: SLAK. - bit_offset: 1 + - name: ALST2 + description: ALST%s. + bit_offset: 18 bit_size: 1 - - name: ERRI - description: ERRI. - bit_offset: 2 + - name: TERR2 + description: TERR%s. + bit_offset: 19 bit_size: 1 - - name: WKUI - description: WKUI. - bit_offset: 3 + - name: ABRQ2 + description: ABRQ%s. + bit_offset: 23 bit_size: 1 - - name: SLAKI - description: SLAKI. - bit_offset: 4 + - name: CODE + description: CODE. + bit_offset: 24 + bit_size: 2 + - name: TME0 + description: Lowest priority flag for mailbox %s. + bit_offset: 26 bit_size: 1 - - name: TXM - description: TXM. - bit_offset: 8 + - name: TME1 + description: Lowest priority flag for mailbox %s. + bit_offset: 27 bit_size: 1 - - name: RXM - description: RXM. - bit_offset: 9 + - name: TME2 + description: Lowest priority flag for mailbox %s. + bit_offset: 28 bit_size: 1 - - name: SAMP - description: SAMP. - bit_offset: 10 + - name: LOW0 + description: Lowest priority flag for mailbox %s. + bit_offset: 29 bit_size: 1 - - name: RX - description: RX. - bit_offset: 11 + - name: LOW1 + description: Lowest priority flag for mailbox %s. + bit_offset: 30 bit_size: 1 -fieldset/RDHR: - description: CAN_RDH0R. + - name: LOW2 + description: Lowest priority flag for mailbox %s. + bit_offset: 31 + bit_size: 1 +fieldset/TX0_TDHR: + description: CAN_TDH0R. fields: - - name: DATA + - name: DATA4 description: DATA%s. bit_offset: 0 bit_size: 8 - array: - len: 4 - stride: 8 -fieldset/RDLR: - description: CAN_RDL0R. + - name: DATA5 + description: DATA%s. + bit_offset: 8 + bit_size: 8 + - name: DATA6 + description: DATA%s. + bit_offset: 16 + bit_size: 8 + - name: DATA7 + description: DATA%s. + bit_offset: 24 + bit_size: 8 +fieldset/TX0_TDLR: + description: CAN_TDL0R. fields: - - name: DATA + - name: DATA0 description: DATA%s. bit_offset: 0 bit_size: 8 - array: - len: 4 - stride: 8 -fieldset/RDTR: - description: CAN_RDT0R. + - name: DATA1 + description: DATA%s. + bit_offset: 8 + bit_size: 8 + - name: DATA2 + description: DATA%s. + bit_offset: 16 + bit_size: 8 + - name: DATA3 + description: DATA%s. + bit_offset: 24 + bit_size: 8 +fieldset/TX0_TDTR: + description: CAN_TDT0R. fields: - name: DLC description: DLC. bit_offset: 0 bit_size: 4 - - name: FMI - description: FMI. + - name: TGT + description: TGT. bit_offset: 8 - bit_size: 8 + bit_size: 1 - name: TIME description: TIME. bit_offset: 16 bit_size: 16 -fieldset/RFR: - description: CAN_RF%sR. +fieldset/TX0_TIR: + description: CAN_TI0R. fields: - - name: FMP - description: FMP0. + - name: TXRQ + description: TXRQ. bit_offset: 0 - bit_size: 2 - - name: FULL - description: FULL0. - bit_offset: 3 - bit_size: 1 - enum: FULL - - name: FOVR - description: FOVR0. - bit_offset: 4 bit_size: 1 - enum: FOVR - - name: RFOM - description: RFOM0. - bit_offset: 5 - bit_size: 1 - enum: RFOM -fieldset/RIR: - description: CAN_RI0R. - fields: - name: RTR description: RTR. bit_offset: 1 bit_size: 1 - enum: RIR_RTR + enum: TX0_TIR_RTR - name: IDE description: IDE. bit_offset: 2 bit_size: 1 - enum: RIR_IDE + enum: TX0_TIR_IDE - name: EXID description: EXID. bit_offset: 3 @@ -477,27 +1376,45 @@ fieldset/RIR: description: STID. bit_offset: 21 bit_size: 11 -fieldset/TDHR: +fieldset/TX1_TDHR: description: CAN_TDH0R. fields: - - name: DATA + - name: DATA4 description: DATA%s. bit_offset: 0 bit_size: 8 - array: - len: 4 - stride: 8 -fieldset/TDLR: + - name: DATA5 + description: DATA%s. + bit_offset: 8 + bit_size: 8 + - name: DATA6 + description: DATA%s. + bit_offset: 16 + bit_size: 8 + - name: DATA7 + description: DATA%s. + bit_offset: 24 + bit_size: 8 +fieldset/TX1_TDLR: description: CAN_TDL0R. fields: - - name: DATA + - name: DATA0 description: DATA%s. bit_offset: 0 bit_size: 8 - array: - len: 4 - stride: 8 -fieldset/TDTR: + - name: DATA1 + description: DATA%s. + bit_offset: 8 + bit_size: 8 + - name: DATA2 + description: DATA%s. + bit_offset: 16 + bit_size: 8 + - name: DATA3 + description: DATA%s. + bit_offset: 24 + bit_size: 8 +fieldset/TX1_TDTR: description: CAN_TDT0R. fields: - name: DLC @@ -512,7 +1429,7 @@ fieldset/TDTR: description: TIME. bit_offset: 16 bit_size: 16 -fieldset/TIR: +fieldset/TX1_TIR: description: CAN_TI0R. fields: - name: TXRQ @@ -523,12 +1440,12 @@ fieldset/TIR: description: RTR. bit_offset: 1 bit_size: 1 - enum: TIR_RTR + enum: TX1_TIR_RTR - name: IDE description: IDE. bit_offset: 2 bit_size: 1 - enum: TIR_IDE + enum: TX1_TIR_IDE - name: EXID description: EXID. bit_offset: 3 @@ -537,62 +1454,84 @@ fieldset/TIR: description: STID. bit_offset: 21 bit_size: 11 -fieldset/TSR: - description: CAN_TSR. +fieldset/TX2_TDHR: + description: CAN_TDH0R. fields: - - name: RQCP - description: RQCP%s. + - name: DATA4 + description: DATA%s. + bit_offset: 0 + bit_size: 8 + - name: DATA5 + description: DATA%s. + bit_offset: 8 + bit_size: 8 + - name: DATA6 + description: DATA%s. + bit_offset: 16 + bit_size: 8 + - name: DATA7 + description: DATA%s. + bit_offset: 24 + bit_size: 8 +fieldset/TX2_TDLR: + description: CAN_TDL0R. + fields: + - name: DATA0 + description: DATA%s. + bit_offset: 0 + bit_size: 8 + - name: DATA1 + description: DATA%s. + bit_offset: 8 + bit_size: 8 + - name: DATA2 + description: DATA%s. + bit_offset: 16 + bit_size: 8 + - name: DATA3 + description: DATA%s. + bit_offset: 24 + bit_size: 8 +fieldset/TX2_TDTR: + description: CAN_TDT0R. + fields: + - name: DLC + description: DLC. + bit_offset: 0 + bit_size: 4 + - name: TGT + description: TGT. + bit_offset: 8 + bit_size: 1 + - name: TIME + description: TIME. + bit_offset: 16 + bit_size: 16 +fieldset/TX2_TIR: + description: CAN_TI0R. + fields: + - name: TXRQ + description: TXRQ. bit_offset: 0 bit_size: 1 - array: - len: 3 - stride: 8 - - name: TXOK - description: TXOK%s. + - name: RTR + description: RTR. bit_offset: 1 bit_size: 1 - array: - len: 3 - stride: 8 - - name: ALST - description: ALST%s. + enum: TX2_TIR_RTR + - name: IDE + description: IDE. bit_offset: 2 bit_size: 1 - array: - len: 3 - stride: 8 - - name: TERR - description: TERR%s. + enum: TX2_TIR_IDE + - name: EXID + description: EXID. bit_offset: 3 - bit_size: 1 - array: - len: 3 - stride: 8 - - name: ABRQ - description: ABRQ%s. - bit_offset: 7 - bit_size: 1 - array: - len: 3 - stride: 8 - - name: CODE - description: CODE. - bit_offset: 24 - bit_size: 2 - - name: TME - description: Lowest priority flag for mailbox %s. - bit_offset: 26 - bit_size: 1 - array: - len: 3 - stride: 1 - - name: LOW - description: Lowest priority flag for mailbox %s. - bit_offset: 29 - bit_size: 1 - array: - len: 3 - stride: 1 + bit_size: 18 + - name: STID + description: STID. + bit_offset: 21 + bit_size: 11 enum/BOFIE: bit_size: 1 variants: @@ -752,7 +1691,25 @@ enum/RFOM: - name: Release description: Set by software to release the output mailbox of the FIFO. value: 1 -enum/RIR_IDE: +enum/RX0_RIR_IDE: + bit_size: 1 + variants: + - name: Standard + description: Standard identifier. + value: 0 + - name: Extended + description: Extended identifier. + value: 1 +enum/RX0_RIR_RTR: + bit_size: 1 + variants: + - name: Data + description: Data frame. + value: 0 + - name: Remote + description: Remote frame. + value: 1 +enum/RX1_RIR_IDE: bit_size: 1 variants: - name: Standard @@ -761,7 +1718,7 @@ enum/RIR_IDE: - name: Extended description: Extended identifier. value: 1 -enum/RIR_RTR: +enum/RX1_RIR_RTR: bit_size: 1 variants: - name: Data @@ -788,7 +1745,16 @@ enum/SLKIE: - name: Enabled description: Interrupt generated when SLAKI bit is set. value: 1 -enum/TIR_IDE: +enum/TMEIE: + bit_size: 1 + variants: + - name: Disabled + description: No interrupt when RQCPx bit is set. + value: 0 + - name: Enabled + description: Interrupt generated when RQCPx bit is set. + value: 1 +enum/TX0_TIR_IDE: bit_size: 1 variants: - name: Standard @@ -797,7 +1763,7 @@ enum/TIR_IDE: - name: Extended description: Extended identifier. value: 1 -enum/TIR_RTR: +enum/TX0_TIR_RTR: bit_size: 1 variants: - name: Data @@ -806,14 +1772,41 @@ enum/TIR_RTR: - name: Remote description: Remote frame. value: 1 -enum/TMEIE: +enum/TX1_TIR_IDE: bit_size: 1 variants: - - name: Disabled - description: No interrupt when RQCPx bit is set. + - name: Standard + description: Standard identifier. value: 0 - - name: Enabled - description: Interrupt generated when RQCPx bit is set. + - name: Extended + description: Extended identifier. + value: 1 +enum/TX1_TIR_RTR: + bit_size: 1 + variants: + - name: Data + description: Data frame. + value: 0 + - name: Remote + description: Remote frame. + value: 1 +enum/TX2_TIR_IDE: + bit_size: 1 + variants: + - name: Standard + description: Standard identifier. + value: 0 + - name: Extended + description: Extended identifier. + value: 1 +enum/TX2_TIR_RTR: + bit_size: 1 + variants: + - name: Data + description: Data frame. + value: 0 + - name: Remote + description: Remote frame. value: 1 enum/WKUIE: bit_size: 1 diff --git a/base/STM32F103/DAC.yaml b/head/STM32F103/DAC.yaml index 0bf7aa1..c98a26f 100644 --- a/base/STM32F103/DAC.yaml +++ b/head/STM32F103/DAC.yaml @@ -10,27 +10,30 @@ block/DAC: byte_offset: 4 access: Write fieldset: SWTRIGR - - name: DHR12R + - name: DHR12R1 description: channel%s 12-bit right-aligned data holding register. - array: - len: 2 - stride: 12 byte_offset: 8 fieldset: DHR12R - - name: DHR12L + - name: DHR12L1 description: channel%s 12-bit left aligned data holding register. - array: - len: 2 - stride: 12 byte_offset: 12 fieldset: DHR12L - - name: DHR8R + - name: DHR8R1 description: channel%s 8-bit right aligned data holding register. - array: - len: 2 - stride: 12 byte_offset: 16 fieldset: DHR8R + - name: DHR12R2 + description: channel%s 12-bit right-aligned data holding register. + byte_offset: 20 + fieldset: DHR12R + - name: DHR12L2 + description: channel%s 12-bit left aligned data holding register. + byte_offset: 24 + fieldset: DHR12L + - name: DHR8R2 + description: channel%s 8-bit right aligned data holding register. + byte_offset: 28 + fieldset: DHR8R - name: DHR12RD description: Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved. byte_offset: 32 @@ -43,75 +46,89 @@ block/DAC: description: DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved. byte_offset: 40 fieldset: DHR8RD - - name: DOR + - name: DOR1 description: channel%s data output register. - array: - len: 2 - stride: 4 byte_offset: 44 access: Read fieldset: DOR + - name: DOR2 + description: channel%s data output register. + byte_offset: 48 + access: Read + fieldset: DOR fieldset/CR: description: Control register (DAC_CR). fields: - - name: EN + - name: EN1 description: DAC channel%s enable. bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 16 enum: EN - - name: BOFF + - name: BOFF1 description: DAC channel%s output buffer disable. bit_offset: 1 bit_size: 1 - array: - len: 2 - stride: 16 enum: BOFF - - name: TEN + - name: TEN1 description: DAC channel%s trigger enable. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 16 enum: TEN - name: TSEL1 description: DAC channel1 trigger selection. bit_offset: 3 bit_size: 3 enum: TSEL1 - - name: WAVE + - name: WAVE1 description: DAC channel%s noise/triangle wave generation enable. bit_offset: 6 bit_size: 2 - array: - len: 2 - stride: 16 enum: WAVE - - name: MAMP + - name: MAMP1 description: DAC channel%s mask/amplitude selector. bit_offset: 8 bit_size: 4 - array: - len: 2 - stride: 16 enum: MAMP - - name: DMAEN + - name: DMAEN1 description: DAC channel%s DMA enable. bit_offset: 12 bit_size: 1 - array: - len: 2 - stride: 16 enum: DMAEN + - name: EN2 + description: DAC channel%s enable. + bit_offset: 16 + bit_size: 1 + enum: EN + - name: BOFF2 + description: DAC channel%s output buffer disable. + bit_offset: 17 + bit_size: 1 + enum: BOFF + - name: TEN2 + description: DAC channel%s trigger enable. + bit_offset: 18 + bit_size: 1 + enum: TEN - name: TSEL2 description: DAC channel2 trigger selection. bit_offset: 19 bit_size: 3 enum: TSEL2 + - name: WAVE2 + description: DAC channel%s noise/triangle wave generation enable. + bit_offset: 22 + bit_size: 2 + enum: WAVE + - name: MAMP2 + description: DAC channel%s mask/amplitude selector. + bit_offset: 24 + bit_size: 4 + enum: MAMP + - name: DMAEN2 + description: DAC channel%s DMA enable. + bit_offset: 28 + bit_size: 1 + enum: DMAEN fieldset/DHR12L: description: channel%s 12-bit left aligned data holding register. fields: @@ -122,13 +139,14 @@ fieldset/DHR12L: fieldset/DHR12LD: description: DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved. fields: - - name: DACCDHR + - name: DACC1DHR description: DAC channel%s 12-bit left-aligned data. bit_offset: 4 bit_size: 12 - array: - len: 2 - stride: 16 + - name: DACC2DHR + description: DAC channel%s 12-bit left-aligned data. + bit_offset: 20 + bit_size: 12 fieldset/DHR12R: description: channel%s 12-bit right-aligned data holding register. fields: @@ -139,13 +157,14 @@ fieldset/DHR12R: fieldset/DHR12RD: description: Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved. fields: - - name: DACCDHR + - name: DACC1DHR description: DAC channel%s 12-bit right-aligned data. bit_offset: 0 bit_size: 12 - array: - len: 2 - stride: 16 + - name: DACC2DHR + description: DAC channel%s 12-bit right-aligned data. + bit_offset: 16 + bit_size: 12 fieldset/DHR8R: description: channel%s 8-bit right aligned data holding register. fields: @@ -156,13 +175,14 @@ fieldset/DHR8R: fieldset/DHR8RD: description: DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved. fields: - - name: DACCDHR + - name: DACC1DHR description: DAC channel%s 8-bit right-aligned data. bit_offset: 0 bit_size: 8 - array: - len: 2 - stride: 8 + - name: DACC2DHR + description: DAC channel%s 8-bit right-aligned data. + bit_offset: 8 + bit_size: 8 fieldset/DOR: description: channel%s data output register. fields: @@ -173,13 +193,15 @@ fieldset/DOR: fieldset/SWTRIGR: description: DAC software trigger register (DAC_SWTRIGR). fields: - - name: SWTRIG + - name: SWTRIG1 description: DAC channel%s software trigger. bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 + enum: SWTRIG + - name: SWTRIG2 + description: DAC channel%s software trigger. + bit_offset: 1 + bit_size: 1 enum: SWTRIG enum/BOFF: bit_size: 1 diff --git a/base/STM32F103/DMA1.yaml b/head/STM32F103/DMA1.yaml index 00a3961..8e40c6e 100644 --- a/base/STM32F103/DMA1.yaml +++ b/head/STM32F103/DMA1.yaml @@ -1,22 +1,136 @@ -block/CH: +block/CH1: description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' items: - name: CR description: DMA channel configuration register (DMA_CCR). byte_offset: 0 - fieldset: CR + fieldset: CH1_CR - name: NDTR description: DMA channel 1 number of data register. byte_offset: 4 - fieldset: NDTR + fieldset: CH1_NDTR - name: PAR description: DMA channel 1 peripheral address register. byte_offset: 8 - fieldset: PAR + fieldset: CH1_PAR - name: MAR description: DMA channel 1 memory address register. byte_offset: 12 - fieldset: MAR + fieldset: CH1_MAR +block/CH2: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: DMA channel configuration register (DMA_CCR). + byte_offset: 0 + fieldset: CH2_CR + - name: NDTR + description: DMA channel 1 number of data register. + byte_offset: 4 + fieldset: CH2_NDTR + - name: PAR + description: DMA channel 1 peripheral address register. + byte_offset: 8 + fieldset: CH2_PAR + - name: MAR + description: DMA channel 1 memory address register. + byte_offset: 12 + fieldset: CH2_MAR +block/CH3: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: DMA channel configuration register (DMA_CCR). + byte_offset: 0 + fieldset: CH3_CR + - name: NDTR + description: DMA channel 1 number of data register. + byte_offset: 4 + fieldset: CH3_NDTR + - name: PAR + description: DMA channel 1 peripheral address register. + byte_offset: 8 + fieldset: CH3_PAR + - name: MAR + description: DMA channel 1 memory address register. + byte_offset: 12 + fieldset: CH3_MAR +block/CH4: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: DMA channel configuration register (DMA_CCR). + byte_offset: 0 + fieldset: CH4_CR + - name: NDTR + description: DMA channel 1 number of data register. + byte_offset: 4 + fieldset: CH4_NDTR + - name: PAR + description: DMA channel 1 peripheral address register. + byte_offset: 8 + fieldset: CH4_PAR + - name: MAR + description: DMA channel 1 memory address register. + byte_offset: 12 + fieldset: CH4_MAR +block/CH5: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: DMA channel configuration register (DMA_CCR). + byte_offset: 0 + fieldset: CH5_CR + - name: NDTR + description: DMA channel 1 number of data register. + byte_offset: 4 + fieldset: CH5_NDTR + - name: PAR + description: DMA channel 1 peripheral address register. + byte_offset: 8 + fieldset: CH5_PAR + - name: MAR + description: DMA channel 1 memory address register. + byte_offset: 12 + fieldset: CH5_MAR +block/CH6: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: DMA channel configuration register (DMA_CCR). + byte_offset: 0 + fieldset: CH6_CR + - name: NDTR + description: DMA channel 1 number of data register. + byte_offset: 4 + fieldset: CH6_NDTR + - name: PAR + description: DMA channel 1 peripheral address register. + byte_offset: 8 + fieldset: CH6_PAR + - name: MAR + description: DMA channel 1 memory address register. + byte_offset: 12 + fieldset: CH6_MAR +block/CH7: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: DMA channel configuration register (DMA_CCR). + byte_offset: 0 + fieldset: CH7_CR + - name: NDTR + description: DMA channel 1 number of data register. + byte_offset: 4 + fieldset: CH7_NDTR + - name: PAR + description: DMA channel 1 peripheral address register. + byte_offset: 8 + fieldset: CH7_PAR + - name: MAR + description: DMA channel 1 memory address register. + byte_offset: 12 + fieldset: CH7_MAR block/DMA1: description: DMA controller. items: @@ -30,201 +144,1524 @@ block/DMA1: byte_offset: 4 access: Write fieldset: IFCR - - name: CH + - name: CH1 description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' - array: - len: 7 - stride: 20 byte_offset: 8 - block: CH -fieldset/CR: + block: CH1 + - name: CH2 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 28 + block: CH2 + - name: CH3 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 48 + block: CH3 + - name: CH4 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 68 + block: CH4 + - name: CH5 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 88 + block: CH5 + - name: CH6 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 108 + block: CH6 + - name: CH7 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 128 + block: CH7 +fieldset/CH1_CR: description: DMA channel configuration register (DMA_CCR). fields: - name: EN description: Channel enable. bit_offset: 0 bit_size: 1 - enum: EN + enum: CH1_CR_EN - name: TCIE description: Transfer complete interrupt enable. bit_offset: 1 bit_size: 1 - enum: TCIE + enum: CH1_CR_TCIE - name: HTIE description: Half Transfer interrupt enable. bit_offset: 2 bit_size: 1 - enum: HTIE + enum: CH1_CR_HTIE - name: TEIE description: Transfer error interrupt enable. bit_offset: 3 bit_size: 1 - enum: TEIE + enum: CH1_CR_TEIE - name: DIR description: Data transfer direction. bit_offset: 4 bit_size: 1 - enum: DIR + enum: CH1_CR_DIR - name: CIRC description: Circular mode. bit_offset: 5 bit_size: 1 - enum: CIRC + enum: CH1_CR_CIRC - name: PINC description: Peripheral increment mode. bit_offset: 6 bit_size: 1 - enum: PINC + enum: CH1_CR_PINC - name: MINC description: Memory increment mode. bit_offset: 7 bit_size: 1 - enum: MINC + enum: CH1_CR_MINC - name: PSIZE description: Peripheral size. bit_offset: 8 bit_size: 2 - enum: PSIZE + enum: CH1_CR_PSIZE - name: MSIZE description: Memory size. bit_offset: 10 bit_size: 2 - enum: MSIZE + enum: CH1_CR_MSIZE - name: PL description: Channel Priority level. bit_offset: 12 bit_size: 2 - enum: PL + enum: CH1_CR_PL - name: MEM2MEM description: Memory to memory mode. bit_offset: 14 bit_size: 1 - enum: MEM2MEM -fieldset/IFCR: - description: DMA interrupt flag clear register (DMA_IFCR). + enum: CH1_CR_MEM2MEM +fieldset/CH1_MAR: + description: DMA channel 1 memory address register. fields: - - name: CGIF - description: Channel %s Global interrupt clear. + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH1_NDTR: + description: DMA channel 1 number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH1_PAR: + description: DMA channel 1 peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/CH2_CR: + description: DMA channel configuration register (DMA_CCR). + fields: + - name: EN + description: Channel enable. bit_offset: 0 bit_size: 1 - array: - len: 7 - stride: 4 - enum: CGIF - - name: CTCIF - description: Channel %s Transfer Complete clear. + enum: CH2_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 7 - stride: 4 - enum: CTCIF - - name: CHTIF - description: Channel %s Half Transfer clear. + enum: CH2_CR_TCIE + - name: HTIE + description: Half Transfer interrupt enable. bit_offset: 2 bit_size: 1 - array: - len: 7 - stride: 4 - enum: CHTIF - - name: CTEIF - description: Channel %s Transfer Error clear. + enum: CH2_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. bit_offset: 3 bit_size: 1 - array: - len: 7 - stride: 4 - enum: CTEIF -fieldset/ISR: - description: DMA interrupt status register (DMA_ISR). + enum: CH2_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH2_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH2_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH2_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH2_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH2_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH2_CR_MSIZE + - name: PL + description: Channel Priority level. + bit_offset: 12 + bit_size: 2 + enum: CH2_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH2_CR_MEM2MEM +fieldset/CH2_MAR: + description: DMA channel 1 memory address register. fields: - - name: GIF - description: Channel %s Global interrupt flag. + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH2_NDTR: + description: DMA channel 1 number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH2_PAR: + description: DMA channel 1 peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/CH3_CR: + description: DMA channel configuration register (DMA_CCR). + fields: + - name: EN + description: Channel enable. bit_offset: 0 bit_size: 1 - array: - len: 7 - stride: 4 - enum: GIF - - name: TCIF - description: Channel %s Transfer Complete flag. + enum: CH3_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 7 - stride: 4 - enum: TCIF - - name: HTIF - description: Channel %s Half Transfer Complete flag. + enum: CH3_CR_TCIE + - name: HTIE + description: Half Transfer interrupt enable. bit_offset: 2 bit_size: 1 - array: - len: 7 - stride: 4 - enum: HTIF - - name: TEIF - description: Channel %s Transfer Error flag. + enum: CH3_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. bit_offset: 3 bit_size: 1 - array: - len: 7 - stride: 4 - enum: TEIF -fieldset/MAR: + enum: CH3_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH3_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH3_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH3_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH3_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH3_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH3_CR_MSIZE + - name: PL + description: Channel Priority level. + bit_offset: 12 + bit_size: 2 + enum: CH3_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH3_CR_MEM2MEM +fieldset/CH3_MAR: description: DMA channel 1 memory address register. fields: - name: MA description: Memory address. bit_offset: 0 bit_size: 32 -fieldset/NDTR: +fieldset/CH3_NDTR: description: DMA channel 1 number of data register. fields: - name: NDT description: Number of data to transfer. bit_offset: 0 bit_size: 16 -fieldset/PAR: +fieldset/CH3_PAR: description: DMA channel 1 peripheral address register. fields: - name: PA description: Peripheral address. bit_offset: 0 bit_size: 32 -enum/CGIF: +fieldset/CH4_CR: + description: DMA channel configuration register (DMA_CCR). + fields: + - name: EN + description: Channel enable. + bit_offset: 0 + bit_size: 1 + enum: CH4_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. + bit_offset: 1 + bit_size: 1 + enum: CH4_CR_TCIE + - name: HTIE + description: Half Transfer interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CH4_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CH4_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH4_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH4_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH4_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH4_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH4_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH4_CR_MSIZE + - name: PL + description: Channel Priority level. + bit_offset: 12 + bit_size: 2 + enum: CH4_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH4_CR_MEM2MEM +fieldset/CH4_MAR: + description: DMA channel 1 memory address register. + fields: + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH4_NDTR: + description: DMA channel 1 number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH4_PAR: + description: DMA channel 1 peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/CH5_CR: + description: DMA channel configuration register (DMA_CCR). + fields: + - name: EN + description: Channel enable. + bit_offset: 0 + bit_size: 1 + enum: CH5_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. + bit_offset: 1 + bit_size: 1 + enum: CH5_CR_TCIE + - name: HTIE + description: Half Transfer interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CH5_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CH5_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH5_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH5_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH5_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH5_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH5_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH5_CR_MSIZE + - name: PL + description: Channel Priority level. + bit_offset: 12 + bit_size: 2 + enum: CH5_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH5_CR_MEM2MEM +fieldset/CH5_MAR: + description: DMA channel 1 memory address register. + fields: + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH5_NDTR: + description: DMA channel 1 number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH5_PAR: + description: DMA channel 1 peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/CH6_CR: + description: DMA channel configuration register (DMA_CCR). + fields: + - name: EN + description: Channel enable. + bit_offset: 0 + bit_size: 1 + enum: CH6_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. + bit_offset: 1 + bit_size: 1 + enum: CH6_CR_TCIE + - name: HTIE + description: Half Transfer interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CH6_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CH6_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH6_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH6_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH6_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH6_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH6_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH6_CR_MSIZE + - name: PL + description: Channel Priority level. + bit_offset: 12 + bit_size: 2 + enum: CH6_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH6_CR_MEM2MEM +fieldset/CH6_MAR: + description: DMA channel 1 memory address register. + fields: + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH6_NDTR: + description: DMA channel 1 number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH6_PAR: + description: DMA channel 1 peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/CH7_CR: + description: DMA channel configuration register (DMA_CCR). + fields: + - name: EN + description: Channel enable. + bit_offset: 0 + bit_size: 1 + enum: CH7_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. + bit_offset: 1 + bit_size: 1 + enum: CH7_CR_TCIE + - name: HTIE + description: Half Transfer interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CH7_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CH7_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH7_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH7_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH7_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH7_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH7_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH7_CR_MSIZE + - name: PL + description: Channel Priority level. + bit_offset: 12 + bit_size: 2 + enum: CH7_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH7_CR_MEM2MEM +fieldset/CH7_MAR: + description: DMA channel 1 memory address register. + fields: + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH7_NDTR: + description: DMA channel 1 number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH7_PAR: + description: DMA channel 1 peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/IFCR: + description: DMA interrupt flag clear register (DMA_IFCR). + fields: + - name: CGIF1 + description: Channel %s Global interrupt clear. + bit_offset: 0 + bit_size: 1 + enum: CGIF + - name: CTCIF1 + description: Channel %s Transfer Complete clear. + bit_offset: 1 + bit_size: 1 + enum: CTCIF + - name: CHTIF1 + description: Channel %s Half Transfer clear. + bit_offset: 2 + bit_size: 1 + enum: CHTIF + - name: CTEIF1 + description: Channel %s Transfer Error clear. + bit_offset: 3 + bit_size: 1 + enum: CTEIF + - name: CGIF2 + description: Channel %s Global interrupt clear. + bit_offset: 4 + bit_size: 1 + enum: CGIF + - name: CTCIF2 + description: Channel %s Transfer Complete clear. + bit_offset: 5 + bit_size: 1 + enum: CTCIF + - name: CHTIF2 + description: Channel %s Half Transfer clear. + bit_offset: 6 + bit_size: 1 + enum: CHTIF + - name: CTEIF2 + description: Channel %s Transfer Error clear. + bit_offset: 7 + bit_size: 1 + enum: CTEIF + - name: CGIF3 + description: Channel %s Global interrupt clear. + bit_offset: 8 + bit_size: 1 + enum: CGIF + - name: CTCIF3 + description: Channel %s Transfer Complete clear. + bit_offset: 9 + bit_size: 1 + enum: CTCIF + - name: CHTIF3 + description: Channel %s Half Transfer clear. + bit_offset: 10 + bit_size: 1 + enum: CHTIF + - name: CTEIF3 + description: Channel %s Transfer Error clear. + bit_offset: 11 + bit_size: 1 + enum: CTEIF + - name: CGIF4 + description: Channel %s Global interrupt clear. + bit_offset: 12 + bit_size: 1 + enum: CGIF + - name: CTCIF4 + description: Channel %s Transfer Complete clear. + bit_offset: 13 + bit_size: 1 + enum: CTCIF + - name: CHTIF4 + description: Channel %s Half Transfer clear. + bit_offset: 14 + bit_size: 1 + enum: CHTIF + - name: CTEIF4 + description: Channel %s Transfer Error clear. + bit_offset: 15 + bit_size: 1 + enum: CTEIF + - name: CGIF5 + description: Channel %s Global interrupt clear. + bit_offset: 16 + bit_size: 1 + enum: CGIF + - name: CTCIF5 + description: Channel %s Transfer Complete clear. + bit_offset: 17 + bit_size: 1 + enum: CTCIF + - name: CHTIF5 + description: Channel %s Half Transfer clear. + bit_offset: 18 + bit_size: 1 + enum: CHTIF + - name: CTEIF5 + description: Channel %s Transfer Error clear. + bit_offset: 19 + bit_size: 1 + enum: CTEIF + - name: CGIF6 + description: Channel %s Global interrupt clear. + bit_offset: 20 + bit_size: 1 + enum: CGIF + - name: CTCIF6 + description: Channel %s Transfer Complete clear. + bit_offset: 21 + bit_size: 1 + enum: CTCIF + - name: CHTIF6 + description: Channel %s Half Transfer clear. + bit_offset: 22 + bit_size: 1 + enum: CHTIF + - name: CTEIF6 + description: Channel %s Transfer Error clear. + bit_offset: 23 + bit_size: 1 + enum: CTEIF + - name: CGIF7 + description: Channel %s Global interrupt clear. + bit_offset: 24 + bit_size: 1 + enum: CGIF + - name: CTCIF7 + description: Channel %s Transfer Complete clear. + bit_offset: 25 + bit_size: 1 + enum: CTCIF + - name: CHTIF7 + description: Channel %s Half Transfer clear. + bit_offset: 26 + bit_size: 1 + enum: CHTIF + - name: CTEIF7 + description: Channel %s Transfer Error clear. + bit_offset: 27 + bit_size: 1 + enum: CTEIF +fieldset/ISR: + description: DMA interrupt status register (DMA_ISR). + fields: + - name: GIF1 + description: Channel %s Global interrupt flag. + bit_offset: 0 + bit_size: 1 + enum: GIF + - name: TCIF1 + description: Channel %s Transfer Complete flag. + bit_offset: 1 + bit_size: 1 + enum: TCIF + - name: HTIF1 + description: Channel %s Half Transfer Complete flag. + bit_offset: 2 + bit_size: 1 + enum: HTIF + - name: TEIF1 + description: Channel %s Transfer Error flag. + bit_offset: 3 + bit_size: 1 + enum: TEIF + - name: GIF2 + description: Channel %s Global interrupt flag. + bit_offset: 4 + bit_size: 1 + enum: GIF + - name: TCIF2 + description: Channel %s Transfer Complete flag. + bit_offset: 5 + bit_size: 1 + enum: TCIF + - name: HTIF2 + description: Channel %s Half Transfer Complete flag. + bit_offset: 6 + bit_size: 1 + enum: HTIF + - name: TEIF2 + description: Channel %s Transfer Error flag. + bit_offset: 7 + bit_size: 1 + enum: TEIF + - name: GIF3 + description: Channel %s Global interrupt flag. + bit_offset: 8 + bit_size: 1 + enum: GIF + - name: TCIF3 + description: Channel %s Transfer Complete flag. + bit_offset: 9 + bit_size: 1 + enum: TCIF + - name: HTIF3 + description: Channel %s Half Transfer Complete flag. + bit_offset: 10 + bit_size: 1 + enum: HTIF + - name: TEIF3 + description: Channel %s Transfer Error flag. + bit_offset: 11 + bit_size: 1 + enum: TEIF + - name: GIF4 + description: Channel %s Global interrupt flag. + bit_offset: 12 + bit_size: 1 + enum: GIF + - name: TCIF4 + description: Channel %s Transfer Complete flag. + bit_offset: 13 + bit_size: 1 + enum: TCIF + - name: HTIF4 + description: Channel %s Half Transfer Complete flag. + bit_offset: 14 + bit_size: 1 + enum: HTIF + - name: TEIF4 + description: Channel %s Transfer Error flag. + bit_offset: 15 + bit_size: 1 + enum: TEIF + - name: GIF5 + description: Channel %s Global interrupt flag. + bit_offset: 16 + bit_size: 1 + enum: GIF + - name: TCIF5 + description: Channel %s Transfer Complete flag. + bit_offset: 17 + bit_size: 1 + enum: TCIF + - name: HTIF5 + description: Channel %s Half Transfer Complete flag. + bit_offset: 18 + bit_size: 1 + enum: HTIF + - name: TEIF5 + description: Channel %s Transfer Error flag. + bit_offset: 19 + bit_size: 1 + enum: TEIF + - name: GIF6 + description: Channel %s Global interrupt flag. + bit_offset: 20 + bit_size: 1 + enum: GIF + - name: TCIF6 + description: Channel %s Transfer Complete flag. + bit_offset: 21 + bit_size: 1 + enum: TCIF + - name: HTIF6 + description: Channel %s Half Transfer Complete flag. + bit_offset: 22 + bit_size: 1 + enum: HTIF + - name: TEIF6 + description: Channel %s Transfer Error flag. + bit_offset: 23 + bit_size: 1 + enum: TEIF + - name: GIF7 + description: Channel %s Global interrupt flag. + bit_offset: 24 + bit_size: 1 + enum: GIF + - name: TCIF7 + description: Channel %s Transfer Complete flag. + bit_offset: 25 + bit_size: 1 + enum: TCIF + - name: HTIF7 + description: Channel %s Half Transfer Complete flag. + bit_offset: 26 + bit_size: 1 + enum: HTIF + - name: TEIF7 + description: Channel %s Transfer Error flag. + bit_offset: 27 + bit_size: 1 + enum: TEIF +enum/CGIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register. + value: 1 +enum/CH1_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH1_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH1_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH1_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. + value: 1 +enum/CH1_CR_MEM2MEM: + bit_size: 1 + variants: + - name: Disabled + description: Memory to memory mode disabled. + value: 0 + - name: Enabled + description: Memory to memory mode enabled. + value: 1 +enum/CH1_CR_MINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH1_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH1_CR_PINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH1_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH1_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH1_CR_TCIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH1_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH2_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH2_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH2_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH2_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. + value: 1 +enum/CH2_CR_MEM2MEM: + bit_size: 1 + variants: + - name: Disabled + description: Memory to memory mode disabled. + value: 0 + - name: Enabled + description: Memory to memory mode enabled. + value: 1 +enum/CH2_CR_MINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH2_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH2_CR_PINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH2_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH2_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH2_CR_TCIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH2_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH3_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH3_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH3_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH3_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. + value: 1 +enum/CH3_CR_MEM2MEM: + bit_size: 1 + variants: + - name: Disabled + description: Memory to memory mode disabled. + value: 0 + - name: Enabled + description: Memory to memory mode enabled. + value: 1 +enum/CH3_CR_MINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH3_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH3_CR_PINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH3_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH3_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH3_CR_TCIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH3_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH4_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH4_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH4_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH4_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. + value: 1 +enum/CH4_CR_MEM2MEM: + bit_size: 1 + variants: + - name: Disabled + description: Memory to memory mode disabled. + value: 0 + - name: Enabled + description: Memory to memory mode enabled. + value: 1 +enum/CH4_CR_MINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH4_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH4_CR_PINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH4_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH4_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH4_CR_TCIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH4_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH5_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH5_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH5_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH5_CR_HTIE: bit_size: 1 variants: - - name: Clear - description: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register. + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. value: 1 -enum/CHTIF: +enum/CH5_CR_MEM2MEM: bit_size: 1 variants: - - name: Clear - description: Clears the HTIF flag in the ISR register. + - name: Disabled + description: Memory to memory mode disabled. + value: 0 + - name: Enabled + description: Memory to memory mode enabled. value: 1 -enum/CIRC: +enum/CH5_CR_MINC: bit_size: 1 variants: - name: Disabled - description: Circular buffer disabled. + description: Increment mode disabled. value: 0 - name: Enabled - description: Circular buffer enabled. + description: Increment mode enabled. value: 1 -enum/CTCIF: +enum/CH5_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH5_CR_PINC: bit_size: 1 variants: - - name: Clear - description: Clears the TCIF flag in the ISR register. + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. value: 1 -enum/CTEIF: +enum/CH5_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH5_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH5_CR_TCIE: bit_size: 1 variants: - - name: Clear - description: Clears the TEIF flag in the ISR register. + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH5_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH6_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. value: 1 -enum/DIR: +enum/CH6_CR_DIR: bit_size: 1 variants: - name: FromPeripheral @@ -233,7 +1670,7 @@ enum/DIR: - name: FromMemory description: Read from memory. value: 1 -enum/EN: +enum/CH6_CR_EN: bit_size: 1 variants: - name: Disabled @@ -242,34 +1679,136 @@ enum/EN: - name: Enabled description: Channel enabled. value: 1 -enum/GIF: +enum/CH6_CR_HTIE: bit_size: 1 variants: - - name: NoEvent - description: No transfer error, half event, complete event. + - name: Disabled + description: Half Transfer interrupt disabled. value: 0 - - name: Event - description: A transfer error, half event or complete event has occured. + - name: Enabled + description: Half Transfer interrupt enabled. value: 1 -enum/HTIE: +enum/CH6_CR_MEM2MEM: bit_size: 1 variants: - name: Disabled - description: Half Transfer interrupt disabled. + description: Memory to memory mode disabled. value: 0 - name: Enabled - description: Half Transfer interrupt enabled. + description: Memory to memory mode enabled. value: 1 -enum/HTIF: +enum/CH6_CR_MINC: bit_size: 1 variants: - - name: NotHalf - description: No half transfer event. + - name: Disabled + description: Increment mode disabled. value: 0 - - name: Half - description: A half transfer event has occured. + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH6_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH6_CR_PINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH6_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH6_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH6_CR_TCIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH6_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH7_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH7_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH7_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH7_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. value: 1 -enum/MEM2MEM: +enum/CH7_CR_MEM2MEM: bit_size: 1 variants: - name: Disabled @@ -278,7 +1817,7 @@ enum/MEM2MEM: - name: Enabled description: Memory to memory mode enabled. value: 1 -enum/MINC: +enum/CH7_CR_MINC: bit_size: 1 variants: - name: Disabled @@ -287,7 +1826,7 @@ enum/MINC: - name: Enabled description: Increment mode enabled. value: 1 -enum/MSIZE: +enum/CH7_CR_MSIZE: bit_size: 2 variants: - name: Bits8 @@ -299,7 +1838,7 @@ enum/MSIZE: - name: Bits32 description: 32-bit size. value: 2 -enum/PINC: +enum/CH7_CR_PINC: bit_size: 1 variants: - name: Disabled @@ -308,7 +1847,7 @@ enum/PINC: - name: Enabled description: Increment mode enabled. value: 1 -enum/PL: +enum/CH7_CR_PL: bit_size: 2 variants: - name: Low @@ -323,7 +1862,7 @@ enum/PL: - name: VeryHigh description: Very high priority. value: 3 -enum/PSIZE: +enum/CH7_CR_PSIZE: bit_size: 2 variants: - name: Bits8 @@ -335,7 +1874,7 @@ enum/PSIZE: - name: Bits32 description: 32-bit size. value: 2 -enum/TCIE: +enum/CH7_CR_TCIE: bit_size: 1 variants: - name: Disabled @@ -344,6 +1883,51 @@ enum/TCIE: - name: Enabled description: Transfer Complete interrupt enabled. value: 1 +enum/CH7_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CHTIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the HTIF flag in the ISR register. + value: 1 +enum/CTCIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the TCIF flag in the ISR register. + value: 1 +enum/CTEIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the TEIF flag in the ISR register. + value: 1 +enum/GIF: + bit_size: 1 + variants: + - name: NoEvent + description: No transfer error, half event, complete event. + value: 0 + - name: Event + description: A transfer error, half event or complete event has occured. + value: 1 +enum/HTIF: + bit_size: 1 + variants: + - name: NotHalf + description: No half transfer event. + value: 0 + - name: Half + description: A half transfer event has occured. + value: 1 enum/TCIF: bit_size: 1 variants: @@ -353,15 +1937,6 @@ enum/TCIF: - name: Complete description: A transfer complete event has occured. value: 1 -enum/TEIE: - bit_size: 1 - variants: - - name: Disabled - description: Transfer Error interrupt disabled. - value: 0 - - name: Enabled - description: Transfer Error interrupt enabled. - value: 1 enum/TEIF: bit_size: 1 variants: diff --git a/base/STM32F103/EXTI.yaml b/head/STM32F103/EXTI.yaml index b922cc7..a8cae21 100644 --- a/base/STM32F103/EXTI.yaml +++ b/head/STM32F103/EXTI.yaml @@ -28,68 +28,590 @@ block/EXTI: fieldset/EMR: description: Event mask register (EXTI_EMR). fields: - - name: MR + - name: MR0 description: Event Mask on line %s. bit_offset: 0 bit_size: 1 - array: - len: 19 - stride: 1 + enum: EMR_MR + - name: MR1 + description: Event Mask on line %s. + bit_offset: 1 + bit_size: 1 + enum: EMR_MR + - name: MR2 + description: Event Mask on line %s. + bit_offset: 2 + bit_size: 1 + enum: EMR_MR + - name: MR3 + description: Event Mask on line %s. + bit_offset: 3 + bit_size: 1 + enum: EMR_MR + - name: MR4 + description: Event Mask on line %s. + bit_offset: 4 + bit_size: 1 + enum: EMR_MR + - name: MR5 + description: Event Mask on line %s. + bit_offset: 5 + bit_size: 1 + enum: EMR_MR + - name: MR6 + description: Event Mask on line %s. + bit_offset: 6 + bit_size: 1 + enum: EMR_MR + - name: MR7 + description: Event Mask on line %s. + bit_offset: 7 + bit_size: 1 + enum: EMR_MR + - name: MR8 + description: Event Mask on line %s. + bit_offset: 8 + bit_size: 1 + enum: EMR_MR + - name: MR9 + description: Event Mask on line %s. + bit_offset: 9 + bit_size: 1 + enum: EMR_MR + - name: MR10 + description: Event Mask on line %s. + bit_offset: 10 + bit_size: 1 + enum: EMR_MR + - name: MR11 + description: Event Mask on line %s. + bit_offset: 11 + bit_size: 1 + enum: EMR_MR + - name: MR12 + description: Event Mask on line %s. + bit_offset: 12 + bit_size: 1 + enum: EMR_MR + - name: MR13 + description: Event Mask on line %s. + bit_offset: 13 + bit_size: 1 + enum: EMR_MR + - name: MR14 + description: Event Mask on line %s. + bit_offset: 14 + bit_size: 1 + enum: EMR_MR + - name: MR15 + description: Event Mask on line %s. + bit_offset: 15 + bit_size: 1 + enum: EMR_MR + - name: MR16 + description: Event Mask on line %s. + bit_offset: 16 + bit_size: 1 + enum: EMR_MR + - name: MR17 + description: Event Mask on line %s. + bit_offset: 17 + bit_size: 1 + enum: EMR_MR + - name: MR18 + description: Event Mask on line %s. + bit_offset: 18 + bit_size: 1 enum: EMR_MR fieldset/FTSR: description: Falling Trigger selection register (EXTI_FTSR). fields: - - name: TR + - name: TR0 description: Falling trigger event configuration of line %s. bit_offset: 0 bit_size: 1 - array: - len: 19 - stride: 1 + enum: FTSR_TR + - name: TR1 + description: Falling trigger event configuration of line %s. + bit_offset: 1 + bit_size: 1 + enum: FTSR_TR + - name: TR2 + description: Falling trigger event configuration of line %s. + bit_offset: 2 + bit_size: 1 + enum: FTSR_TR + - name: TR3 + description: Falling trigger event configuration of line %s. + bit_offset: 3 + bit_size: 1 + enum: FTSR_TR + - name: TR4 + description: Falling trigger event configuration of line %s. + bit_offset: 4 + bit_size: 1 + enum: FTSR_TR + - name: TR5 + description: Falling trigger event configuration of line %s. + bit_offset: 5 + bit_size: 1 + enum: FTSR_TR + - name: TR6 + description: Falling trigger event configuration of line %s. + bit_offset: 6 + bit_size: 1 + enum: FTSR_TR + - name: TR7 + description: Falling trigger event configuration of line %s. + bit_offset: 7 + bit_size: 1 + enum: FTSR_TR + - name: TR8 + description: Falling trigger event configuration of line %s. + bit_offset: 8 + bit_size: 1 + enum: FTSR_TR + - name: TR9 + description: Falling trigger event configuration of line %s. + bit_offset: 9 + bit_size: 1 + enum: FTSR_TR + - name: TR10 + description: Falling trigger event configuration of line %s. + bit_offset: 10 + bit_size: 1 + enum: FTSR_TR + - name: TR11 + description: Falling trigger event configuration of line %s. + bit_offset: 11 + bit_size: 1 + enum: FTSR_TR + - name: TR12 + description: Falling trigger event configuration of line %s. + bit_offset: 12 + bit_size: 1 + enum: FTSR_TR + - name: TR13 + description: Falling trigger event configuration of line %s. + bit_offset: 13 + bit_size: 1 + enum: FTSR_TR + - name: TR14 + description: Falling trigger event configuration of line %s. + bit_offset: 14 + bit_size: 1 + enum: FTSR_TR + - name: TR15 + description: Falling trigger event configuration of line %s. + bit_offset: 15 + bit_size: 1 + enum: FTSR_TR + - name: TR16 + description: Falling trigger event configuration of line %s. + bit_offset: 16 + bit_size: 1 + enum: FTSR_TR + - name: TR17 + description: Falling trigger event configuration of line %s. + bit_offset: 17 + bit_size: 1 + enum: FTSR_TR + - name: TR18 + description: Falling trigger event configuration of line %s. + bit_offset: 18 + bit_size: 1 enum: FTSR_TR fieldset/IMR: description: Interrupt mask register (EXTI_IMR). fields: - - name: MR + - name: MR0 description: Interrupt Mask on line %s. bit_offset: 0 bit_size: 1 - array: - len: 19 - stride: 1 + enum: IMR_MR + - name: MR1 + description: Interrupt Mask on line %s. + bit_offset: 1 + bit_size: 1 + enum: IMR_MR + - name: MR2 + description: Interrupt Mask on line %s. + bit_offset: 2 + bit_size: 1 + enum: IMR_MR + - name: MR3 + description: Interrupt Mask on line %s. + bit_offset: 3 + bit_size: 1 + enum: IMR_MR + - name: MR4 + description: Interrupt Mask on line %s. + bit_offset: 4 + bit_size: 1 + enum: IMR_MR + - name: MR5 + description: Interrupt Mask on line %s. + bit_offset: 5 + bit_size: 1 + enum: IMR_MR + - name: MR6 + description: Interrupt Mask on line %s. + bit_offset: 6 + bit_size: 1 + enum: IMR_MR + - name: MR7 + description: Interrupt Mask on line %s. + bit_offset: 7 + bit_size: 1 + enum: IMR_MR + - name: MR8 + description: Interrupt Mask on line %s. + bit_offset: 8 + bit_size: 1 + enum: IMR_MR + - name: MR9 + description: Interrupt Mask on line %s. + bit_offset: 9 + bit_size: 1 + enum: IMR_MR + - name: MR10 + description: Interrupt Mask on line %s. + bit_offset: 10 + bit_size: 1 + enum: IMR_MR + - name: MR11 + description: Interrupt Mask on line %s. + bit_offset: 11 + bit_size: 1 + enum: IMR_MR + - name: MR12 + description: Interrupt Mask on line %s. + bit_offset: 12 + bit_size: 1 + enum: IMR_MR + - name: MR13 + description: Interrupt Mask on line %s. + bit_offset: 13 + bit_size: 1 + enum: IMR_MR + - name: MR14 + description: Interrupt Mask on line %s. + bit_offset: 14 + bit_size: 1 + enum: IMR_MR + - name: MR15 + description: Interrupt Mask on line %s. + bit_offset: 15 + bit_size: 1 + enum: IMR_MR + - name: MR16 + description: Interrupt Mask on line %s. + bit_offset: 16 + bit_size: 1 + enum: IMR_MR + - name: MR17 + description: Interrupt Mask on line %s. + bit_offset: 17 + bit_size: 1 + enum: IMR_MR + - name: MR18 + description: Interrupt Mask on line %s. + bit_offset: 18 + bit_size: 1 enum: IMR_MR fieldset/PR: description: Pending register (EXTI_PR). fields: - - name: PR + - name: PR0 description: Pending bit %s. bit_offset: 0 bit_size: 1 - array: - len: 19 - stride: 1 + enum: PR + - name: PR1 + description: Pending bit %s. + bit_offset: 1 + bit_size: 1 + enum: PR + - name: PR2 + description: Pending bit %s. + bit_offset: 2 + bit_size: 1 + enum: PR + - name: PR3 + description: Pending bit %s. + bit_offset: 3 + bit_size: 1 + enum: PR + - name: PR4 + description: Pending bit %s. + bit_offset: 4 + bit_size: 1 + enum: PR + - name: PR5 + description: Pending bit %s. + bit_offset: 5 + bit_size: 1 + enum: PR + - name: PR6 + description: Pending bit %s. + bit_offset: 6 + bit_size: 1 + enum: PR + - name: PR7 + description: Pending bit %s. + bit_offset: 7 + bit_size: 1 + enum: PR + - name: PR8 + description: Pending bit %s. + bit_offset: 8 + bit_size: 1 + enum: PR + - name: PR9 + description: Pending bit %s. + bit_offset: 9 + bit_size: 1 + enum: PR + - name: PR10 + description: Pending bit %s. + bit_offset: 10 + bit_size: 1 + enum: PR + - name: PR11 + description: Pending bit %s. + bit_offset: 11 + bit_size: 1 + enum: PR + - name: PR12 + description: Pending bit %s. + bit_offset: 12 + bit_size: 1 + enum: PR + - name: PR13 + description: Pending bit %s. + bit_offset: 13 + bit_size: 1 + enum: PR + - name: PR14 + description: Pending bit %s. + bit_offset: 14 + bit_size: 1 + enum: PR + - name: PR15 + description: Pending bit %s. + bit_offset: 15 + bit_size: 1 + enum: PR + - name: PR16 + description: Pending bit %s. + bit_offset: 16 + bit_size: 1 + enum: PR + - name: PR17 + description: Pending bit %s. + bit_offset: 17 + bit_size: 1 + enum: PR + - name: PR18 + description: Pending bit %s. + bit_offset: 18 + bit_size: 1 enum: PR fieldset/RTSR: description: Rising Trigger selection register (EXTI_RTSR). fields: - - name: TR + - name: TR0 description: Rising trigger event configuration of line %s. bit_offset: 0 bit_size: 1 - array: - len: 19 - stride: 1 + enum: RTSR_TR + - name: TR1 + description: Rising trigger event configuration of line %s. + bit_offset: 1 + bit_size: 1 + enum: RTSR_TR + - name: TR2 + description: Rising trigger event configuration of line %s. + bit_offset: 2 + bit_size: 1 + enum: RTSR_TR + - name: TR3 + description: Rising trigger event configuration of line %s. + bit_offset: 3 + bit_size: 1 + enum: RTSR_TR + - name: TR4 + description: Rising trigger event configuration of line %s. + bit_offset: 4 + bit_size: 1 + enum: RTSR_TR + - name: TR5 + description: Rising trigger event configuration of line %s. + bit_offset: 5 + bit_size: 1 + enum: RTSR_TR + - name: TR6 + description: Rising trigger event configuration of line %s. + bit_offset: 6 + bit_size: 1 + enum: RTSR_TR + - name: TR7 + description: Rising trigger event configuration of line %s. + bit_offset: 7 + bit_size: 1 + enum: RTSR_TR + - name: TR8 + description: Rising trigger event configuration of line %s. + bit_offset: 8 + bit_size: 1 + enum: RTSR_TR + - name: TR9 + description: Rising trigger event configuration of line %s. + bit_offset: 9 + bit_size: 1 + enum: RTSR_TR + - name: TR10 + description: Rising trigger event configuration of line %s. + bit_offset: 10 + bit_size: 1 + enum: RTSR_TR + - name: TR11 + description: Rising trigger event configuration of line %s. + bit_offset: 11 + bit_size: 1 + enum: RTSR_TR + - name: TR12 + description: Rising trigger event configuration of line %s. + bit_offset: 12 + bit_size: 1 + enum: RTSR_TR + - name: TR13 + description: Rising trigger event configuration of line %s. + bit_offset: 13 + bit_size: 1 + enum: RTSR_TR + - name: TR14 + description: Rising trigger event configuration of line %s. + bit_offset: 14 + bit_size: 1 + enum: RTSR_TR + - name: TR15 + description: Rising trigger event configuration of line %s. + bit_offset: 15 + bit_size: 1 + enum: RTSR_TR + - name: TR16 + description: Rising trigger event configuration of line %s. + bit_offset: 16 + bit_size: 1 + enum: RTSR_TR + - name: TR17 + description: Rising trigger event configuration of line %s. + bit_offset: 17 + bit_size: 1 + enum: RTSR_TR + - name: TR18 + description: Rising trigger event configuration of line %s. + bit_offset: 18 + bit_size: 1 enum: RTSR_TR fieldset/SWIER: description: Software interrupt event register (EXTI_SWIER). fields: - - name: SWIER + - name: SWIER0 description: Software Interrupt on line %s. bit_offset: 0 bit_size: 1 - array: - len: 19 - stride: 1 + enum: SWIER + - name: SWIER1 + description: Software Interrupt on line %s. + bit_offset: 1 + bit_size: 1 + enum: SWIER + - name: SWIER2 + description: Software Interrupt on line %s. + bit_offset: 2 + bit_size: 1 + enum: SWIER + - name: SWIER3 + description: Software Interrupt on line %s. + bit_offset: 3 + bit_size: 1 + enum: SWIER + - name: SWIER4 + description: Software Interrupt on line %s. + bit_offset: 4 + bit_size: 1 + enum: SWIER + - name: SWIER5 + description: Software Interrupt on line %s. + bit_offset: 5 + bit_size: 1 + enum: SWIER + - name: SWIER6 + description: Software Interrupt on line %s. + bit_offset: 6 + bit_size: 1 + enum: SWIER + - name: SWIER7 + description: Software Interrupt on line %s. + bit_offset: 7 + bit_size: 1 + enum: SWIER + - name: SWIER8 + description: Software Interrupt on line %s. + bit_offset: 8 + bit_size: 1 + enum: SWIER + - name: SWIER9 + description: Software Interrupt on line %s. + bit_offset: 9 + bit_size: 1 + enum: SWIER + - name: SWIER10 + description: Software Interrupt on line %s. + bit_offset: 10 + bit_size: 1 + enum: SWIER + - name: SWIER11 + description: Software Interrupt on line %s. + bit_offset: 11 + bit_size: 1 + enum: SWIER + - name: SWIER12 + description: Software Interrupt on line %s. + bit_offset: 12 + bit_size: 1 + enum: SWIER + - name: SWIER13 + description: Software Interrupt on line %s. + bit_offset: 13 + bit_size: 1 + enum: SWIER + - name: SWIER14 + description: Software Interrupt on line %s. + bit_offset: 14 + bit_size: 1 + enum: SWIER + - name: SWIER15 + description: Software Interrupt on line %s. + bit_offset: 15 + bit_size: 1 + enum: SWIER + - name: SWIER16 + description: Software Interrupt on line %s. + bit_offset: 16 + bit_size: 1 + enum: SWIER + - name: SWIER17 + description: Software Interrupt on line %s. + bit_offset: 17 + bit_size: 1 + enum: SWIER + - name: SWIER18 + description: Software Interrupt on line %s. + bit_offset: 18 + bit_size: 1 enum: SWIER enum/EMR_MR: bit_size: 1 diff --git a/base/STM32F103/FSMC.yaml b/head/STM32F103/FSMC.yaml index 8c5d202..69a4e26 100644 --- a/base/STM32F103/FSMC.yaml +++ b/head/STM32F103/FSMC.yaml @@ -5,67 +5,112 @@ block/FSMC: description: SRAM/NOR-Flash chip-select control register 1. byte_offset: 0 fieldset: BCR1 - - name: BTR + - name: BTR1 description: SRAM/NOR-Flash chip-select timing register %s. - array: - len: 4 - stride: 8 byte_offset: 4 fieldset: BTR - - name: BCR + - name: BCR2 description: SRAM/NOR-Flash chip-select control register %s. - array: - len: 3 - stride: 8 byte_offset: 8 fieldset: BCR - - name: PCR + - name: BTR2 + description: SRAM/NOR-Flash chip-select timing register %s. + byte_offset: 12 + fieldset: BTR + - name: BCR3 + description: SRAM/NOR-Flash chip-select control register %s. + byte_offset: 16 + fieldset: BCR + - name: BTR3 + description: SRAM/NOR-Flash chip-select timing register %s. + byte_offset: 20 + fieldset: BTR + - name: BCR4 + description: SRAM/NOR-Flash chip-select control register %s. + byte_offset: 24 + fieldset: BCR + - name: BTR4 + description: SRAM/NOR-Flash chip-select timing register %s. + byte_offset: 28 + fieldset: BTR + - name: PCR2 description: PC Card/NAND Flash control register %s. - array: - len: 3 - stride: 32 byte_offset: 96 fieldset: PCR - - name: SR + - name: SR2 description: FIFO status and interrupt register %s. - array: - len: 3 - stride: 32 byte_offset: 100 fieldset: SR - - name: PMEM + - name: PMEM2 description: Common memory space timing register %s. - array: - len: 3 - stride: 32 byte_offset: 104 fieldset: PMEM - - name: PATT + - name: PATT2 description: Attribute memory space timing register %s. - array: - len: 3 - stride: 32 byte_offset: 108 fieldset: PATT - - name: ECCR + - name: ECCR2 description: ECC result register %s. - array: - len: 2 - stride: 32 byte_offset: 116 access: Read fieldset: ECCR + - name: PCR3 + description: PC Card/NAND Flash control register %s. + byte_offset: 128 + fieldset: PCR + - name: SR3 + description: FIFO status and interrupt register %s. + byte_offset: 132 + fieldset: SR + - name: PMEM3 + description: Common memory space timing register %s. + byte_offset: 136 + fieldset: PMEM + - name: PATT3 + description: Attribute memory space timing register %s. + byte_offset: 140 + fieldset: PATT + - name: ECCR3 + description: ECC result register %s. + byte_offset: 148 + access: Read + fieldset: ECCR + - name: PCR4 + description: PC Card/NAND Flash control register %s. + byte_offset: 160 + fieldset: PCR + - name: SR4 + description: FIFO status and interrupt register %s. + byte_offset: 164 + fieldset: SR + - name: PMEM4 + description: Common memory space timing register %s. + byte_offset: 168 + fieldset: PMEM + - name: PATT4 + description: Attribute memory space timing register %s. + byte_offset: 172 + fieldset: PATT - name: PIO4 description: I/O space timing register 4. byte_offset: 176 fieldset: PIO4 - - name: BWTR + - name: BWTR1 description: SRAM/NOR-Flash write timing registers %s. - array: - len: 4 - stride: 8 byte_offset: 260 fieldset: BWTR + - name: BWTR2 + description: SRAM/NOR-Flash write timing registers %s. + byte_offset: 268 + fieldset: BWTR + - name: BWTR3 + description: SRAM/NOR-Flash write timing registers %s. + byte_offset: 276 + fieldset: BWTR + - name: BWTR4 + description: SRAM/NOR-Flash write timing registers %s. + byte_offset: 284 + fieldset: BWTR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register %s. fields: [] diff --git a/base/STM32F103/GPIOA.yaml b/head/STM32F103/GPIOA.yaml index 8478ad0..5c4dc8c 100644 --- a/base/STM32F103/GPIOA.yaml +++ b/head/STM32F103/GPIOA.yaml @@ -35,32 +35,248 @@ block/GPIOA: fieldset/BRR: description: Port bit reset register (GPIOn_BRR). fields: - - name: BR + - name: BR0 description: Reset bit %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: BRR_BR + - name: BR1 + description: Reset bit %s. + bit_offset: 1 + bit_size: 1 + enum: BRR_BR + - name: BR2 + description: Reset bit %s. + bit_offset: 2 + bit_size: 1 + enum: BRR_BR + - name: BR3 + description: Reset bit %s. + bit_offset: 3 + bit_size: 1 + enum: BRR_BR + - name: BR4 + description: Reset bit %s. + bit_offset: 4 + bit_size: 1 + enum: BRR_BR + - name: BR5 + description: Reset bit %s. + bit_offset: 5 + bit_size: 1 + enum: BRR_BR + - name: BR6 + description: Reset bit %s. + bit_offset: 6 + bit_size: 1 + enum: BRR_BR + - name: BR7 + description: Reset bit %s. + bit_offset: 7 + bit_size: 1 + enum: BRR_BR + - name: BR8 + description: Reset bit %s. + bit_offset: 8 + bit_size: 1 + enum: BRR_BR + - name: BR9 + description: Reset bit %s. + bit_offset: 9 + bit_size: 1 + enum: BRR_BR + - name: BR10 + description: Reset bit %s. + bit_offset: 10 + bit_size: 1 + enum: BRR_BR + - name: BR11 + description: Reset bit %s. + bit_offset: 11 + bit_size: 1 + enum: BRR_BR + - name: BR12 + description: Reset bit %s. + bit_offset: 12 + bit_size: 1 + enum: BRR_BR + - name: BR13 + description: Reset bit %s. + bit_offset: 13 + bit_size: 1 + enum: BRR_BR + - name: BR14 + description: Reset bit %s. + bit_offset: 14 + bit_size: 1 + enum: BRR_BR + - name: BR15 + description: Reset bit %s. + bit_offset: 15 + bit_size: 1 enum: BRR_BR fieldset/BSRR: description: Port bit set/reset register (GPIOn_BSRR). fields: - - name: BS + - name: BS0 description: Set bit %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 enum: BS - - name: BR + - name: BS1 + description: Set bit %s. + bit_offset: 1 + bit_size: 1 + enum: BS + - name: BS2 + description: Set bit %s. + bit_offset: 2 + bit_size: 1 + enum: BS + - name: BS3 + description: Set bit %s. + bit_offset: 3 + bit_size: 1 + enum: BS + - name: BS4 + description: Set bit %s. + bit_offset: 4 + bit_size: 1 + enum: BS + - name: BS5 + description: Set bit %s. + bit_offset: 5 + bit_size: 1 + enum: BS + - name: BS6 + description: Set bit %s. + bit_offset: 6 + bit_size: 1 + enum: BS + - name: BS7 + description: Set bit %s. + bit_offset: 7 + bit_size: 1 + enum: BS + - name: BS8 + description: Set bit %s. + bit_offset: 8 + bit_size: 1 + enum: BS + - name: BS9 + description: Set bit %s. + bit_offset: 9 + bit_size: 1 + enum: BS + - name: BS10 + description: Set bit %s. + bit_offset: 10 + bit_size: 1 + enum: BS + - name: BS11 + description: Set bit %s. + bit_offset: 11 + bit_size: 1 + enum: BS + - name: BS12 + description: Set bit %s. + bit_offset: 12 + bit_size: 1 + enum: BS + - name: BS13 + description: Set bit %s. + bit_offset: 13 + bit_size: 1 + enum: BS + - name: BS14 + description: Set bit %s. + bit_offset: 14 + bit_size: 1 + enum: BS + - name: BS15 + description: Set bit %s. + bit_offset: 15 + bit_size: 1 + enum: BS + - name: BR0 description: Reset bit %s. bit_offset: 16 bit_size: 1 - array: - len: 16 - stride: 1 + enum: BSRR_BR + - name: BR1 + description: Reset bit %s. + bit_offset: 17 + bit_size: 1 + enum: BSRR_BR + - name: BR2 + description: Reset bit %s. + bit_offset: 18 + bit_size: 1 + enum: BSRR_BR + - name: BR3 + description: Reset bit %s. + bit_offset: 19 + bit_size: 1 + enum: BSRR_BR + - name: BR4 + description: Reset bit %s. + bit_offset: 20 + bit_size: 1 + enum: BSRR_BR + - name: BR5 + description: Reset bit %s. + bit_offset: 21 + bit_size: 1 + enum: BSRR_BR + - name: BR6 + description: Reset bit %s. + bit_offset: 22 + bit_size: 1 + enum: BSRR_BR + - name: BR7 + description: Reset bit %s. + bit_offset: 23 + bit_size: 1 + enum: BSRR_BR + - name: BR8 + description: Reset bit %s. + bit_offset: 24 + bit_size: 1 + enum: BSRR_BR + - name: BR9 + description: Reset bit %s. + bit_offset: 25 + bit_size: 1 + enum: BSRR_BR + - name: BR10 + description: Reset bit %s. + bit_offset: 26 + bit_size: 1 + enum: BSRR_BR + - name: BR11 + description: Reset bit %s. + bit_offset: 27 + bit_size: 1 + enum: BSRR_BR + - name: BR12 + description: Reset bit %s. + bit_offset: 28 + bit_size: 1 + enum: BSRR_BR + - name: BR13 + description: Reset bit %s. + bit_offset: 29 + bit_size: 1 + enum: BSRR_BR + - name: BR14 + description: Reset bit %s. + bit_offset: 30 + bit_size: 1 + enum: BSRR_BR + - name: BR15 + description: Reset bit %s. + bit_offset: 31 + bit_size: 1 enum: BSRR_BR fieldset/CRH: description: Port configuration register high (GPIOn_CRL). @@ -68,43 +284,251 @@ fieldset/CRH: fieldset/CRL: description: Port configuration register low (GPIOn_CRL). fields: - - name: MODE + - name: MODE0 description: Port n.%s mode bits. bit_offset: 0 bit_size: 2 - array: - len: 8 - stride: 4 enum: MODE - - name: CNF + - name: CNF0 description: Port n.%s configuration bits. bit_offset: 2 bit_size: 2 - array: - len: 8 - stride: 4 + enum: CNF + - name: MODE1 + description: Port n.%s mode bits. + bit_offset: 4 + bit_size: 2 + enum: MODE + - name: CNF1 + description: Port n.%s configuration bits. + bit_offset: 6 + bit_size: 2 + enum: CNF + - name: MODE2 + description: Port n.%s mode bits. + bit_offset: 8 + bit_size: 2 + enum: MODE + - name: CNF2 + description: Port n.%s configuration bits. + bit_offset: 10 + bit_size: 2 + enum: CNF + - name: MODE3 + description: Port n.%s mode bits. + bit_offset: 12 + bit_size: 2 + enum: MODE + - name: CNF3 + description: Port n.%s configuration bits. + bit_offset: 14 + bit_size: 2 + enum: CNF + - name: MODE4 + description: Port n.%s mode bits. + bit_offset: 16 + bit_size: 2 + enum: MODE + - name: CNF4 + description: Port n.%s configuration bits. + bit_offset: 18 + bit_size: 2 + enum: CNF + - name: MODE5 + description: Port n.%s mode bits. + bit_offset: 20 + bit_size: 2 + enum: MODE + - name: CNF5 + description: Port n.%s configuration bits. + bit_offset: 22 + bit_size: 2 + enum: CNF + - name: MODE6 + description: Port n.%s mode bits. + bit_offset: 24 + bit_size: 2 + enum: MODE + - name: CNF6 + description: Port n.%s configuration bits. + bit_offset: 26 + bit_size: 2 + enum: CNF + - name: MODE7 + description: Port n.%s mode bits. + bit_offset: 28 + bit_size: 2 + enum: MODE + - name: CNF7 + description: Port n.%s configuration bits. + bit_offset: 30 + bit_size: 2 enum: CNF fieldset/IDR: description: Port input data register (GPIOn_IDR). fields: - - name: IDR + - name: IDR0 description: Port input data. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: IDR + - name: IDR1 + description: Port input data. + bit_offset: 1 + bit_size: 1 + enum: IDR + - name: IDR2 + description: Port input data. + bit_offset: 2 + bit_size: 1 + enum: IDR + - name: IDR3 + description: Port input data. + bit_offset: 3 + bit_size: 1 + enum: IDR + - name: IDR4 + description: Port input data. + bit_offset: 4 + bit_size: 1 + enum: IDR + - name: IDR5 + description: Port input data. + bit_offset: 5 + bit_size: 1 + enum: IDR + - name: IDR6 + description: Port input data. + bit_offset: 6 + bit_size: 1 + enum: IDR + - name: IDR7 + description: Port input data. + bit_offset: 7 + bit_size: 1 + enum: IDR + - name: IDR8 + description: Port input data. + bit_offset: 8 + bit_size: 1 + enum: IDR + - name: IDR9 + description: Port input data. + bit_offset: 9 + bit_size: 1 + enum: IDR + - name: IDR10 + description: Port input data. + bit_offset: 10 + bit_size: 1 + enum: IDR + - name: IDR11 + description: Port input data. + bit_offset: 11 + bit_size: 1 + enum: IDR + - name: IDR12 + description: Port input data. + bit_offset: 12 + bit_size: 1 + enum: IDR + - name: IDR13 + description: Port input data. + bit_offset: 13 + bit_size: 1 + enum: IDR + - name: IDR14 + description: Port input data. + bit_offset: 14 + bit_size: 1 + enum: IDR + - name: IDR15 + description: Port input data. + bit_offset: 15 + bit_size: 1 enum: IDR fieldset/LCKR: description: Port configuration lock register. fields: - - name: LCK + - name: LCK0 description: Port A Lock bit %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: LCK + - name: LCK1 + description: Port A Lock bit %s. + bit_offset: 1 + bit_size: 1 + enum: LCK + - name: LCK2 + description: Port A Lock bit %s. + bit_offset: 2 + bit_size: 1 + enum: LCK + - name: LCK3 + description: Port A Lock bit %s. + bit_offset: 3 + bit_size: 1 + enum: LCK + - name: LCK4 + description: Port A Lock bit %s. + bit_offset: 4 + bit_size: 1 + enum: LCK + - name: LCK5 + description: Port A Lock bit %s. + bit_offset: 5 + bit_size: 1 + enum: LCK + - name: LCK6 + description: Port A Lock bit %s. + bit_offset: 6 + bit_size: 1 + enum: LCK + - name: LCK7 + description: Port A Lock bit %s. + bit_offset: 7 + bit_size: 1 + enum: LCK + - name: LCK8 + description: Port A Lock bit %s. + bit_offset: 8 + bit_size: 1 + enum: LCK + - name: LCK9 + description: Port A Lock bit %s. + bit_offset: 9 + bit_size: 1 + enum: LCK + - name: LCK10 + description: Port A Lock bit %s. + bit_offset: 10 + bit_size: 1 + enum: LCK + - name: LCK11 + description: Port A Lock bit %s. + bit_offset: 11 + bit_size: 1 + enum: LCK + - name: LCK12 + description: Port A Lock bit %s. + bit_offset: 12 + bit_size: 1 + enum: LCK + - name: LCK13 + description: Port A Lock bit %s. + bit_offset: 13 + bit_size: 1 + enum: LCK + - name: LCK14 + description: Port A Lock bit %s. + bit_offset: 14 + bit_size: 1 + enum: LCK + - name: LCK15 + description: Port A Lock bit %s. + bit_offset: 15 + bit_size: 1 enum: LCK - name: LCKK description: Lock key. @@ -114,13 +538,85 @@ fieldset/LCKR: fieldset/ODR: description: Port output data register (GPIOn_ODR). fields: - - name: ODR + - name: ODR0 description: Port output data. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: ODR + - name: ODR1 + description: Port output data. + bit_offset: 1 + bit_size: 1 + enum: ODR + - name: ODR2 + description: Port output data. + bit_offset: 2 + bit_size: 1 + enum: ODR + - name: ODR3 + description: Port output data. + bit_offset: 3 + bit_size: 1 + enum: ODR + - name: ODR4 + description: Port output data. + bit_offset: 4 + bit_size: 1 + enum: ODR + - name: ODR5 + description: Port output data. + bit_offset: 5 + bit_size: 1 + enum: ODR + - name: ODR6 + description: Port output data. + bit_offset: 6 + bit_size: 1 + enum: ODR + - name: ODR7 + description: Port output data. + bit_offset: 7 + bit_size: 1 + enum: ODR + - name: ODR8 + description: Port output data. + bit_offset: 8 + bit_size: 1 + enum: ODR + - name: ODR9 + description: Port output data. + bit_offset: 9 + bit_size: 1 + enum: ODR + - name: ODR10 + description: Port output data. + bit_offset: 10 + bit_size: 1 + enum: ODR + - name: ODR11 + description: Port output data. + bit_offset: 11 + bit_size: 1 + enum: ODR + - name: ODR12 + description: Port output data. + bit_offset: 12 + bit_size: 1 + enum: ODR + - name: ODR13 + description: Port output data. + bit_offset: 13 + bit_size: 1 + enum: ODR + - name: ODR14 + description: Port output data. + bit_offset: 14 + bit_size: 1 + enum: ODR + - name: ODR15 + description: Port output data. + bit_offset: 15 + bit_size: 1 enum: ODR enum/BRR_BR: bit_size: 1 diff --git a/base/STM32F103/OTG_FS_DEVICE.yaml b/head/STM32F103/OTG_FS_DEVICE.yaml index 7adc511..6998e84 100644 --- a/base/STM32F103/OTG_FS_DEVICE.yaml +++ b/head/STM32F103/OTG_FS_DEVICE.yaml @@ -1,14 +1,3 @@ -block/DIEP: - description: Device IN endpoint X. - items: - - name: CTL - description: OTG device endpoint-1 control register. - byte_offset: 0 - fieldset: DIEP_CTL - - name: TSIZ - description: device endpoint-1 transfer size register. - byte_offset: 16 - fieldset: DIEP_TSIZ block/DIEP0: description: Device IN endpoint 0. items: @@ -29,17 +18,39 @@ block/DIEP0: byte_offset: 24 access: Read fieldset: TXFSTS -block/DOEP: +block/DIEP1: description: Device IN endpoint X. items: - name: CTL - description: device endpoint-1 control register. + description: OTG device endpoint-1 control register. byte_offset: 0 - fieldset: DOEP_CTL + fieldset: DIEP1_CTL - name: TSIZ - description: device OUT endpoint-1 transfer size register. + description: device endpoint-1 transfer size register. + byte_offset: 16 + fieldset: DIEP1_TSIZ +block/DIEP2: + description: Device IN endpoint X. + items: + - name: CTL + description: OTG device endpoint-1 control register. + byte_offset: 0 + fieldset: DIEP2_CTL + - name: TSIZ + description: device endpoint-1 transfer size register. byte_offset: 16 - fieldset: DOEP_TSIZ + fieldset: DIEP2_TSIZ +block/DIEP3: + description: Device IN endpoint X. + items: + - name: CTL + description: OTG device endpoint-1 control register. + byte_offset: 0 + fieldset: DIEP3_CTL + - name: TSIZ + description: device endpoint-1 transfer size register. + byte_offset: 16 + fieldset: DIEP3_TSIZ block/DOEP0: description: Device OUT endpoint 0. items: @@ -55,6 +66,39 @@ block/DOEP0: description: device OUT endpoint-0 transfer size register. byte_offset: 16 fieldset: DOEP0_TSIZ +block/DOEP1: + description: Device IN endpoint X. + items: + - name: CTL + description: device endpoint-1 control register. + byte_offset: 0 + fieldset: DOEP1_CTL + - name: TSIZ + description: device OUT endpoint-1 transfer size register. + byte_offset: 16 + fieldset: DOEP1_TSIZ +block/DOEP2: + description: Device IN endpoint X. + items: + - name: CTL + description: device endpoint-1 control register. + byte_offset: 0 + fieldset: DOEP2_CTL + - name: TSIZ + description: device OUT endpoint-1 transfer size register. + byte_offset: 16 + fieldset: DOEP2_TSIZ +block/DOEP3: + description: Device IN endpoint X. + items: + - name: CTL + description: device endpoint-1 control register. + byte_offset: 0 + fieldset: DOEP3_CTL + - name: TSIZ + description: device OUT endpoint-1 transfer size register. + byte_offset: 16 + fieldset: DOEP3_TSIZ block/OTG_FS_DEVICE: description: USB on the go full speed. items: @@ -104,24 +148,34 @@ block/OTG_FS_DEVICE: description: Device IN endpoint 0. byte_offset: 256 block: DIEP0 - - name: DIEP + - name: DIEP1 description: Device IN endpoint X. - array: - len: 3 - stride: 32 byte_offset: 288 - block: DIEP + block: DIEP1 + - name: DIEP2 + description: Device IN endpoint X. + byte_offset: 320 + block: DIEP2 + - name: DIEP3 + description: Device IN endpoint X. + byte_offset: 352 + block: DIEP3 - name: DOEP0 description: Device OUT endpoint 0. byte_offset: 768 block: DOEP0 - - name: DOEP + - name: DOEP1 description: Device IN endpoint X. - array: - len: 3 - stride: 32 byte_offset: 800 - block: DOEP + block: DOEP1 + - name: DOEP2 + description: Device IN endpoint X. + byte_offset: 832 + block: DOEP2 + - name: DOEP3 + description: Device IN endpoint X. + byte_offset: 864 + block: DOEP3 fieldset/DAINT: description: OTG_FS device all endpoints interrupt register (OTG_FS_DAINT). fields: @@ -287,41 +341,147 @@ fieldset/DIEP0_TSIZ: description: Packet count. bit_offset: 19 bit_size: 2 -fieldset/DIEPEMPMSK: - description: OTG_FS device IN endpoint FIFO empty interrupt mask register. +fieldset/DIEP1_CTL: + description: OTG device endpoint-1 control register. fields: - - name: INEPTXFEM - description: IN EP Tx FIFO empty interrupt mask bits. + - name: MPSIZ + description: MPSIZ. bit_offset: 0 - bit_size: 16 -fieldset/DIEPMSK: - description: OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK). + bit_size: 11 + - name: USBAEP + description: USBAEP. + bit_offset: 15 + bit_size: 1 + - name: EONUM_DPID + description: EONUM/DPID. + bit_offset: 16 + bit_size: 1 + - name: NAKSTS + description: NAKSTS. + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: EPTYP. + bit_offset: 18 + bit_size: 2 + - name: STALL + description: STALL handshake. + bit_offset: 21 + bit_size: 1 + - name: TXFNUM + description: TXFNUM. + bit_offset: 22 + bit_size: 4 + - name: CNAK + description: CNAK. + bit_offset: 26 + bit_size: 1 + - name: SNAK + description: SNAK. + bit_offset: 27 + bit_size: 1 + - name: SD0PID_SEVNFRM + description: SD0PID/SEVNFRM. + bit_offset: 28 + bit_size: 1 + - name: SODDFRM_SD1PID + description: SODDFRM/SD1PID. + bit_offset: 29 + bit_size: 1 + - name: EPDIS + description: EPDIS. + bit_offset: 30 + bit_size: 1 + - name: EPENA + description: EPENA. + bit_offset: 31 + bit_size: 1 +fieldset/DIEP1_TSIZ: + description: device endpoint-1 transfer size register. fields: - - name: XFRCM - description: Transfer completed interrupt mask. + - name: XFRSIZ + description: Transfer size. + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count. + bit_offset: 19 + bit_size: 10 + - name: MCNT + description: Multi count. + bit_offset: 29 + bit_size: 2 +fieldset/DIEP2_CTL: + description: OTG device endpoint-1 control register. + fields: + - name: MPSIZ + description: MPSIZ. bit_offset: 0 + bit_size: 11 + - name: USBAEP + description: USBAEP. + bit_offset: 15 bit_size: 1 - - name: EPDM - description: Endpoint disabled interrupt mask. - bit_offset: 1 + - name: EONUM_DPID + description: EONUM/DPID. + bit_offset: 16 bit_size: 1 - - name: TOM - description: Timeout condition mask (Non-isochronous endpoints). - bit_offset: 3 + - name: NAKSTS + description: NAKSTS. + bit_offset: 17 bit_size: 1 - - name: ITTXFEMSK - description: IN token received when TxFIFO empty mask. - bit_offset: 4 + - name: EPTYP + description: EPTYP. + bit_offset: 18 + bit_size: 2 + - name: STALL + description: STALL handshake. + bit_offset: 21 bit_size: 1 - - name: INEPNMM - description: IN token received with EP mismatch mask. - bit_offset: 5 + - name: TXFNUM + description: TXFNUM. + bit_offset: 22 + bit_size: 4 + - name: CNAK + description: CNAK. + bit_offset: 26 bit_size: 1 - - name: INEPNEM - description: IN endpoint NAK effective mask. - bit_offset: 6 + - name: SNAK + description: SNAK. + bit_offset: 27 bit_size: 1 -fieldset/DIEP_CTL: + - name: SD0PID_SEVNFRM + description: SD0PID/SEVNFRM. + bit_offset: 28 + bit_size: 1 + - name: SODDFRM_SD1PID + description: SODDFRM/SD1PID. + bit_offset: 29 + bit_size: 1 + - name: EPDIS + description: EPDIS. + bit_offset: 30 + bit_size: 1 + - name: EPENA + description: EPENA. + bit_offset: 31 + bit_size: 1 +fieldset/DIEP2_TSIZ: + description: device endpoint-1 transfer size register. + fields: + - name: XFRSIZ + description: Transfer size. + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count. + bit_offset: 19 + bit_size: 10 + - name: MCNT + description: Multi count. + bit_offset: 29 + bit_size: 2 +fieldset/DIEP3_CTL: description: OTG device endpoint-1 control register. fields: - name: MPSIZ @@ -376,7 +536,7 @@ fieldset/DIEP_CTL: description: EPENA. bit_offset: 31 bit_size: 1 -fieldset/DIEP_TSIZ: +fieldset/DIEP3_TSIZ: description: device endpoint-1 transfer size register. fields: - name: XFRSIZ @@ -391,6 +551,40 @@ fieldset/DIEP_TSIZ: description: Multi count. bit_offset: 29 bit_size: 2 +fieldset/DIEPEMPMSK: + description: OTG_FS device IN endpoint FIFO empty interrupt mask register. + fields: + - name: INEPTXFEM + description: IN EP Tx FIFO empty interrupt mask bits. + bit_offset: 0 + bit_size: 16 +fieldset/DIEPMSK: + description: OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK). + fields: + - name: XFRCM + description: Transfer completed interrupt mask. + bit_offset: 0 + bit_size: 1 + - name: EPDM + description: Endpoint disabled interrupt mask. + bit_offset: 1 + bit_size: 1 + - name: TOM + description: Timeout condition mask (Non-isochronous endpoints). + bit_offset: 3 + bit_size: 1 + - name: ITTXFEMSK + description: IN token received when TxFIFO empty mask. + bit_offset: 4 + bit_size: 1 + - name: INEPNMM + description: IN token received with EP mismatch mask. + bit_offset: 5 + bit_size: 1 + - name: INEPNEM + description: IN endpoint NAK effective mask. + bit_offset: 6 + bit_size: 1 fieldset/DOEP0_CTL: description: device endpoint-0 control register. fields: @@ -472,26 +666,147 @@ fieldset/DOEP0_TSIZ: description: SETUP packet count. bit_offset: 29 bit_size: 2 -fieldset/DOEPMSK: - description: OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK). +fieldset/DOEP1_CTL: + description: device endpoint-1 control register. fields: - - name: XFRCM - description: Transfer completed interrupt mask. + - name: MPSIZ + description: MPSIZ. bit_offset: 0 + bit_size: 11 + - name: USBAEP + description: USBAEP. + bit_offset: 15 bit_size: 1 - - name: EPDM - description: Endpoint disabled interrupt mask. - bit_offset: 1 + - name: EONUM_DPID + description: EONUM/DPID. + bit_offset: 16 bit_size: 1 - - name: STUPM - description: SETUP phase done mask. - bit_offset: 3 + - name: NAKSTS + description: NAKSTS. + bit_offset: 17 bit_size: 1 - - name: OTEPDM - description: OUT token received when endpoint disabled mask. - bit_offset: 4 + - name: EPTYP + description: EPTYP. + bit_offset: 18 + bit_size: 2 + - name: SNPM + description: SNPM. + bit_offset: 20 + bit_size: 1 + - name: STALL + description: STALL handshake. + bit_offset: 21 bit_size: 1 -fieldset/DOEP_CTL: + - name: CNAK + description: CNAK. + bit_offset: 26 + bit_size: 1 + - name: SNAK + description: SNAK. + bit_offset: 27 + bit_size: 1 + - name: SD0PID_SEVNFRM + description: SD0PID/SEVNFRM. + bit_offset: 28 + bit_size: 1 + - name: SODDFRM + description: SODDFRM. + bit_offset: 29 + bit_size: 1 + - name: EPDIS + description: EPDIS. + bit_offset: 30 + bit_size: 1 + - name: EPENA + description: EPENA. + bit_offset: 31 + bit_size: 1 +fieldset/DOEP1_TSIZ: + description: device OUT endpoint-1 transfer size register. + fields: + - name: XFRSIZ + description: Transfer size. + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count. + bit_offset: 19 + bit_size: 10 + - name: RXDPID_STUPCNT + description: Received data PID/SETUP packet count. + bit_offset: 29 + bit_size: 2 +fieldset/DOEP2_CTL: + description: device endpoint-1 control register. + fields: + - name: MPSIZ + description: MPSIZ. + bit_offset: 0 + bit_size: 11 + - name: USBAEP + description: USBAEP. + bit_offset: 15 + bit_size: 1 + - name: EONUM_DPID + description: EONUM/DPID. + bit_offset: 16 + bit_size: 1 + - name: NAKSTS + description: NAKSTS. + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: EPTYP. + bit_offset: 18 + bit_size: 2 + - name: SNPM + description: SNPM. + bit_offset: 20 + bit_size: 1 + - name: STALL + description: STALL handshake. + bit_offset: 21 + bit_size: 1 + - name: CNAK + description: CNAK. + bit_offset: 26 + bit_size: 1 + - name: SNAK + description: SNAK. + bit_offset: 27 + bit_size: 1 + - name: SD0PID_SEVNFRM + description: SD0PID/SEVNFRM. + bit_offset: 28 + bit_size: 1 + - name: SODDFRM + description: SODDFRM. + bit_offset: 29 + bit_size: 1 + - name: EPDIS + description: EPDIS. + bit_offset: 30 + bit_size: 1 + - name: EPENA + description: EPENA. + bit_offset: 31 + bit_size: 1 +fieldset/DOEP2_TSIZ: + description: device OUT endpoint-1 transfer size register. + fields: + - name: XFRSIZ + description: Transfer size. + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count. + bit_offset: 19 + bit_size: 10 + - name: RXDPID_STUPCNT + description: Received data PID/SETUP packet count. + bit_offset: 29 + bit_size: 2 +fieldset/DOEP3_CTL: description: device endpoint-1 control register. fields: - name: MPSIZ @@ -546,7 +861,7 @@ fieldset/DOEP_CTL: description: EPENA. bit_offset: 31 bit_size: 1 -fieldset/DOEP_TSIZ: +fieldset/DOEP3_TSIZ: description: device OUT endpoint-1 transfer size register. fields: - name: XFRSIZ @@ -561,6 +876,25 @@ fieldset/DOEP_TSIZ: description: Received data PID/SETUP packet count. bit_offset: 29 bit_size: 2 +fieldset/DOEPMSK: + description: OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK). + fields: + - name: XFRCM + description: Transfer completed interrupt mask. + bit_offset: 0 + bit_size: 1 + - name: EPDM + description: Endpoint disabled interrupt mask. + bit_offset: 1 + bit_size: 1 + - name: STUPM + description: SETUP phase done mask. + bit_offset: 3 + bit_size: 1 + - name: OTEPDM + description: OUT token received when endpoint disabled mask. + bit_offset: 4 + bit_size: 1 fieldset/DSTS: description: OTG_FS device status register (OTG_FS_DSTS). fields: diff --git a/base/STM32F103/OTG_FS_GLOBAL.yaml b/head/STM32F103/OTG_FS_GLOBAL.yaml index 8f8a3a2..00a8197 100644 --- a/base/STM32F103/OTG_FS_GLOBAL.yaml +++ b/head/STM32F103/OTG_FS_GLOBAL.yaml @@ -78,13 +78,18 @@ block/OTG_FS_GLOBAL: description: OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ). byte_offset: 256 fieldset: HPTXFSIZ - - name: DIEPTXF + - name: DIEPTXF1 description: OTG_FS device IN endpoint transmit FIFO size register. - array: - len: 3 - stride: 4 byte_offset: 260 fieldset: DIEPTXF + - name: DIEPTXF2 + description: OTG_FS device IN endpoint transmit FIFO size register. + byte_offset: 264 + fieldset: DIEPTXF + - name: DIEPTXF3 + description: OTG_FS device IN endpoint transmit FIFO size register. + byte_offset: 268 + fieldset: DIEPTXF fieldset/CID: description: core ID register. fields: diff --git a/base/STM32F103/OTG_FS_HOST.yaml b/head/STM32F103/OTG_FS_HOST.yaml index 41b46f4..6e5cac2 100644 --- a/base/STM32F103/OTG_FS_HOST.yaml +++ b/head/STM32F103/OTG_FS_HOST.yaml @@ -1,22 +1,155 @@ -block/HC: +block/HC0: description: Host channel. items: - name: CHAR description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). byte_offset: 0 - fieldset: CHAR + fieldset: HC0_CHAR - name: INT description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). byte_offset: 8 - fieldset: INT + fieldset: HC0_INT - name: INTMSK description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). byte_offset: 12 - fieldset: INTMSK + fieldset: HC0_INTMSK - name: TSIZ description: OTG_FS host channel-0 transfer size register. byte_offset: 16 - fieldset: TSIZ + fieldset: HC0_TSIZ +block/HC1: + description: Host channel. + items: + - name: CHAR + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + byte_offset: 0 + fieldset: HC1_CHAR + - name: INT + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + byte_offset: 8 + fieldset: HC1_INT + - name: INTMSK + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + byte_offset: 12 + fieldset: HC1_INTMSK + - name: TSIZ + description: OTG_FS host channel-0 transfer size register. + byte_offset: 16 + fieldset: HC1_TSIZ +block/HC2: + description: Host channel. + items: + - name: CHAR + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + byte_offset: 0 + fieldset: HC2_CHAR + - name: INT + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + byte_offset: 8 + fieldset: HC2_INT + - name: INTMSK + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + byte_offset: 12 + fieldset: HC2_INTMSK + - name: TSIZ + description: OTG_FS host channel-0 transfer size register. + byte_offset: 16 + fieldset: HC2_TSIZ +block/HC3: + description: Host channel. + items: + - name: CHAR + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + byte_offset: 0 + fieldset: HC3_CHAR + - name: INT + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + byte_offset: 8 + fieldset: HC3_INT + - name: INTMSK + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + byte_offset: 12 + fieldset: HC3_INTMSK + - name: TSIZ + description: OTG_FS host channel-0 transfer size register. + byte_offset: 16 + fieldset: HC3_TSIZ +block/HC4: + description: Host channel. + items: + - name: CHAR + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + byte_offset: 0 + fieldset: HC4_CHAR + - name: INT + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + byte_offset: 8 + fieldset: HC4_INT + - name: INTMSK + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + byte_offset: 12 + fieldset: HC4_INTMSK + - name: TSIZ + description: OTG_FS host channel-0 transfer size register. + byte_offset: 16 + fieldset: HC4_TSIZ +block/HC5: + description: Host channel. + items: + - name: CHAR + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + byte_offset: 0 + fieldset: HC5_CHAR + - name: INT + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + byte_offset: 8 + fieldset: HC5_INT + - name: INTMSK + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + byte_offset: 12 + fieldset: HC5_INTMSK + - name: TSIZ + description: OTG_FS host channel-0 transfer size register. + byte_offset: 16 + fieldset: HC5_TSIZ +block/HC6: + description: Host channel. + items: + - name: CHAR + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + byte_offset: 0 + fieldset: HC6_CHAR + - name: INT + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + byte_offset: 8 + fieldset: HC6_INT + - name: INTMSK + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + byte_offset: 12 + fieldset: HC6_INTMSK + - name: TSIZ + description: OTG_FS host channel-0 transfer size register. + byte_offset: 16 + fieldset: HC6_TSIZ +block/HC7: + description: Host channel. + items: + - name: CHAR + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + byte_offset: 0 + fieldset: HC7_CHAR + - name: INT + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + byte_offset: 8 + fieldset: HC7_INT + - name: INTMSK + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + byte_offset: 12 + fieldset: HC7_INTMSK + - name: TSIZ + description: OTG_FS host channel-0 transfer size register. + byte_offset: 16 + fieldset: HC7_TSIZ block/OTG_FS_HOST: description: USB on the go full speed. items: @@ -50,14 +183,53 @@ block/OTG_FS_HOST: description: OTG_FS host port control and status register (OTG_FS_HPRT). byte_offset: 64 fieldset: HPRT - - name: HC + - name: HC0 description: Host channel. - array: - len: 8 - stride: 32 byte_offset: 256 - block: HC -fieldset/CHAR: + block: HC0 + - name: HC1 + description: Host channel. + byte_offset: 288 + block: HC1 + - name: HC2 + description: Host channel. + byte_offset: 320 + block: HC2 + - name: HC3 + description: Host channel. + byte_offset: 352 + block: HC3 + - name: HC4 + description: Host channel. + byte_offset: 384 + block: HC4 + - name: HC5 + description: Host channel. + byte_offset: 416 + block: HC5 + - name: HC6 + description: Host channel. + byte_offset: 448 + block: HC6 + - name: HC7 + description: Host channel. + byte_offset: 480 + block: HC7 +fieldset/HAINT: + description: OTG_FS Host all channels interrupt register. + fields: + - name: HAINT + description: Channel interrupts. + bit_offset: 0 + bit_size: 16 +fieldset/HAINTMSK: + description: OTG_FS host all channels interrupt mask register. + fields: + - name: HAINTM + description: Channel interrupt mask. + bit_offset: 0 + bit_size: 16 +fieldset/HC0_CHAR: description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). fields: - name: MPSIZ @@ -100,120 +272,7 @@ fieldset/CHAR: description: Channel enable. bit_offset: 31 bit_size: 1 -fieldset/HAINT: - description: OTG_FS Host all channels interrupt register. - fields: - - name: HAINT - description: Channel interrupts. - bit_offset: 0 - bit_size: 16 -fieldset/HAINTMSK: - description: OTG_FS host all channels interrupt mask register. - fields: - - name: HAINTM - description: Channel interrupt mask. - bit_offset: 0 - bit_size: 16 -fieldset/HCFG: - description: OTG_FS host configuration register (OTG_FS_HCFG). - fields: - - name: FSLSPCS - description: FS/LS PHY clock select. - bit_offset: 0 - bit_size: 2 - - name: FSLSS - description: FS- and LS-only support. - bit_offset: 2 - bit_size: 1 -fieldset/HFIR: - description: OTG_FS Host frame interval register. - fields: - - name: FRIVL - description: Frame interval. - bit_offset: 0 - bit_size: 16 -fieldset/HFNUM: - description: OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM). - fields: - - name: FRNUM - description: Frame number. - bit_offset: 0 - bit_size: 16 - - name: FTREM - description: Frame time remaining. - bit_offset: 16 - bit_size: 16 -fieldset/HPRT: - description: OTG_FS host port control and status register (OTG_FS_HPRT). - fields: - - name: PCSTS - description: Port connect status. - bit_offset: 0 - bit_size: 1 - - name: PCDET - description: Port connect detected. - bit_offset: 1 - bit_size: 1 - - name: PENA - description: Port enable. - bit_offset: 2 - bit_size: 1 - - name: PENCHNG - description: Port enable/disable change. - bit_offset: 3 - bit_size: 1 - - name: POCA - description: Port overcurrent active. - bit_offset: 4 - bit_size: 1 - - name: POCCHNG - description: Port overcurrent change. - bit_offset: 5 - bit_size: 1 - - name: PRES - description: Port resume. - bit_offset: 6 - bit_size: 1 - - name: PSUSP - description: Port suspend. - bit_offset: 7 - bit_size: 1 - - name: PRST - description: Port reset. - bit_offset: 8 - bit_size: 1 - - name: PLSTS - description: Port line status. - bit_offset: 10 - bit_size: 2 - - name: PPWR - description: Port power. - bit_offset: 12 - bit_size: 1 - - name: PTCTL - description: Port test control. - bit_offset: 13 - bit_size: 4 - - name: PSPD - description: Port speed. - bit_offset: 17 - bit_size: 2 -fieldset/HPTXSTS: - description: OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS). - fields: - - name: PTXFSAVL - description: Periodic transmit data FIFO space available. - bit_offset: 0 - bit_size: 16 - - name: PTXQSAV - description: Periodic transmit request queue space available. - bit_offset: 16 - bit_size: 8 - - name: PTXQTOP - description: Top of the periodic transmit request queue. - bit_offset: 24 - bit_size: 8 -fieldset/INT: +fieldset/HC0_INT: description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). fields: - name: XFRC @@ -252,7 +311,7 @@ fieldset/INT: description: Data toggle error. bit_offset: 10 bit_size: 1 -fieldset/INTMSK: +fieldset/HC0_INTMSK: description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). fields: - name: XFRCM @@ -295,7 +354,7 @@ fieldset/INTMSK: description: Data toggle error mask. bit_offset: 10 bit_size: 1 -fieldset/TSIZ: +fieldset/HC0_TSIZ: description: OTG_FS host channel-0 transfer size register. fields: - name: XFRSIZ @@ -310,3 +369,1082 @@ fieldset/TSIZ: description: Data PID. bit_offset: 29 bit_size: 2 +fieldset/HC1_CHAR: + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + fields: + - name: MPSIZ + description: Maximum packet size. + bit_offset: 0 + bit_size: 11 + - name: EPNUM + description: Endpoint number. + bit_offset: 11 + bit_size: 4 + - name: EPDIR + description: Endpoint direction. + bit_offset: 15 + bit_size: 1 + - name: LSDEV + description: Low-speed device. + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: Endpoint type. + bit_offset: 18 + bit_size: 2 + - name: MCNT + description: Multicount. + bit_offset: 20 + bit_size: 2 + - name: DAD + description: Device address. + bit_offset: 22 + bit_size: 7 + - name: ODDFRM + description: Odd frame. + bit_offset: 29 + bit_size: 1 + - name: CHDIS + description: Channel disable. + bit_offset: 30 + bit_size: 1 + - name: CHENA + description: Channel enable. + bit_offset: 31 + bit_size: 1 +fieldset/HC1_INT: + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + fields: + - name: XFRC + description: Transfer completed. + bit_offset: 0 + bit_size: 1 + - name: CHH + description: Channel halted. + bit_offset: 1 + bit_size: 1 + - name: STALL + description: STALL response received interrupt. + bit_offset: 3 + bit_size: 1 + - name: NAK + description: NAK response received interrupt. + bit_offset: 4 + bit_size: 1 + - name: ACK + description: ACK response received/transmitted interrupt. + bit_offset: 5 + bit_size: 1 + - name: TXERR + description: Transaction error. + bit_offset: 7 + bit_size: 1 + - name: BBERR + description: Babble error. + bit_offset: 8 + bit_size: 1 + - name: FRMOR + description: Frame overrun. + bit_offset: 9 + bit_size: 1 + - name: DTERR + description: Data toggle error. + bit_offset: 10 + bit_size: 1 +fieldset/HC1_INTMSK: + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + fields: + - name: XFRCM + description: Transfer completed mask. + bit_offset: 0 + bit_size: 1 + - name: CHHM + description: Channel halted mask. + bit_offset: 1 + bit_size: 1 + - name: STALLM + description: STALL response received interrupt mask. + bit_offset: 3 + bit_size: 1 + - name: NAKM + description: NAK response received interrupt mask. + bit_offset: 4 + bit_size: 1 + - name: ACKM + description: ACK response received/transmitted interrupt mask. + bit_offset: 5 + bit_size: 1 + - name: NYET + description: response received interrupt mask. + bit_offset: 6 + bit_size: 1 + - name: TXERRM + description: Transaction error mask. + bit_offset: 7 + bit_size: 1 + - name: BBERRM + description: Babble error mask. + bit_offset: 8 + bit_size: 1 + - name: FRMORM + description: Frame overrun mask. + bit_offset: 9 + bit_size: 1 + - name: DTERRM + description: Data toggle error mask. + bit_offset: 10 + bit_size: 1 +fieldset/HC1_TSIZ: + description: OTG_FS host channel-0 transfer size register. + fields: + - name: XFRSIZ + description: Transfer size. + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count. + bit_offset: 19 + bit_size: 10 + - name: DPID + description: Data PID. + bit_offset: 29 + bit_size: 2 +fieldset/HC2_CHAR: + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + fields: + - name: MPSIZ + description: Maximum packet size. + bit_offset: 0 + bit_size: 11 + - name: EPNUM + description: Endpoint number. + bit_offset: 11 + bit_size: 4 + - name: EPDIR + description: Endpoint direction. + bit_offset: 15 + bit_size: 1 + - name: LSDEV + description: Low-speed device. + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: Endpoint type. + bit_offset: 18 + bit_size: 2 + - name: MCNT + description: Multicount. + bit_offset: 20 + bit_size: 2 + - name: DAD + description: Device address. + bit_offset: 22 + bit_size: 7 + - name: ODDFRM + description: Odd frame. + bit_offset: 29 + bit_size: 1 + - name: CHDIS + description: Channel disable. + bit_offset: 30 + bit_size: 1 + - name: CHENA + description: Channel enable. + bit_offset: 31 + bit_size: 1 +fieldset/HC2_INT: + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + fields: + - name: XFRC + description: Transfer completed. + bit_offset: 0 + bit_size: 1 + - name: CHH + description: Channel halted. + bit_offset: 1 + bit_size: 1 + - name: STALL + description: STALL response received interrupt. + bit_offset: 3 + bit_size: 1 + - name: NAK + description: NAK response received interrupt. + bit_offset: 4 + bit_size: 1 + - name: ACK + description: ACK response received/transmitted interrupt. + bit_offset: 5 + bit_size: 1 + - name: TXERR + description: Transaction error. + bit_offset: 7 + bit_size: 1 + - name: BBERR + description: Babble error. + bit_offset: 8 + bit_size: 1 + - name: FRMOR + description: Frame overrun. + bit_offset: 9 + bit_size: 1 + - name: DTERR + description: Data toggle error. + bit_offset: 10 + bit_size: 1 +fieldset/HC2_INTMSK: + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + fields: + - name: XFRCM + description: Transfer completed mask. + bit_offset: 0 + bit_size: 1 + - name: CHHM + description: Channel halted mask. + bit_offset: 1 + bit_size: 1 + - name: STALLM + description: STALL response received interrupt mask. + bit_offset: 3 + bit_size: 1 + - name: NAKM + description: NAK response received interrupt mask. + bit_offset: 4 + bit_size: 1 + - name: ACKM + description: ACK response received/transmitted interrupt mask. + bit_offset: 5 + bit_size: 1 + - name: NYET + description: response received interrupt mask. + bit_offset: 6 + bit_size: 1 + - name: TXERRM + description: Transaction error mask. + bit_offset: 7 + bit_size: 1 + - name: BBERRM + description: Babble error mask. + bit_offset: 8 + bit_size: 1 + - name: FRMORM + description: Frame overrun mask. + bit_offset: 9 + bit_size: 1 + - name: DTERRM + description: Data toggle error mask. + bit_offset: 10 + bit_size: 1 +fieldset/HC2_TSIZ: + description: OTG_FS host channel-0 transfer size register. + fields: + - name: XFRSIZ + description: Transfer size. + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count. + bit_offset: 19 + bit_size: 10 + - name: DPID + description: Data PID. + bit_offset: 29 + bit_size: 2 +fieldset/HC3_CHAR: + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + fields: + - name: MPSIZ + description: Maximum packet size. + bit_offset: 0 + bit_size: 11 + - name: EPNUM + description: Endpoint number. + bit_offset: 11 + bit_size: 4 + - name: EPDIR + description: Endpoint direction. + bit_offset: 15 + bit_size: 1 + - name: LSDEV + description: Low-speed device. + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: Endpoint type. + bit_offset: 18 + bit_size: 2 + - name: MCNT + description: Multicount. + bit_offset: 20 + bit_size: 2 + - name: DAD + description: Device address. + bit_offset: 22 + bit_size: 7 + - name: ODDFRM + description: Odd frame. + bit_offset: 29 + bit_size: 1 + - name: CHDIS + description: Channel disable. + bit_offset: 30 + bit_size: 1 + - name: CHENA + description: Channel enable. + bit_offset: 31 + bit_size: 1 +fieldset/HC3_INT: + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + fields: + - name: XFRC + description: Transfer completed. + bit_offset: 0 + bit_size: 1 + - name: CHH + description: Channel halted. + bit_offset: 1 + bit_size: 1 + - name: STALL + description: STALL response received interrupt. + bit_offset: 3 + bit_size: 1 + - name: NAK + description: NAK response received interrupt. + bit_offset: 4 + bit_size: 1 + - name: ACK + description: ACK response received/transmitted interrupt. + bit_offset: 5 + bit_size: 1 + - name: TXERR + description: Transaction error. + bit_offset: 7 + bit_size: 1 + - name: BBERR + description: Babble error. + bit_offset: 8 + bit_size: 1 + - name: FRMOR + description: Frame overrun. + bit_offset: 9 + bit_size: 1 + - name: DTERR + description: Data toggle error. + bit_offset: 10 + bit_size: 1 +fieldset/HC3_INTMSK: + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + fields: + - name: XFRCM + description: Transfer completed mask. + bit_offset: 0 + bit_size: 1 + - name: CHHM + description: Channel halted mask. + bit_offset: 1 + bit_size: 1 + - name: STALLM + description: STALL response received interrupt mask. + bit_offset: 3 + bit_size: 1 + - name: NAKM + description: NAK response received interrupt mask. + bit_offset: 4 + bit_size: 1 + - name: ACKM + description: ACK response received/transmitted interrupt mask. + bit_offset: 5 + bit_size: 1 + - name: NYET + description: response received interrupt mask. + bit_offset: 6 + bit_size: 1 + - name: TXERRM + description: Transaction error mask. + bit_offset: 7 + bit_size: 1 + - name: BBERRM + description: Babble error mask. + bit_offset: 8 + bit_size: 1 + - name: FRMORM + description: Frame overrun mask. + bit_offset: 9 + bit_size: 1 + - name: DTERRM + description: Data toggle error mask. + bit_offset: 10 + bit_size: 1 +fieldset/HC3_TSIZ: + description: OTG_FS host channel-0 transfer size register. + fields: + - name: XFRSIZ + description: Transfer size. + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count. + bit_offset: 19 + bit_size: 10 + - name: DPID + description: Data PID. + bit_offset: 29 + bit_size: 2 +fieldset/HC4_CHAR: + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + fields: + - name: MPSIZ + description: Maximum packet size. + bit_offset: 0 + bit_size: 11 + - name: EPNUM + description: Endpoint number. + bit_offset: 11 + bit_size: 4 + - name: EPDIR + description: Endpoint direction. + bit_offset: 15 + bit_size: 1 + - name: LSDEV + description: Low-speed device. + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: Endpoint type. + bit_offset: 18 + bit_size: 2 + - name: MCNT + description: Multicount. + bit_offset: 20 + bit_size: 2 + - name: DAD + description: Device address. + bit_offset: 22 + bit_size: 7 + - name: ODDFRM + description: Odd frame. + bit_offset: 29 + bit_size: 1 + - name: CHDIS + description: Channel disable. + bit_offset: 30 + bit_size: 1 + - name: CHENA + description: Channel enable. + bit_offset: 31 + bit_size: 1 +fieldset/HC4_INT: + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + fields: + - name: XFRC + description: Transfer completed. + bit_offset: 0 + bit_size: 1 + - name: CHH + description: Channel halted. + bit_offset: 1 + bit_size: 1 + - name: STALL + description: STALL response received interrupt. + bit_offset: 3 + bit_size: 1 + - name: NAK + description: NAK response received interrupt. + bit_offset: 4 + bit_size: 1 + - name: ACK + description: ACK response received/transmitted interrupt. + bit_offset: 5 + bit_size: 1 + - name: TXERR + description: Transaction error. + bit_offset: 7 + bit_size: 1 + - name: BBERR + description: Babble error. + bit_offset: 8 + bit_size: 1 + - name: FRMOR + description: Frame overrun. + bit_offset: 9 + bit_size: 1 + - name: DTERR + description: Data toggle error. + bit_offset: 10 + bit_size: 1 +fieldset/HC4_INTMSK: + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + fields: + - name: XFRCM + description: Transfer completed mask. + bit_offset: 0 + bit_size: 1 + - name: CHHM + description: Channel halted mask. + bit_offset: 1 + bit_size: 1 + - name: STALLM + description: STALL response received interrupt mask. + bit_offset: 3 + bit_size: 1 + - name: NAKM + description: NAK response received interrupt mask. + bit_offset: 4 + bit_size: 1 + - name: ACKM + description: ACK response received/transmitted interrupt mask. + bit_offset: 5 + bit_size: 1 + - name: NYET + description: response received interrupt mask. + bit_offset: 6 + bit_size: 1 + - name: TXERRM + description: Transaction error mask. + bit_offset: 7 + bit_size: 1 + - name: BBERRM + description: Babble error mask. + bit_offset: 8 + bit_size: 1 + - name: FRMORM + description: Frame overrun mask. + bit_offset: 9 + bit_size: 1 + - name: DTERRM + description: Data toggle error mask. + bit_offset: 10 + bit_size: 1 +fieldset/HC4_TSIZ: + description: OTG_FS host channel-0 transfer size register. + fields: + - name: XFRSIZ + description: Transfer size. + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count. + bit_offset: 19 + bit_size: 10 + - name: DPID + description: Data PID. + bit_offset: 29 + bit_size: 2 +fieldset/HC5_CHAR: + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + fields: + - name: MPSIZ + description: Maximum packet size. + bit_offset: 0 + bit_size: 11 + - name: EPNUM + description: Endpoint number. + bit_offset: 11 + bit_size: 4 + - name: EPDIR + description: Endpoint direction. + bit_offset: 15 + bit_size: 1 + - name: LSDEV + description: Low-speed device. + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: Endpoint type. + bit_offset: 18 + bit_size: 2 + - name: MCNT + description: Multicount. + bit_offset: 20 + bit_size: 2 + - name: DAD + description: Device address. + bit_offset: 22 + bit_size: 7 + - name: ODDFRM + description: Odd frame. + bit_offset: 29 + bit_size: 1 + - name: CHDIS + description: Channel disable. + bit_offset: 30 + bit_size: 1 + - name: CHENA + description: Channel enable. + bit_offset: 31 + bit_size: 1 +fieldset/HC5_INT: + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + fields: + - name: XFRC + description: Transfer completed. + bit_offset: 0 + bit_size: 1 + - name: CHH + description: Channel halted. + bit_offset: 1 + bit_size: 1 + - name: STALL + description: STALL response received interrupt. + bit_offset: 3 + bit_size: 1 + - name: NAK + description: NAK response received interrupt. + bit_offset: 4 + bit_size: 1 + - name: ACK + description: ACK response received/transmitted interrupt. + bit_offset: 5 + bit_size: 1 + - name: TXERR + description: Transaction error. + bit_offset: 7 + bit_size: 1 + - name: BBERR + description: Babble error. + bit_offset: 8 + bit_size: 1 + - name: FRMOR + description: Frame overrun. + bit_offset: 9 + bit_size: 1 + - name: DTERR + description: Data toggle error. + bit_offset: 10 + bit_size: 1 +fieldset/HC5_INTMSK: + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + fields: + - name: XFRCM + description: Transfer completed mask. + bit_offset: 0 + bit_size: 1 + - name: CHHM + description: Channel halted mask. + bit_offset: 1 + bit_size: 1 + - name: STALLM + description: STALL response received interrupt mask. + bit_offset: 3 + bit_size: 1 + - name: NAKM + description: NAK response received interrupt mask. + bit_offset: 4 + bit_size: 1 + - name: ACKM + description: ACK response received/transmitted interrupt mask. + bit_offset: 5 + bit_size: 1 + - name: NYET + description: response received interrupt mask. + bit_offset: 6 + bit_size: 1 + - name: TXERRM + description: Transaction error mask. + bit_offset: 7 + bit_size: 1 + - name: BBERRM + description: Babble error mask. + bit_offset: 8 + bit_size: 1 + - name: FRMORM + description: Frame overrun mask. + bit_offset: 9 + bit_size: 1 + - name: DTERRM + description: Data toggle error mask. + bit_offset: 10 + bit_size: 1 +fieldset/HC5_TSIZ: + description: OTG_FS host channel-0 transfer size register. + fields: + - name: XFRSIZ + description: Transfer size. + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count. + bit_offset: 19 + bit_size: 10 + - name: DPID + description: Data PID. + bit_offset: 29 + bit_size: 2 +fieldset/HC6_CHAR: + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + fields: + - name: MPSIZ + description: Maximum packet size. + bit_offset: 0 + bit_size: 11 + - name: EPNUM + description: Endpoint number. + bit_offset: 11 + bit_size: 4 + - name: EPDIR + description: Endpoint direction. + bit_offset: 15 + bit_size: 1 + - name: LSDEV + description: Low-speed device. + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: Endpoint type. + bit_offset: 18 + bit_size: 2 + - name: MCNT + description: Multicount. + bit_offset: 20 + bit_size: 2 + - name: DAD + description: Device address. + bit_offset: 22 + bit_size: 7 + - name: ODDFRM + description: Odd frame. + bit_offset: 29 + bit_size: 1 + - name: CHDIS + description: Channel disable. + bit_offset: 30 + bit_size: 1 + - name: CHENA + description: Channel enable. + bit_offset: 31 + bit_size: 1 +fieldset/HC6_INT: + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + fields: + - name: XFRC + description: Transfer completed. + bit_offset: 0 + bit_size: 1 + - name: CHH + description: Channel halted. + bit_offset: 1 + bit_size: 1 + - name: STALL + description: STALL response received interrupt. + bit_offset: 3 + bit_size: 1 + - name: NAK + description: NAK response received interrupt. + bit_offset: 4 + bit_size: 1 + - name: ACK + description: ACK response received/transmitted interrupt. + bit_offset: 5 + bit_size: 1 + - name: TXERR + description: Transaction error. + bit_offset: 7 + bit_size: 1 + - name: BBERR + description: Babble error. + bit_offset: 8 + bit_size: 1 + - name: FRMOR + description: Frame overrun. + bit_offset: 9 + bit_size: 1 + - name: DTERR + description: Data toggle error. + bit_offset: 10 + bit_size: 1 +fieldset/HC6_INTMSK: + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + fields: + - name: XFRCM + description: Transfer completed mask. + bit_offset: 0 + bit_size: 1 + - name: CHHM + description: Channel halted mask. + bit_offset: 1 + bit_size: 1 + - name: STALLM + description: STALL response received interrupt mask. + bit_offset: 3 + bit_size: 1 + - name: NAKM + description: NAK response received interrupt mask. + bit_offset: 4 + bit_size: 1 + - name: ACKM + description: ACK response received/transmitted interrupt mask. + bit_offset: 5 + bit_size: 1 + - name: NYET + description: response received interrupt mask. + bit_offset: 6 + bit_size: 1 + - name: TXERRM + description: Transaction error mask. + bit_offset: 7 + bit_size: 1 + - name: BBERRM + description: Babble error mask. + bit_offset: 8 + bit_size: 1 + - name: FRMORM + description: Frame overrun mask. + bit_offset: 9 + bit_size: 1 + - name: DTERRM + description: Data toggle error mask. + bit_offset: 10 + bit_size: 1 +fieldset/HC6_TSIZ: + description: OTG_FS host channel-0 transfer size register. + fields: + - name: XFRSIZ + description: Transfer size. + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count. + bit_offset: 19 + bit_size: 10 + - name: DPID + description: Data PID. + bit_offset: 29 + bit_size: 2 +fieldset/HC7_CHAR: + description: OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0). + fields: + - name: MPSIZ + description: Maximum packet size. + bit_offset: 0 + bit_size: 11 + - name: EPNUM + description: Endpoint number. + bit_offset: 11 + bit_size: 4 + - name: EPDIR + description: Endpoint direction. + bit_offset: 15 + bit_size: 1 + - name: LSDEV + description: Low-speed device. + bit_offset: 17 + bit_size: 1 + - name: EPTYP + description: Endpoint type. + bit_offset: 18 + bit_size: 2 + - name: MCNT + description: Multicount. + bit_offset: 20 + bit_size: 2 + - name: DAD + description: Device address. + bit_offset: 22 + bit_size: 7 + - name: ODDFRM + description: Odd frame. + bit_offset: 29 + bit_size: 1 + - name: CHDIS + description: Channel disable. + bit_offset: 30 + bit_size: 1 + - name: CHENA + description: Channel enable. + bit_offset: 31 + bit_size: 1 +fieldset/HC7_INT: + description: OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0). + fields: + - name: XFRC + description: Transfer completed. + bit_offset: 0 + bit_size: 1 + - name: CHH + description: Channel halted. + bit_offset: 1 + bit_size: 1 + - name: STALL + description: STALL response received interrupt. + bit_offset: 3 + bit_size: 1 + - name: NAK + description: NAK response received interrupt. + bit_offset: 4 + bit_size: 1 + - name: ACK + description: ACK response received/transmitted interrupt. + bit_offset: 5 + bit_size: 1 + - name: TXERR + description: Transaction error. + bit_offset: 7 + bit_size: 1 + - name: BBERR + description: Babble error. + bit_offset: 8 + bit_size: 1 + - name: FRMOR + description: Frame overrun. + bit_offset: 9 + bit_size: 1 + - name: DTERR + description: Data toggle error. + bit_offset: 10 + bit_size: 1 +fieldset/HC7_INTMSK: + description: OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0). + fields: + - name: XFRCM + description: Transfer completed mask. + bit_offset: 0 + bit_size: 1 + - name: CHHM + description: Channel halted mask. + bit_offset: 1 + bit_size: 1 + - name: STALLM + description: STALL response received interrupt mask. + bit_offset: 3 + bit_size: 1 + - name: NAKM + description: NAK response received interrupt mask. + bit_offset: 4 + bit_size: 1 + - name: ACKM + description: ACK response received/transmitted interrupt mask. + bit_offset: 5 + bit_size: 1 + - name: NYET + description: response received interrupt mask. + bit_offset: 6 + bit_size: 1 + - name: TXERRM + description: Transaction error mask. + bit_offset: 7 + bit_size: 1 + - name: BBERRM + description: Babble error mask. + bit_offset: 8 + bit_size: 1 + - name: FRMORM + description: Frame overrun mask. + bit_offset: 9 + bit_size: 1 + - name: DTERRM + description: Data toggle error mask. + bit_offset: 10 + bit_size: 1 +fieldset/HC7_TSIZ: + description: OTG_FS host channel-0 transfer size register. + fields: + - name: XFRSIZ + description: Transfer size. + bit_offset: 0 + bit_size: 19 + - name: PKTCNT + description: Packet count. + bit_offset: 19 + bit_size: 10 + - name: DPID + description: Data PID. + bit_offset: 29 + bit_size: 2 +fieldset/HCFG: + description: OTG_FS host configuration register (OTG_FS_HCFG). + fields: + - name: FSLSPCS + description: FS/LS PHY clock select. + bit_offset: 0 + bit_size: 2 + - name: FSLSS + description: FS- and LS-only support. + bit_offset: 2 + bit_size: 1 +fieldset/HFIR: + description: OTG_FS Host frame interval register. + fields: + - name: FRIVL + description: Frame interval. + bit_offset: 0 + bit_size: 16 +fieldset/HFNUM: + description: OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM). + fields: + - name: FRNUM + description: Frame number. + bit_offset: 0 + bit_size: 16 + - name: FTREM + description: Frame time remaining. + bit_offset: 16 + bit_size: 16 +fieldset/HPRT: + description: OTG_FS host port control and status register (OTG_FS_HPRT). + fields: + - name: PCSTS + description: Port connect status. + bit_offset: 0 + bit_size: 1 + - name: PCDET + description: Port connect detected. + bit_offset: 1 + bit_size: 1 + - name: PENA + description: Port enable. + bit_offset: 2 + bit_size: 1 + - name: PENCHNG + description: Port enable/disable change. + bit_offset: 3 + bit_size: 1 + - name: POCA + description: Port overcurrent active. + bit_offset: 4 + bit_size: 1 + - name: POCCHNG + description: Port overcurrent change. + bit_offset: 5 + bit_size: 1 + - name: PRES + description: Port resume. + bit_offset: 6 + bit_size: 1 + - name: PSUSP + description: Port suspend. + bit_offset: 7 + bit_size: 1 + - name: PRST + description: Port reset. + bit_offset: 8 + bit_size: 1 + - name: PLSTS + description: Port line status. + bit_offset: 10 + bit_size: 2 + - name: PPWR + description: Port power. + bit_offset: 12 + bit_size: 1 + - name: PTCTL + description: Port test control. + bit_offset: 13 + bit_size: 4 + - name: PSPD + description: Port speed. + bit_offset: 17 + bit_size: 2 +fieldset/HPTXSTS: + description: OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS). + fields: + - name: PTXFSAVL + description: Periodic transmit data FIFO space available. + bit_offset: 0 + bit_size: 16 + - name: PTXQSAV + description: Periodic transmit request queue space available. + bit_offset: 16 + bit_size: 8 + - name: PTXQTOP + description: Top of the periodic transmit request queue. + bit_offset: 24 + bit_size: 8 diff --git a/base/STM32F103/SDIO.yaml b/head/STM32F103/SDIO.yaml index 6ebb440..a0d8ace 100644 --- a/base/STM32F103/SDIO.yaml +++ b/head/STM32F103/SDIO.yaml @@ -22,14 +22,26 @@ block/SDIO: byte_offset: 16 access: Read fieldset: RESPCMD - - name: RESP + - name: RESP1 description: SDIO response %s register. - array: - len: 4 - stride: 4 byte_offset: 20 access: Read fieldset: RESP + - name: RESP2 + description: SDIO response %s register. + byte_offset: 24 + access: Read + fieldset: RESP + - name: RESP3 + description: SDIO response %s register. + byte_offset: 28 + access: Read + fieldset: RESP + - name: RESP4 + description: SDIO response %s register. + byte_offset: 32 + access: Read + fieldset: RESP - name: DTIMER description: 'Bits 31:0 = DATATIME: Data timeout period.' byte_offset: 36 diff --git a/base/STM32F103/TIM1.yaml b/head/STM32F103/TIM1.yaml index d1593e2..b5bc546 100644 --- a/base/STM32F103/TIM1.yaml +++ b/head/STM32F103/TIM1.yaml @@ -77,14 +77,26 @@ block/TIM1: byte_offset: 48 bit_size: 16 fieldset: RCR - - name: CCR + - name: CCR1 description: capture/compare register. - array: - len: 4 - stride: 4 byte_offset: 52 bit_size: 16 fieldset: CCR + - name: CCR2 + description: capture/compare register. + byte_offset: 56 + bit_size: 16 + fieldset: CCR + - name: CCR3 + description: capture/compare register. + byte_offset: 60 + bit_size: 16 + fieldset: CCR + - name: CCR4 + description: capture/compare register. + byte_offset: 64 + bit_size: 16 + fieldset: CCR - name: BDTR description: break and dead-time register. byte_offset: 68 @@ -154,38 +166,76 @@ fieldset/CCER: description: capture/compare enable register. bit_size: 16 fields: - - name: CCE + - name: CC1E description: Capture/Compare %s output enable. bit_offset: 0 bit_size: 1 - array: - len: 4 - stride: 4 enum: CCE - - name: CCP + - name: CC1P description: Capture/Compare %s output Polarity. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 4 enum: CCP - - name: CCNE + - name: CC1NE description: Capture/Compare %s complementary output enable. bit_offset: 2 bit_size: 1 - array: - len: 3 - stride: 4 enum: CCNE - - name: CCNP + - name: CC1NP description: Capture/Compare %s output Polarity. bit_offset: 3 bit_size: 1 - array: - len: 3 - stride: 4 enum: CCNP + - name: CC2E + description: Capture/Compare %s output enable. + bit_offset: 4 + bit_size: 1 + enum: CCE + - name: CC2P + description: Capture/Compare %s output Polarity. + bit_offset: 5 + bit_size: 1 + enum: CCP + - name: CC2NE + description: Capture/Compare %s complementary output enable. + bit_offset: 6 + bit_size: 1 + enum: CCNE + - name: CC2NP + description: Capture/Compare %s output Polarity. + bit_offset: 7 + bit_size: 1 + enum: CCNP + - name: CC3E + description: Capture/Compare %s output enable. + bit_offset: 8 + bit_size: 1 + enum: CCE + - name: CC3P + description: Capture/Compare %s output Polarity. + bit_offset: 9 + bit_size: 1 + enum: CCP + - name: CC3NE + description: Capture/Compare %s complementary output enable. + bit_offset: 10 + bit_size: 1 + enum: CCNE + - name: CC3NP + description: Capture/Compare %s output Polarity. + bit_offset: 11 + bit_size: 1 + enum: CCNP + - name: CC4E + description: Capture/Compare %s output enable. + bit_offset: 12 + bit_size: 1 + enum: CCE + - name: CC4P + description: Capture/Compare %s output Polarity. + bit_offset: 13 + bit_size: 1 + enum: CCP fieldset/CCMR1_Input: description: capture/compare mode register 1 (input mode). bit_size: 16 @@ -195,70 +245,84 @@ fieldset/CCMR1_Input: bit_offset: 0 bit_size: 2 enum: CC1S - - name: ICPSC + - name: IC1PSC description: Input capture %s prescaler. bit_offset: 2 bit_size: 2 - array: - len: 2 - stride: 8 enum: ICPSC - - name: ICF + - name: IC1F description: Input capture %s filter. bit_offset: 4 bit_size: 4 - array: - len: 2 - stride: 8 enum: ICF - name: CC2S description: Capture/Compare 2 selection. bit_offset: 8 bit_size: 2 enum: CC2S + - name: IC2PSC + description: Input capture %s prescaler. + bit_offset: 10 + bit_size: 2 + enum: ICPSC + - name: IC2F + description: Input capture %s filter. + bit_offset: 12 + bit_size: 4 + enum: ICF fieldset/CCMR1_Output: description: capture/compare mode register (output mode). bit_size: 16 fields: - - name: CCS + - name: CC1S description: Capture/Compare %s selection. bit_offset: 0 bit_size: 2 - array: - len: 2 - stride: 8 enum: CCS - - name: OCFE + - name: OC1FE description: Output compare %s fast enable. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCFE - - name: OCPE + - name: OC1PE description: Output compare %s preload enable. bit_offset: 3 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCPE - - name: OCM + - name: OC1M description: Output compare %s mode. bit_offset: 4 bit_size: 3 - array: - len: 2 - stride: 8 enum: OCM - - name: OCCE + - name: OC1CE description: Output compare %s clear enable. bit_offset: 7 bit_size: 1 - array: - len: 2 - stride: 8 + enum: OCCE + - name: CC2S + description: Capture/Compare %s selection. + bit_offset: 8 + bit_size: 2 + enum: CCS + - name: OC2FE + description: Output compare %s fast enable. + bit_offset: 10 + bit_size: 1 + enum: OCFE + - name: OC2PE + description: Output compare %s preload enable. + bit_offset: 11 + bit_size: 1 + enum: OCPE + - name: OC2M + description: Output compare %s mode. + bit_offset: 12 + bit_size: 3 + enum: OCM + - name: OC2CE + description: Output compare %s clear enable. + bit_offset: 15 + bit_size: 1 enum: OCCE fieldset/CCMR2_Input: description: capture/compare mode register 2 (input mode). @@ -367,22 +431,41 @@ fieldset/CR2: bit_offset: 7 bit_size: 1 enum: TI1S - - name: OIS + - name: OIS1 description: Output Idle state (OC%s output). bit_offset: 8 bit_size: 1 - array: - len: 4 - stride: 2 enum: OIS - - name: OISN + - name: OIS1N description: Output Idle state (OC%sN output). bit_offset: 9 bit_size: 1 - array: - len: 3 - stride: 2 enum: OISN + - name: OIS2 + description: Output Idle state (OC%s output). + bit_offset: 10 + bit_size: 1 + enum: OIS + - name: OIS2N + description: Output Idle state (OC%sN output). + bit_offset: 11 + bit_size: 1 + enum: OISN + - name: OIS3 + description: Output Idle state (OC%s output). + bit_offset: 12 + bit_size: 1 + enum: OIS + - name: OIS3N + description: Output Idle state (OC%sN output). + bit_offset: 13 + bit_size: 1 + enum: OISN + - name: OIS4 + description: Output Idle state (OC%s output). + bit_offset: 14 + bit_size: 1 + enum: OIS fieldset/DCR: description: DMA control register. bit_size: 16 @@ -404,13 +487,25 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 enum: UIE - - name: CCIE + - name: CC1IE description: Capture/Compare %s interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIE + - name: CC2IE + description: Capture/Compare %s interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CCIE + - name: CC3IE + description: Capture/Compare %s interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CCIE + - name: CC4IE + description: Capture/Compare %s interrupt enable. + bit_offset: 4 + bit_size: 1 enum: CCIE - name: COMIE description: COM interrupt enable. @@ -432,13 +527,25 @@ fieldset/DIER: bit_offset: 8 bit_size: 1 enum: UDE - - name: CCDE + - name: CC1DE description: Capture/Compare %s DMA request enable. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCDE + - name: CC2DE + description: Capture/Compare %s DMA request enable. + bit_offset: 10 + bit_size: 1 + enum: CCDE + - name: CC3DE + description: Capture/Compare %s DMA request enable. + bit_offset: 11 + bit_size: 1 + enum: CCDE + - name: CC4DE + description: Capture/Compare %s DMA request enable. + bit_offset: 12 + bit_size: 1 enum: CCDE - name: COMDE description: COM DMA request enable. @@ -466,13 +573,25 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 enum: UG - - name: CCG + - name: CC1G description: Capture/compare %s generation. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCG + - name: CC2G + description: Capture/compare %s generation. + bit_offset: 2 + bit_size: 1 + enum: CCG + - name: CC3G + description: Capture/compare %s generation. + bit_offset: 3 + bit_size: 1 + enum: CCG + - name: CC4G + description: Capture/compare %s generation. + bit_offset: 4 + bit_size: 1 enum: CCG - name: COMG description: Capture/Compare control update generation. @@ -553,13 +672,25 @@ fieldset/SR: bit_offset: 0 bit_size: 1 enum: UIF - - name: CCIF + - name: CC1IF description: Capture/compare %s interrupt flag. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIF + - name: CC2IF + description: Capture/compare %s interrupt flag. + bit_offset: 2 + bit_size: 1 + enum: CCIF + - name: CC3IF + description: Capture/compare %s interrupt flag. + bit_offset: 3 + bit_size: 1 + enum: CCIF + - name: CC4IF + description: Capture/compare %s interrupt flag. + bit_offset: 4 + bit_size: 1 enum: CCIF - name: COMIF description: COM interrupt flag. @@ -576,13 +707,25 @@ fieldset/SR: bit_offset: 7 bit_size: 1 enum: BIF - - name: CCOF + - name: CC1OF description: Capture/Compare %s overcapture flag. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCOF + - name: CC2OF + description: Capture/Compare %s overcapture flag. + bit_offset: 10 + bit_size: 1 + enum: CCOF + - name: CC3OF + description: Capture/Compare %s overcapture flag. + bit_offset: 11 + bit_size: 1 + enum: CCOF + - name: CC4OF + description: Capture/Compare %s overcapture flag. + bit_offset: 12 + bit_size: 1 enum: CCOF enum/AOE: bit_size: 1 diff --git a/base/STM32F103/TIM10.yaml b/head/STM32F103/TIM10.yaml index f80e27c..5c7c69f 100644 --- a/base/STM32F103/TIM10.yaml +++ b/head/STM32F103/TIM10.yaml @@ -57,11 +57,8 @@ block/TIM10: byte_offset: 44 bit_size: 16 fieldset: ARR - - name: CCR + - name: CCR1 description: capture/compare register. - array: - len: 1 - stride: 2 byte_offset: 52 bit_size: 16 fieldset: CCR @@ -77,29 +74,20 @@ fieldset/CCER: description: capture/compare enable register. bit_size: 16 fields: - - name: CCE + - name: CC1E description: Capture/Compare %s output enable. bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCE - - name: CCP + - name: CC1P description: Capture/Compare %s output Polarity. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCP - - name: CCNP + - name: CC1NP description: Capture/Compare %s output Polarity. bit_offset: 3 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/CCMR1_Input: description: capture/compare mode register (input mode). bit_size: 16 @@ -109,57 +97,39 @@ fieldset/CCMR1_Input: bit_offset: 0 bit_size: 2 enum: CC1S - - name: ICPSC + - name: IC1PSC description: Input capture %s prescaler. bit_offset: 2 bit_size: 2 - array: - len: 1 - stride: 0 enum: ICPSC - - name: ICF + - name: IC1F description: Input capture %s filter. bit_offset: 4 bit_size: 4 - array: - len: 1 - stride: 0 enum: ICF fieldset/CCMR1_Output: description: capture/compare mode register (output mode). bit_size: 16 fields: - - name: CCS + - name: CC1S description: Capture/Compare %s selection. bit_offset: 0 bit_size: 2 - array: - len: 1 - stride: 0 enum: CCS - - name: OCFE + - name: OC1FE description: Output compare %s fast enable. bit_offset: 2 bit_size: 1 - array: - len: 1 - stride: 0 enum: OCFE - - name: OCPE + - name: OC1PE description: Output compare %s preload enable. bit_offset: 3 bit_size: 1 - array: - len: 1 - stride: 0 enum: OCPE - - name: OCM + - name: OC1M description: Output compare %s mode. bit_offset: 4 bit_size: 3 - array: - len: 1 - stride: 0 enum: OCM fieldset/CCR: description: capture/compare register. @@ -228,13 +198,10 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 enum: UIE - - name: CCIE + - name: CC1IE description: Capture/Compare %s interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCIE fieldset/EGR: description: event generation register. @@ -245,13 +212,10 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 enum: UG - - name: CCG + - name: CC1G description: Capture/compare %s generation. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCG fieldset/PSC: description: prescaler. @@ -270,21 +234,15 @@ fieldset/SR: bit_offset: 0 bit_size: 1 enum: UIF - - name: CCIF + - name: CC1IF description: Capture/compare %s interrupt flag. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCIF - - name: CCOF + - name: CC1OF description: Capture/Compare %s overcapture flag. bit_offset: 9 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCOF enum/ARPE: bit_size: 1 diff --git a/base/STM32F103/TIM2.yaml b/head/STM32F103/TIM2.yaml index b5de09d..3c44ac4 100644 --- a/base/STM32F103/TIM2.yaml +++ b/head/STM32F103/TIM2.yaml @@ -72,14 +72,26 @@ block/TIM2: byte_offset: 44 bit_size: 16 fieldset: ARR - - name: CCR + - name: CCR1 description: capture/compare register. - array: - len: 4 - stride: 4 byte_offset: 52 bit_size: 16 fieldset: CCR + - name: CCR2 + description: capture/compare register. + byte_offset: 56 + bit_size: 16 + fieldset: CCR + - name: CCR3 + description: capture/compare register. + byte_offset: 60 + bit_size: 16 + fieldset: CCR + - name: CCR4 + description: capture/compare register. + byte_offset: 64 + bit_size: 16 + fieldset: CCR - name: DCR description: DMA control register. byte_offset: 72 @@ -102,21 +114,45 @@ fieldset/CCER: description: capture/compare enable register. bit_size: 16 fields: - - name: CCE + - name: CC1E description: Capture/Compare %s output enable. bit_offset: 0 bit_size: 1 - array: - len: 4 - stride: 4 enum: CCE - - name: CCP + - name: CC1P description: Capture/Compare %s output Polarity. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 4 + enum: CCP + - name: CC2E + description: Capture/Compare %s output enable. + bit_offset: 4 + bit_size: 1 + enum: CCE + - name: CC2P + description: Capture/Compare %s output Polarity. + bit_offset: 5 + bit_size: 1 + enum: CCP + - name: CC3E + description: Capture/Compare %s output enable. + bit_offset: 8 + bit_size: 1 + enum: CCE + - name: CC3P + description: Capture/Compare %s output Polarity. + bit_offset: 9 + bit_size: 1 + enum: CCP + - name: CC4E + description: Capture/Compare %s output enable. + bit_offset: 12 + bit_size: 1 + enum: CCE + - name: CC4P + description: Capture/Compare %s output Polarity. + bit_offset: 13 + bit_size: 1 enum: CCP fieldset/CCMR1_Input: description: capture/compare mode register 1 (input mode). @@ -127,70 +163,84 @@ fieldset/CCMR1_Input: bit_offset: 0 bit_size: 2 enum: CC1S - - name: ICPSC + - name: IC1PSC description: Input capture %s prescaler. bit_offset: 2 bit_size: 2 - array: - len: 2 - stride: 8 enum: ICPSC - - name: ICF + - name: IC1F description: Input capture %s filter. bit_offset: 4 bit_size: 4 - array: - len: 2 - stride: 8 enum: ICF - name: CC2S description: Capture/compare 2 selection. bit_offset: 8 bit_size: 2 enum: CC2S + - name: IC2PSC + description: Input capture %s prescaler. + bit_offset: 10 + bit_size: 2 + enum: ICPSC + - name: IC2F + description: Input capture %s filter. + bit_offset: 12 + bit_size: 4 + enum: ICF fieldset/CCMR1_Output: description: capture/compare mode register 1 (output mode). bit_size: 16 fields: - - name: CCS + - name: CC1S description: Capture/Compare %s selection. bit_offset: 0 bit_size: 2 - array: - len: 2 - stride: 8 enum: CCS - - name: OCFE + - name: OC1FE description: Output compare %s fast enable. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCFE - - name: OCPE + - name: OC1PE description: Output compare %s preload enable. bit_offset: 3 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCPE - - name: OCM + - name: OC1M description: Output compare %s mode. bit_offset: 4 bit_size: 3 - array: - len: 2 - stride: 8 enum: OCM - - name: OCCE + - name: OC1CE description: Output compare %s clear enable. bit_offset: 7 bit_size: 1 - array: - len: 2 - stride: 8 + enum: OCCE + - name: CC2S + description: Capture/Compare %s selection. + bit_offset: 8 + bit_size: 2 + enum: CCS + - name: OC2FE + description: Output compare %s fast enable. + bit_offset: 10 + bit_size: 1 + enum: OCFE + - name: OC2PE + description: Output compare %s preload enable. + bit_offset: 11 + bit_size: 1 + enum: OCPE + - name: OC2M + description: Output compare %s mode. + bit_offset: 12 + bit_size: 3 + enum: OCM + - name: OC2CE + description: Output compare %s clear enable. + bit_offset: 15 + bit_size: 1 enum: OCCE fieldset/CCMR2_Input: description: capture/compare mode register 2 (input mode). @@ -310,13 +360,25 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 enum: UIE - - name: CCIE + - name: CC1IE description: Capture/Compare %s interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIE + - name: CC2IE + description: Capture/Compare %s interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CCIE + - name: CC3IE + description: Capture/Compare %s interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CCIE + - name: CC4IE + description: Capture/Compare %s interrupt enable. + bit_offset: 4 + bit_size: 1 enum: CCIE - name: TIE description: Trigger interrupt enable. @@ -328,13 +390,25 @@ fieldset/DIER: bit_offset: 8 bit_size: 1 enum: UDE - - name: CCDE + - name: CC1DE description: Capture/Compare %s DMA request enable. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCDE + - name: CC2DE + description: Capture/Compare %s DMA request enable. + bit_offset: 10 + bit_size: 1 + enum: CCDE + - name: CC3DE + description: Capture/Compare %s DMA request enable. + bit_offset: 11 + bit_size: 1 + enum: CCDE + - name: CC4DE + description: Capture/Compare %s DMA request enable. + bit_offset: 12 + bit_size: 1 enum: CCDE - name: TDE description: Trigger DMA request enable. @@ -358,13 +432,25 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 enum: UG - - name: CCG + - name: CC1G description: Capture/compare %s generation. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCG + - name: CC2G + description: Capture/compare %s generation. + bit_offset: 2 + bit_size: 1 + enum: CCG + - name: CC3G + description: Capture/compare %s generation. + bit_offset: 3 + bit_size: 1 + enum: CCG + - name: CC4G + description: Capture/compare %s generation. + bit_offset: 4 + bit_size: 1 enum: CCG - name: TG description: Trigger generation. @@ -427,26 +513,50 @@ fieldset/SR: bit_offset: 0 bit_size: 1 enum: UIF - - name: CCIF + - name: CC1IF description: Capture/compare %s interrupt flag. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIF + - name: CC2IF + description: Capture/compare %s interrupt flag. + bit_offset: 2 + bit_size: 1 + enum: CCIF + - name: CC3IF + description: Capture/compare %s interrupt flag. + bit_offset: 3 + bit_size: 1 + enum: CCIF + - name: CC4IF + description: Capture/compare %s interrupt flag. + bit_offset: 4 + bit_size: 1 enum: CCIF - name: TIF description: Trigger interrupt flag. bit_offset: 6 bit_size: 1 enum: TIF - - name: CCOF + - name: CC1OF description: Capture/Compare %s overcapture flag. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCOF + - name: CC2OF + description: Capture/Compare %s overcapture flag. + bit_offset: 10 + bit_size: 1 + enum: CCOF + - name: CC3OF + description: Capture/Compare %s overcapture flag. + bit_offset: 11 + bit_size: 1 + enum: CCOF + - name: CC4OF + description: Capture/Compare %s overcapture flag. + bit_offset: 12 + bit_size: 1 enum: CCOF enum/ARPE: bit_size: 1 diff --git a/base/STM32F103/TIM9.yaml b/head/STM32F103/TIM9.yaml index 2977274..6687626 100644 --- a/base/STM32F103/TIM9.yaml +++ b/head/STM32F103/TIM9.yaml @@ -62,14 +62,16 @@ block/TIM9: byte_offset: 44 bit_size: 16 fieldset: ARR - - name: CCR + - name: CCR1 description: capture/compare register. - array: - len: 2 - stride: 4 byte_offset: 52 bit_size: 16 fieldset: CCR + - name: CCR2 + description: capture/compare register. + byte_offset: 56 + bit_size: 16 + fieldset: CCR fieldset/ARR: description: auto-reload register. bit_size: 16 @@ -82,29 +84,34 @@ fieldset/CCER: description: capture/compare enable register. bit_size: 16 fields: - - name: CCE + - name: CC1E description: Capture/Compare %s output enable. bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 4 enum: CCE - - name: CCP + - name: CC1P description: Capture/Compare %s output Polarity. bit_offset: 1 bit_size: 1 - array: - len: 2 - stride: 4 enum: CCP - - name: CCNP + - name: CC1NP description: Capture/Compare %s output Polarity. bit_offset: 3 bit_size: 1 - array: - len: 2 - stride: 4 + - name: CC2E + description: Capture/Compare %s output enable. + bit_offset: 4 + bit_size: 1 + enum: CCE + - name: CC2P + description: Capture/Compare %s output Polarity. + bit_offset: 5 + bit_size: 1 + enum: CCP + - name: CC2NP + description: Capture/Compare %s output Polarity. + bit_offset: 7 + bit_size: 1 fieldset/CCMR1_Input: description: capture/compare mode register 1 (input mode). bit_size: 16 @@ -114,62 +121,74 @@ fieldset/CCMR1_Input: bit_offset: 0 bit_size: 2 enum: CC1S - - name: ICPSC + - name: IC1PSC description: Input capture %s prescaler. bit_offset: 2 bit_size: 2 - array: - len: 2 - stride: 8 enum: ICPSC - - name: ICF + - name: IC1F description: Input capture %s filter. bit_offset: 4 bit_size: 4 - array: - len: 2 - stride: 8 enum: ICF - name: CC2S description: Capture/Compare 2 selection. bit_offset: 8 bit_size: 2 enum: CC2S + - name: IC2PSC + description: Input capture %s prescaler. + bit_offset: 10 + bit_size: 2 + enum: ICPSC + - name: IC2F + description: Input capture %s filter. + bit_offset: 12 + bit_size: 4 + enum: ICF fieldset/CCMR1_Output: description: capture/compare mode register 1 (output mode). bit_size: 16 fields: - - name: CCS + - name: CC1S description: Capture/Compare %s selection. bit_offset: 0 bit_size: 2 - array: - len: 2 - stride: 8 enum: CCS - - name: OCFE + - name: OC1FE description: Output compare %s fast enable. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCFE - - name: OCPE + - name: OC1PE description: Output compare %s preload enable. bit_offset: 3 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCPE - - name: OCM + - name: OC1M description: Output compare %s mode. bit_offset: 4 bit_size: 3 - array: - len: 2 - stride: 8 + enum: OCM + - name: CC2S + description: Capture/Compare %s selection. + bit_offset: 8 + bit_size: 2 + enum: CCS + - name: OC2FE + description: Output compare %s fast enable. + bit_offset: 10 + bit_size: 1 + enum: OCFE + - name: OC2PE + description: Output compare %s preload enable. + bit_offset: 11 + bit_size: 1 + enum: OCPE + - name: OC2M + description: Output compare %s mode. + bit_offset: 12 + bit_size: 3 enum: OCM fieldset/CCR: description: capture/compare register. @@ -238,13 +257,15 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 enum: UIE - - name: CCIE + - name: CC1IE description: Capture/Compare %s interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 2 - stride: 1 + enum: CCIE + - name: CC2IE + description: Capture/Compare %s interrupt enable. + bit_offset: 2 + bit_size: 1 enum: CCIE - name: TIE description: Trigger interrupt enable. @@ -260,13 +281,15 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 enum: UG - - name: CCG + - name: CC1G description: Capture/compare %s generation. bit_offset: 1 bit_size: 1 - array: - len: 2 - stride: 1 + enum: CCG + - name: CC2G + description: Capture/compare %s generation. + bit_offset: 2 + bit_size: 1 enum: CCG - name: TG description: Trigger generation. @@ -308,26 +331,30 @@ fieldset/SR: bit_offset: 0 bit_size: 1 enum: UIF - - name: CCIF + - name: CC1IF description: Capture/compare %s interrupt flag. bit_offset: 1 bit_size: 1 - array: - len: 2 - stride: 1 + enum: CCIF + - name: CC2IF + description: Capture/compare %s interrupt flag. + bit_offset: 2 + bit_size: 1 enum: CCIF - name: TIF description: Trigger interrupt flag. bit_offset: 6 bit_size: 1 enum: TIF - - name: CCOF + - name: CC1OF description: Capture/Compare %s overcapture flag. bit_offset: 9 bit_size: 1 - array: - len: 2 - stride: 1 + enum: CCOF + - name: CC2OF + description: Capture/Compare %s overcapture flag. + bit_offset: 10 + bit_size: 1 enum: CCOF enum/ARPE: bit_size: 1 diff --git a/base/STM32F103/USB.yaml b/head/STM32F103/USB.yaml index b4a02b6..f00e4cb 100644 --- a/base/STM32F103/USB.yaml +++ b/head/STM32F103/USB.yaml @@ -1,13 +1,38 @@ block/USB: description: Universal serial bus full-speed device interface. items: - - name: EPR + - name: EP0R description: endpoint %s register. - array: - len: 8 - stride: 4 byte_offset: 0 fieldset: EPR + - name: EP1R + description: endpoint %s register. + byte_offset: 4 + fieldset: EPR + - name: EP2R + description: endpoint %s register. + byte_offset: 8 + fieldset: EPR + - name: EP3R + description: endpoint %s register. + byte_offset: 12 + fieldset: EPR + - name: EP4R + description: endpoint %s register. + byte_offset: 16 + fieldset: EPR + - name: EP5R + description: endpoint %s register. + byte_offset: 20 + fieldset: EPR + - name: EP6R + description: endpoint %s register. + byte_offset: 24 + fieldset: EPR + - name: EP7R + description: endpoint %s register. + byte_offset: 28 + fieldset: EPR - name: CNTR description: control register. byte_offset: 64 diff --git a/base/STM32MP157/DSI.yaml b/head/STM32MP157/DSI.yaml index 925a77d..ee3f755 100644 --- a/base/STM32MP157/DSI.yaml +++ b/head/STM32MP157/DSI.yaml @@ -444,20 +444,90 @@ fieldset/DLTRCR: fieldset/FIR0: description: DSI Host force interrupt register 0. fields: - - name: FAE + - name: FAE0 description: Force acknowledge error %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 - - name: FPE + - name: FAE1 + description: Force acknowledge error %s. + bit_offset: 1 + bit_size: 1 + - name: FAE2 + description: Force acknowledge error %s. + bit_offset: 2 + bit_size: 1 + - name: FAE3 + description: Force acknowledge error %s. + bit_offset: 3 + bit_size: 1 + - name: FAE4 + description: Force acknowledge error %s. + bit_offset: 4 + bit_size: 1 + - name: FAE5 + description: Force acknowledge error %s. + bit_offset: 5 + bit_size: 1 + - name: FAE6 + description: Force acknowledge error %s. + bit_offset: 6 + bit_size: 1 + - name: FAE7 + description: Force acknowledge error %s. + bit_offset: 7 + bit_size: 1 + - name: FAE8 + description: Force acknowledge error %s. + bit_offset: 8 + bit_size: 1 + - name: FAE9 + description: Force acknowledge error %s. + bit_offset: 9 + bit_size: 1 + - name: FAE10 + description: Force acknowledge error %s. + bit_offset: 10 + bit_size: 1 + - name: FAE11 + description: Force acknowledge error %s. + bit_offset: 11 + bit_size: 1 + - name: FAE12 + description: Force acknowledge error %s. + bit_offset: 12 + bit_size: 1 + - name: FAE13 + description: Force acknowledge error %s. + bit_offset: 13 + bit_size: 1 + - name: FAE14 + description: Force acknowledge error %s. + bit_offset: 14 + bit_size: 1 + - name: FAE15 + description: Force acknowledge error %s. + bit_offset: 15 + bit_size: 1 + - name: FPE0 description: Force PHY error %s. bit_offset: 16 bit_size: 1 - array: - len: 5 - stride: 1 + - name: FPE1 + description: Force PHY error %s. + bit_offset: 17 + bit_size: 1 + - name: FPE2 + description: Force PHY error %s. + bit_offset: 18 + bit_size: 1 + - name: FPE3 + description: Force PHY error %s. + bit_offset: 19 + bit_size: 1 + - name: FPE4 + description: Force PHY error %s. + bit_offset: 20 + bit_size: 1 fieldset/FIR1: description: DSI Host force interrupt register 1. fields: @@ -603,20 +673,90 @@ fieldset/HWCFGR: fieldset/IER0: description: DSI Host interrupt enable register 0. fields: - - name: AEIE + - name: AE0IE description: Acknowledge error %s interrupt enable. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 - - name: PEIE + - name: AE1IE + description: Acknowledge error %s interrupt enable. + bit_offset: 1 + bit_size: 1 + - name: AE2IE + description: Acknowledge error %s interrupt enable. + bit_offset: 2 + bit_size: 1 + - name: AE3IE + description: Acknowledge error %s interrupt enable. + bit_offset: 3 + bit_size: 1 + - name: AE4IE + description: Acknowledge error %s interrupt enable. + bit_offset: 4 + bit_size: 1 + - name: AE5IE + description: Acknowledge error %s interrupt enable. + bit_offset: 5 + bit_size: 1 + - name: AE6IE + description: Acknowledge error %s interrupt enable. + bit_offset: 6 + bit_size: 1 + - name: AE7IE + description: Acknowledge error %s interrupt enable. + bit_offset: 7 + bit_size: 1 + - name: AE8IE + description: Acknowledge error %s interrupt enable. + bit_offset: 8 + bit_size: 1 + - name: AE9IE + description: Acknowledge error %s interrupt enable. + bit_offset: 9 + bit_size: 1 + - name: AE10IE + description: Acknowledge error %s interrupt enable. + bit_offset: 10 + bit_size: 1 + - name: AE11IE + description: Acknowledge error %s interrupt enable. + bit_offset: 11 + bit_size: 1 + - name: AE12IE + description: Acknowledge error %s interrupt enable. + bit_offset: 12 + bit_size: 1 + - name: AE13IE + description: Acknowledge error %s interrupt enable. + bit_offset: 13 + bit_size: 1 + - name: AE14IE + description: Acknowledge error %s interrupt enable. + bit_offset: 14 + bit_size: 1 + - name: AE15IE + description: Acknowledge error %s interrupt enable. + bit_offset: 15 + bit_size: 1 + - name: PE0IE description: PHY error %s interrupt enable. bit_offset: 16 bit_size: 1 - array: - len: 5 - stride: 1 + - name: PE1IE + description: PHY error %s interrupt enable. + bit_offset: 17 + bit_size: 1 + - name: PE2IE + description: PHY error %s interrupt enable. + bit_offset: 18 + bit_size: 1 + - name: PE3IE + description: PHY error %s interrupt enable. + bit_offset: 19 + bit_size: 1 + - name: PE4IE + description: PHY error %s interrupt enable. + bit_offset: 20 + bit_size: 1 fieldset/IER1: description: DSI Host interrupt enable register 1. fields: @@ -682,20 +822,90 @@ fieldset/IPIDR: fieldset/ISR0: description: DSI Host interrupt and status register 0. fields: - - name: AE + - name: AE0 description: Acknowledge error %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 - - name: PE + - name: AE1 + description: Acknowledge error %s. + bit_offset: 1 + bit_size: 1 + - name: AE2 + description: Acknowledge error %s. + bit_offset: 2 + bit_size: 1 + - name: AE3 + description: Acknowledge error %s. + bit_offset: 3 + bit_size: 1 + - name: AE4 + description: Acknowledge error %s. + bit_offset: 4 + bit_size: 1 + - name: AE5 + description: Acknowledge error %s. + bit_offset: 5 + bit_size: 1 + - name: AE6 + description: Acknowledge error %s. + bit_offset: 6 + bit_size: 1 + - name: AE7 + description: Acknowledge error %s. + bit_offset: 7 + bit_size: 1 + - name: AE8 + description: Acknowledge error %s. + bit_offset: 8 + bit_size: 1 + - name: AE9 + description: Acknowledge error %s. + bit_offset: 9 + bit_size: 1 + - name: AE10 + description: Acknowledge error %s. + bit_offset: 10 + bit_size: 1 + - name: AE11 + description: Acknowledge error %s. + bit_offset: 11 + bit_size: 1 + - name: AE12 + description: Acknowledge error %s. + bit_offset: 12 + bit_size: 1 + - name: AE13 + description: Acknowledge error %s. + bit_offset: 13 + bit_size: 1 + - name: AE14 + description: Acknowledge error %s. + bit_offset: 14 + bit_size: 1 + - name: AE15 + description: Acknowledge error %s. + bit_offset: 15 + bit_size: 1 + - name: PE0 description: PHY error %s. bit_offset: 16 bit_size: 1 - array: - len: 5 - stride: 1 + - name: PE1 + description: PHY error %s. + bit_offset: 17 + bit_size: 1 + - name: PE2 + description: PHY error %s. + bit_offset: 18 + bit_size: 1 + - name: PE3 + description: PHY error %s. + bit_offset: 19 + bit_size: 1 + - name: PE4 + description: PHY error %s. + bit_offset: 20 + bit_size: 1 fieldset/ISR1: description: DSI Host interrupt and status register 1. fields: diff --git a/base/STM32MP157/GPIOA.yaml b/head/STM32MP157/GPIOA.yaml index 8697c69..9b7a62f 100644 --- a/base/STM32MP157/GPIOA.yaml +++ b/head/STM32MP157/GPIOA.yaml @@ -124,43 +124,291 @@ fieldset/AFRH: fieldset/AFRL: description: GPIO alternate function low register. fields: - - name: AFR + - name: AFR0 description: AFR%s. bit_offset: 0 bit_size: 4 - array: - len: 8 - stride: 4 + enum: AFR + - name: AFR1 + description: AFR%s. + bit_offset: 4 + bit_size: 4 + enum: AFR + - name: AFR2 + description: AFR%s. + bit_offset: 8 + bit_size: 4 + enum: AFR + - name: AFR3 + description: AFR%s. + bit_offset: 12 + bit_size: 4 + enum: AFR + - name: AFR4 + description: AFR%s. + bit_offset: 16 + bit_size: 4 + enum: AFR + - name: AFR5 + description: AFR%s. + bit_offset: 20 + bit_size: 4 + enum: AFR + - name: AFR6 + description: AFR%s. + bit_offset: 24 + bit_size: 4 + enum: AFR + - name: AFR7 + description: AFR%s. + bit_offset: 28 + bit_size: 4 enum: AFR fieldset/BRR: description: GPIO port bit reset register. fields: - - name: BR + - name: BR0 description: Port x reset pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: BRR_BR + - name: BR1 + description: Port x reset pin %s. + bit_offset: 1 + bit_size: 1 + enum: BRR_BR + - name: BR2 + description: Port x reset pin %s. + bit_offset: 2 + bit_size: 1 + enum: BRR_BR + - name: BR3 + description: Port x reset pin %s. + bit_offset: 3 + bit_size: 1 + enum: BRR_BR + - name: BR4 + description: Port x reset pin %s. + bit_offset: 4 + bit_size: 1 + enum: BRR_BR + - name: BR5 + description: Port x reset pin %s. + bit_offset: 5 + bit_size: 1 + enum: BRR_BR + - name: BR6 + description: Port x reset pin %s. + bit_offset: 6 + bit_size: 1 + enum: BRR_BR + - name: BR7 + description: Port x reset pin %s. + bit_offset: 7 + bit_size: 1 + enum: BRR_BR + - name: BR8 + description: Port x reset pin %s. + bit_offset: 8 + bit_size: 1 + enum: BRR_BR + - name: BR9 + description: Port x reset pin %s. + bit_offset: 9 + bit_size: 1 + enum: BRR_BR + - name: BR10 + description: Port x reset pin %s. + bit_offset: 10 + bit_size: 1 + enum: BRR_BR + - name: BR11 + description: Port x reset pin %s. + bit_offset: 11 + bit_size: 1 + enum: BRR_BR + - name: BR12 + description: Port x reset pin %s. + bit_offset: 12 + bit_size: 1 + enum: BRR_BR + - name: BR13 + description: Port x reset pin %s. + bit_offset: 13 + bit_size: 1 + enum: BRR_BR + - name: BR14 + description: Port x reset pin %s. + bit_offset: 14 + bit_size: 1 + enum: BRR_BR + - name: BR15 + description: Port x reset pin %s. + bit_offset: 15 + bit_size: 1 enum: BRR_BR fieldset/BSRR: description: GPIO port bit set/reset register. fields: - - name: BS + - name: BS0 description: Port x set pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 enum: BS - - name: BR + - name: BS1 + description: Port x set pin %s. + bit_offset: 1 + bit_size: 1 + enum: BS + - name: BS2 + description: Port x set pin %s. + bit_offset: 2 + bit_size: 1 + enum: BS + - name: BS3 + description: Port x set pin %s. + bit_offset: 3 + bit_size: 1 + enum: BS + - name: BS4 + description: Port x set pin %s. + bit_offset: 4 + bit_size: 1 + enum: BS + - name: BS5 + description: Port x set pin %s. + bit_offset: 5 + bit_size: 1 + enum: BS + - name: BS6 + description: Port x set pin %s. + bit_offset: 6 + bit_size: 1 + enum: BS + - name: BS7 + description: Port x set pin %s. + bit_offset: 7 + bit_size: 1 + enum: BS + - name: BS8 + description: Port x set pin %s. + bit_offset: 8 + bit_size: 1 + enum: BS + - name: BS9 + description: Port x set pin %s. + bit_offset: 9 + bit_size: 1 + enum: BS + - name: BS10 + description: Port x set pin %s. + bit_offset: 10 + bit_size: 1 + enum: BS + - name: BS11 + description: Port x set pin %s. + bit_offset: 11 + bit_size: 1 + enum: BS + - name: BS12 + description: Port x set pin %s. + bit_offset: 12 + bit_size: 1 + enum: BS + - name: BS13 + description: Port x set pin %s. + bit_offset: 13 + bit_size: 1 + enum: BS + - name: BS14 + description: Port x set pin %s. + bit_offset: 14 + bit_size: 1 + enum: BS + - name: BS15 + description: Port x set pin %s. + bit_offset: 15 + bit_size: 1 + enum: BS + - name: BR0 description: Port x reset pin %s. bit_offset: 16 bit_size: 1 - array: - len: 16 - stride: 1 + enum: BSRR_BR + - name: BR1 + description: Port x reset pin %s. + bit_offset: 17 + bit_size: 1 + enum: BSRR_BR + - name: BR2 + description: Port x reset pin %s. + bit_offset: 18 + bit_size: 1 + enum: BSRR_BR + - name: BR3 + description: Port x reset pin %s. + bit_offset: 19 + bit_size: 1 + enum: BSRR_BR + - name: BR4 + description: Port x reset pin %s. + bit_offset: 20 + bit_size: 1 + enum: BSRR_BR + - name: BR5 + description: Port x reset pin %s. + bit_offset: 21 + bit_size: 1 + enum: BSRR_BR + - name: BR6 + description: Port x reset pin %s. + bit_offset: 22 + bit_size: 1 + enum: BSRR_BR + - name: BR7 + description: Port x reset pin %s. + bit_offset: 23 + bit_size: 1 + enum: BSRR_BR + - name: BR8 + description: Port x reset pin %s. + bit_offset: 24 + bit_size: 1 + enum: BSRR_BR + - name: BR9 + description: Port x reset pin %s. + bit_offset: 25 + bit_size: 1 + enum: BSRR_BR + - name: BR10 + description: Port x reset pin %s. + bit_offset: 26 + bit_size: 1 + enum: BSRR_BR + - name: BR11 + description: Port x reset pin %s. + bit_offset: 27 + bit_size: 1 + enum: BSRR_BR + - name: BR12 + description: Port x reset pin %s. + bit_offset: 28 + bit_size: 1 + enum: BSRR_BR + - name: BR13 + description: Port x reset pin %s. + bit_offset: 29 + bit_size: 1 + enum: BSRR_BR + - name: BR14 + description: Port x reset pin %s. + bit_offset: 30 + bit_size: 1 + enum: BSRR_BR + - name: BR15 + description: Port x reset pin %s. + bit_offset: 31 + bit_size: 1 enum: BSRR_BR fieldset/HWCFGR0: description: GPIO hardware configuration register 0. @@ -322,13 +570,85 @@ fieldset/HWCFGR9: fieldset/IDR: description: GPIO port input data register. fields: - - name: IDR + - name: IDR0 description: Port input data pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: IDR + - name: IDR1 + description: Port input data pin %s. + bit_offset: 1 + bit_size: 1 + enum: IDR + - name: IDR2 + description: Port input data pin %s. + bit_offset: 2 + bit_size: 1 + enum: IDR + - name: IDR3 + description: Port input data pin %s. + bit_offset: 3 + bit_size: 1 + enum: IDR + - name: IDR4 + description: Port input data pin %s. + bit_offset: 4 + bit_size: 1 + enum: IDR + - name: IDR5 + description: Port input data pin %s. + bit_offset: 5 + bit_size: 1 + enum: IDR + - name: IDR6 + description: Port input data pin %s. + bit_offset: 6 + bit_size: 1 + enum: IDR + - name: IDR7 + description: Port input data pin %s. + bit_offset: 7 + bit_size: 1 + enum: IDR + - name: IDR8 + description: Port input data pin %s. + bit_offset: 8 + bit_size: 1 + enum: IDR + - name: IDR9 + description: Port input data pin %s. + bit_offset: 9 + bit_size: 1 + enum: IDR + - name: IDR10 + description: Port input data pin %s. + bit_offset: 10 + bit_size: 1 + enum: IDR + - name: IDR11 + description: Port input data pin %s. + bit_offset: 11 + bit_size: 1 + enum: IDR + - name: IDR12 + description: Port input data pin %s. + bit_offset: 12 + bit_size: 1 + enum: IDR + - name: IDR13 + description: Port input data pin %s. + bit_offset: 13 + bit_size: 1 + enum: IDR + - name: IDR14 + description: Port input data pin %s. + bit_offset: 14 + bit_size: 1 + enum: IDR + - name: IDR15 + description: Port input data pin %s. + bit_offset: 15 + bit_size: 1 enum: IDR fieldset/IPIDR: description: GPIO identification register. @@ -340,73 +660,505 @@ fieldset/IPIDR: fieldset/LCKR: description: This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). fields: - - name: LCK + - name: LCK0 description: Port x lock pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 enum: LCK - - name: LCKK - description: LCKK. - bit_offset: 16 + - name: LCK1 + description: Port x lock pin %s. + bit_offset: 1 bit_size: 1 - enum: LCKK -fieldset/MODER: - description: GPIO port mode register. - fields: - - name: MODER - description: Port x configuration pin %s. - bit_offset: 0 - bit_size: 2 - array: - len: 16 - stride: 2 - enum: MODER -fieldset/ODR: - description: GPIO port output data register. - fields: - - name: ODR - description: Port output data pin %s. - bit_offset: 0 + enum: LCK + - name: LCK2 + description: Port x lock pin %s. + bit_offset: 2 bit_size: 1 - array: - len: 16 - stride: 1 - enum: ODR -fieldset/OSPEEDR: - description: GPIO port output speed register. - fields: - - name: OSPEEDR - description: Port x configuration pin %s. - bit_offset: 0 - bit_size: 2 - array: - len: 16 - stride: 2 - enum: OSPEEDR -fieldset/OTYPER: - description: GPIO port output type register. - fields: - - name: OT - description: Port x configuration pin %s. - bit_offset: 0 + enum: LCK + - name: LCK3 + description: Port x lock pin %s. + bit_offset: 3 + bit_size: 1 + enum: LCK + - name: LCK4 + description: Port x lock pin %s. + bit_offset: 4 + bit_size: 1 + enum: LCK + - name: LCK5 + description: Port x lock pin %s. + bit_offset: 5 + bit_size: 1 + enum: LCK + - name: LCK6 + description: Port x lock pin %s. + bit_offset: 6 + bit_size: 1 + enum: LCK + - name: LCK7 + description: Port x lock pin %s. + bit_offset: 7 + bit_size: 1 + enum: LCK + - name: LCK8 + description: Port x lock pin %s. + bit_offset: 8 + bit_size: 1 + enum: LCK + - name: LCK9 + description: Port x lock pin %s. + bit_offset: 9 + bit_size: 1 + enum: LCK + - name: LCK10 + description: Port x lock pin %s. + bit_offset: 10 + bit_size: 1 + enum: LCK + - name: LCK11 + description: Port x lock pin %s. + bit_offset: 11 + bit_size: 1 + enum: LCK + - name: LCK12 + description: Port x lock pin %s. + bit_offset: 12 + bit_size: 1 + enum: LCK + - name: LCK13 + description: Port x lock pin %s. + bit_offset: 13 + bit_size: 1 + enum: LCK + - name: LCK14 + description: Port x lock pin %s. + bit_offset: 14 + bit_size: 1 + enum: LCK + - name: LCK15 + description: Port x lock pin %s. + bit_offset: 15 + bit_size: 1 + enum: LCK + - name: LCKK + description: LCKK. + bit_offset: 16 + bit_size: 1 + enum: LCKK +fieldset/MODER: + description: GPIO port mode register. + fields: + - name: MODER0 + description: Port x configuration pin %s. + bit_offset: 0 + bit_size: 2 + enum: MODER + - name: MODER1 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 2 + enum: MODER + - name: MODER2 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 2 + enum: MODER + - name: MODER3 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 2 + enum: MODER + - name: MODER4 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 2 + enum: MODER + - name: MODER5 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 2 + enum: MODER + - name: MODER6 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 2 + enum: MODER + - name: MODER7 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 2 + enum: MODER + - name: MODER8 + description: Port x configuration pin %s. + bit_offset: 16 + bit_size: 2 + enum: MODER + - name: MODER9 + description: Port x configuration pin %s. + bit_offset: 18 + bit_size: 2 + enum: MODER + - name: MODER10 + description: Port x configuration pin %s. + bit_offset: 20 + bit_size: 2 + enum: MODER + - name: MODER11 + description: Port x configuration pin %s. + bit_offset: 22 + bit_size: 2 + enum: MODER + - name: MODER12 + description: Port x configuration pin %s. + bit_offset: 24 + bit_size: 2 + enum: MODER + - name: MODER13 + description: Port x configuration pin %s. + bit_offset: 26 + bit_size: 2 + enum: MODER + - name: MODER14 + description: Port x configuration pin %s. + bit_offset: 28 + bit_size: 2 + enum: MODER + - name: MODER15 + description: Port x configuration pin %s. + bit_offset: 30 + bit_size: 2 + enum: MODER +fieldset/ODR: + description: GPIO port output data register. + fields: + - name: ODR0 + description: Port output data pin %s. + bit_offset: 0 + bit_size: 1 + enum: ODR + - name: ODR1 + description: Port output data pin %s. + bit_offset: 1 + bit_size: 1 + enum: ODR + - name: ODR2 + description: Port output data pin %s. + bit_offset: 2 + bit_size: 1 + enum: ODR + - name: ODR3 + description: Port output data pin %s. + bit_offset: 3 + bit_size: 1 + enum: ODR + - name: ODR4 + description: Port output data pin %s. + bit_offset: 4 + bit_size: 1 + enum: ODR + - name: ODR5 + description: Port output data pin %s. + bit_offset: 5 + bit_size: 1 + enum: ODR + - name: ODR6 + description: Port output data pin %s. + bit_offset: 6 + bit_size: 1 + enum: ODR + - name: ODR7 + description: Port output data pin %s. + bit_offset: 7 + bit_size: 1 + enum: ODR + - name: ODR8 + description: Port output data pin %s. + bit_offset: 8 + bit_size: 1 + enum: ODR + - name: ODR9 + description: Port output data pin %s. + bit_offset: 9 + bit_size: 1 + enum: ODR + - name: ODR10 + description: Port output data pin %s. + bit_offset: 10 + bit_size: 1 + enum: ODR + - name: ODR11 + description: Port output data pin %s. + bit_offset: 11 + bit_size: 1 + enum: ODR + - name: ODR12 + description: Port output data pin %s. + bit_offset: 12 + bit_size: 1 + enum: ODR + - name: ODR13 + description: Port output data pin %s. + bit_offset: 13 + bit_size: 1 + enum: ODR + - name: ODR14 + description: Port output data pin %s. + bit_offset: 14 + bit_size: 1 + enum: ODR + - name: ODR15 + description: Port output data pin %s. + bit_offset: 15 + bit_size: 1 + enum: ODR +fieldset/OSPEEDR: + description: GPIO port output speed register. + fields: + - name: OSPEEDR0 + description: Port x configuration pin %s. + bit_offset: 0 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR1 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR2 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR3 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR4 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR5 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR6 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR7 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR8 + description: Port x configuration pin %s. + bit_offset: 16 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR9 + description: Port x configuration pin %s. + bit_offset: 18 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR10 + description: Port x configuration pin %s. + bit_offset: 20 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR11 + description: Port x configuration pin %s. + bit_offset: 22 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR12 + description: Port x configuration pin %s. + bit_offset: 24 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR13 + description: Port x configuration pin %s. + bit_offset: 26 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR14 + description: Port x configuration pin %s. + bit_offset: 28 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR15 + description: Port x configuration pin %s. + bit_offset: 30 + bit_size: 2 + enum: OSPEEDR +fieldset/OTYPER: + description: GPIO port output type register. + fields: + - name: OT0 + description: Port x configuration pin %s. + bit_offset: 0 + bit_size: 1 + enum: OT + - name: OT1 + description: Port x configuration pin %s. + bit_offset: 1 + bit_size: 1 + enum: OT + - name: OT2 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 1 + enum: OT + - name: OT3 + description: Port x configuration pin %s. + bit_offset: 3 + bit_size: 1 + enum: OT + - name: OT4 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 1 + enum: OT + - name: OT5 + description: Port x configuration pin %s. + bit_offset: 5 + bit_size: 1 + enum: OT + - name: OT6 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 1 + enum: OT + - name: OT7 + description: Port x configuration pin %s. + bit_offset: 7 + bit_size: 1 + enum: OT + - name: OT8 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 1 + enum: OT + - name: OT9 + description: Port x configuration pin %s. + bit_offset: 9 + bit_size: 1 + enum: OT + - name: OT10 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 1 + enum: OT + - name: OT11 + description: Port x configuration pin %s. + bit_offset: 11 + bit_size: 1 + enum: OT + - name: OT12 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 1 + enum: OT + - name: OT13 + description: Port x configuration pin %s. + bit_offset: 13 + bit_size: 1 + enum: OT + - name: OT14 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 1 + enum: OT + - name: OT15 + description: Port x configuration pin %s. + bit_offset: 15 bit_size: 1 - array: - len: 16 - stride: 1 enum: OT fieldset/PUPDR: description: GPIO port pull-up/pull-down register. fields: - - name: PUPDR + - name: PUPDR0 description: Port x configuration pin %s. bit_offset: 0 bit_size: 2 - array: - len: 16 - stride: 2 + enum: PUPDR + - name: PUPDR1 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 2 + enum: PUPDR + - name: PUPDR2 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 2 + enum: PUPDR + - name: PUPDR3 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 2 + enum: PUPDR + - name: PUPDR4 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 2 + enum: PUPDR + - name: PUPDR5 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 2 + enum: PUPDR + - name: PUPDR6 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 2 + enum: PUPDR + - name: PUPDR7 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 2 + enum: PUPDR + - name: PUPDR8 + description: Port x configuration pin %s. + bit_offset: 16 + bit_size: 2 + enum: PUPDR + - name: PUPDR9 + description: Port x configuration pin %s. + bit_offset: 18 + bit_size: 2 + enum: PUPDR + - name: PUPDR10 + description: Port x configuration pin %s. + bit_offset: 20 + bit_size: 2 + enum: PUPDR + - name: PUPDR11 + description: Port x configuration pin %s. + bit_offset: 22 + bit_size: 2 + enum: PUPDR + - name: PUPDR12 + description: Port x configuration pin %s. + bit_offset: 24 + bit_size: 2 + enum: PUPDR + - name: PUPDR13 + description: Port x configuration pin %s. + bit_offset: 26 + bit_size: 2 + enum: PUPDR + - name: PUPDR14 + description: Port x configuration pin %s. + bit_offset: 28 + bit_size: 2 + enum: PUPDR + - name: PUPDR15 + description: Port x configuration pin %s. + bit_offset: 30 + bit_size: 2 enum: PUPDR fieldset/SIDR: description: GPIO size identification register. diff --git a/base/STM32MP157/RTC.yaml b/head/STM32MP157/RTC.yaml index c38f0a3..d9399bf 100644 --- a/base/STM32MP157/RTC.yaml +++ b/head/STM32MP157/RTC.yaml @@ -48,20 +48,22 @@ block/RTC: byte_offset: 44 access: Write fieldset: SHIFTR - - name: ALRMR + - name: ALRMAR description: Alarm %s register. - array: - len: 2 - stride: 8 byte_offset: 64 fieldset: ALRMR - - name: ALRMSSR + - name: ALRMASSR description: Alarm %s sub-second register. - array: - len: 2 - stride: 8 byte_offset: 68 fieldset: ALRMSSR + - name: ALRMBR + description: Alarm %s register. + byte_offset: 72 + fieldset: ALRMR + - name: ALRMBSSR + description: Alarm %s sub-second register. + byte_offset: 76 + fieldset: ALRMSSR - name: SR description: 'This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.' byte_offset: 80 @@ -243,13 +245,15 @@ fieldset/CR: bit_offset: 6 bit_size: 1 enum: FMT - - name: ALRE + - name: ALRAE description: Alarm %s enable. bit_offset: 8 bit_size: 1 - array: - len: 2 - stride: 1 + enum: ALRE + - name: ALRBE + description: Alarm %s enable. + bit_offset: 9 + bit_size: 1 enum: ALRE - name: WUTE description: WUTE. @@ -261,13 +265,15 @@ fieldset/CR: bit_offset: 11 bit_size: 1 enum: TSE - - name: ALRIE + - name: ALRAIE description: Alarm %s interrupt enable. bit_offset: 12 bit_size: 1 - array: - len: 2 - stride: 1 + enum: ALRIE + - name: ALRBIE + description: Alarm %s interrupt enable. + bit_offset: 13 + bit_size: 1 enum: ALRIE - name: WUTIE description: WUTIE. @@ -405,13 +411,14 @@ fieldset/HWCFGR: fieldset/ICSR: description: 'This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.' fields: - - name: ALRWF + - name: ALRAWF description: Alarm %s write flag. bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 + - name: ALRBWF + description: Alarm %s write flag. + bit_offset: 1 + bit_size: 1 - name: WUTWF description: WUTWF. bit_offset: 2 @@ -457,13 +464,15 @@ fieldset/IPIDR: fieldset/MISR: description: RTC non-secure masked interrupt status register. fields: - - name: ALRMF + - name: ALRAMF description: Alarm %s masked flag. bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 + enum: ALRMF + - name: ALRBMF + description: Alarm %s masked flag. + bit_offset: 1 + bit_size: 1 enum: ALRMF - name: WUTMF description: WUTMF. @@ -609,13 +618,15 @@ fieldset/SMISR: fieldset/SR: description: 'This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.' fields: - - name: ALRF + - name: ALRAF description: Alarm %s flag. bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 + enum: ALRF + - name: ALRBF + description: Alarm %s flag. + bit_offset: 1 + bit_size: 1 enum: ALRF - name: WUTF description: WUTF. diff --git a/base/STM32MP157/TAMP.yaml b/head/STM32MP157/TAMP.yaml index 3944aac..5513422 100644 --- a/base/STM32MP157/TAMP.yaml +++ b/head/STM32MP157/TAMP.yaml @@ -64,13 +64,134 @@ block/TAMP: description: TAMP configuration register. byte_offset: 80 fieldset: CFGR - - name: BKPR + - name: BKP0R description: TAMP backup %s register. - array: - len: 32 - stride: 4 byte_offset: 256 fieldset: BKPR + - name: BKP1R + description: TAMP backup %s register. + byte_offset: 260 + fieldset: BKPR + - name: BKP2R + description: TAMP backup %s register. + byte_offset: 264 + fieldset: BKPR + - name: BKP3R + description: TAMP backup %s register. + byte_offset: 268 + fieldset: BKPR + - name: BKP4R + description: TAMP backup %s register. + byte_offset: 272 + fieldset: BKPR + - name: BKP5R + description: TAMP backup %s register. + byte_offset: 276 + fieldset: BKPR + - name: BKP6R + description: TAMP backup %s register. + byte_offset: 280 + fieldset: BKPR + - name: BKP7R + description: TAMP backup %s register. + byte_offset: 284 + fieldset: BKPR + - name: BKP8R + description: TAMP backup %s register. + byte_offset: 288 + fieldset: BKPR + - name: BKP9R + description: TAMP backup %s register. + byte_offset: 292 + fieldset: BKPR + - name: BKP10R + description: TAMP backup %s register. + byte_offset: 296 + fieldset: BKPR + - name: BKP11R + description: TAMP backup %s register. + byte_offset: 300 + fieldset: BKPR + - name: BKP12R + description: TAMP backup %s register. + byte_offset: 304 + fieldset: BKPR + - name: BKP13R + description: TAMP backup %s register. + byte_offset: 308 + fieldset: BKPR + - name: BKP14R + description: TAMP backup %s register. + byte_offset: 312 + fieldset: BKPR + - name: BKP15R + description: TAMP backup %s register. + byte_offset: 316 + fieldset: BKPR + - name: BKP16R + description: TAMP backup %s register. + byte_offset: 320 + fieldset: BKPR + - name: BKP17R + description: TAMP backup %s register. + byte_offset: 324 + fieldset: BKPR + - name: BKP18R + description: TAMP backup %s register. + byte_offset: 328 + fieldset: BKPR + - name: BKP19R + description: TAMP backup %s register. + byte_offset: 332 + fieldset: BKPR + - name: BKP20R + description: TAMP backup %s register. + byte_offset: 336 + fieldset: BKPR + - name: BKP21R + description: TAMP backup %s register. + byte_offset: 340 + fieldset: BKPR + - name: BKP22R + description: TAMP backup %s register. + byte_offset: 344 + fieldset: BKPR + - name: BKP23R + description: TAMP backup %s register. + byte_offset: 348 + fieldset: BKPR + - name: BKP24R + description: TAMP backup %s register. + byte_offset: 352 + fieldset: BKPR + - name: BKP25R + description: TAMP backup %s register. + byte_offset: 356 + fieldset: BKPR + - name: BKP26R + description: TAMP backup %s register. + byte_offset: 360 + fieldset: BKPR + - name: BKP27R + description: TAMP backup %s register. + byte_offset: 364 + fieldset: BKPR + - name: BKP28R + description: TAMP backup %s register. + byte_offset: 368 + fieldset: BKPR + - name: BKP29R + description: TAMP backup %s register. + byte_offset: 372 + fieldset: BKPR + - name: BKP30R + description: TAMP backup %s register. + byte_offset: 376 + fieldset: BKPR + - name: BKP31R + description: TAMP backup %s register. + byte_offset: 380 + fieldset: BKPR - name: HWCFGR2 description: TAMP hardware configuration register 2. byte_offset: 1004 diff --git a/base/STM32WB55/ADC1.yaml b/head/STM32WB55/ADC1.yaml index 39aeda8..a456391 100644 --- a/base/STM32WB55/ADC1.yaml +++ b/head/STM32WB55/ADC1.yaml @@ -65,21 +65,42 @@ block/ADC1: description: ADC group injected sequencer register. byte_offset: 76 fieldset: JSQR - - name: OFR + - name: OFR1 description: ADC offset number %s register. - array: - len: 4 - stride: 4 byte_offset: 96 fieldset: OFR - - name: JDR + - name: OFR2 + description: ADC offset number %s register. + byte_offset: 100 + fieldset: OFR + - name: OFR3 + description: ADC offset number %s register. + byte_offset: 104 + fieldset: OFR + - name: OFR4 + description: ADC offset number %s register. + byte_offset: 108 + fieldset: OFR + - name: JDR1 description: ADC group injected sequencer rank %s register. - array: - len: 4 - stride: 4 byte_offset: 128 access: Read fieldset: JDR + - name: JDR2 + description: ADC group injected sequencer rank %s register. + byte_offset: 132 + access: Read + fieldset: JDR + - name: JDR3 + description: ADC group injected sequencer rank %s register. + byte_offset: 136 + access: Read + fieldset: JDR + - name: JDR4 + description: ADC group injected sequencer rank %s register. + byte_offset: 140 + access: Read + fieldset: JDR - name: AWD2CR description: ADC analog watchdog 2 configuration register. byte_offset: 160 @@ -99,24 +120,198 @@ block/ADC1: fieldset/AWD2CR: description: ADC analog watchdog 2 configuration register. fields: - - name: AWD2CH + - name: AWD2CH0 description: ADC analog watchdog 2 monitored channel selection. bit_offset: 0 bit_size: 1 - array: - len: 19 - stride: 1 + enum: AWD2CH + - name: AWD2CH1 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 1 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH2 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 2 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH3 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 3 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH4 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 4 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH5 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 5 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH6 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 6 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH7 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 7 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH8 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 8 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH9 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 9 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH10 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 10 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH11 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 11 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH12 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 12 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH13 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 13 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH14 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 14 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH15 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 15 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH16 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 16 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH17 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 17 + bit_size: 1 + enum: AWD2CH + - name: AWD2CH18 + description: ADC analog watchdog 2 monitored channel selection. + bit_offset: 18 + bit_size: 1 enum: AWD2CH fieldset/AWD3CR: description: ADC analog watchdog 3 configuration register. fields: - - name: AWD3CH + - name: AWD3CH0 description: ADC analog watchdog 3 monitored channel selection. bit_offset: 0 bit_size: 1 - array: - len: 19 - stride: 1 + enum: AWD3CH + - name: AWD3CH1 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 1 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH2 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 2 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH3 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 3 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH4 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 4 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH5 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 5 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH6 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 6 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH7 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 7 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH8 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 8 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH9 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 9 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH10 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 10 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH11 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 11 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH12 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 12 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH13 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 13 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH14 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 14 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH15 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 15 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH16 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 16 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH17 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 17 + bit_size: 1 + enum: AWD3CH + - name: AWD3CH18 + description: ADC analog watchdog 3 monitored channel selection. + bit_offset: 18 + bit_size: 1 enum: AWD3CH fieldset/CALFACT: description: ADC calibration factors register. @@ -313,13 +508,100 @@ fieldset/CR: fieldset/DIFSEL: description: ADC channel differential or single-ended mode selection register. fields: - - name: DIFSEL + - name: DIFSEL0 description: Differential mode for channel %s. bit_offset: 0 bit_size: 1 - array: - len: 19 - stride: 1 + enum: DIFSEL + - name: DIFSEL1 + description: Differential mode for channel %s. + bit_offset: 1 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL2 + description: Differential mode for channel %s. + bit_offset: 2 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL3 + description: Differential mode for channel %s. + bit_offset: 3 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL4 + description: Differential mode for channel %s. + bit_offset: 4 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL5 + description: Differential mode for channel %s. + bit_offset: 5 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL6 + description: Differential mode for channel %s. + bit_offset: 6 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL7 + description: Differential mode for channel %s. + bit_offset: 7 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL8 + description: Differential mode for channel %s. + bit_offset: 8 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL9 + description: Differential mode for channel %s. + bit_offset: 9 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL10 + description: Differential mode for channel %s. + bit_offset: 10 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL11 + description: Differential mode for channel %s. + bit_offset: 11 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL12 + description: Differential mode for channel %s. + bit_offset: 12 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL13 + description: Differential mode for channel %s. + bit_offset: 13 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL14 + description: Differential mode for channel %s. + bit_offset: 14 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL15 + description: Differential mode for channel %s. + bit_offset: 15 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL16 + description: Differential mode for channel %s. + bit_offset: 16 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL17 + description: Differential mode for channel %s. + bit_offset: 17 + bit_size: 1 + enum: DIFSEL + - name: DIFSEL18 + description: Differential mode for channel %s. + bit_offset: 18 + bit_size: 1 enum: DIFSEL fieldset/DR: description: ADC group regular conversion data register. @@ -366,13 +648,20 @@ fieldset/IER: bit_offset: 6 bit_size: 1 enum: JEOSIE - - name: AWDIE + - name: AWD1IE description: Analog watchdog %s interrupt enable. bit_offset: 7 bit_size: 1 - array: - len: 3 - stride: 1 + enum: AWDIE + - name: AWD2IE + description: Analog watchdog %s interrupt enable. + bit_offset: 8 + bit_size: 1 + enum: AWDIE + - name: AWD3IE + description: Analog watchdog %s interrupt enable. + bit_offset: 9 + bit_size: 1 enum: AWDIE - name: JQOVFIE description: ADC group injected contexts queue overflow interrupt. @@ -417,13 +706,20 @@ fieldset/ISR: bit_offset: 6 bit_size: 1 enum: JEOS - - name: AWD + - name: AWD1 description: Analog watchdog %s flag. bit_offset: 7 bit_size: 1 - array: - len: 3 - stride: 1 + enum: AWD + - name: AWD2 + description: Analog watchdog %s flag. + bit_offset: 8 + bit_size: 1 + enum: AWD + - name: AWD3 + description: Analog watchdog %s flag. + bit_offset: 9 + bit_size: 1 enum: AWD - name: JQOVF description: ADC group injected contexts queue overflow flag. @@ -454,13 +750,22 @@ fieldset/JSQR: bit_offset: 6 bit_size: 2 enum: JEXTEN - - name: JSQ + - name: JSQ1 description: '%s conversion in injected sequence.' bit_offset: 8 bit_size: 5 - array: - len: 4 - stride: 6 + - name: JSQ2 + description: '%s conversion in injected sequence.' + bit_offset: 14 + bit_size: 5 + - name: JSQ3 + description: '%s conversion in injected sequence.' + bit_offset: 20 + bit_size: 5 + - name: JSQ4 + description: '%s conversion in injected sequence.' + bit_offset: 26 + bit_size: 5 fieldset/OFR: description: ADC offset number %s register. fields: @@ -480,13 +785,55 @@ fieldset/OFR: fieldset/SMPR1: description: ADC sampling time register 1. fields: - - name: SMP + - name: SMP0 description: Channel %s sample time selection. bit_offset: 0 bit_size: 3 - array: - len: 10 - stride: 3 + enum: SMP + - name: SMP1 + description: Channel %s sample time selection. + bit_offset: 3 + bit_size: 3 + enum: SMP + - name: SMP2 + description: Channel %s sample time selection. + bit_offset: 6 + bit_size: 3 + enum: SMP + - name: SMP3 + description: Channel %s sample time selection. + bit_offset: 9 + bit_size: 3 + enum: SMP + - name: SMP4 + description: Channel %s sample time selection. + bit_offset: 12 + bit_size: 3 + enum: SMP + - name: SMP5 + description: Channel %s sample time selection. + bit_offset: 15 + bit_size: 3 + enum: SMP + - name: SMP6 + description: Channel %s sample time selection. + bit_offset: 18 + bit_size: 3 + enum: SMP + - name: SMP7 + description: Channel %s sample time selection. + bit_offset: 21 + bit_size: 3 + enum: SMP + - name: SMP8 + description: Channel %s sample time selection. + bit_offset: 24 + bit_size: 3 + enum: SMP + - name: SMP9 + description: Channel %s sample time selection. + bit_offset: 27 + bit_size: 3 enum: SMP fieldset/SMPR2: description: ADC sampling time register 2. @@ -498,13 +845,22 @@ fieldset/SQR1: description: Regular channel sequence length. bit_offset: 0 bit_size: 4 - - name: SQ + - name: SQ1 description: '%s conversion in regular sequence.' bit_offset: 6 bit_size: 5 - array: - len: 4 - stride: 6 + - name: SQ2 + description: '%s conversion in regular sequence.' + bit_offset: 12 + bit_size: 5 + - name: SQ3 + description: '%s conversion in regular sequence.' + bit_offset: 18 + bit_size: 5 + - name: SQ4 + description: '%s conversion in regular sequence.' + bit_offset: 24 + bit_size: 5 fieldset/SQR2: description: ADC group regular sequencer ranks register 2. fields: [] diff --git a/base/STM32WB55/DMA1.yaml b/head/STM32WB55/DMA1.yaml index 62f62d7..b09ab44 100644 --- a/base/STM32WB55/DMA1.yaml +++ b/head/STM32WB55/DMA1.yaml @@ -1,22 +1,136 @@ -block/CH: +block/CH1: description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' items: - name: CR description: channel x configuration register. byte_offset: 0 - fieldset: CR + fieldset: CH1_CR - name: NDTR description: channel x number of data register. byte_offset: 4 - fieldset: NDTR + fieldset: CH1_NDTR - name: PAR description: channel x peripheral address register. byte_offset: 8 - fieldset: PAR + fieldset: CH1_PAR - name: MAR description: channel x memory address register. byte_offset: 12 - fieldset: MAR + fieldset: CH1_MAR +block/CH2: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: channel x configuration register. + byte_offset: 0 + fieldset: CH2_CR + - name: NDTR + description: channel x number of data register. + byte_offset: 4 + fieldset: CH2_NDTR + - name: PAR + description: channel x peripheral address register. + byte_offset: 8 + fieldset: CH2_PAR + - name: MAR + description: channel x memory address register. + byte_offset: 12 + fieldset: CH2_MAR +block/CH3: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: channel x configuration register. + byte_offset: 0 + fieldset: CH3_CR + - name: NDTR + description: channel x number of data register. + byte_offset: 4 + fieldset: CH3_NDTR + - name: PAR + description: channel x peripheral address register. + byte_offset: 8 + fieldset: CH3_PAR + - name: MAR + description: channel x memory address register. + byte_offset: 12 + fieldset: CH3_MAR +block/CH4: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: channel x configuration register. + byte_offset: 0 + fieldset: CH4_CR + - name: NDTR + description: channel x number of data register. + byte_offset: 4 + fieldset: CH4_NDTR + - name: PAR + description: channel x peripheral address register. + byte_offset: 8 + fieldset: CH4_PAR + - name: MAR + description: channel x memory address register. + byte_offset: 12 + fieldset: CH4_MAR +block/CH5: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: channel x configuration register. + byte_offset: 0 + fieldset: CH5_CR + - name: NDTR + description: channel x number of data register. + byte_offset: 4 + fieldset: CH5_NDTR + - name: PAR + description: channel x peripheral address register. + byte_offset: 8 + fieldset: CH5_PAR + - name: MAR + description: channel x memory address register. + byte_offset: 12 + fieldset: CH5_MAR +block/CH6: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: channel x configuration register. + byte_offset: 0 + fieldset: CH6_CR + - name: NDTR + description: channel x number of data register. + byte_offset: 4 + fieldset: CH6_NDTR + - name: PAR + description: channel x peripheral address register. + byte_offset: 8 + fieldset: CH6_PAR + - name: MAR + description: channel x memory address register. + byte_offset: 12 + fieldset: CH6_MAR +block/CH7: + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + items: + - name: CR + description: channel x configuration register. + byte_offset: 0 + fieldset: CH7_CR + - name: NDTR + description: channel x number of data register. + byte_offset: 4 + fieldset: CH7_NDTR + - name: PAR + description: channel x peripheral address register. + byte_offset: 8 + fieldset: CH7_PAR + - name: MAR + description: channel x memory address register. + byte_offset: 12 + fieldset: CH7_MAR block/DMA1: description: Direct memory access controller. items: @@ -30,201 +144,1524 @@ block/DMA1: byte_offset: 4 access: Write fieldset: IFCR - - name: CH + - name: CH1 description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' - array: - len: 7 - stride: 20 byte_offset: 8 - block: CH -fieldset/CR: + block: CH1 + - name: CH2 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 28 + block: CH2 + - name: CH3 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 48 + block: CH3 + - name: CH4 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 68 + block: CH4 + - name: CH5 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 88 + block: CH5 + - name: CH6 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 108 + block: CH6 + - name: CH7 + description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers.' + byte_offset: 128 + block: CH7 +fieldset/CH1_CR: description: channel x configuration register. fields: - name: EN description: Channel enable. bit_offset: 0 bit_size: 1 - enum: EN + enum: CH1_CR_EN - name: TCIE description: Transfer complete interrupt enable. bit_offset: 1 bit_size: 1 - enum: TCIE + enum: CH1_CR_TCIE - name: HTIE description: Half transfer interrupt enable. bit_offset: 2 bit_size: 1 - enum: HTIE + enum: CH1_CR_HTIE - name: TEIE description: Transfer error interrupt enable. bit_offset: 3 bit_size: 1 - enum: TEIE + enum: CH1_CR_TEIE - name: DIR description: Data transfer direction. bit_offset: 4 bit_size: 1 - enum: DIR + enum: CH1_CR_DIR - name: CIRC description: Circular mode. bit_offset: 5 bit_size: 1 - enum: CIRC + enum: CH1_CR_CIRC - name: PINC description: Peripheral increment mode. bit_offset: 6 bit_size: 1 - enum: PINC + enum: CH1_CR_PINC - name: MINC description: Memory increment mode. bit_offset: 7 bit_size: 1 - enum: MINC + enum: CH1_CR_MINC - name: PSIZE description: Peripheral size. bit_offset: 8 bit_size: 2 - enum: PSIZE + enum: CH1_CR_PSIZE - name: MSIZE description: Memory size. bit_offset: 10 bit_size: 2 - enum: MSIZE + enum: CH1_CR_MSIZE - name: PL description: Channel priority level. bit_offset: 12 bit_size: 2 - enum: PL + enum: CH1_CR_PL - name: MEM2MEM description: Memory to memory mode. bit_offset: 14 bit_size: 1 - enum: MEM2MEM -fieldset/IFCR: - description: interrupt flag clear register. + enum: CH1_CR_MEM2MEM +fieldset/CH1_MAR: + description: channel x memory address register. fields: - - name: CGIF - description: Channel %s Global interrupt clear. + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH1_NDTR: + description: channel x number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH1_PAR: + description: channel x peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/CH2_CR: + description: channel x configuration register. + fields: + - name: EN + description: Channel enable. bit_offset: 0 bit_size: 1 - array: - len: 7 - stride: 4 - enum: CGIF - - name: CTCIF - description: Channel %s Transfer Complete clear. + enum: CH2_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 7 - stride: 4 - enum: CTCIF - - name: CHTIF - description: Channel %s Half Transfer clear. + enum: CH2_CR_TCIE + - name: HTIE + description: Half transfer interrupt enable. bit_offset: 2 bit_size: 1 - array: - len: 7 - stride: 4 - enum: CHTIF - - name: CTEIF - description: Channel %s Transfer Error clear. + enum: CH2_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. bit_offset: 3 bit_size: 1 - array: - len: 7 - stride: 4 - enum: CTEIF -fieldset/ISR: - description: interrupt status register. + enum: CH2_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH2_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH2_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH2_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH2_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH2_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH2_CR_MSIZE + - name: PL + description: Channel priority level. + bit_offset: 12 + bit_size: 2 + enum: CH2_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH2_CR_MEM2MEM +fieldset/CH2_MAR: + description: channel x memory address register. fields: - - name: GIF - description: Channel %s Global interrupt flag. + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH2_NDTR: + description: channel x number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH2_PAR: + description: channel x peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/CH3_CR: + description: channel x configuration register. + fields: + - name: EN + description: Channel enable. bit_offset: 0 bit_size: 1 - array: - len: 7 - stride: 4 - enum: GIF - - name: TCIF - description: Channel %s Transfer Complete flag. + enum: CH3_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 7 - stride: 4 - enum: TCIF - - name: HTIF - description: Channel %s Half Transfer Complete flag. + enum: CH3_CR_TCIE + - name: HTIE + description: Half transfer interrupt enable. bit_offset: 2 bit_size: 1 - array: - len: 7 - stride: 4 - enum: HTIF - - name: TEIF - description: Channel %s Transfer Error flag. + enum: CH3_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. bit_offset: 3 bit_size: 1 - array: - len: 7 - stride: 4 - enum: TEIF -fieldset/MAR: + enum: CH3_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH3_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH3_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH3_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH3_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH3_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH3_CR_MSIZE + - name: PL + description: Channel priority level. + bit_offset: 12 + bit_size: 2 + enum: CH3_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH3_CR_MEM2MEM +fieldset/CH3_MAR: description: channel x memory address register. fields: - name: MA description: Memory address. bit_offset: 0 bit_size: 32 -fieldset/NDTR: +fieldset/CH3_NDTR: description: channel x number of data register. fields: - name: NDT description: Number of data to transfer. bit_offset: 0 bit_size: 16 -fieldset/PAR: +fieldset/CH3_PAR: description: channel x peripheral address register. fields: - name: PA description: Peripheral address. bit_offset: 0 bit_size: 32 -enum/CGIF: +fieldset/CH4_CR: + description: channel x configuration register. + fields: + - name: EN + description: Channel enable. + bit_offset: 0 + bit_size: 1 + enum: CH4_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. + bit_offset: 1 + bit_size: 1 + enum: CH4_CR_TCIE + - name: HTIE + description: Half transfer interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CH4_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CH4_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH4_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH4_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH4_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH4_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH4_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH4_CR_MSIZE + - name: PL + description: Channel priority level. + bit_offset: 12 + bit_size: 2 + enum: CH4_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH4_CR_MEM2MEM +fieldset/CH4_MAR: + description: channel x memory address register. + fields: + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH4_NDTR: + description: channel x number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH4_PAR: + description: channel x peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/CH5_CR: + description: channel x configuration register. + fields: + - name: EN + description: Channel enable. + bit_offset: 0 + bit_size: 1 + enum: CH5_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. + bit_offset: 1 + bit_size: 1 + enum: CH5_CR_TCIE + - name: HTIE + description: Half transfer interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CH5_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CH5_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH5_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH5_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH5_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH5_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH5_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH5_CR_MSIZE + - name: PL + description: Channel priority level. + bit_offset: 12 + bit_size: 2 + enum: CH5_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH5_CR_MEM2MEM +fieldset/CH5_MAR: + description: channel x memory address register. + fields: + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH5_NDTR: + description: channel x number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH5_PAR: + description: channel x peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/CH6_CR: + description: channel x configuration register. + fields: + - name: EN + description: Channel enable. + bit_offset: 0 + bit_size: 1 + enum: CH6_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. + bit_offset: 1 + bit_size: 1 + enum: CH6_CR_TCIE + - name: HTIE + description: Half transfer interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CH6_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CH6_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH6_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH6_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH6_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH6_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH6_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH6_CR_MSIZE + - name: PL + description: Channel priority level. + bit_offset: 12 + bit_size: 2 + enum: CH6_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH6_CR_MEM2MEM +fieldset/CH6_MAR: + description: channel x memory address register. + fields: + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH6_NDTR: + description: channel x number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH6_PAR: + description: channel x peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/CH7_CR: + description: channel x configuration register. + fields: + - name: EN + description: Channel enable. + bit_offset: 0 + bit_size: 1 + enum: CH7_CR_EN + - name: TCIE + description: Transfer complete interrupt enable. + bit_offset: 1 + bit_size: 1 + enum: CH7_CR_TCIE + - name: HTIE + description: Half transfer interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CH7_CR_HTIE + - name: TEIE + description: Transfer error interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CH7_CR_TEIE + - name: DIR + description: Data transfer direction. + bit_offset: 4 + bit_size: 1 + enum: CH7_CR_DIR + - name: CIRC + description: Circular mode. + bit_offset: 5 + bit_size: 1 + enum: CH7_CR_CIRC + - name: PINC + description: Peripheral increment mode. + bit_offset: 6 + bit_size: 1 + enum: CH7_CR_PINC + - name: MINC + description: Memory increment mode. + bit_offset: 7 + bit_size: 1 + enum: CH7_CR_MINC + - name: PSIZE + description: Peripheral size. + bit_offset: 8 + bit_size: 2 + enum: CH7_CR_PSIZE + - name: MSIZE + description: Memory size. + bit_offset: 10 + bit_size: 2 + enum: CH7_CR_MSIZE + - name: PL + description: Channel priority level. + bit_offset: 12 + bit_size: 2 + enum: CH7_CR_PL + - name: MEM2MEM + description: Memory to memory mode. + bit_offset: 14 + bit_size: 1 + enum: CH7_CR_MEM2MEM +fieldset/CH7_MAR: + description: channel x memory address register. + fields: + - name: MA + description: Memory address. + bit_offset: 0 + bit_size: 32 +fieldset/CH7_NDTR: + description: channel x number of data register. + fields: + - name: NDT + description: Number of data to transfer. + bit_offset: 0 + bit_size: 16 +fieldset/CH7_PAR: + description: channel x peripheral address register. + fields: + - name: PA + description: Peripheral address. + bit_offset: 0 + bit_size: 32 +fieldset/IFCR: + description: interrupt flag clear register. + fields: + - name: CGIF1 + description: Channel %s Global interrupt clear. + bit_offset: 0 + bit_size: 1 + enum: CGIF + - name: CTCIF1 + description: Channel %s Transfer Complete clear. + bit_offset: 1 + bit_size: 1 + enum: CTCIF + - name: CHTIF1 + description: Channel %s Half Transfer clear. + bit_offset: 2 + bit_size: 1 + enum: CHTIF + - name: CTEIF1 + description: Channel %s Transfer Error clear. + bit_offset: 3 + bit_size: 1 + enum: CTEIF + - name: CGIF2 + description: Channel %s Global interrupt clear. + bit_offset: 4 + bit_size: 1 + enum: CGIF + - name: CTCIF2 + description: Channel %s Transfer Complete clear. + bit_offset: 5 + bit_size: 1 + enum: CTCIF + - name: CHTIF2 + description: Channel %s Half Transfer clear. + bit_offset: 6 + bit_size: 1 + enum: CHTIF + - name: CTEIF2 + description: Channel %s Transfer Error clear. + bit_offset: 7 + bit_size: 1 + enum: CTEIF + - name: CGIF3 + description: Channel %s Global interrupt clear. + bit_offset: 8 + bit_size: 1 + enum: CGIF + - name: CTCIF3 + description: Channel %s Transfer Complete clear. + bit_offset: 9 + bit_size: 1 + enum: CTCIF + - name: CHTIF3 + description: Channel %s Half Transfer clear. + bit_offset: 10 + bit_size: 1 + enum: CHTIF + - name: CTEIF3 + description: Channel %s Transfer Error clear. + bit_offset: 11 + bit_size: 1 + enum: CTEIF + - name: CGIF4 + description: Channel %s Global interrupt clear. + bit_offset: 12 + bit_size: 1 + enum: CGIF + - name: CTCIF4 + description: Channel %s Transfer Complete clear. + bit_offset: 13 + bit_size: 1 + enum: CTCIF + - name: CHTIF4 + description: Channel %s Half Transfer clear. + bit_offset: 14 + bit_size: 1 + enum: CHTIF + - name: CTEIF4 + description: Channel %s Transfer Error clear. + bit_offset: 15 + bit_size: 1 + enum: CTEIF + - name: CGIF5 + description: Channel %s Global interrupt clear. + bit_offset: 16 + bit_size: 1 + enum: CGIF + - name: CTCIF5 + description: Channel %s Transfer Complete clear. + bit_offset: 17 + bit_size: 1 + enum: CTCIF + - name: CHTIF5 + description: Channel %s Half Transfer clear. + bit_offset: 18 + bit_size: 1 + enum: CHTIF + - name: CTEIF5 + description: Channel %s Transfer Error clear. + bit_offset: 19 + bit_size: 1 + enum: CTEIF + - name: CGIF6 + description: Channel %s Global interrupt clear. + bit_offset: 20 + bit_size: 1 + enum: CGIF + - name: CTCIF6 + description: Channel %s Transfer Complete clear. + bit_offset: 21 + bit_size: 1 + enum: CTCIF + - name: CHTIF6 + description: Channel %s Half Transfer clear. + bit_offset: 22 + bit_size: 1 + enum: CHTIF + - name: CTEIF6 + description: Channel %s Transfer Error clear. + bit_offset: 23 + bit_size: 1 + enum: CTEIF + - name: CGIF7 + description: Channel %s Global interrupt clear. + bit_offset: 24 + bit_size: 1 + enum: CGIF + - name: CTCIF7 + description: Channel %s Transfer Complete clear. + bit_offset: 25 + bit_size: 1 + enum: CTCIF + - name: CHTIF7 + description: Channel %s Half Transfer clear. + bit_offset: 26 + bit_size: 1 + enum: CHTIF + - name: CTEIF7 + description: Channel %s Transfer Error clear. + bit_offset: 27 + bit_size: 1 + enum: CTEIF +fieldset/ISR: + description: interrupt status register. + fields: + - name: GIF1 + description: Channel %s Global interrupt flag. + bit_offset: 0 + bit_size: 1 + enum: GIF + - name: TCIF1 + description: Channel %s Transfer Complete flag. + bit_offset: 1 + bit_size: 1 + enum: TCIF + - name: HTIF1 + description: Channel %s Half Transfer Complete flag. + bit_offset: 2 + bit_size: 1 + enum: HTIF + - name: TEIF1 + description: Channel %s Transfer Error flag. + bit_offset: 3 + bit_size: 1 + enum: TEIF + - name: GIF2 + description: Channel %s Global interrupt flag. + bit_offset: 4 + bit_size: 1 + enum: GIF + - name: TCIF2 + description: Channel %s Transfer Complete flag. + bit_offset: 5 + bit_size: 1 + enum: TCIF + - name: HTIF2 + description: Channel %s Half Transfer Complete flag. + bit_offset: 6 + bit_size: 1 + enum: HTIF + - name: TEIF2 + description: Channel %s Transfer Error flag. + bit_offset: 7 + bit_size: 1 + enum: TEIF + - name: GIF3 + description: Channel %s Global interrupt flag. + bit_offset: 8 + bit_size: 1 + enum: GIF + - name: TCIF3 + description: Channel %s Transfer Complete flag. + bit_offset: 9 + bit_size: 1 + enum: TCIF + - name: HTIF3 + description: Channel %s Half Transfer Complete flag. + bit_offset: 10 + bit_size: 1 + enum: HTIF + - name: TEIF3 + description: Channel %s Transfer Error flag. + bit_offset: 11 + bit_size: 1 + enum: TEIF + - name: GIF4 + description: Channel %s Global interrupt flag. + bit_offset: 12 + bit_size: 1 + enum: GIF + - name: TCIF4 + description: Channel %s Transfer Complete flag. + bit_offset: 13 + bit_size: 1 + enum: TCIF + - name: HTIF4 + description: Channel %s Half Transfer Complete flag. + bit_offset: 14 + bit_size: 1 + enum: HTIF + - name: TEIF4 + description: Channel %s Transfer Error flag. + bit_offset: 15 + bit_size: 1 + enum: TEIF + - name: GIF5 + description: Channel %s Global interrupt flag. + bit_offset: 16 + bit_size: 1 + enum: GIF + - name: TCIF5 + description: Channel %s Transfer Complete flag. + bit_offset: 17 + bit_size: 1 + enum: TCIF + - name: HTIF5 + description: Channel %s Half Transfer Complete flag. + bit_offset: 18 + bit_size: 1 + enum: HTIF + - name: TEIF5 + description: Channel %s Transfer Error flag. + bit_offset: 19 + bit_size: 1 + enum: TEIF + - name: GIF6 + description: Channel %s Global interrupt flag. + bit_offset: 20 + bit_size: 1 + enum: GIF + - name: TCIF6 + description: Channel %s Transfer Complete flag. + bit_offset: 21 + bit_size: 1 + enum: TCIF + - name: HTIF6 + description: Channel %s Half Transfer Complete flag. + bit_offset: 22 + bit_size: 1 + enum: HTIF + - name: TEIF6 + description: Channel %s Transfer Error flag. + bit_offset: 23 + bit_size: 1 + enum: TEIF + - name: GIF7 + description: Channel %s Global interrupt flag. + bit_offset: 24 + bit_size: 1 + enum: GIF + - name: TCIF7 + description: Channel %s Transfer Complete flag. + bit_offset: 25 + bit_size: 1 + enum: TCIF + - name: HTIF7 + description: Channel %s Half Transfer Complete flag. + bit_offset: 26 + bit_size: 1 + enum: HTIF + - name: TEIF7 + description: Channel %s Transfer Error flag. + bit_offset: 27 + bit_size: 1 + enum: TEIF +enum/CGIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register. + value: 1 +enum/CH1_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH1_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH1_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH1_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. + value: 1 +enum/CH1_CR_MEM2MEM: + bit_size: 1 + variants: + - name: Disabled + description: Memory to memory mode disabled. + value: 0 + - name: Enabled + description: Memory to memory mode enabled. + value: 1 +enum/CH1_CR_MINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH1_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH1_CR_PINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH1_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH1_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH1_CR_TCIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH1_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH2_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH2_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH2_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH2_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. + value: 1 +enum/CH2_CR_MEM2MEM: + bit_size: 1 + variants: + - name: Disabled + description: Memory to memory mode disabled. + value: 0 + - name: Enabled + description: Memory to memory mode enabled. + value: 1 +enum/CH2_CR_MINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH2_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH2_CR_PINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH2_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH2_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH2_CR_TCIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH2_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH3_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH3_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH3_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH3_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. + value: 1 +enum/CH3_CR_MEM2MEM: + bit_size: 1 + variants: + - name: Disabled + description: Memory to memory mode disabled. + value: 0 + - name: Enabled + description: Memory to memory mode enabled. + value: 1 +enum/CH3_CR_MINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH3_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH3_CR_PINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH3_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH3_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH3_CR_TCIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH3_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH4_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH4_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH4_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH4_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. + value: 1 +enum/CH4_CR_MEM2MEM: + bit_size: 1 + variants: + - name: Disabled + description: Memory to memory mode disabled. + value: 0 + - name: Enabled + description: Memory to memory mode enabled. + value: 1 +enum/CH4_CR_MINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH4_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH4_CR_PINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH4_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH4_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH4_CR_TCIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH4_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH5_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH5_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH5_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH5_CR_HTIE: bit_size: 1 variants: - - name: Clear - description: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register. + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. value: 1 -enum/CHTIF: +enum/CH5_CR_MEM2MEM: bit_size: 1 variants: - - name: Clear - description: Clears the HTIF flag in the ISR register. + - name: Disabled + description: Memory to memory mode disabled. + value: 0 + - name: Enabled + description: Memory to memory mode enabled. value: 1 -enum/CIRC: +enum/CH5_CR_MINC: bit_size: 1 variants: - name: Disabled - description: Circular buffer disabled. + description: Increment mode disabled. value: 0 - name: Enabled - description: Circular buffer enabled. + description: Increment mode enabled. value: 1 -enum/CTCIF: +enum/CH5_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH5_CR_PINC: bit_size: 1 variants: - - name: Clear - description: Clears the TCIF flag in the ISR register. + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. value: 1 -enum/CTEIF: +enum/CH5_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH5_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH5_CR_TCIE: bit_size: 1 variants: - - name: Clear - description: Clears the TEIF flag in the ISR register. + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH5_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH6_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. value: 1 -enum/DIR: +enum/CH6_CR_DIR: bit_size: 1 variants: - name: FromPeripheral @@ -233,7 +1670,7 @@ enum/DIR: - name: FromMemory description: Read from memory. value: 1 -enum/EN: +enum/CH6_CR_EN: bit_size: 1 variants: - name: Disabled @@ -242,34 +1679,136 @@ enum/EN: - name: Enabled description: Channel enabled. value: 1 -enum/GIF: +enum/CH6_CR_HTIE: bit_size: 1 variants: - - name: NoEvent - description: No transfer error, half event, complete event. + - name: Disabled + description: Half Transfer interrupt disabled. value: 0 - - name: Event - description: A transfer error, half event or complete event has occured. + - name: Enabled + description: Half Transfer interrupt enabled. value: 1 -enum/HTIE: +enum/CH6_CR_MEM2MEM: bit_size: 1 variants: - name: Disabled - description: Half Transfer interrupt disabled. + description: Memory to memory mode disabled. value: 0 - name: Enabled - description: Half Transfer interrupt enabled. + description: Memory to memory mode enabled. value: 1 -enum/HTIF: +enum/CH6_CR_MINC: bit_size: 1 variants: - - name: NotHalf - description: No half transfer event. + - name: Disabled + description: Increment mode disabled. value: 0 - - name: Half - description: A half transfer event has occured. + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH6_CR_MSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH6_CR_PINC: + bit_size: 1 + variants: + - name: Disabled + description: Increment mode disabled. + value: 0 + - name: Enabled + description: Increment mode enabled. + value: 1 +enum/CH6_CR_PL: + bit_size: 2 + variants: + - name: Low + description: Low priority. + value: 0 + - name: Medium + description: Medium priority. + value: 1 + - name: High + description: High priority. + value: 2 + - name: VeryHigh + description: Very high priority. + value: 3 +enum/CH6_CR_PSIZE: + bit_size: 2 + variants: + - name: Bits8 + description: 8-bit size. + value: 0 + - name: Bits16 + description: 16-bit size. + value: 1 + - name: Bits32 + description: 32-bit size. + value: 2 +enum/CH6_CR_TCIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Complete interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Complete interrupt enabled. + value: 1 +enum/CH6_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CH7_CR_CIRC: + bit_size: 1 + variants: + - name: Disabled + description: Circular buffer disabled. + value: 0 + - name: Enabled + description: Circular buffer enabled. + value: 1 +enum/CH7_CR_DIR: + bit_size: 1 + variants: + - name: FromPeripheral + description: Read from peripheral. + value: 0 + - name: FromMemory + description: Read from memory. + value: 1 +enum/CH7_CR_EN: + bit_size: 1 + variants: + - name: Disabled + description: Channel disabled. + value: 0 + - name: Enabled + description: Channel enabled. + value: 1 +enum/CH7_CR_HTIE: + bit_size: 1 + variants: + - name: Disabled + description: Half Transfer interrupt disabled. + value: 0 + - name: Enabled + description: Half Transfer interrupt enabled. value: 1 -enum/MEM2MEM: +enum/CH7_CR_MEM2MEM: bit_size: 1 variants: - name: Disabled @@ -278,7 +1817,7 @@ enum/MEM2MEM: - name: Enabled description: Memory to memory mode enabled. value: 1 -enum/MINC: +enum/CH7_CR_MINC: bit_size: 1 variants: - name: Disabled @@ -287,7 +1826,7 @@ enum/MINC: - name: Enabled description: Increment mode enabled. value: 1 -enum/MSIZE: +enum/CH7_CR_MSIZE: bit_size: 2 variants: - name: Bits8 @@ -299,7 +1838,7 @@ enum/MSIZE: - name: Bits32 description: 32-bit size. value: 2 -enum/PINC: +enum/CH7_CR_PINC: bit_size: 1 variants: - name: Disabled @@ -308,7 +1847,7 @@ enum/PINC: - name: Enabled description: Increment mode enabled. value: 1 -enum/PL: +enum/CH7_CR_PL: bit_size: 2 variants: - name: Low @@ -323,7 +1862,7 @@ enum/PL: - name: VeryHigh description: Very high priority. value: 3 -enum/PSIZE: +enum/CH7_CR_PSIZE: bit_size: 2 variants: - name: Bits8 @@ -335,7 +1874,7 @@ enum/PSIZE: - name: Bits32 description: 32-bit size. value: 2 -enum/TCIE: +enum/CH7_CR_TCIE: bit_size: 1 variants: - name: Disabled @@ -344,6 +1883,51 @@ enum/TCIE: - name: Enabled description: Transfer Complete interrupt enabled. value: 1 +enum/CH7_CR_TEIE: + bit_size: 1 + variants: + - name: Disabled + description: Transfer Error interrupt disabled. + value: 0 + - name: Enabled + description: Transfer Error interrupt enabled. + value: 1 +enum/CHTIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the HTIF flag in the ISR register. + value: 1 +enum/CTCIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the TCIF flag in the ISR register. + value: 1 +enum/CTEIF: + bit_size: 1 + variants: + - name: Clear + description: Clears the TEIF flag in the ISR register. + value: 1 +enum/GIF: + bit_size: 1 + variants: + - name: NoEvent + description: No transfer error, half event, complete event. + value: 0 + - name: Event + description: A transfer error, half event or complete event has occured. + value: 1 +enum/HTIF: + bit_size: 1 + variants: + - name: NotHalf + description: No half transfer event. + value: 0 + - name: Half + description: A half transfer event has occured. + value: 1 enum/TCIF: bit_size: 1 variants: @@ -353,15 +1937,6 @@ enum/TCIF: - name: Complete description: A transfer complete event has occured. value: 1 -enum/TEIE: - bit_size: 1 - variants: - - name: Disabled - description: Transfer Error interrupt disabled. - value: 0 - - name: Enabled - description: Transfer Error interrupt enabled. - value: 1 enum/TEIF: bit_size: 1 variants: diff --git a/base/STM32WB55/DMAMUX1.yaml b/head/STM32WB55/DMAMUX1.yaml index c969c04..1c0def9 100644 --- a/base/STM32WB55/DMAMUX1.yaml +++ b/head/STM32WB55/DMAMUX1.yaml @@ -1,13 +1,62 @@ block/DMAMUX1: description: Direct memory access Multiplexer. items: - - name: CCR + - name: CCR0 description: DMA Multiplexer Channel %s Control register. - array: - len: 14 - stride: 4 byte_offset: 0 fieldset: CCR + - name: CCR1 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 4 + fieldset: CCR + - name: CCR2 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 8 + fieldset: CCR + - name: CCR3 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 12 + fieldset: CCR + - name: CCR4 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 16 + fieldset: CCR + - name: CCR5 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 20 + fieldset: CCR + - name: CCR6 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 24 + fieldset: CCR + - name: CCR7 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 28 + fieldset: CCR + - name: CCR8 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 32 + fieldset: CCR + - name: CCR9 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 36 + fieldset: CCR + - name: CCR10 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 40 + fieldset: CCR + - name: CCR11 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 44 + fieldset: CCR + - name: CCR12 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 48 + fieldset: CCR + - name: CCR13 + description: DMA Multiplexer Channel %s Control register. + byte_offset: 52 + fieldset: CCR - name: CSR description: DMA Multiplexer Channel Status register. byte_offset: 128 @@ -18,13 +67,22 @@ block/DMAMUX1: byte_offset: 132 access: Write fieldset: CFR - - name: RGCR + - name: RGCR0 description: DMA Request Generator %s Control Register. - array: - len: 4 - stride: 4 byte_offset: 256 fieldset: RGCR + - name: RGCR1 + description: DMA Request Generator %s Control Register. + byte_offset: 260 + fieldset: RGCR + - name: RGCR2 + description: DMA Request Generator %s Control Register. + byte_offset: 264 + fieldset: RGCR + - name: RGCR3 + description: DMA Request Generator %s Control Register. + byte_offset: 268 + fieldset: RGCR - name: RGSR description: DMA Request Generator Status Register. byte_offset: 320 @@ -73,35 +131,171 @@ fieldset/CCR: fieldset/CFR: description: DMA Channel Clear Flag Register. fields: - - name: CSOF + - name: CSOF0 description: Synchronization Clear Overrun Flag %s. bit_offset: 0 bit_size: 1 - array: - len: 14 - stride: 1 + enum: CSOF + - name: CSOF1 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 1 + bit_size: 1 + enum: CSOF + - name: CSOF2 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 2 + bit_size: 1 + enum: CSOF + - name: CSOF3 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 3 + bit_size: 1 + enum: CSOF + - name: CSOF4 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 4 + bit_size: 1 + enum: CSOF + - name: CSOF5 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 5 + bit_size: 1 + enum: CSOF + - name: CSOF6 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 6 + bit_size: 1 + enum: CSOF + - name: CSOF7 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 7 + bit_size: 1 + enum: CSOF + - name: CSOF8 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 8 + bit_size: 1 + enum: CSOF + - name: CSOF9 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 9 + bit_size: 1 + enum: CSOF + - name: CSOF10 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 10 + bit_size: 1 + enum: CSOF + - name: CSOF11 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 11 + bit_size: 1 + enum: CSOF + - name: CSOF12 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 12 + bit_size: 1 + enum: CSOF + - name: CSOF13 + description: Synchronization Clear Overrun Flag %s. + bit_offset: 13 + bit_size: 1 enum: CSOF fieldset/CSR: description: DMA Multiplexer Channel Status register. fields: - - name: SOF + - name: SOF0 description: Synchronization Overrun Flag %s. bit_offset: 0 bit_size: 1 - array: - len: 14 - stride: 1 + enum: SOF + - name: SOF1 + description: Synchronization Overrun Flag %s. + bit_offset: 1 + bit_size: 1 + enum: SOF + - name: SOF2 + description: Synchronization Overrun Flag %s. + bit_offset: 2 + bit_size: 1 + enum: SOF + - name: SOF3 + description: Synchronization Overrun Flag %s. + bit_offset: 3 + bit_size: 1 + enum: SOF + - name: SOF4 + description: Synchronization Overrun Flag %s. + bit_offset: 4 + bit_size: 1 + enum: SOF + - name: SOF5 + description: Synchronization Overrun Flag %s. + bit_offset: 5 + bit_size: 1 + enum: SOF + - name: SOF6 + description: Synchronization Overrun Flag %s. + bit_offset: 6 + bit_size: 1 + enum: SOF + - name: SOF7 + description: Synchronization Overrun Flag %s. + bit_offset: 7 + bit_size: 1 + enum: SOF + - name: SOF8 + description: Synchronization Overrun Flag %s. + bit_offset: 8 + bit_size: 1 + enum: SOF + - name: SOF9 + description: Synchronization Overrun Flag %s. + bit_offset: 9 + bit_size: 1 + enum: SOF + - name: SOF10 + description: Synchronization Overrun Flag %s. + bit_offset: 10 + bit_size: 1 + enum: SOF + - name: SOF11 + description: Synchronization Overrun Flag %s. + bit_offset: 11 + bit_size: 1 + enum: SOF + - name: SOF12 + description: Synchronization Overrun Flag %s. + bit_offset: 12 + bit_size: 1 + enum: SOF + - name: SOF13 + description: Synchronization Overrun Flag %s. + bit_offset: 13 + bit_size: 1 enum: SOF fieldset/RGCFR: description: DMA Request Generator Clear Flag Register. fields: - - name: COF + - name: COF0 description: Generator Clear Overrun Flag %s. bit_offset: 0 bit_size: 1 - array: - len: 4 - stride: 1 + enum: COF + - name: COF1 + description: Generator Clear Overrun Flag %s. + bit_offset: 1 + bit_size: 1 + enum: COF + - name: COF2 + description: Generator Clear Overrun Flag %s. + bit_offset: 2 + bit_size: 1 + enum: COF + - name: COF3 + description: Generator Clear Overrun Flag %s. + bit_offset: 3 + bit_size: 1 enum: COF fieldset/RGCR: description: DMA Request Generator %s Control Register. @@ -132,13 +326,25 @@ fieldset/RGCR: fieldset/RGSR: description: DMA Request Generator Status Register. fields: - - name: OF + - name: OF0 description: Generator Overrun Flag %s. bit_offset: 0 bit_size: 1 - array: - len: 4 - stride: 1 + enum: OF + - name: OF1 + description: Generator Overrun Flag %s. + bit_offset: 1 + bit_size: 1 + enum: OF + - name: OF2 + description: Generator Overrun Flag %s. + bit_offset: 2 + bit_size: 1 + enum: OF + - name: OF3 + description: Generator Overrun Flag %s. + bit_offset: 3 + bit_size: 1 enum: OF enum/COF: bit_size: 1 diff --git a/base/STM32WB55/GPIOA.yaml b/head/STM32WB55/GPIOA.yaml index 47e9b40..f98d9c2 100644 --- a/base/STM32WB55/GPIOA.yaml +++ b/head/STM32WB55/GPIOA.yaml @@ -54,64 +54,449 @@ fieldset/AFRH: fieldset/AFRL: description: GPIO alternate function low register. fields: - - name: AFR + - name: AFREL0 description: Alternate function selection for port x bit y (y = 0..7). bit_offset: 0 bit_size: 4 - array: - len: 8 - stride: 4 + - name: AFREL1 + description: Alternate function selection for port x bit y (y = 0..7). + bit_offset: 4 + bit_size: 4 + - name: AFREL2 + description: Alternate function selection for port x bit y (y = 0..7). + bit_offset: 8 + bit_size: 4 + - name: AFREL3 + description: Alternate function selection for port x bit y (y = 0..7). + bit_offset: 12 + bit_size: 4 + - name: AFREL4 + description: Alternate function selection for port x bit y (y = 0..7). + bit_offset: 16 + bit_size: 4 + - name: AFREL5 + description: Alternate function selection for port x bit y (y = 0..7). + bit_offset: 20 + bit_size: 4 + - name: AFREL6 + description: Alternate function selection for port x bit y (y = 0..7). + bit_offset: 24 + bit_size: 4 + - name: AFREL7 + description: Alternate function selection for port x bit y (y = 0..7). + bit_offset: 28 + bit_size: 4 fieldset/BRR: description: port bit reset register. fields: - - name: BR + - name: BR0 description: Port x reset pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: BRR_BR + - name: BR1 + description: Port x reset pin %s. + bit_offset: 1 + bit_size: 1 + enum: BRR_BR + - name: BR2 + description: Port x reset pin %s. + bit_offset: 2 + bit_size: 1 + enum: BRR_BR + - name: BR3 + description: Port x reset pin %s. + bit_offset: 3 + bit_size: 1 + enum: BRR_BR + - name: BR4 + description: Port x reset pin %s. + bit_offset: 4 + bit_size: 1 + enum: BRR_BR + - name: BR5 + description: Port x reset pin %s. + bit_offset: 5 + bit_size: 1 + enum: BRR_BR + - name: BR6 + description: Port x reset pin %s. + bit_offset: 6 + bit_size: 1 + enum: BRR_BR + - name: BR7 + description: Port x reset pin %s. + bit_offset: 7 + bit_size: 1 + enum: BRR_BR + - name: BR8 + description: Port x reset pin %s. + bit_offset: 8 + bit_size: 1 + enum: BRR_BR + - name: BR9 + description: Port x reset pin %s. + bit_offset: 9 + bit_size: 1 + enum: BRR_BR + - name: BR10 + description: Port x reset pin %s. + bit_offset: 10 + bit_size: 1 + enum: BRR_BR + - name: BR11 + description: Port x reset pin %s. + bit_offset: 11 + bit_size: 1 + enum: BRR_BR + - name: BR12 + description: Port x reset pin %s. + bit_offset: 12 + bit_size: 1 + enum: BRR_BR + - name: BR13 + description: Port x reset pin %s. + bit_offset: 13 + bit_size: 1 + enum: BRR_BR + - name: BR14 + description: Port x reset pin %s. + bit_offset: 14 + bit_size: 1 + enum: BRR_BR + - name: BR15 + description: Port x reset pin %s. + bit_offset: 15 + bit_size: 1 enum: BRR_BR fieldset/BSRR: description: GPIO port bit set/reset register. fields: - - name: BS + - name: BS0 description: Port x set pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 enum: BS - - name: BR + - name: BS1 + description: Port x set pin %s. + bit_offset: 1 + bit_size: 1 + enum: BS + - name: BS2 + description: Port x set pin %s. + bit_offset: 2 + bit_size: 1 + enum: BS + - name: BS3 + description: Port x set pin %s. + bit_offset: 3 + bit_size: 1 + enum: BS + - name: BS4 + description: Port x set pin %s. + bit_offset: 4 + bit_size: 1 + enum: BS + - name: BS5 + description: Port x set pin %s. + bit_offset: 5 + bit_size: 1 + enum: BS + - name: BS6 + description: Port x set pin %s. + bit_offset: 6 + bit_size: 1 + enum: BS + - name: BS7 + description: Port x set pin %s. + bit_offset: 7 + bit_size: 1 + enum: BS + - name: BS8 + description: Port x set pin %s. + bit_offset: 8 + bit_size: 1 + enum: BS + - name: BS9 + description: Port x set pin %s. + bit_offset: 9 + bit_size: 1 + enum: BS + - name: BS10 + description: Port x set pin %s. + bit_offset: 10 + bit_size: 1 + enum: BS + - name: BS11 + description: Port x set pin %s. + bit_offset: 11 + bit_size: 1 + enum: BS + - name: BS12 + description: Port x set pin %s. + bit_offset: 12 + bit_size: 1 + enum: BS + - name: BS13 + description: Port x set pin %s. + bit_offset: 13 + bit_size: 1 + enum: BS + - name: BS14 + description: Port x set pin %s. + bit_offset: 14 + bit_size: 1 + enum: BS + - name: BS15 + description: Port x set pin %s. + bit_offset: 15 + bit_size: 1 + enum: BS + - name: BR0 description: Port x reset pin %s. bit_offset: 16 bit_size: 1 - array: - len: 16 - stride: 1 + enum: BSRR_BR + - name: BR1 + description: Port x reset pin %s. + bit_offset: 17 + bit_size: 1 + enum: BSRR_BR + - name: BR2 + description: Port x reset pin %s. + bit_offset: 18 + bit_size: 1 + enum: BSRR_BR + - name: BR3 + description: Port x reset pin %s. + bit_offset: 19 + bit_size: 1 + enum: BSRR_BR + - name: BR4 + description: Port x reset pin %s. + bit_offset: 20 + bit_size: 1 + enum: BSRR_BR + - name: BR5 + description: Port x reset pin %s. + bit_offset: 21 + bit_size: 1 + enum: BSRR_BR + - name: BR6 + description: Port x reset pin %s. + bit_offset: 22 + bit_size: 1 + enum: BSRR_BR + - name: BR7 + description: Port x reset pin %s. + bit_offset: 23 + bit_size: 1 + enum: BSRR_BR + - name: BR8 + description: Port x reset pin %s. + bit_offset: 24 + bit_size: 1 + enum: BSRR_BR + - name: BR9 + description: Port x reset pin %s. + bit_offset: 25 + bit_size: 1 + enum: BSRR_BR + - name: BR10 + description: Port x reset pin %s. + bit_offset: 26 + bit_size: 1 + enum: BSRR_BR + - name: BR11 + description: Port x reset pin %s. + bit_offset: 27 + bit_size: 1 + enum: BSRR_BR + - name: BR12 + description: Port x reset pin %s. + bit_offset: 28 + bit_size: 1 + enum: BSRR_BR + - name: BR13 + description: Port x reset pin %s. + bit_offset: 29 + bit_size: 1 + enum: BSRR_BR + - name: BR14 + description: Port x reset pin %s. + bit_offset: 30 + bit_size: 1 + enum: BSRR_BR + - name: BR15 + description: Port x reset pin %s. + bit_offset: 31 + bit_size: 1 enum: BSRR_BR fieldset/IDR: description: GPIO port input data register. fields: - - name: IDR + - name: IDR0 description: Port input data pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: IDR + - name: IDR1 + description: Port input data pin %s. + bit_offset: 1 + bit_size: 1 + enum: IDR + - name: IDR2 + description: Port input data pin %s. + bit_offset: 2 + bit_size: 1 + enum: IDR + - name: IDR3 + description: Port input data pin %s. + bit_offset: 3 + bit_size: 1 + enum: IDR + - name: IDR4 + description: Port input data pin %s. + bit_offset: 4 + bit_size: 1 + enum: IDR + - name: IDR5 + description: Port input data pin %s. + bit_offset: 5 + bit_size: 1 + enum: IDR + - name: IDR6 + description: Port input data pin %s. + bit_offset: 6 + bit_size: 1 + enum: IDR + - name: IDR7 + description: Port input data pin %s. + bit_offset: 7 + bit_size: 1 + enum: IDR + - name: IDR8 + description: Port input data pin %s. + bit_offset: 8 + bit_size: 1 + enum: IDR + - name: IDR9 + description: Port input data pin %s. + bit_offset: 9 + bit_size: 1 + enum: IDR + - name: IDR10 + description: Port input data pin %s. + bit_offset: 10 + bit_size: 1 + enum: IDR + - name: IDR11 + description: Port input data pin %s. + bit_offset: 11 + bit_size: 1 + enum: IDR + - name: IDR12 + description: Port input data pin %s. + bit_offset: 12 + bit_size: 1 + enum: IDR + - name: IDR13 + description: Port input data pin %s. + bit_offset: 13 + bit_size: 1 + enum: IDR + - name: IDR14 + description: Port input data pin %s. + bit_offset: 14 + bit_size: 1 + enum: IDR + - name: IDR15 + description: Port input data pin %s. + bit_offset: 15 + bit_size: 1 enum: IDR fieldset/LCKR: description: GPIO port configuration lock register. fields: - - name: LCK + - name: LCK0 description: Port x lock pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: LCK + - name: LCK1 + description: Port x lock pin %s. + bit_offset: 1 + bit_size: 1 + enum: LCK + - name: LCK2 + description: Port x lock pin %s. + bit_offset: 2 + bit_size: 1 + enum: LCK + - name: LCK3 + description: Port x lock pin %s. + bit_offset: 3 + bit_size: 1 + enum: LCK + - name: LCK4 + description: Port x lock pin %s. + bit_offset: 4 + bit_size: 1 + enum: LCK + - name: LCK5 + description: Port x lock pin %s. + bit_offset: 5 + bit_size: 1 + enum: LCK + - name: LCK6 + description: Port x lock pin %s. + bit_offset: 6 + bit_size: 1 + enum: LCK + - name: LCK7 + description: Port x lock pin %s. + bit_offset: 7 + bit_size: 1 + enum: LCK + - name: LCK8 + description: Port x lock pin %s. + bit_offset: 8 + bit_size: 1 + enum: LCK + - name: LCK9 + description: Port x lock pin %s. + bit_offset: 9 + bit_size: 1 + enum: LCK + - name: LCK10 + description: Port x lock pin %s. + bit_offset: 10 + bit_size: 1 + enum: LCK + - name: LCK11 + description: Port x lock pin %s. + bit_offset: 11 + bit_size: 1 + enum: LCK + - name: LCK12 + description: Port x lock pin %s. + bit_offset: 12 + bit_size: 1 + enum: LCK + - name: LCK13 + description: Port x lock pin %s. + bit_offset: 13 + bit_size: 1 + enum: LCK + - name: LCK14 + description: Port x lock pin %s. + bit_offset: 14 + bit_size: 1 + enum: LCK + - name: LCK15 + description: Port x lock pin %s. + bit_offset: 15 + bit_size: 1 enum: LCK - name: LCKK description: Port x lock bit y (y= 0..15). @@ -121,57 +506,417 @@ fieldset/LCKR: fieldset/MODER: description: GPIO port mode register. fields: - - name: MODER + - name: MODER0 description: Port x configuration pin %s. bit_offset: 0 bit_size: 2 - array: - len: 16 - stride: 2 + enum: MODER + - name: MODER1 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 2 + enum: MODER + - name: MODER2 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 2 + enum: MODER + - name: MODER3 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 2 + enum: MODER + - name: MODER4 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 2 + enum: MODER + - name: MODER5 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 2 + enum: MODER + - name: MODER6 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 2 + enum: MODER + - name: MODER7 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 2 + enum: MODER + - name: MODER8 + description: Port x configuration pin %s. + bit_offset: 16 + bit_size: 2 + enum: MODER + - name: MODER9 + description: Port x configuration pin %s. + bit_offset: 18 + bit_size: 2 + enum: MODER + - name: MODER10 + description: Port x configuration pin %s. + bit_offset: 20 + bit_size: 2 + enum: MODER + - name: MODER11 + description: Port x configuration pin %s. + bit_offset: 22 + bit_size: 2 + enum: MODER + - name: MODER12 + description: Port x configuration pin %s. + bit_offset: 24 + bit_size: 2 + enum: MODER + - name: MODER13 + description: Port x configuration pin %s. + bit_offset: 26 + bit_size: 2 + enum: MODER + - name: MODER14 + description: Port x configuration pin %s. + bit_offset: 28 + bit_size: 2 + enum: MODER + - name: MODER15 + description: Port x configuration pin %s. + bit_offset: 30 + bit_size: 2 enum: MODER fieldset/ODR: description: GPIO port output data register. fields: - - name: ODR + - name: ODR0 description: Port output data pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: ODR + - name: ODR1 + description: Port output data pin %s. + bit_offset: 1 + bit_size: 1 + enum: ODR + - name: ODR2 + description: Port output data pin %s. + bit_offset: 2 + bit_size: 1 + enum: ODR + - name: ODR3 + description: Port output data pin %s. + bit_offset: 3 + bit_size: 1 + enum: ODR + - name: ODR4 + description: Port output data pin %s. + bit_offset: 4 + bit_size: 1 + enum: ODR + - name: ODR5 + description: Port output data pin %s. + bit_offset: 5 + bit_size: 1 + enum: ODR + - name: ODR6 + description: Port output data pin %s. + bit_offset: 6 + bit_size: 1 + enum: ODR + - name: ODR7 + description: Port output data pin %s. + bit_offset: 7 + bit_size: 1 + enum: ODR + - name: ODR8 + description: Port output data pin %s. + bit_offset: 8 + bit_size: 1 + enum: ODR + - name: ODR9 + description: Port output data pin %s. + bit_offset: 9 + bit_size: 1 + enum: ODR + - name: ODR10 + description: Port output data pin %s. + bit_offset: 10 + bit_size: 1 + enum: ODR + - name: ODR11 + description: Port output data pin %s. + bit_offset: 11 + bit_size: 1 + enum: ODR + - name: ODR12 + description: Port output data pin %s. + bit_offset: 12 + bit_size: 1 + enum: ODR + - name: ODR13 + description: Port output data pin %s. + bit_offset: 13 + bit_size: 1 + enum: ODR + - name: ODR14 + description: Port output data pin %s. + bit_offset: 14 + bit_size: 1 + enum: ODR + - name: ODR15 + description: Port output data pin %s. + bit_offset: 15 + bit_size: 1 enum: ODR fieldset/OSPEEDR: description: GPIO port output speed register. fields: - - name: OSPEEDR + - name: OSPEEDR0 description: Port x configuration pin %s. bit_offset: 0 bit_size: 2 - array: - len: 16 - stride: 2 + enum: OSPEEDR + - name: OSPEEDR1 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR2 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR3 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR4 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR5 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR6 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR7 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR8 + description: Port x configuration pin %s. + bit_offset: 16 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR9 + description: Port x configuration pin %s. + bit_offset: 18 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR10 + description: Port x configuration pin %s. + bit_offset: 20 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR11 + description: Port x configuration pin %s. + bit_offset: 22 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR12 + description: Port x configuration pin %s. + bit_offset: 24 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR13 + description: Port x configuration pin %s. + bit_offset: 26 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR14 + description: Port x configuration pin %s. + bit_offset: 28 + bit_size: 2 + enum: OSPEEDR + - name: OSPEEDR15 + description: Port x configuration pin %s. + bit_offset: 30 + bit_size: 2 enum: OSPEEDR fieldset/OTYPER: description: GPIO port output type register. fields: - - name: OT + - name: OT0 description: Port x configuration pin %s. bit_offset: 0 bit_size: 1 - array: - len: 16 - stride: 1 + enum: OT + - name: OT1 + description: Port x configuration pin %s. + bit_offset: 1 + bit_size: 1 + enum: OT + - name: OT2 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 1 + enum: OT + - name: OT3 + description: Port x configuration pin %s. + bit_offset: 3 + bit_size: 1 + enum: OT + - name: OT4 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 1 + enum: OT + - name: OT5 + description: Port x configuration pin %s. + bit_offset: 5 + bit_size: 1 + enum: OT + - name: OT6 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 1 + enum: OT + - name: OT7 + description: Port x configuration pin %s. + bit_offset: 7 + bit_size: 1 + enum: OT + - name: OT8 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 1 + enum: OT + - name: OT9 + description: Port x configuration pin %s. + bit_offset: 9 + bit_size: 1 + enum: OT + - name: OT10 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 1 + enum: OT + - name: OT11 + description: Port x configuration pin %s. + bit_offset: 11 + bit_size: 1 + enum: OT + - name: OT12 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 1 + enum: OT + - name: OT13 + description: Port x configuration pin %s. + bit_offset: 13 + bit_size: 1 + enum: OT + - name: OT14 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 1 + enum: OT + - name: OT15 + description: Port x configuration pin %s. + bit_offset: 15 + bit_size: 1 enum: OT fieldset/PUPDR: description: GPIO port pull-up/pull-down register. fields: - - name: PUPDR + - name: PUPDR0 description: Port x configuration pin %s. bit_offset: 0 bit_size: 2 - array: - len: 16 - stride: 2 + enum: PUPDR + - name: PUPDR1 + description: Port x configuration pin %s. + bit_offset: 2 + bit_size: 2 + enum: PUPDR + - name: PUPDR2 + description: Port x configuration pin %s. + bit_offset: 4 + bit_size: 2 + enum: PUPDR + - name: PUPDR3 + description: Port x configuration pin %s. + bit_offset: 6 + bit_size: 2 + enum: PUPDR + - name: PUPDR4 + description: Port x configuration pin %s. + bit_offset: 8 + bit_size: 2 + enum: PUPDR + - name: PUPDR5 + description: Port x configuration pin %s. + bit_offset: 10 + bit_size: 2 + enum: PUPDR + - name: PUPDR6 + description: Port x configuration pin %s. + bit_offset: 12 + bit_size: 2 + enum: PUPDR + - name: PUPDR7 + description: Port x configuration pin %s. + bit_offset: 14 + bit_size: 2 + enum: PUPDR + - name: PUPDR8 + description: Port x configuration pin %s. + bit_offset: 16 + bit_size: 2 + enum: PUPDR + - name: PUPDR9 + description: Port x configuration pin %s. + bit_offset: 18 + bit_size: 2 + enum: PUPDR + - name: PUPDR10 + description: Port x configuration pin %s. + bit_offset: 20 + bit_size: 2 + enum: PUPDR + - name: PUPDR11 + description: Port x configuration pin %s. + bit_offset: 22 + bit_size: 2 + enum: PUPDR + - name: PUPDR12 + description: Port x configuration pin %s. + bit_offset: 24 + bit_size: 2 + enum: PUPDR + - name: PUPDR13 + description: Port x configuration pin %s. + bit_offset: 26 + bit_size: 2 + enum: PUPDR + - name: PUPDR14 + description: Port x configuration pin %s. + bit_offset: 28 + bit_size: 2 + enum: PUPDR + - name: PUPDR15 + description: Port x configuration pin %s. + bit_offset: 30 + bit_size: 2 enum: PUPDR enum/BRR_BR: bit_size: 1 diff --git a/base/STM32WB55/HSEM.yaml b/head/STM32WB55/HSEM.yaml index bead0f4..d2901b5 100644 --- a/base/STM32WB55/HSEM.yaml +++ b/head/STM32WB55/HSEM.yaml @@ -1,21 +1,294 @@ block/HSEM: description: HSEM. items: - - name: R + - name: R0 description: HSEM register HSEM_R%s. - array: - len: 32 - stride: 4 byte_offset: 0 fieldset: R - - name: RLR + - name: R1 + description: HSEM register HSEM_R%s. + byte_offset: 4 + fieldset: R + - name: R2 + description: HSEM register HSEM_R%s. + byte_offset: 8 + fieldset: R + - name: R3 + description: HSEM register HSEM_R%s. + byte_offset: 12 + fieldset: R + - name: R4 + description: HSEM register HSEM_R%s. + byte_offset: 16 + fieldset: R + - name: R5 + description: HSEM register HSEM_R%s. + byte_offset: 20 + fieldset: R + - name: R6 + description: HSEM register HSEM_R%s. + byte_offset: 24 + fieldset: R + - name: R7 + description: HSEM register HSEM_R%s. + byte_offset: 28 + fieldset: R + - name: R8 + description: HSEM register HSEM_R%s. + byte_offset: 32 + fieldset: R + - name: R9 + description: HSEM register HSEM_R%s. + byte_offset: 36 + fieldset: R + - name: R10 + description: HSEM register HSEM_R%s. + byte_offset: 40 + fieldset: R + - name: R11 + description: HSEM register HSEM_R%s. + byte_offset: 44 + fieldset: R + - name: R12 + description: HSEM register HSEM_R%s. + byte_offset: 48 + fieldset: R + - name: R13 + description: HSEM register HSEM_R%s. + byte_offset: 52 + fieldset: R + - name: R14 + description: HSEM register HSEM_R%s. + byte_offset: 56 + fieldset: R + - name: R15 + description: HSEM register HSEM_R%s. + byte_offset: 60 + fieldset: R + - name: R16 + description: HSEM register HSEM_R%s. + byte_offset: 64 + fieldset: R + - name: R17 + description: HSEM register HSEM_R%s. + byte_offset: 68 + fieldset: R + - name: R18 + description: HSEM register HSEM_R%s. + byte_offset: 72 + fieldset: R + - name: R19 + description: HSEM register HSEM_R%s. + byte_offset: 76 + fieldset: R + - name: R20 + description: HSEM register HSEM_R%s. + byte_offset: 80 + fieldset: R + - name: R21 + description: HSEM register HSEM_R%s. + byte_offset: 84 + fieldset: R + - name: R22 + description: HSEM register HSEM_R%s. + byte_offset: 88 + fieldset: R + - name: R23 + description: HSEM register HSEM_R%s. + byte_offset: 92 + fieldset: R + - name: R24 + description: HSEM register HSEM_R%s. + byte_offset: 96 + fieldset: R + - name: R25 + description: HSEM register HSEM_R%s. + byte_offset: 100 + fieldset: R + - name: R26 + description: HSEM register HSEM_R%s. + byte_offset: 104 + fieldset: R + - name: R27 + description: HSEM register HSEM_R%s. + byte_offset: 108 + fieldset: R + - name: R28 + description: HSEM register HSEM_R%s. + byte_offset: 112 + fieldset: R + - name: R29 + description: HSEM register HSEM_R%s. + byte_offset: 116 + fieldset: R + - name: R30 + description: HSEM register HSEM_R%s. + byte_offset: 120 + fieldset: R + - name: R31 + description: HSEM register HSEM_R%s. + byte_offset: 124 + fieldset: R + - name: RLR0 description: Semaphore %s read lock register. - array: - len: 32 - stride: 4 byte_offset: 128 access: Read fieldset: RLR + - name: RLR1 + description: Semaphore %s read lock register. + byte_offset: 132 + access: Read + fieldset: RLR + - name: RLR2 + description: Semaphore %s read lock register. + byte_offset: 136 + access: Read + fieldset: RLR + - name: RLR3 + description: Semaphore %s read lock register. + byte_offset: 140 + access: Read + fieldset: RLR + - name: RLR4 + description: Semaphore %s read lock register. + byte_offset: 144 + access: Read + fieldset: RLR + - name: RLR5 + description: Semaphore %s read lock register. + byte_offset: 148 + access: Read + fieldset: RLR + - name: RLR6 + description: Semaphore %s read lock register. + byte_offset: 152 + access: Read + fieldset: RLR + - name: RLR7 + description: Semaphore %s read lock register. + byte_offset: 156 + access: Read + fieldset: RLR + - name: RLR8 + description: Semaphore %s read lock register. + byte_offset: 160 + access: Read + fieldset: RLR + - name: RLR9 + description: Semaphore %s read lock register. + byte_offset: 164 + access: Read + fieldset: RLR + - name: RLR10 + description: Semaphore %s read lock register. + byte_offset: 168 + access: Read + fieldset: RLR + - name: RLR11 + description: Semaphore %s read lock register. + byte_offset: 172 + access: Read + fieldset: RLR + - name: RLR12 + description: Semaphore %s read lock register. + byte_offset: 176 + access: Read + fieldset: RLR + - name: RLR13 + description: Semaphore %s read lock register. + byte_offset: 180 + access: Read + fieldset: RLR + - name: RLR14 + description: Semaphore %s read lock register. + byte_offset: 184 + access: Read + fieldset: RLR + - name: RLR15 + description: Semaphore %s read lock register. + byte_offset: 188 + access: Read + fieldset: RLR + - name: RLR16 + description: Semaphore %s read lock register. + byte_offset: 192 + access: Read + fieldset: RLR + - name: RLR17 + description: Semaphore %s read lock register. + byte_offset: 196 + access: Read + fieldset: RLR + - name: RLR18 + description: Semaphore %s read lock register. + byte_offset: 200 + access: Read + fieldset: RLR + - name: RLR19 + description: Semaphore %s read lock register. + byte_offset: 204 + access: Read + fieldset: RLR + - name: RLR20 + description: Semaphore %s read lock register. + byte_offset: 208 + access: Read + fieldset: RLR + - name: RLR21 + description: Semaphore %s read lock register. + byte_offset: 212 + access: Read + fieldset: RLR + - name: RLR22 + description: Semaphore %s read lock register. + byte_offset: 216 + access: Read + fieldset: RLR + - name: RLR23 + description: Semaphore %s read lock register. + byte_offset: 220 + access: Read + fieldset: RLR + - name: RLR24 + description: Semaphore %s read lock register. + byte_offset: 224 + access: Read + fieldset: RLR + - name: RLR25 + description: Semaphore %s read lock register. + byte_offset: 228 + access: Read + fieldset: RLR + - name: RLR26 + description: Semaphore %s read lock register. + byte_offset: 232 + access: Read + fieldset: RLR + - name: RLR27 + description: Semaphore %s read lock register. + byte_offset: 236 + access: Read + fieldset: RLR + - name: RLR28 + description: Semaphore %s read lock register. + byte_offset: 240 + access: Read + fieldset: RLR + - name: RLR29 + description: Semaphore %s read lock register. + byte_offset: 244 + access: Read + fieldset: RLR + - name: RLR30 + description: Semaphore %s read lock register. + byte_offset: 248 + access: Read + fieldset: RLR + - name: RLR31 + description: Semaphore %s read lock register. + byte_offset: 252 + access: Read + fieldset: RLR - name: C1IER description: HSEM Interrupt enable register. byte_offset: 256 @@ -88,90 +361,1306 @@ block/HSEM: fieldset/C1ICR: description: HSEM Interrupt clear register. fields: - - name: ISC + - name: ISC0 description: Interrupt semaphore %s clear bit. bit_offset: 0 bit_size: 1 - array: - len: 32 - stride: 1 enum: C1ICR_ISC -fieldset/C1IER: - description: HSEM Interrupt enable register. - fields: - - name: ISE - description: Interrupt semaphore %s enable bit. - bit_offset: 0 + - name: ISC1 + description: Interrupt semaphore %s clear bit. + bit_offset: 1 bit_size: 1 - array: - len: 32 - stride: 1 - enum: C1IER_ISE -fieldset/C1ISR: - description: HSEM Interrupt status register. - fields: - - name: ISF - description: Interrupt semaphore %s status bit before enable (mask). - bit_offset: 0 + enum: C1ICR_ISC + - name: ISC2 + description: Interrupt semaphore %s clear bit. + bit_offset: 2 bit_size: 1 - array: - len: 32 - stride: 1 - enum: C1ISR_ISF -fieldset/C1MISR: - description: HSEM Masked interrupt status register. - fields: - - name: MISF - description: Masked interrupt semaphore %s status bit after enable (mask). - bit_offset: 0 + enum: C1ICR_ISC + - name: ISC3 + description: Interrupt semaphore %s clear bit. + bit_offset: 3 bit_size: 1 - array: - len: 32 - stride: 1 - enum: C1MISR_MISF -fieldset/C2ICR: - description: HSEM Interrupt clear register. - fields: - - name: ISC + enum: C1ICR_ISC + - name: ISC4 description: Interrupt semaphore %s clear bit. - bit_offset: 0 + bit_offset: 4 bit_size: 1 - array: - len: 32 - stride: 1 - enum: C2ICR_ISC -fieldset/C2IER: - description: HSEM Interrupt enable register. - fields: - - name: ISE - description: Interrupt semaphore %s enable bit. - bit_offset: 0 + enum: C1ICR_ISC + - name: ISC5 + description: Interrupt semaphore %s clear bit. + bit_offset: 5 bit_size: 1 - array: - len: 32 - stride: 1 - enum: C2IER_ISE -fieldset/C2ISR: - description: HSEM Interrupt status register. - fields: - - name: ISF - description: Interrupt semaphore %s status bit before enable (mask). - bit_offset: 0 + enum: C1ICR_ISC + - name: ISC6 + description: Interrupt semaphore %s clear bit. + bit_offset: 6 bit_size: 1 - array: - len: 32 - stride: 1 - enum: C2ISR_ISF -fieldset/C2MISR: - description: HSEM Masked interrupt status register. - fields: - - name: MISF - description: Masked interrupt semaphore %s status bit after enable (mask). - bit_offset: 0 + enum: C1ICR_ISC + - name: ISC7 + description: Interrupt semaphore %s clear bit. + bit_offset: 7 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC8 + description: Interrupt semaphore %s clear bit. + bit_offset: 8 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC9 + description: Interrupt semaphore %s clear bit. + bit_offset: 9 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC10 + description: Interrupt semaphore %s clear bit. + bit_offset: 10 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC11 + description: Interrupt semaphore %s clear bit. + bit_offset: 11 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC12 + description: Interrupt semaphore %s clear bit. + bit_offset: 12 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC13 + description: Interrupt semaphore %s clear bit. + bit_offset: 13 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC14 + description: Interrupt semaphore %s clear bit. + bit_offset: 14 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC15 + description: Interrupt semaphore %s clear bit. + bit_offset: 15 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC16 + description: Interrupt semaphore %s clear bit. + bit_offset: 16 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC17 + description: Interrupt semaphore %s clear bit. + bit_offset: 17 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC18 + description: Interrupt semaphore %s clear bit. + bit_offset: 18 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC19 + description: Interrupt semaphore %s clear bit. + bit_offset: 19 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC20 + description: Interrupt semaphore %s clear bit. + bit_offset: 20 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC21 + description: Interrupt semaphore %s clear bit. + bit_offset: 21 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC22 + description: Interrupt semaphore %s clear bit. + bit_offset: 22 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC23 + description: Interrupt semaphore %s clear bit. + bit_offset: 23 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC24 + description: Interrupt semaphore %s clear bit. + bit_offset: 24 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC25 + description: Interrupt semaphore %s clear bit. + bit_offset: 25 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC26 + description: Interrupt semaphore %s clear bit. + bit_offset: 26 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC27 + description: Interrupt semaphore %s clear bit. + bit_offset: 27 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC28 + description: Interrupt semaphore %s clear bit. + bit_offset: 28 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC29 + description: Interrupt semaphore %s clear bit. + bit_offset: 29 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC30 + description: Interrupt semaphore %s clear bit. + bit_offset: 30 + bit_size: 1 + enum: C1ICR_ISC + - name: ISC31 + description: Interrupt semaphore %s clear bit. + bit_offset: 31 + bit_size: 1 + enum: C1ICR_ISC +fieldset/C1IER: + description: HSEM Interrupt enable register. + fields: + - name: ISE0 + description: Interrupt semaphore %s enable bit. + bit_offset: 0 + bit_size: 1 + enum: C1IER_ISE + - name: ISE1 + description: Interrupt semaphore %s enable bit. + bit_offset: 1 + bit_size: 1 + enum: C1IER_ISE + - name: ISE2 + description: Interrupt semaphore %s enable bit. + bit_offset: 2 + bit_size: 1 + enum: C1IER_ISE + - name: ISE3 + description: Interrupt semaphore %s enable bit. + bit_offset: 3 + bit_size: 1 + enum: C1IER_ISE + - name: ISE4 + description: Interrupt semaphore %s enable bit. + bit_offset: 4 + bit_size: 1 + enum: C1IER_ISE + - name: ISE5 + description: Interrupt semaphore %s enable bit. + bit_offset: 5 + bit_size: 1 + enum: C1IER_ISE + - name: ISE6 + description: Interrupt semaphore %s enable bit. + bit_offset: 6 + bit_size: 1 + enum: C1IER_ISE + - name: ISE7 + description: Interrupt semaphore %s enable bit. + bit_offset: 7 + bit_size: 1 + enum: C1IER_ISE + - name: ISE8 + description: Interrupt semaphore %s enable bit. + bit_offset: 8 + bit_size: 1 + enum: C1IER_ISE + - name: ISE9 + description: Interrupt semaphore %s enable bit. + bit_offset: 9 + bit_size: 1 + enum: C1IER_ISE + - name: ISE10 + description: Interrupt semaphore %s enable bit. + bit_offset: 10 + bit_size: 1 + enum: C1IER_ISE + - name: ISE11 + description: Interrupt semaphore %s enable bit. + bit_offset: 11 + bit_size: 1 + enum: C1IER_ISE + - name: ISE12 + description: Interrupt semaphore %s enable bit. + bit_offset: 12 + bit_size: 1 + enum: C1IER_ISE + - name: ISE13 + description: Interrupt semaphore %s enable bit. + bit_offset: 13 + bit_size: 1 + enum: C1IER_ISE + - name: ISE14 + description: Interrupt semaphore %s enable bit. + bit_offset: 14 + bit_size: 1 + enum: C1IER_ISE + - name: ISE15 + description: Interrupt semaphore %s enable bit. + bit_offset: 15 + bit_size: 1 + enum: C1IER_ISE + - name: ISE16 + description: Interrupt semaphore %s enable bit. + bit_offset: 16 + bit_size: 1 + enum: C1IER_ISE + - name: ISE17 + description: Interrupt semaphore %s enable bit. + bit_offset: 17 + bit_size: 1 + enum: C1IER_ISE + - name: ISE18 + description: Interrupt semaphore %s enable bit. + bit_offset: 18 + bit_size: 1 + enum: C1IER_ISE + - name: ISE19 + description: Interrupt semaphore %s enable bit. + bit_offset: 19 + bit_size: 1 + enum: C1IER_ISE + - name: ISE20 + description: Interrupt semaphore %s enable bit. + bit_offset: 20 + bit_size: 1 + enum: C1IER_ISE + - name: ISE21 + description: Interrupt semaphore %s enable bit. + bit_offset: 21 + bit_size: 1 + enum: C1IER_ISE + - name: ISE22 + description: Interrupt semaphore %s enable bit. + bit_offset: 22 + bit_size: 1 + enum: C1IER_ISE + - name: ISE23 + description: Interrupt semaphore %s enable bit. + bit_offset: 23 + bit_size: 1 + enum: C1IER_ISE + - name: ISE24 + description: Interrupt semaphore %s enable bit. + bit_offset: 24 + bit_size: 1 + enum: C1IER_ISE + - name: ISE25 + description: Interrupt semaphore %s enable bit. + bit_offset: 25 + bit_size: 1 + enum: C1IER_ISE + - name: ISE26 + description: Interrupt semaphore %s enable bit. + bit_offset: 26 + bit_size: 1 + enum: C1IER_ISE + - name: ISE27 + description: Interrupt semaphore %s enable bit. + bit_offset: 27 + bit_size: 1 + enum: C1IER_ISE + - name: ISE28 + description: Interrupt semaphore %s enable bit. + bit_offset: 28 + bit_size: 1 + enum: C1IER_ISE + - name: ISE29 + description: Interrupt semaphore %s enable bit. + bit_offset: 29 + bit_size: 1 + enum: C1IER_ISE + - name: ISE30 + description: Interrupt semaphore %s enable bit. + bit_offset: 30 + bit_size: 1 + enum: C1IER_ISE + - name: ISE31 + description: Interrupt semaphore %s enable bit. + bit_offset: 31 + bit_size: 1 + enum: C1IER_ISE +fieldset/C1ISR: + description: HSEM Interrupt status register. + fields: + - name: ISF0 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 0 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF1 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 1 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF2 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 2 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF3 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 3 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF4 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 4 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF5 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 5 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF6 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 6 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF7 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 7 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF8 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 8 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF9 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 9 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF10 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 10 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF11 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 11 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF12 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 12 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF13 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 13 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF14 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 14 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF15 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 15 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF16 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 16 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF17 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 17 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF18 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 18 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF19 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 19 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF20 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 20 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF21 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 21 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF22 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 22 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF23 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 23 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF24 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 24 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF25 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 25 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF26 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 26 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF27 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 27 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF28 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 28 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF29 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 29 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF30 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 30 + bit_size: 1 + enum: C1ISR_ISF + - name: ISF31 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 31 + bit_size: 1 + enum: C1ISR_ISF +fieldset/C1MISR: + description: HSEM Masked interrupt status register. + fields: + - name: MISF0 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 0 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF1 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 1 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF2 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 2 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF3 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 3 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF4 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 4 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF5 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 5 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF6 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 6 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF7 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 7 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF8 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 8 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF9 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 9 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF10 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 10 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF11 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 11 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF12 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 12 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF13 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 13 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF14 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 14 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF15 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 15 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF16 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 16 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF17 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 17 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF18 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 18 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF19 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 19 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF20 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 20 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF21 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 21 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF22 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 22 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF23 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 23 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF24 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 24 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF25 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 25 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF26 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 26 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF27 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 27 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF28 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 28 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF29 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 29 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF30 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 30 + bit_size: 1 + enum: C1MISR_MISF + - name: MISF31 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 31 + bit_size: 1 + enum: C1MISR_MISF +fieldset/C2ICR: + description: HSEM Interrupt clear register. + fields: + - name: ISC0 + description: Interrupt semaphore %s clear bit. + bit_offset: 0 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC1 + description: Interrupt semaphore %s clear bit. + bit_offset: 1 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC2 + description: Interrupt semaphore %s clear bit. + bit_offset: 2 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC3 + description: Interrupt semaphore %s clear bit. + bit_offset: 3 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC4 + description: Interrupt semaphore %s clear bit. + bit_offset: 4 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC5 + description: Interrupt semaphore %s clear bit. + bit_offset: 5 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC6 + description: Interrupt semaphore %s clear bit. + bit_offset: 6 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC7 + description: Interrupt semaphore %s clear bit. + bit_offset: 7 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC8 + description: Interrupt semaphore %s clear bit. + bit_offset: 8 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC9 + description: Interrupt semaphore %s clear bit. + bit_offset: 9 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC10 + description: Interrupt semaphore %s clear bit. + bit_offset: 10 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC11 + description: Interrupt semaphore %s clear bit. + bit_offset: 11 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC12 + description: Interrupt semaphore %s clear bit. + bit_offset: 12 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC13 + description: Interrupt semaphore %s clear bit. + bit_offset: 13 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC14 + description: Interrupt semaphore %s clear bit. + bit_offset: 14 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC15 + description: Interrupt semaphore %s clear bit. + bit_offset: 15 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC16 + description: Interrupt semaphore %s clear bit. + bit_offset: 16 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC17 + description: Interrupt semaphore %s clear bit. + bit_offset: 17 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC18 + description: Interrupt semaphore %s clear bit. + bit_offset: 18 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC19 + description: Interrupt semaphore %s clear bit. + bit_offset: 19 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC20 + description: Interrupt semaphore %s clear bit. + bit_offset: 20 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC21 + description: Interrupt semaphore %s clear bit. + bit_offset: 21 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC22 + description: Interrupt semaphore %s clear bit. + bit_offset: 22 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC23 + description: Interrupt semaphore %s clear bit. + bit_offset: 23 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC24 + description: Interrupt semaphore %s clear bit. + bit_offset: 24 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC25 + description: Interrupt semaphore %s clear bit. + bit_offset: 25 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC26 + description: Interrupt semaphore %s clear bit. + bit_offset: 26 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC27 + description: Interrupt semaphore %s clear bit. + bit_offset: 27 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC28 + description: Interrupt semaphore %s clear bit. + bit_offset: 28 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC29 + description: Interrupt semaphore %s clear bit. + bit_offset: 29 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC30 + description: Interrupt semaphore %s clear bit. + bit_offset: 30 + bit_size: 1 + enum: C2ICR_ISC + - name: ISC31 + description: Interrupt semaphore %s clear bit. + bit_offset: 31 + bit_size: 1 + enum: C2ICR_ISC +fieldset/C2IER: + description: HSEM Interrupt enable register. + fields: + - name: ISE0 + description: Interrupt semaphore %s enable bit. + bit_offset: 0 + bit_size: 1 + enum: C2IER_ISE + - name: ISE1 + description: Interrupt semaphore %s enable bit. + bit_offset: 1 + bit_size: 1 + enum: C2IER_ISE + - name: ISE2 + description: Interrupt semaphore %s enable bit. + bit_offset: 2 + bit_size: 1 + enum: C2IER_ISE + - name: ISE3 + description: Interrupt semaphore %s enable bit. + bit_offset: 3 + bit_size: 1 + enum: C2IER_ISE + - name: ISE4 + description: Interrupt semaphore %s enable bit. + bit_offset: 4 + bit_size: 1 + enum: C2IER_ISE + - name: ISE5 + description: Interrupt semaphore %s enable bit. + bit_offset: 5 + bit_size: 1 + enum: C2IER_ISE + - name: ISE6 + description: Interrupt semaphore %s enable bit. + bit_offset: 6 + bit_size: 1 + enum: C2IER_ISE + - name: ISE7 + description: Interrupt semaphore %s enable bit. + bit_offset: 7 + bit_size: 1 + enum: C2IER_ISE + - name: ISE8 + description: Interrupt semaphore %s enable bit. + bit_offset: 8 + bit_size: 1 + enum: C2IER_ISE + - name: ISE9 + description: Interrupt semaphore %s enable bit. + bit_offset: 9 + bit_size: 1 + enum: C2IER_ISE + - name: ISE10 + description: Interrupt semaphore %s enable bit. + bit_offset: 10 + bit_size: 1 + enum: C2IER_ISE + - name: ISE11 + description: Interrupt semaphore %s enable bit. + bit_offset: 11 + bit_size: 1 + enum: C2IER_ISE + - name: ISE12 + description: Interrupt semaphore %s enable bit. + bit_offset: 12 + bit_size: 1 + enum: C2IER_ISE + - name: ISE13 + description: Interrupt semaphore %s enable bit. + bit_offset: 13 + bit_size: 1 + enum: C2IER_ISE + - name: ISE14 + description: Interrupt semaphore %s enable bit. + bit_offset: 14 + bit_size: 1 + enum: C2IER_ISE + - name: ISE15 + description: Interrupt semaphore %s enable bit. + bit_offset: 15 + bit_size: 1 + enum: C2IER_ISE + - name: ISE16 + description: Interrupt semaphore %s enable bit. + bit_offset: 16 + bit_size: 1 + enum: C2IER_ISE + - name: ISE17 + description: Interrupt semaphore %s enable bit. + bit_offset: 17 + bit_size: 1 + enum: C2IER_ISE + - name: ISE18 + description: Interrupt semaphore %s enable bit. + bit_offset: 18 + bit_size: 1 + enum: C2IER_ISE + - name: ISE19 + description: Interrupt semaphore %s enable bit. + bit_offset: 19 + bit_size: 1 + enum: C2IER_ISE + - name: ISE20 + description: Interrupt semaphore %s enable bit. + bit_offset: 20 + bit_size: 1 + enum: C2IER_ISE + - name: ISE21 + description: Interrupt semaphore %s enable bit. + bit_offset: 21 + bit_size: 1 + enum: C2IER_ISE + - name: ISE22 + description: Interrupt semaphore %s enable bit. + bit_offset: 22 + bit_size: 1 + enum: C2IER_ISE + - name: ISE23 + description: Interrupt semaphore %s enable bit. + bit_offset: 23 + bit_size: 1 + enum: C2IER_ISE + - name: ISE24 + description: Interrupt semaphore %s enable bit. + bit_offset: 24 + bit_size: 1 + enum: C2IER_ISE + - name: ISE25 + description: Interrupt semaphore %s enable bit. + bit_offset: 25 + bit_size: 1 + enum: C2IER_ISE + - name: ISE26 + description: Interrupt semaphore %s enable bit. + bit_offset: 26 + bit_size: 1 + enum: C2IER_ISE + - name: ISE27 + description: Interrupt semaphore %s enable bit. + bit_offset: 27 + bit_size: 1 + enum: C2IER_ISE + - name: ISE28 + description: Interrupt semaphore %s enable bit. + bit_offset: 28 + bit_size: 1 + enum: C2IER_ISE + - name: ISE29 + description: Interrupt semaphore %s enable bit. + bit_offset: 29 + bit_size: 1 + enum: C2IER_ISE + - name: ISE30 + description: Interrupt semaphore %s enable bit. + bit_offset: 30 + bit_size: 1 + enum: C2IER_ISE + - name: ISE31 + description: Interrupt semaphore %s enable bit. + bit_offset: 31 + bit_size: 1 + enum: C2IER_ISE +fieldset/C2ISR: + description: HSEM Interrupt status register. + fields: + - name: ISF0 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 0 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF1 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 1 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF2 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 2 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF3 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 3 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF4 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 4 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF5 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 5 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF6 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 6 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF7 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 7 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF8 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 8 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF9 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 9 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF10 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 10 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF11 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 11 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF12 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 12 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF13 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 13 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF14 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 14 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF15 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 15 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF16 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 16 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF17 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 17 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF18 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 18 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF19 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 19 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF20 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 20 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF21 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 21 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF22 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 22 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF23 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 23 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF24 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 24 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF25 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 25 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF26 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 26 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF27 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 27 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF28 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 28 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF29 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 29 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF30 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 30 + bit_size: 1 + enum: C2ISR_ISF + - name: ISF31 + description: Interrupt semaphore %s status bit before enable (mask). + bit_offset: 31 + bit_size: 1 + enum: C2ISR_ISF +fieldset/C2MISR: + description: HSEM Masked interrupt status register. + fields: + - name: MISF0 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 0 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF1 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 1 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF2 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 2 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF3 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 3 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF4 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 4 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF5 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 5 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF6 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 6 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF7 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 7 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF8 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 8 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF9 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 9 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF10 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 10 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF11 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 11 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF12 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 12 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF13 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 13 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF14 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 14 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF15 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 15 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF16 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 16 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF17 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 17 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF18 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 18 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF19 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 19 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF20 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 20 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF21 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 21 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF22 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 22 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF23 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 23 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF24 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 24 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF25 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 25 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF26 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 26 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF27 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 27 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF28 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 28 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF29 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 29 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF30 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 30 + bit_size: 1 + enum: C2MISR_MISF + - name: MISF31 + description: Masked interrupt semaphore %s status bit after enable (mask). + bit_offset: 31 bit_size: 1 - array: - len: 32 - stride: 1 enum: C2MISR_MISF fieldset/CR: description: Semaphore Clear register. diff --git a/base/STM32WB55/RTC.yaml b/head/STM32WB55/RTC.yaml index d8d685c..fe32700 100644 --- a/base/STM32WB55/RTC.yaml +++ b/head/STM32WB55/RTC.yaml @@ -25,13 +25,14 @@ block/RTC: description: wakeup timer register. byte_offset: 20 fieldset: WUTR - - name: ALRMR + - name: ALRMAR description: Alarm %s register. - array: - len: 2 - stride: 4 byte_offset: 28 fieldset: ALRMR + - name: ALRMBR + description: Alarm %s register. + byte_offset: 32 + fieldset: ALRMR - name: WPR description: write protection register. byte_offset: 36 @@ -55,24 +56,98 @@ block/RTC: description: tamper configuration register. byte_offset: 64 fieldset: TAMPCR - - name: ALRMSSR + - name: ALRMASSR description: Alarm %s sub-second register. - array: - len: 2 - stride: 4 byte_offset: 68 fieldset: ALRMSSR + - name: ALRMBSSR + description: Alarm %s sub-second register. + byte_offset: 72 + fieldset: ALRMSSR - name: OR description: option register. byte_offset: 76 fieldset: OR - - name: BKPR + - name: BKP0R description: backup register. - array: - len: 20 - stride: 4 byte_offset: 80 fieldset: BKPR + - name: BKP1R + description: backup register. + byte_offset: 84 + fieldset: BKPR + - name: BKP2R + description: backup register. + byte_offset: 88 + fieldset: BKPR + - name: BKP3R + description: backup register. + byte_offset: 92 + fieldset: BKPR + - name: BKP4R + description: backup register. + byte_offset: 96 + fieldset: BKPR + - name: BKP5R + description: backup register. + byte_offset: 100 + fieldset: BKPR + - name: BKP6R + description: backup register. + byte_offset: 104 + fieldset: BKPR + - name: BKP7R + description: backup register. + byte_offset: 108 + fieldset: BKPR + - name: BKP8R + description: backup register. + byte_offset: 112 + fieldset: BKPR + - name: BKP9R + description: backup register. + byte_offset: 116 + fieldset: BKPR + - name: BKP10R + description: backup register. + byte_offset: 120 + fieldset: BKPR + - name: BKP11R + description: backup register. + byte_offset: 124 + fieldset: BKPR + - name: BKP12R + description: backup register. + byte_offset: 128 + fieldset: BKPR + - name: BKP13R + description: backup register. + byte_offset: 132 + fieldset: BKPR + - name: BKP14R + description: backup register. + byte_offset: 136 + fieldset: BKPR + - name: BKP15R + description: backup register. + byte_offset: 140 + fieldset: BKPR + - name: BKP16R + description: backup register. + byte_offset: 144 + fieldset: BKPR + - name: BKP17R + description: backup register. + byte_offset: 148 + fieldset: BKPR + - name: BKP18R + description: backup register. + byte_offset: 152 + fieldset: BKPR + - name: BKP19R + description: backup register. + byte_offset: 156 + fieldset: BKPR fieldset/ALRMR: description: Alarm %s register. fields: @@ -206,13 +281,15 @@ fieldset/CR: bit_offset: 6 bit_size: 1 enum: FMT - - name: ALRE + - name: ALRAE description: Alarm %s enable. bit_offset: 8 bit_size: 1 - array: - len: 2 - stride: 1 + enum: ALRE + - name: ALRBE + description: Alarm %s enable. + bit_offset: 9 + bit_size: 1 enum: ALRE - name: WUTE description: Wakeup timer enable. @@ -224,13 +301,15 @@ fieldset/CR: bit_offset: 11 bit_size: 1 enum: TSE - - name: ALRIE + - name: ALRAIE description: Alarm %s interrupt enable. bit_offset: 12 bit_size: 1 - array: - len: 2 - stride: 1 + enum: ALRIE + - name: ALRBIE + description: Alarm %s interrupt enable. + bit_offset: 13 + bit_size: 1 enum: ALRIE - name: WUTIE description: Wakeup timer interrupt enable. @@ -316,13 +395,15 @@ fieldset/DR: fieldset/ISR: description: initialization and status register. fields: - - name: ALRWF + - name: ALRAWF description: Alarm %s write flag. bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 + enum: ALRWF + - name: ALRBWF + description: Alarm %s write flag. + bit_offset: 1 + bit_size: 1 enum: ALRWF - name: WUTWF description: Wakeup timer write flag. @@ -354,13 +435,15 @@ fieldset/ISR: bit_offset: 7 bit_size: 1 enum: INIT - - name: ALRF + - name: ALRAF description: Alarm %s flag. bit_offset: 8 bit_size: 1 - array: - len: 2 - stride: 1 + enum: ALRF + - name: ALRBF + description: Alarm %s flag. + bit_offset: 9 + bit_size: 1 enum: ALRF - name: WUTF description: Wakeup timer flag. diff --git a/base/STM32WB55/SAI1.yaml b/head/STM32WB55/SAI1.yaml index 06044f6..e05abd1 100644 --- a/base/STM32WB55/SAI1.yaml +++ b/head/STM32WB55/SAI1.yaml @@ -1,50 +1,88 @@ -block/CH: +block/CHA: description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR. items: - name: CR1 description: AConfiguration register 1. byte_offset: 0 - fieldset: CR1 + fieldset: CHA_CR1 - name: CR2 description: AConfiguration register 2. byte_offset: 4 - fieldset: CR2 + fieldset: CHA_CR2 - name: FRCR description: AFRCR. byte_offset: 8 - fieldset: FRCR + fieldset: CHA_FRCR - name: SLOTR description: ASlot register. byte_offset: 12 - fieldset: SLOTR + fieldset: CHA_SLOTR - name: IM description: AInterrupt mask register2. byte_offset: 16 - fieldset: IM + fieldset: CHA_IM - name: SR description: AStatus register. byte_offset: 20 access: Read - fieldset: SR + fieldset: CHA_SR - name: CLRFR description: AClear flag register. byte_offset: 24 access: Write - fieldset: CLRFR + fieldset: CHA_CLRFR - name: DR description: AData register. byte_offset: 28 - fieldset: DR + fieldset: CHA_DR +block/CHB: + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR. + items: + - name: CR1 + description: AConfiguration register 1. + byte_offset: 0 + fieldset: CHB_CR1 + - name: CR2 + description: AConfiguration register 2. + byte_offset: 4 + fieldset: CHB_CR2 + - name: FRCR + description: AFRCR. + byte_offset: 8 + fieldset: CHB_FRCR + - name: SLOTR + description: ASlot register. + byte_offset: 12 + fieldset: CHB_SLOTR + - name: IM + description: AInterrupt mask register2. + byte_offset: 16 + fieldset: CHB_IM + - name: SR + description: AStatus register. + byte_offset: 20 + access: Read + fieldset: CHB_SR + - name: CLRFR + description: AClear flag register. + byte_offset: 24 + access: Write + fieldset: CHB_CLRFR + - name: DR + description: AData register. + byte_offset: 28 + fieldset: CHB_DR block/SAI1: description: Serial audio interface. items: - - name: CH + - name: CHA description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR. - array: - len: 2 - stride: 32 byte_offset: 4 - block: CH + block: CHA + - name: CHB + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR. + byte_offset: 36 + block: CHB - name: PDMCR description: PDM control register. byte_offset: 68 @@ -53,97 +91,97 @@ block/SAI1: description: PDM delay register. byte_offset: 72 fieldset: PDMDLY -fieldset/CLRFR: +fieldset/CHA_CLRFR: description: AClear flag register. fields: - name: COVRUDR description: Clear overrun / underrun. bit_offset: 0 bit_size: 1 - enum: COVRUDR + enum: CHA_CLRFR_COVRUDR - name: CMUTEDET description: Mute detection flag. bit_offset: 1 bit_size: 1 - enum: CMUTEDET + enum: CHA_CLRFR_CMUTEDET - name: CWCKCFG description: Clear wrong clock configuration flag. bit_offset: 2 bit_size: 1 - enum: CWCKCFG + enum: CHA_CLRFR_CWCKCFG - name: CCNRDY description: Clear codec not ready flag. bit_offset: 4 bit_size: 1 - enum: CCNRDY + enum: CHA_CLRFR_CCNRDY - name: CAFSDET description: Clear anticipated frame synchronization detection flag. bit_offset: 5 bit_size: 1 - enum: CAFSDET + enum: CHA_CLRFR_CAFSDET - name: CLFSDET description: Clear late frame synchronization detection flag. bit_offset: 6 bit_size: 1 - enum: CLFSDET -fieldset/CR1: + enum: CHA_CLRFR_CLFSDET +fieldset/CHA_CR1: description: AConfiguration register 1. fields: - name: MODE description: Audio block mode. bit_offset: 0 bit_size: 2 - enum: MODE + enum: CHA_CR1_MODE - name: PRTCFG description: Protocol configuration. bit_offset: 2 bit_size: 2 - enum: PRTCFG + enum: CHA_CR1_PRTCFG - name: DS description: Data size. bit_offset: 5 bit_size: 3 - enum: DS + enum: CHA_CR1_DS - name: LSBFIRST description: Least significant bit first. bit_offset: 8 bit_size: 1 - enum: LSBFIRST + enum: CHA_CR1_LSBFIRST - name: CKSTR description: Clock strobing edge. bit_offset: 9 bit_size: 1 - enum: CKSTR + enum: CHA_CR1_CKSTR - name: SYNCEN description: Synchronization enable. bit_offset: 10 bit_size: 2 - enum: SYNCEN + enum: CHA_CR1_SYNCEN - name: MONO description: Mono mode. bit_offset: 12 bit_size: 1 - enum: MONO + enum: CHA_CR1_MONO - name: OUTDRIV description: Output drive. bit_offset: 13 bit_size: 1 - enum: OUTDRIV + enum: CHA_CR1_OUTDRIV - name: SAIEN description: Audio block B enable. bit_offset: 16 bit_size: 1 - enum: SAIEN + enum: CHA_CR1_SAIEN - name: DMAEN description: DMA enable. bit_offset: 17 bit_size: 1 - enum: DMAEN + enum: CHA_CR1_DMAEN - name: NODIV description: No divider. bit_offset: 19 bit_size: 1 - enum: NODIV + enum: CHA_CR1_NODIV - name: MCKDIV description: Master clock divider. bit_offset: 20 @@ -156,19 +194,19 @@ fieldset/CR1: description: Master clock generation enable. bit_offset: 27 bit_size: 1 -fieldset/CR2: +fieldset/CHA_CR2: description: AConfiguration register 2. fields: - name: FTH description: FIFO threshold. bit_offset: 0 bit_size: 3 - enum: FTH + enum: CHA_CR2_FTH - name: FFLUSH description: FIFO flush. bit_offset: 3 bit_size: 1 - enum: FFLUSH + enum: CHA_CR2_FFLUSH - name: TRIS description: Tristate management on data line. bit_offset: 4 @@ -177,12 +215,12 @@ fieldset/CR2: description: Mute. bit_offset: 5 bit_size: 1 - enum: MUTE + enum: CHA_CR2_MUTE - name: MUTEVAL description: Mute value. bit_offset: 6 bit_size: 1 - enum: MUTEVAL + enum: CHA_CR2_MUTEVAL - name: MUTECNT description: Mute counter. bit_offset: 7 @@ -191,20 +229,20 @@ fieldset/CR2: description: Complement bit. bit_offset: 13 bit_size: 1 - enum: CPL + enum: CHA_CR2_CPL - name: COMP description: Companding mode. bit_offset: 14 bit_size: 2 - enum: COMP -fieldset/DR: + enum: CHA_CR2_COMP +fieldset/CHA_DR: description: AData register. fields: - name: DATA description: Data. bit_offset: 0 bit_size: 32 -fieldset/FRCR: +fieldset/CHA_FRCR: description: AFRCR. fields: - name: FRL @@ -223,86 +261,51 @@ fieldset/FRCR: description: Frame synchronization polarity. bit_offset: 17 bit_size: 1 - enum: FSPOL + enum: CHA_FRCR_FSPOL - name: FSOFF description: Frame synchronization offset. bit_offset: 18 bit_size: 1 - enum: FSOFF -fieldset/IM: + enum: CHA_FRCR_FSOFF +fieldset/CHA_IM: description: AInterrupt mask register2. fields: - name: OVRUDRIE description: Overrun/underrun interrupt enable. bit_offset: 0 bit_size: 1 - enum: OVRUDRIE + enum: CHA_IM_OVRUDRIE - name: MUTEDETIE description: Mute detection interrupt enable. bit_offset: 1 bit_size: 1 - enum: MUTEDETIE + enum: CHA_IM_MUTEDETIE - name: WCKCFGIE description: Wrong clock configuration interrupt enable. bit_offset: 2 bit_size: 1 - enum: WCKCFGIE + enum: CHA_IM_WCKCFGIE - name: FREQIE description: FIFO request interrupt enable. bit_offset: 3 bit_size: 1 - enum: FREQIE + enum: CHA_IM_FREQIE - name: CNRDYIE description: Codec not ready interrupt enable. bit_offset: 4 bit_size: 1 - enum: CNRDYIE + enum: CHA_IM_CNRDYIE - name: AFSDETIE description: Anticipated frame synchronization detection interrupt enable. bit_offset: 5 bit_size: 1 - enum: AFSDETIE + enum: CHA_IM_AFSDETIE - name: LFSDETIE description: Late frame synchronization detection interrupt enable. bit_offset: 6 bit_size: 1 - enum: LFSDETIE -fieldset/PDMCR: - description: PDM control register. - fields: - - name: PDMEN - description: PDM enable. - bit_offset: 0 - bit_size: 1 - - name: MICNBR - description: Number of microphones. - bit_offset: 4 - bit_size: 2 - - name: CKEN - description: Clock enable of bitstream clock number %s. - bit_offset: 8 - bit_size: 1 - array: - len: 4 - stride: 1 -fieldset/PDMDLY: - description: PDM delay register. - fields: - - name: DLYML - description: Delay line adjust for first microphone of pair %s. - bit_offset: 0 - bit_size: 3 - array: - len: 4 - stride: 8 - - name: DLYMR - description: Delay line adjust for second microphone of pair %s. - bit_offset: 4 - bit_size: 3 - array: - len: 4 - stride: 8 -fieldset/SLOTR: + enum: CHA_IM_LFSDETIE +fieldset/CHA_SLOTR: description: ASlot register. fields: - name: FBOFF @@ -313,7 +316,7 @@ fieldset/SLOTR: description: Slot size. bit_offset: 6 bit_size: 2 - enum: SLOTSZ + enum: CHA_SLOTR_SLOTSZ - name: NBSLOT description: Number of slots in an audio frame. bit_offset: 8 @@ -322,285 +325,877 @@ fieldset/SLOTR: description: Slot enable. bit_offset: 16 bit_size: 16 - enum: SLOTEN -fieldset/SR: + enum: CHA_SLOTR_SLOTEN +fieldset/CHA_SR: description: AStatus register. fields: - name: OVRUDR description: Overrun / underrun. bit_offset: 0 bit_size: 1 - enum: OVRUDR + enum: CHA_SR_OVRUDR - name: MUTEDET description: Mute detection. bit_offset: 1 bit_size: 1 - enum: MUTEDET + enum: CHA_SR_MUTEDET - name: WCKCFG description: Wrong clock configuration flag. This bit is read only. bit_offset: 2 bit_size: 1 - enum: WCKCFG + enum: CHA_SR_WCKCFG - name: FREQ description: FIFO request. bit_offset: 3 bit_size: 1 - enum: FREQ + enum: CHA_SR_FREQ - name: CNRDY description: Codec not ready. bit_offset: 4 bit_size: 1 - enum: CNRDY + enum: CHA_SR_CNRDY - name: AFSDET description: Anticipated frame synchronization detection. bit_offset: 5 bit_size: 1 - enum: AFSDET + enum: CHA_SR_AFSDET - name: LFSDET description: Late frame synchronization detection. bit_offset: 6 bit_size: 1 - enum: LFSDET + enum: CHA_SR_LFSDET - name: FLVL description: FIFO level threshold. bit_offset: 16 bit_size: 3 - enum: FLVL -enum/AFSDET: - bit_size: 1 - variants: - - name: NoError - description: No error. - value: 0 - - name: EarlySync - description: Frame synchronization signal is detected earlier than expected. - value: 1 -enum/AFSDETIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is disabled. - value: 0 - - name: Enabled - description: Interrupt is enabled. - value: 1 -enum/CAFSDET: - bit_size: 1 - variants: - - name: Clear - description: Clears the AFSDET flag. - value: 1 -enum/CCNRDY: - bit_size: 1 - variants: - - name: Clear - description: Clears the CNRDY flag. - value: 1 -enum/CKSTR: - bit_size: 1 - variants: - - name: FallingEdge - description: Data strobing edge is falling edge of SCK. - value: 0 - - name: RisingEdge - description: Data strobing edge is rising edge of SCK. - value: 1 -enum/CLFSDET: - bit_size: 1 - variants: - - name: Clear - description: Clears the LFSDET flag. - value: 1 -enum/CMUTEDET: - bit_size: 1 - variants: - - name: Clear - description: Clears the MUTEDET flag. - value: 1 -enum/CNRDY: - bit_size: 1 - variants: - - name: Ready - description: External AC’97 Codec is ready. - value: 0 - - name: NotReady - description: External AC’97 Codec is not ready. - value: 1 -enum/CNRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is disabled. - value: 0 - - name: Enabled - description: Interrupt is enabled. - value: 1 -enum/COMP: - bit_size: 2 - variants: - - name: NoCompanding - description: No companding algorithm. - value: 0 - - name: MuLaw - description: μ-Law algorithm. - value: 2 - - name: ALaw - description: A-Law algorithm. - value: 3 -enum/COVRUDR: - bit_size: 1 - variants: - - name: Clear - description: Clears the OVRUDR flag. - value: 1 -enum/CPL: - bit_size: 1 - variants: - - name: OnesComplement - description: 1’s complement representation. - value: 0 - - name: TwosComplement - description: 2’s complement representation. - value: 1 -enum/CWCKCFG: - bit_size: 1 - variants: - - name: Clear - description: Clears the WCKCFG flag. - value: 1 -enum/DMAEN: - bit_size: 1 - variants: - - name: Disabled - description: DMA disabled. - value: 0 - - name: Enabled - description: DMA enabled. - value: 1 -enum/DS: - bit_size: 3 - variants: - - name: Bit8 - description: 8 bits. - value: 2 - - name: Bit10 - description: 10 bits. - value: 3 - - name: Bit16 - description: 16 bits. - value: 4 - - name: Bit20 - description: 20 bits. - value: 5 - - name: Bit24 - description: 24 bits. - value: 6 - - name: Bit32 - description: 32 bits. - value: 7 -enum/FFLUSH: - bit_size: 1 - variants: - - name: NoFlush - description: No FIFO flush. - value: 0 - - name: Flush - description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. - value: 1 -enum/FLVL: - bit_size: 3 - variants: - - name: Empty - description: FIFO empty. - value: 0 - - name: Quarter1 - description: FIFO <= 1⁄4 but not empty. - value: 1 - - name: Quarter2 - description: 1⁄4 < FIFO <= 1⁄2. - value: 2 - - name: Quarter3 - description: 1⁄2 < FIFO <= 3⁄4. - value: 3 - - name: Quarter4 - description: 3⁄4 < FIFO but not full. - value: 4 - - name: Full - description: FIFO full. - value: 5 -enum/FREQ: - bit_size: 1 - variants: - - name: NoRequest - description: No FIFO request. - value: 0 - - name: Request - description: FIFO request to read or to write the SAI_xDR. - value: 1 -enum/FREQIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is disabled. - value: 0 - - name: Enabled - description: Interrupt is enabled. - value: 1 -enum/FSOFF: - bit_size: 1 - variants: - - name: OnFirst - description: FS is asserted on the first bit of the slot 0. - value: 0 - - name: BeforeFirst - description: FS is asserted one bit before the first bit of the slot 0. - value: 1 -enum/FSPOL: - bit_size: 1 - variants: - - name: FallingEdge - description: FS is active low (falling edge). - value: 0 - - name: RisingEdge - description: FS is active high (rising edge). - value: 1 -enum/FTH: - bit_size: 3 - variants: - - name: Empty - description: FIFO empty. - value: 0 - - name: Quarter1 - description: 1⁄4 FIFO. - value: 1 - - name: Quarter2 - description: 1⁄2 FIFO. - value: 2 - - name: Quarter3 - description: 3⁄4 FIFO. - value: 3 - - name: Full - description: FIFO full. - value: 4 -enum/LFSDET: - bit_size: 1 - variants: - - name: NoError - description: No error. - value: 0 - - name: NoSync - description: Frame synchronization signal is not present at the right time. - value: 1 -enum/LFSDETIE: - bit_size: 1 - variants: + enum: CHA_SR_FLVL +fieldset/CHB_CLRFR: + description: AClear flag register. + fields: + - name: COVRUDR + description: Clear overrun / underrun. + bit_offset: 0 + bit_size: 1 + enum: CHB_CLRFR_COVRUDR + - name: CMUTEDET + description: Mute detection flag. + bit_offset: 1 + bit_size: 1 + enum: CHB_CLRFR_CMUTEDET + - name: CWCKCFG + description: Clear wrong clock configuration flag. + bit_offset: 2 + bit_size: 1 + enum: CHB_CLRFR_CWCKCFG + - name: CCNRDY + description: Clear codec not ready flag. + bit_offset: 4 + bit_size: 1 + enum: CHB_CLRFR_CCNRDY + - name: CAFSDET + description: Clear anticipated frame synchronization detection flag. + bit_offset: 5 + bit_size: 1 + enum: CHB_CLRFR_CAFSDET + - name: CLFSDET + description: Clear late frame synchronization detection flag. + bit_offset: 6 + bit_size: 1 + enum: CHB_CLRFR_CLFSDET +fieldset/CHB_CR1: + description: AConfiguration register 1. + fields: + - name: MODE + description: Audio block mode. + bit_offset: 0 + bit_size: 2 + enum: CHB_CR1_MODE + - name: PRTCFG + description: Protocol configuration. + bit_offset: 2 + bit_size: 2 + enum: CHB_CR1_PRTCFG + - name: DS + description: Data size. + bit_offset: 5 + bit_size: 3 + enum: CHB_CR1_DS + - name: LSBFIRST + description: Least significant bit first. + bit_offset: 8 + bit_size: 1 + enum: CHB_CR1_LSBFIRST + - name: CKSTR + description: Clock strobing edge. + bit_offset: 9 + bit_size: 1 + enum: CHB_CR1_CKSTR + - name: SYNCEN + description: Synchronization enable. + bit_offset: 10 + bit_size: 2 + enum: CHB_CR1_SYNCEN + - name: MONO + description: Mono mode. + bit_offset: 12 + bit_size: 1 + enum: CHB_CR1_MONO + - name: OUTDRIV + description: Output drive. + bit_offset: 13 + bit_size: 1 + enum: CHB_CR1_OUTDRIV + - name: SAIEN + description: Audio block B enable. + bit_offset: 16 + bit_size: 1 + enum: CHB_CR1_SAIEN + - name: DMAEN + description: DMA enable. + bit_offset: 17 + bit_size: 1 + enum: CHB_CR1_DMAEN + - name: NODIV + description: No divider. + bit_offset: 19 + bit_size: 1 + enum: CHB_CR1_NODIV + - name: MCKDIV + description: Master clock divider. + bit_offset: 20 + bit_size: 6 + - name: OSR + description: Oversampling ratio for master clock. + bit_offset: 26 + bit_size: 1 + - name: MCKEN + description: Master clock generation enable. + bit_offset: 27 + bit_size: 1 +fieldset/CHB_CR2: + description: AConfiguration register 2. + fields: + - name: FTH + description: FIFO threshold. + bit_offset: 0 + bit_size: 3 + enum: CHB_CR2_FTH + - name: FFLUSH + description: FIFO flush. + bit_offset: 3 + bit_size: 1 + enum: CHB_CR2_FFLUSH + - name: TRIS + description: Tristate management on data line. + bit_offset: 4 + bit_size: 1 + - name: MUTE + description: Mute. + bit_offset: 5 + bit_size: 1 + enum: CHB_CR2_MUTE + - name: MUTEVAL + description: Mute value. + bit_offset: 6 + bit_size: 1 + enum: CHB_CR2_MUTEVAL + - name: MUTECNT + description: Mute counter. + bit_offset: 7 + bit_size: 6 + - name: CPL + description: Complement bit. + bit_offset: 13 + bit_size: 1 + enum: CHB_CR2_CPL + - name: COMP + description: Companding mode. + bit_offset: 14 + bit_size: 2 + enum: CHB_CR2_COMP +fieldset/CHB_DR: + description: AData register. + fields: + - name: DATA + description: Data. + bit_offset: 0 + bit_size: 32 +fieldset/CHB_FRCR: + description: AFRCR. + fields: + - name: FRL + description: Frame length. + bit_offset: 0 + bit_size: 8 + - name: FSALL + description: Frame synchronization active level length. + bit_offset: 8 + bit_size: 7 + - name: FSDEF + description: Frame synchronization definition. + bit_offset: 16 + bit_size: 1 + - name: FSPOL + description: Frame synchronization polarity. + bit_offset: 17 + bit_size: 1 + enum: CHB_FRCR_FSPOL + - name: FSOFF + description: Frame synchronization offset. + bit_offset: 18 + bit_size: 1 + enum: CHB_FRCR_FSOFF +fieldset/CHB_IM: + description: AInterrupt mask register2. + fields: + - name: OVRUDRIE + description: Overrun/underrun interrupt enable. + bit_offset: 0 + bit_size: 1 + enum: CHB_IM_OVRUDRIE + - name: MUTEDETIE + description: Mute detection interrupt enable. + bit_offset: 1 + bit_size: 1 + enum: CHB_IM_MUTEDETIE + - name: WCKCFGIE + description: Wrong clock configuration interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CHB_IM_WCKCFGIE + - name: FREQIE + description: FIFO request interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CHB_IM_FREQIE + - name: CNRDYIE + description: Codec not ready interrupt enable. + bit_offset: 4 + bit_size: 1 + enum: CHB_IM_CNRDYIE + - name: AFSDETIE + description: Anticipated frame synchronization detection interrupt enable. + bit_offset: 5 + bit_size: 1 + enum: CHB_IM_AFSDETIE + - name: LFSDETIE + description: Late frame synchronization detection interrupt enable. + bit_offset: 6 + bit_size: 1 + enum: CHB_IM_LFSDETIE +fieldset/CHB_SLOTR: + description: ASlot register. + fields: + - name: FBOFF + description: First bit offset. + bit_offset: 0 + bit_size: 5 + - name: SLOTSZ + description: Slot size. + bit_offset: 6 + bit_size: 2 + enum: CHB_SLOTR_SLOTSZ + - name: NBSLOT + description: Number of slots in an audio frame. + bit_offset: 8 + bit_size: 4 + - name: SLOTEN + description: Slot enable. + bit_offset: 16 + bit_size: 16 + enum: CHB_SLOTR_SLOTEN +fieldset/CHB_SR: + description: AStatus register. + fields: + - name: OVRUDR + description: Overrun / underrun. + bit_offset: 0 + bit_size: 1 + enum: CHB_SR_OVRUDR + - name: MUTEDET + description: Mute detection. + bit_offset: 1 + bit_size: 1 + enum: CHB_SR_MUTEDET + - name: WCKCFG + description: Wrong clock configuration flag. This bit is read only. + bit_offset: 2 + bit_size: 1 + enum: CHB_SR_WCKCFG + - name: FREQ + description: FIFO request. + bit_offset: 3 + bit_size: 1 + enum: CHB_SR_FREQ + - name: CNRDY + description: Codec not ready. + bit_offset: 4 + bit_size: 1 + enum: CHB_SR_CNRDY + - name: AFSDET + description: Anticipated frame synchronization detection. + bit_offset: 5 + bit_size: 1 + enum: CHB_SR_AFSDET + - name: LFSDET + description: Late frame synchronization detection. + bit_offset: 6 + bit_size: 1 + enum: CHB_SR_LFSDET + - name: FLVL + description: FIFO level threshold. + bit_offset: 16 + bit_size: 3 + enum: CHB_SR_FLVL +fieldset/PDMCR: + description: PDM control register. + fields: + - name: PDMEN + description: PDM enable. + bit_offset: 0 + bit_size: 1 + - name: MICNBR + description: Number of microphones. + bit_offset: 4 + bit_size: 2 + - name: CKEN1 + description: Clock enable of bitstream clock number %s. + bit_offset: 8 + bit_size: 1 + - name: CKEN2 + description: Clock enable of bitstream clock number %s. + bit_offset: 9 + bit_size: 1 + - name: CKEN3 + description: Clock enable of bitstream clock number %s. + bit_offset: 10 + bit_size: 1 + - name: CKEN4 + description: Clock enable of bitstream clock number %s. + bit_offset: 11 + bit_size: 1 +fieldset/PDMDLY: + description: PDM delay register. + fields: + - name: DLYM1L + description: Delay line adjust for first microphone of pair %s. + bit_offset: 0 + bit_size: 3 + - name: DLYM1R + description: Delay line adjust for second microphone of pair %s. + bit_offset: 4 + bit_size: 3 + - name: DLYM2L + description: Delay line adjust for first microphone of pair %s. + bit_offset: 8 + bit_size: 3 + - name: DLYM2R + description: Delay line adjust for second microphone of pair %s. + bit_offset: 12 + bit_size: 3 + - name: DLYM3L + description: Delay line adjust for first microphone of pair %s. + bit_offset: 16 + bit_size: 3 + - name: DLYM3R + description: Delay line adjust for second microphone of pair %s. + bit_offset: 20 + bit_size: 3 + - name: DLYM4L + description: Delay line adjust for first microphone of pair %s. + bit_offset: 24 + bit_size: 3 + - name: DLYM4R + description: Delay line adjust for second microphone of pair %s. + bit_offset: 28 + bit_size: 3 +enum/CHA_CLRFR_CAFSDET: + bit_size: 1 + variants: + - name: Clear + description: Clears the AFSDET flag. + value: 1 +enum/CHA_CLRFR_CCNRDY: + bit_size: 1 + variants: + - name: Clear + description: Clears the CNRDY flag. + value: 1 +enum/CHA_CLRFR_CLFSDET: + bit_size: 1 + variants: + - name: Clear + description: Clears the LFSDET flag. + value: 1 +enum/CHA_CLRFR_CMUTEDET: + bit_size: 1 + variants: + - name: Clear + description: Clears the MUTEDET flag. + value: 1 +enum/CHA_CLRFR_COVRUDR: + bit_size: 1 + variants: + - name: Clear + description: Clears the OVRUDR flag. + value: 1 +enum/CHA_CLRFR_CWCKCFG: + bit_size: 1 + variants: + - name: Clear + description: Clears the WCKCFG flag. + value: 1 +enum/CHA_CR1_CKSTR: + bit_size: 1 + variants: + - name: FallingEdge + description: Data strobing edge is falling edge of SCK. + value: 0 + - name: RisingEdge + description: Data strobing edge is rising edge of SCK. + value: 1 +enum/CHA_CR1_DMAEN: + bit_size: 1 + variants: + - name: Disabled + description: DMA disabled. + value: 0 + - name: Enabled + description: DMA enabled. + value: 1 +enum/CHA_CR1_DS: + bit_size: 3 + variants: + - name: Bit8 + description: 8 bits. + value: 2 + - name: Bit10 + description: 10 bits. + value: 3 + - name: Bit16 + description: 16 bits. + value: 4 + - name: Bit20 + description: 20 bits. + value: 5 + - name: Bit24 + description: 24 bits. + value: 6 + - name: Bit32 + description: 32 bits. + value: 7 +enum/CHA_CR1_LSBFIRST: + bit_size: 1 + variants: + - name: MsbFirst + description: Data are transferred with MSB first. + value: 0 + - name: LsbFirst + description: Data are transferred with LSB first. + value: 1 +enum/CHA_CR1_MODE: + bit_size: 2 + variants: + - name: MasterTx + description: Master transmitter. + value: 0 + - name: MasterRx + description: Master receiver. + value: 1 + - name: SlaveTx + description: Slave transmitter. + value: 2 + - name: SlaveRx + description: Slave receiver. + value: 3 +enum/CHA_CR1_MONO: + bit_size: 1 + variants: + - name: Stereo + description: Stereo mode. + value: 0 + - name: Mono + description: Mono mode. + value: 1 +enum/CHA_CR1_NODIV: + bit_size: 1 + variants: + - name: MasterClock + description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value. + value: 0 + - name: NoDiv + description: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + value: 1 +enum/CHA_CR1_OUTDRIV: + bit_size: 1 + variants: + - name: OnStart + description: Audio block output driven when SAIEN is set. + value: 0 + - name: Immediately + description: Audio block output driven immediately after the setting of this bit. + value: 1 +enum/CHA_CR1_PRTCFG: + bit_size: 2 + variants: + - name: Free + description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol. + value: 0 + - name: Spdif + description: SPDIF protocol. + value: 1 + - name: Ac97 + description: AC’97 protocol. + value: 2 +enum/CHA_CR1_SAIEN: + bit_size: 1 + variants: + - name: Disabled + description: SAI audio block disabled. + value: 0 + - name: Enabled + description: SAI audio block enabled. + value: 1 +enum/CHA_CR1_SYNCEN: + bit_size: 2 + variants: + - name: Asynchronous + description: audio sub-block in asynchronous mode. + value: 0 + - name: Internal + description: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode. + value: 1 + - name: External + description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode. + value: 2 +enum/CHA_CR2_COMP: + bit_size: 2 + variants: + - name: NoCompanding + description: No companding algorithm. + value: 0 + - name: MuLaw + description: μ-Law algorithm. + value: 2 + - name: ALaw + description: A-Law algorithm. + value: 3 +enum/CHA_CR2_CPL: + bit_size: 1 + variants: + - name: OnesComplement + description: 1’s complement representation. + value: 0 + - name: TwosComplement + description: 2’s complement representation. + value: 1 +enum/CHA_CR2_FFLUSH: + bit_size: 1 + variants: + - name: NoFlush + description: No FIFO flush. + value: 0 + - name: Flush + description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. + value: 1 +enum/CHA_CR2_FTH: + bit_size: 3 + variants: + - name: Empty + description: FIFO empty. + value: 0 + - name: Quarter1 + description: 1⁄4 FIFO. + value: 1 + - name: Quarter2 + description: 1⁄2 FIFO. + value: 2 + - name: Quarter3 + description: 3⁄4 FIFO. + value: 3 + - name: Full + description: FIFO full. + value: 4 +enum/CHA_CR2_MUTE: + bit_size: 1 + variants: + - name: Disabled + description: No mute mode. + value: 0 + - name: Enabled + description: Mute mode enabled. + value: 1 +enum/CHA_CR2_MUTEVAL: + bit_size: 1 + variants: + - name: SendZero + description: Bit value 0 is sent during the mute mode. + value: 0 + - name: SendLast + description: Last values are sent during the mute mode. + value: 1 +enum/CHA_FRCR_FSOFF: + bit_size: 1 + variants: + - name: OnFirst + description: FS is asserted on the first bit of the slot 0. + value: 0 + - name: BeforeFirst + description: FS is asserted one bit before the first bit of the slot 0. + value: 1 +enum/CHA_FRCR_FSPOL: + bit_size: 1 + variants: + - name: FallingEdge + description: FS is active low (falling edge). + value: 0 + - name: RisingEdge + description: FS is active high (rising edge). + value: 1 +enum/CHA_IM_AFSDETIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled. + value: 0 + - name: Enabled + description: Interrupt is enabled. + value: 1 +enum/CHA_IM_CNRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled. + value: 0 + - name: Enabled + description: Interrupt is enabled. + value: 1 +enum/CHA_IM_FREQIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled. + value: 0 + - name: Enabled + description: Interrupt is enabled. + value: 1 +enum/CHA_IM_LFSDETIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled. + value: 0 + - name: Enabled + description: Interrupt is enabled. + value: 1 +enum/CHA_IM_MUTEDETIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled. + value: 0 + - name: Enabled + description: Interrupt is enabled. + value: 1 +enum/CHA_IM_OVRUDRIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled. + value: 0 + - name: Enabled + description: Interrupt is enabled. + value: 1 +enum/CHA_IM_WCKCFGIE: + bit_size: 1 + variants: - name: Disabled description: Interrupt is disabled. value: 0 - name: Enabled - description: Interrupt is enabled. + description: Interrupt is enabled. + value: 1 +enum/CHA_SLOTR_SLOTEN: + bit_size: 16 + variants: + - name: Inactive + description: Inactive slot. + value: 0 + - name: Active + description: Active slot. + value: 1 +enum/CHA_SLOTR_SLOTSZ: + bit_size: 2 + variants: + - name: DataSize + description: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register). + value: 0 + - name: Bit16 + description: 16-bit. + value: 1 + - name: Bit32 + description: 32-bit. + value: 2 +enum/CHA_SR_AFSDET: + bit_size: 1 + variants: + - name: NoError + description: No error. + value: 0 + - name: EarlySync + description: Frame synchronization signal is detected earlier than expected. + value: 1 +enum/CHA_SR_CNRDY: + bit_size: 1 + variants: + - name: Ready + description: External AC’97 Codec is ready. + value: 0 + - name: NotReady + description: External AC’97 Codec is not ready. + value: 1 +enum/CHA_SR_FLVL: + bit_size: 3 + variants: + - name: Empty + description: FIFO empty. + value: 0 + - name: Quarter1 + description: FIFO <= 1⁄4 but not empty. + value: 1 + - name: Quarter2 + description: 1⁄4 < FIFO <= 1⁄2. + value: 2 + - name: Quarter3 + description: 1⁄2 < FIFO <= 3⁄4. + value: 3 + - name: Quarter4 + description: 3⁄4 < FIFO but not full. + value: 4 + - name: Full + description: FIFO full. + value: 5 +enum/CHA_SR_FREQ: + bit_size: 1 + variants: + - name: NoRequest + description: No FIFO request. + value: 0 + - name: Request + description: FIFO request to read or to write the SAI_xDR. + value: 1 +enum/CHA_SR_LFSDET: + bit_size: 1 + variants: + - name: NoError + description: No error. + value: 0 + - name: NoSync + description: Frame synchronization signal is not present at the right time. + value: 1 +enum/CHA_SR_MUTEDET: + bit_size: 1 + variants: + - name: NoMute + description: No MUTE detection on the SD input line. + value: 0 + - name: Mute + description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame. + value: 1 +enum/CHA_SR_OVRUDR: + bit_size: 1 + variants: + - name: NoError + description: No overrun/underrun error. + value: 0 + - name: Overrun + description: Overrun/underrun error detection. + value: 1 +enum/CHA_SR_WCKCFG: + bit_size: 1 + variants: + - name: Correct + description: Clock configuration is correct. + value: 0 + - name: Wrong + description: Clock configuration does not respect the rule concerning the frame length specification. + value: 1 +enum/CHB_CLRFR_CAFSDET: + bit_size: 1 + variants: + - name: Clear + description: Clears the AFSDET flag. + value: 1 +enum/CHB_CLRFR_CCNRDY: + bit_size: 1 + variants: + - name: Clear + description: Clears the CNRDY flag. + value: 1 +enum/CHB_CLRFR_CLFSDET: + bit_size: 1 + variants: + - name: Clear + description: Clears the LFSDET flag. + value: 1 +enum/CHB_CLRFR_CMUTEDET: + bit_size: 1 + variants: + - name: Clear + description: Clears the MUTEDET flag. + value: 1 +enum/CHB_CLRFR_COVRUDR: + bit_size: 1 + variants: + - name: Clear + description: Clears the OVRUDR flag. + value: 1 +enum/CHB_CLRFR_CWCKCFG: + bit_size: 1 + variants: + - name: Clear + description: Clears the WCKCFG flag. + value: 1 +enum/CHB_CR1_CKSTR: + bit_size: 1 + variants: + - name: FallingEdge + description: Data strobing edge is falling edge of SCK. + value: 0 + - name: RisingEdge + description: Data strobing edge is rising edge of SCK. + value: 1 +enum/CHB_CR1_DMAEN: + bit_size: 1 + variants: + - name: Disabled + description: DMA disabled. + value: 0 + - name: Enabled + description: DMA enabled. value: 1 -enum/LSBFIRST: +enum/CHB_CR1_DS: + bit_size: 3 + variants: + - name: Bit8 + description: 8 bits. + value: 2 + - name: Bit10 + description: 10 bits. + value: 3 + - name: Bit16 + description: 16 bits. + value: 4 + - name: Bit20 + description: 20 bits. + value: 5 + - name: Bit24 + description: 24 bits. + value: 6 + - name: Bit32 + description: 32 bits. + value: 7 +enum/CHB_CR1_LSBFIRST: bit_size: 1 variants: - name: MsbFirst @@ -609,7 +1204,7 @@ enum/LSBFIRST: - name: LsbFirst description: Data are transferred with LSB first. value: 1 -enum/MODE: +enum/CHB_CR1_MODE: bit_size: 2 variants: - name: MasterTx @@ -624,7 +1219,7 @@ enum/MODE: - name: SlaveRx description: Slave receiver. value: 3 -enum/MONO: +enum/CHB_CR1_MONO: bit_size: 1 variants: - name: Stereo @@ -633,34 +1228,115 @@ enum/MONO: - name: Mono description: Mono mode. value: 1 -enum/MUTE: +enum/CHB_CR1_NODIV: + bit_size: 1 + variants: + - name: MasterClock + description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value. + value: 0 + - name: NoDiv + description: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + value: 1 +enum/CHB_CR1_OUTDRIV: + bit_size: 1 + variants: + - name: OnStart + description: Audio block output driven when SAIEN is set. + value: 0 + - name: Immediately + description: Audio block output driven immediately after the setting of this bit. + value: 1 +enum/CHB_CR1_PRTCFG: + bit_size: 2 + variants: + - name: Free + description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol. + value: 0 + - name: Spdif + description: SPDIF protocol. + value: 1 + - name: Ac97 + description: AC’97 protocol. + value: 2 +enum/CHB_CR1_SAIEN: bit_size: 1 variants: - name: Disabled - description: No mute mode. + description: SAI audio block disabled. value: 0 - name: Enabled - description: Mute mode enabled. + description: SAI audio block enabled. + value: 1 +enum/CHB_CR1_SYNCEN: + bit_size: 2 + variants: + - name: Asynchronous + description: audio sub-block in asynchronous mode. + value: 0 + - name: Internal + description: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode. + value: 1 + - name: External + description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode. + value: 2 +enum/CHB_CR2_COMP: + bit_size: 2 + variants: + - name: NoCompanding + description: No companding algorithm. + value: 0 + - name: MuLaw + description: μ-Law algorithm. + value: 2 + - name: ALaw + description: A-Law algorithm. + value: 3 +enum/CHB_CR2_CPL: + bit_size: 1 + variants: + - name: OnesComplement + description: 1’s complement representation. + value: 0 + - name: TwosComplement + description: 2’s complement representation. value: 1 -enum/MUTEDET: +enum/CHB_CR2_FFLUSH: bit_size: 1 variants: - - name: NoMute - description: No MUTE detection on the SD input line. + - name: NoFlush + description: No FIFO flush. value: 0 - - name: Mute - description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame. + - name: Flush + description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared. + value: 1 +enum/CHB_CR2_FTH: + bit_size: 3 + variants: + - name: Empty + description: FIFO empty. + value: 0 + - name: Quarter1 + description: 1⁄4 FIFO. value: 1 -enum/MUTEDETIE: + - name: Quarter2 + description: 1⁄2 FIFO. + value: 2 + - name: Quarter3 + description: 3⁄4 FIFO. + value: 3 + - name: Full + description: FIFO full. + value: 4 +enum/CHB_CR2_MUTE: bit_size: 1 variants: - name: Disabled - description: Interrupt is disabled. + description: No mute mode. value: 0 - name: Enabled - description: Interrupt is enabled. + description: Mute mode enabled. value: 1 -enum/MUTEVAL: +enum/CHB_CR2_MUTEVAL: bit_size: 1 variants: - name: SendZero @@ -669,34 +1345,34 @@ enum/MUTEVAL: - name: SendLast description: Last values are sent during the mute mode. value: 1 -enum/NODIV: +enum/CHB_FRCR_FSOFF: bit_size: 1 variants: - - name: MasterClock - description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value. + - name: OnFirst + description: FS is asserted on the first bit of the slot 0. value: 0 - - name: NoDiv - description: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL. + - name: BeforeFirst + description: FS is asserted one bit before the first bit of the slot 0. value: 1 -enum/OUTDRIV: +enum/CHB_FRCR_FSPOL: bit_size: 1 variants: - - name: OnStart - description: Audio block output driven when SAIEN is set. + - name: FallingEdge + description: FS is active low (falling edge). value: 0 - - name: Immediately - description: Audio block output driven immediately after the setting of this bit. + - name: RisingEdge + description: FS is active high (rising edge). value: 1 -enum/OVRUDR: +enum/CHB_IM_AFSDETIE: bit_size: 1 variants: - - name: NoError - description: No overrun/underrun error. + - name: Disabled + description: Interrupt is disabled. value: 0 - - name: Overrun - description: Overrun/underrun error detection. + - name: Enabled + description: Interrupt is enabled. value: 1 -enum/OVRUDRIE: +enum/CHB_IM_CNRDYIE: bit_size: 1 variants: - name: Disabled @@ -705,28 +1381,52 @@ enum/OVRUDRIE: - name: Enabled description: Interrupt is enabled. value: 1 -enum/PRTCFG: - bit_size: 2 +enum/CHB_IM_FREQIE: + bit_size: 1 variants: - - name: Free - description: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol. + - name: Disabled + description: Interrupt is disabled. value: 0 - - name: Spdif - description: SPDIF protocol. + - name: Enabled + description: Interrupt is enabled. value: 1 - - name: Ac97 - description: AC’97 protocol. - value: 2 -enum/SAIEN: +enum/CHB_IM_LFSDETIE: bit_size: 1 variants: - name: Disabled - description: SAI audio block disabled. + description: Interrupt is disabled. value: 0 - name: Enabled - description: SAI audio block enabled. + description: Interrupt is enabled. + value: 1 +enum/CHB_IM_MUTEDETIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled. + value: 0 + - name: Enabled + description: Interrupt is enabled. + value: 1 +enum/CHB_IM_OVRUDRIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled. + value: 0 + - name: Enabled + description: Interrupt is enabled. + value: 1 +enum/CHB_IM_WCKCFGIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt is disabled. + value: 0 + - name: Enabled + description: Interrupt is enabled. value: 1 -enum/SLOTEN: +enum/CHB_SLOTR_SLOTEN: bit_size: 16 variants: - name: Inactive @@ -735,7 +1435,7 @@ enum/SLOTEN: - name: Active description: Active slot. value: 1 -enum/SLOTSZ: +enum/CHB_SLOTR_SLOTSZ: bit_size: 2 variants: - name: DataSize @@ -747,33 +1447,87 @@ enum/SLOTSZ: - name: Bit32 description: 32-bit. value: 2 -enum/SYNCEN: - bit_size: 2 +enum/CHB_SR_AFSDET: + bit_size: 1 variants: - - name: Asynchronous - description: audio sub-block in asynchronous mode. + - name: NoError + description: No error. value: 0 - - name: Internal - description: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode. + - name: EarlySync + description: Frame synchronization signal is detected earlier than expected. value: 1 - - name: External - description: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode. +enum/CHB_SR_CNRDY: + bit_size: 1 + variants: + - name: Ready + description: External AC’97 Codec is ready. + value: 0 + - name: NotReady + description: External AC’97 Codec is not ready. + value: 1 +enum/CHB_SR_FLVL: + bit_size: 3 + variants: + - name: Empty + description: FIFO empty. + value: 0 + - name: Quarter1 + description: FIFO <= 1⁄4 but not empty. + value: 1 + - name: Quarter2 + description: 1⁄4 < FIFO <= 1⁄2. value: 2 -enum/WCKCFG: + - name: Quarter3 + description: 1⁄2 < FIFO <= 3⁄4. + value: 3 + - name: Quarter4 + description: 3⁄4 < FIFO but not full. + value: 4 + - name: Full + description: FIFO full. + value: 5 +enum/CHB_SR_FREQ: bit_size: 1 variants: - - name: Correct - description: Clock configuration is correct. + - name: NoRequest + description: No FIFO request. value: 0 - - name: Wrong - description: Clock configuration does not respect the rule concerning the frame length specification. + - name: Request + description: FIFO request to read or to write the SAI_xDR. value: 1 -enum/WCKCFGIE: +enum/CHB_SR_LFSDET: bit_size: 1 variants: - - name: Disabled - description: Interrupt is disabled. + - name: NoError + description: No error. value: 0 - - name: Enabled - description: Interrupt is enabled. + - name: NoSync + description: Frame synchronization signal is not present at the right time. + value: 1 +enum/CHB_SR_MUTEDET: + bit_size: 1 + variants: + - name: NoMute + description: No MUTE detection on the SD input line. + value: 0 + - name: Mute + description: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame. + value: 1 +enum/CHB_SR_OVRUDR: + bit_size: 1 + variants: + - name: NoError + description: No overrun/underrun error. + value: 0 + - name: Overrun + description: Overrun/underrun error detection. + value: 1 +enum/CHB_SR_WCKCFG: + bit_size: 1 + variants: + - name: Correct + description: Clock configuration is correct. + value: 0 + - name: Wrong + description: Clock configuration does not respect the rule concerning the frame length specification. value: 1 diff --git a/base/STM32WB55/TIM1.yaml b/head/STM32WB55/TIM1.yaml index ad0dccb..807435e 100644 --- a/base/STM32WB55/TIM1.yaml +++ b/head/STM32WB55/TIM1.yaml @@ -72,14 +72,26 @@ block/TIM1: description: repetition counter register. byte_offset: 48 fieldset: RCR - - name: CCR + - name: CCR1 description: capture/compare register. - array: - len: 4 - stride: 4 byte_offset: 52 bit_size: 16 fieldset: CCR + - name: CCR2 + description: capture/compare register. + byte_offset: 56 + bit_size: 16 + fieldset: CCR + - name: CCR3 + description: capture/compare register. + byte_offset: 60 + bit_size: 16 + fieldset: CCR + - name: CCR4 + description: capture/compare register. + byte_offset: 64 + bit_size: 16 + fieldset: CCR - name: BDTR description: break and dead-time register. byte_offset: 68 @@ -251,38 +263,101 @@ fieldset/BDTR: fieldset/CCER: description: capture/compare enable register. fields: - - name: CCE + - name: CC1E description: Capture/Compare %s output enable. bit_offset: 0 bit_size: 1 - array: - len: 6 - stride: 4 enum: CCE - - name: CCP + - name: CC1P description: Capture/Compare %s output Polarity. bit_offset: 1 bit_size: 1 - array: - len: 6 - stride: 4 enum: CCP - - name: CCNE + - name: CC1NE description: Capture/Compare %s complementary output enable. bit_offset: 2 bit_size: 1 - array: - len: 3 - stride: 4 enum: CCNE - - name: CCNP + - name: CC1NP description: Capture/Compare %s output Polarity. bit_offset: 3 bit_size: 1 - array: - len: 4 - stride: 4 enum: CCNP + - name: CC2E + description: Capture/Compare %s output enable. + bit_offset: 4 + bit_size: 1 + enum: CCE + - name: CC2P + description: Capture/Compare %s output Polarity. + bit_offset: 5 + bit_size: 1 + enum: CCP + - name: CC2NE + description: Capture/Compare %s complementary output enable. + bit_offset: 6 + bit_size: 1 + enum: CCNE + - name: CC2NP + description: Capture/Compare %s output Polarity. + bit_offset: 7 + bit_size: 1 + enum: CCNP + - name: CC3E + description: Capture/Compare %s output enable. + bit_offset: 8 + bit_size: 1 + enum: CCE + - name: CC3P + description: Capture/Compare %s output Polarity. + bit_offset: 9 + bit_size: 1 + enum: CCP + - name: CC3NE + description: Capture/Compare %s complementary output enable. + bit_offset: 10 + bit_size: 1 + enum: CCNE + - name: CC3NP + description: Capture/Compare %s output Polarity. + bit_offset: 11 + bit_size: 1 + enum: CCNP + - name: CC4E + description: Capture/Compare %s output enable. + bit_offset: 12 + bit_size: 1 + enum: CCE + - name: CC4P + description: Capture/Compare %s output Polarity. + bit_offset: 13 + bit_size: 1 + enum: CCP + - name: CC4NP + description: Capture/Compare %s output Polarity. + bit_offset: 15 + bit_size: 1 + enum: CCNP + - name: CC5E + description: Capture/Compare %s output enable. + bit_offset: 16 + bit_size: 1 + enum: CCE + - name: CC5P + description: Capture/Compare %s output Polarity. + bit_offset: 17 + bit_size: 1 + enum: CCP + - name: CC6E + description: Capture/Compare %s output enable. + bit_offset: 20 + bit_size: 1 + enum: CCE + - name: CC6P + description: Capture/Compare %s output Polarity. + bit_offset: 21 + bit_size: 1 + enum: CCP fieldset/CCMR1_Input: description: capture/compare mode register 1 (output mode). fields: @@ -291,77 +366,93 @@ fieldset/CCMR1_Input: bit_offset: 0 bit_size: 2 enum: CC1S - - name: ICPSC + - name: IC1PSC description: Input capture %s prescaler. bit_offset: 2 bit_size: 2 - array: - len: 2 - stride: 8 enum: ICPSC - - name: ICF + - name: IC1F description: Input capture %s filter. bit_offset: 4 bit_size: 4 - array: - len: 2 - stride: 8 enum: ICF - name: CC2S description: capture/Compare 2 selection. bit_offset: 8 bit_size: 2 enum: CC2S + - name: IC2PSC + description: Input capture %s prescaler. + bit_offset: 10 + bit_size: 2 + enum: ICPSC + - name: IC2F + description: Input capture %s filter. + bit_offset: 12 + bit_size: 4 + enum: ICF fieldset/CCMR1_Output: description: capture/compare mode register 1 (output mode). fields: - - name: CCS + - name: CC1S description: Capture/Compare %s selection. bit_offset: 0 bit_size: 2 - array: - len: 2 - stride: 8 enum: CCS - - name: OCFE + - name: OC1FE description: Output compare %s fast enable. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCFE - - name: OCPE + - name: OC1PE description: Output compare %s preload enable. bit_offset: 3 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCPE - - name: OCM + - name: OC1M description: Output compare %s mode. bit_offset: 4 bit_size: 3 - array: - len: 2 - stride: 8 enum: OCM - - name: OCCE + - name: OC1CE description: Output compare %s clear enable. bit_offset: 7 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCCE - - name: OCM_3 + - name: CC2S + description: Capture/Compare %s selection. + bit_offset: 8 + bit_size: 2 + enum: CCS + - name: OC2FE + description: Output compare %s fast enable. + bit_offset: 10 + bit_size: 1 + enum: OCFE + - name: OC2PE + description: Output compare %s preload enable. + bit_offset: 11 + bit_size: 1 + enum: OCPE + - name: OC2M + description: Output compare %s mode. + bit_offset: 12 + bit_size: 3 + enum: OCM + - name: OC2CE + description: Output compare %s clear enable. + bit_offset: 15 + bit_size: 1 + enum: OCCE + - name: OC1M_3 description: Output compare %s mode, bit 3. bit_offset: 16 bit_size: 1 - array: - len: 2 - stride: 8 + enum: OCM_3 + - name: OC2M_3 + description: Output compare %s mode, bit 3. + bit_offset: 24 + bit_size: 1 enum: OCM_3 fieldset/CCMR2_Input: description: capture/compare mode register 2 (output mode). @@ -515,22 +606,51 @@ fieldset/CR2: bit_offset: 7 bit_size: 1 enum: TI1S - - name: OIS + - name: OIS1 description: Output Idle state (OC%s output). bit_offset: 8 bit_size: 1 - array: - len: 6 - stride: 2 enum: OIS - - name: OISN + - name: OIS1N description: Output Idle state (OC%sN output). bit_offset: 9 bit_size: 1 - array: - len: 3 - stride: 2 enum: OISN + - name: OIS2 + description: Output Idle state (OC%s output). + bit_offset: 10 + bit_size: 1 + enum: OIS + - name: OIS2N + description: Output Idle state (OC%sN output). + bit_offset: 11 + bit_size: 1 + enum: OISN + - name: OIS3 + description: Output Idle state (OC%s output). + bit_offset: 12 + bit_size: 1 + enum: OIS + - name: OIS3N + description: Output Idle state (OC%sN output). + bit_offset: 13 + bit_size: 1 + enum: OISN + - name: OIS4 + description: Output Idle state (OC%s output). + bit_offset: 14 + bit_size: 1 + enum: OIS + - name: OIS5 + description: Output Idle state (OC%s output). + bit_offset: 16 + bit_size: 1 + enum: OIS + - name: OIS6 + description: Output Idle state (OC%s output). + bit_offset: 18 + bit_size: 1 + enum: OIS - name: MMS2 description: Master mode selection 2. bit_offset: 20 @@ -556,13 +676,25 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 enum: UIE - - name: CCIE + - name: CC1IE description: Capture/Compare %s interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIE + - name: CC2IE + description: Capture/Compare %s interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CCIE + - name: CC3IE + description: Capture/Compare %s interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CCIE + - name: CC4IE + description: Capture/Compare %s interrupt enable. + bit_offset: 4 + bit_size: 1 enum: CCIE - name: COMIE description: COM interrupt enable. @@ -584,13 +716,25 @@ fieldset/DIER: bit_offset: 8 bit_size: 1 enum: UDE - - name: CCDE + - name: CC1DE description: Capture/Compare %s DMA request enable. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCDE + - name: CC2DE + description: Capture/Compare %s DMA request enable. + bit_offset: 10 + bit_size: 1 + enum: CCDE + - name: CC3DE + description: Capture/Compare %s DMA request enable. + bit_offset: 11 + bit_size: 1 + enum: CCDE + - name: CC4DE + description: Capture/Compare %s DMA request enable. + bit_offset: 12 + bit_size: 1 enum: CCDE - name: COMDE description: COM DMA request enable. @@ -618,13 +762,25 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 enum: UG - - name: CCG + - name: CC1G description: Capture/compare %s generation. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCG + - name: CC2G + description: Capture/compare %s generation. + bit_offset: 2 + bit_size: 1 + enum: CCG + - name: CC3G + description: Capture/compare %s generation. + bit_offset: 3 + bit_size: 1 + enum: CCG + - name: CC4G + description: Capture/compare %s generation. + bit_offset: 4 + bit_size: 1 enum: CCG - name: COMG description: Capture/Compare control update generation. @@ -724,13 +880,25 @@ fieldset/SR: bit_offset: 0 bit_size: 1 enum: UIF - - name: CCIF + - name: CC1IF description: Capture/compare %s interrupt flag. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIF + - name: CC2IF + description: Capture/compare %s interrupt flag. + bit_offset: 2 + bit_size: 1 + enum: CCIF + - name: CC3IF + description: Capture/compare %s interrupt flag. + bit_offset: 3 + bit_size: 1 + enum: CCIF + - name: CC4IF + description: Capture/compare %s interrupt flag. + bit_offset: 4 + bit_size: 1 enum: CCIF - name: COMIF description: COM interrupt flag. @@ -752,13 +920,25 @@ fieldset/SR: bit_offset: 8 bit_size: 1 enum: B2IF - - name: CCOF + - name: CC1OF description: Capture/Compare %s overcapture flag. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCOF + - name: CC2OF + description: Capture/Compare %s overcapture flag. + bit_offset: 10 + bit_size: 1 + enum: CCOF + - name: CC3OF + description: Capture/Compare %s overcapture flag. + bit_offset: 11 + bit_size: 1 + enum: CCOF + - name: CC4OF + description: Capture/Compare %s overcapture flag. + bit_offset: 12 + bit_size: 1 enum: CCOF - name: SBIF description: System Break interrupt flag. diff --git a/base/STM32WB55/TIM16.yaml b/head/STM32WB55/TIM16.yaml index c33d153..fdadcbd 100644 --- a/base/STM32WB55/TIM16.yaml +++ b/head/STM32WB55/TIM16.yaml @@ -64,11 +64,8 @@ block/TIM16: byte_offset: 48 bit_size: 16 fieldset: RCR - - name: CCR + - name: CCR1 description: capture/compare register. - array: - len: 1 - stride: 2 byte_offset: 52 bit_size: 16 fieldset: CCR @@ -187,37 +184,25 @@ fieldset/CCER: description: capture/compare enable register. bit_size: 16 fields: - - name: CCE + - name: CC1E description: Capture/Compare %s output enable. bit_offset: 0 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCE - - name: CCP + - name: CC1P description: Capture/Compare %s output Polarity. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCP - - name: CCNE + - name: CC1NE description: Capture/Compare %s complementary output enable. bit_offset: 2 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCNE - - name: CCNP + - name: CC1NP description: Capture/Compare %s output Polarity. bit_offset: 3 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCNP fieldset/CCMR1_Input: description: capture/compare mode register 1 (input mode). @@ -227,64 +212,43 @@ fieldset/CCMR1_Input: bit_offset: 0 bit_size: 2 enum: CC1S - - name: ICPSC + - name: IC1PSC description: Input capture %s prescaler. bit_offset: 2 bit_size: 2 - array: - len: 1 - stride: 0 enum: ICPSC - - name: ICF + - name: IC1F description: Input capture %s filter. bit_offset: 4 bit_size: 4 - array: - len: 1 - stride: 0 enum: ICF fieldset/CCMR1_Output: description: capture/compare mode register (output mode). fields: - - name: CCS + - name: CC1S description: Capture/Compare %s selection. bit_offset: 0 bit_size: 2 - array: - len: 1 - stride: 0 enum: CCS - - name: OCFE + - name: OC1FE description: Output compare %s fast enable. bit_offset: 2 bit_size: 1 - array: - len: 1 - stride: 0 enum: OCFE - - name: OCPE + - name: OC1PE description: Output compare %s preload enable. bit_offset: 3 bit_size: 1 - array: - len: 1 - stride: 0 enum: OCPE - - name: OCM + - name: OC1M description: Output compare %s mode. bit_offset: 4 bit_size: 3 - array: - len: 1 - stride: 0 enum: OCM - - name: OCM_3 + - name: OC1M_3 description: Output compare %s mode, bit 3. bit_offset: 16 bit_size: 1 - array: - len: 1 - stride: 0 fieldset/CCR: description: capture/compare register. bit_size: 16 @@ -369,21 +333,15 @@ fieldset/CR2: bit_offset: 3 bit_size: 1 enum: CCDS - - name: OIS + - name: OIS1 description: Output Idle state (OC%s output). bit_offset: 8 bit_size: 1 - array: - len: 1 - stride: 0 enum: OIS - - name: OISN + - name: OIS1N description: Output Idle state (OC%sN output). bit_offset: 9 bit_size: 1 - array: - len: 1 - stride: 0 enum: OISN fieldset/DCR: description: DMA control register. @@ -406,13 +364,10 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 enum: UIE - - name: CCIE + - name: CC1IE description: Capture/Compare %s interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCIE - name: COMIE description: COM interrupt enable. @@ -429,13 +384,10 @@ fieldset/DIER: bit_offset: 8 bit_size: 1 enum: UDE - - name: CCDE + - name: CC1DE description: Capture/Compare %s DMA request enable. bit_offset: 9 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCDE fieldset/DMAR: description: DMA address for full transfer. @@ -454,13 +406,10 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 enum: UG - - name: CCG + - name: CC1G description: Capture/compare %s generation. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCG - name: COMG description: Capture/Compare control update generation. @@ -504,13 +453,10 @@ fieldset/SR: bit_offset: 0 bit_size: 1 enum: UIF - - name: CCIF + - name: CC1IF description: Capture/compare %s interrupt flag. bit_offset: 1 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCIF - name: COMIF description: COM interrupt flag. @@ -522,13 +468,10 @@ fieldset/SR: bit_offset: 7 bit_size: 1 enum: BIF - - name: CCOF + - name: CC1OF description: Capture/Compare %s overcapture flag. bit_offset: 9 bit_size: 1 - array: - len: 1 - stride: 0 enum: CCOF fieldset/TISEL: description: input selection register. diff --git a/base/STM32WB55/TIM2.yaml b/head/STM32WB55/TIM2.yaml index 30f47cf..5e5e172 100644 --- a/base/STM32WB55/TIM2.yaml +++ b/head/STM32WB55/TIM2.yaml @@ -69,13 +69,22 @@ block/TIM2: description: auto-reload register. byte_offset: 44 fieldset: ARR - - name: CCR + - name: CCR1 description: capture/compare register. - array: - len: 4 - stride: 4 byte_offset: 52 fieldset: CCR + - name: CCR2 + description: capture/compare register. + byte_offset: 56 + fieldset: CCR + - name: CCR3 + description: capture/compare register. + byte_offset: 60 + fieldset: CCR + - name: CCR4 + description: capture/compare register. + byte_offset: 64 + fieldset: CCR - name: DCR description: DMA control register. byte_offset: 72 @@ -112,29 +121,62 @@ fieldset/CCER: description: capture/compare enable register. bit_size: 16 fields: - - name: CCE + - name: CC1E description: Capture/Compare %s output enable. bit_offset: 0 bit_size: 1 - array: - len: 4 - stride: 4 enum: CCE - - name: CCP + - name: CC1P description: Capture/Compare %s output Polarity. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 4 enum: CCP - - name: CCNP + - name: CC1NP description: Capture/Compare %s output Polarity. bit_offset: 3 bit_size: 1 - array: - len: 4 - stride: 4 + - name: CC2E + description: Capture/Compare %s output enable. + bit_offset: 4 + bit_size: 1 + enum: CCE + - name: CC2P + description: Capture/Compare %s output Polarity. + bit_offset: 5 + bit_size: 1 + enum: CCP + - name: CC2NP + description: Capture/Compare %s output Polarity. + bit_offset: 7 + bit_size: 1 + - name: CC3E + description: Capture/Compare %s output enable. + bit_offset: 8 + bit_size: 1 + enum: CCE + - name: CC3P + description: Capture/Compare %s output Polarity. + bit_offset: 9 + bit_size: 1 + enum: CCP + - name: CC3NP + description: Capture/Compare %s output Polarity. + bit_offset: 11 + bit_size: 1 + - name: CC4E + description: Capture/Compare %s output enable. + bit_offset: 12 + bit_size: 1 + enum: CCE + - name: CC4P + description: Capture/Compare %s output Polarity. + bit_offset: 13 + bit_size: 1 + enum: CCP + - name: CC4NP + description: Capture/Compare %s output Polarity. + bit_offset: 15 + bit_size: 1 fieldset/CCMR1_Input: description: capture/compare mode register 1 (input mode). fields: @@ -143,76 +185,91 @@ fieldset/CCMR1_Input: bit_offset: 0 bit_size: 2 enum: CC1S - - name: ICPSC + - name: IC1PSC description: Input capture %s prescaler. bit_offset: 2 bit_size: 2 - array: - len: 2 - stride: 8 enum: ICPSC - - name: ICF + - name: IC1F description: Input capture %s filter. bit_offset: 4 bit_size: 4 - array: - len: 2 - stride: 8 enum: ICF - name: CC2S description: Capture/compare 2 selection. bit_offset: 8 bit_size: 2 enum: CC2S + - name: IC2PSC + description: Input capture %s prescaler. + bit_offset: 10 + bit_size: 2 + enum: ICPSC + - name: IC2F + description: Input capture %s filter. + bit_offset: 12 + bit_size: 4 + enum: ICF fieldset/CCMR1_Output: description: capture/compare mode register 1 (output mode). fields: - - name: CCS + - name: CC1S description: Capture/Compare %s selection. bit_offset: 0 bit_size: 2 - array: - len: 2 - stride: 8 enum: CCS - - name: OCFE + - name: OC1FE description: Output compare %s fast enable. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCFE - - name: OCPE + - name: OC1PE description: Output compare %s preload enable. bit_offset: 3 bit_size: 1 - array: - len: 2 - stride: 8 enum: OCPE - - name: OCM + - name: OC1M description: Output compare %s mode. bit_offset: 4 bit_size: 3 - array: - len: 2 - stride: 8 enum: OCM - - name: OCCE + - name: OC1CE description: Output compare %s clear enable. bit_offset: 7 bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCM_3 + - name: CC2S + description: Capture/Compare %s selection. + bit_offset: 8 + bit_size: 2 + enum: CCS + - name: OC2FE + description: Output compare %s fast enable. + bit_offset: 10 + bit_size: 1 + enum: OCFE + - name: OC2PE + description: Output compare %s preload enable. + bit_offset: 11 + bit_size: 1 + enum: OCPE + - name: OC2M + description: Output compare %s mode. + bit_offset: 12 + bit_size: 3 + enum: OCM + - name: OC2CE + description: Output compare %s clear enable. + bit_offset: 15 + bit_size: 1 + - name: OC1M_3 description: Output compare %s mode, bit 3. bit_offset: 16 bit_size: 1 - array: - len: 2 - stride: 8 + enum: OCM_3 + - name: OC2M_3 + description: Output compare %s mode, bit 3. + bit_offset: 24 + bit_size: 1 enum: OCM_3 fieldset/CCMR2_Input: description: capture/compare mode register 2 (input mode). @@ -344,13 +401,25 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 enum: UIE - - name: CCIE + - name: CC1IE description: Capture/Compare %s interrupt enable. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIE + - name: CC2IE + description: Capture/Compare %s interrupt enable. + bit_offset: 2 + bit_size: 1 + enum: CCIE + - name: CC3IE + description: Capture/Compare %s interrupt enable. + bit_offset: 3 + bit_size: 1 + enum: CCIE + - name: CC4IE + description: Capture/Compare %s interrupt enable. + bit_offset: 4 + bit_size: 1 enum: CCIE - name: TIE description: Trigger interrupt enable. @@ -360,13 +429,25 @@ fieldset/DIER: description: Update DMA request enable. bit_offset: 8 bit_size: 1 - - name: CCDE + - name: CC1DE description: Capture/Compare %s DMA request enable. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCDE + - name: CC2DE + description: Capture/Compare %s DMA request enable. + bit_offset: 10 + bit_size: 1 + enum: CCDE + - name: CC3DE + description: Capture/Compare %s DMA request enable. + bit_offset: 11 + bit_size: 1 + enum: CCDE + - name: CC4DE + description: Capture/Compare %s DMA request enable. + bit_offset: 12 + bit_size: 1 enum: CCDE fieldset/DMAR: description: DMA address for full transfer. @@ -385,13 +466,25 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 enum: UG - - name: CCG + - name: CC1G description: Capture/compare %s generation. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCG + - name: CC2G + description: Capture/compare %s generation. + bit_offset: 2 + bit_size: 1 + enum: CCG + - name: CC3G + description: Capture/compare %s generation. + bit_offset: 3 + bit_size: 1 + enum: CCG + - name: CC4G + description: Capture/compare %s generation. + bit_offset: 4 + bit_size: 1 enum: CCG - name: TG description: Trigger generation. @@ -468,25 +561,49 @@ fieldset/SR: bit_offset: 0 bit_size: 1 enum: UIF - - name: CCIF + - name: CC1IF description: Capture/compare %s interrupt flag. bit_offset: 1 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCIF + - name: CC2IF + description: Capture/compare %s interrupt flag. + bit_offset: 2 + bit_size: 1 + enum: CCIF + - name: CC3IF + description: Capture/compare %s interrupt flag. + bit_offset: 3 + bit_size: 1 + enum: CCIF + - name: CC4IF + description: Capture/compare %s interrupt flag. + bit_offset: 4 + bit_size: 1 enum: CCIF - name: TIF description: Trigger interrupt flag. bit_offset: 6 bit_size: 1 - - name: CCOF + - name: CC1OF description: Capture/Compare %s overcapture flag. bit_offset: 9 bit_size: 1 - array: - len: 4 - stride: 1 + enum: CCOF + - name: CC2OF + description: Capture/Compare %s overcapture flag. + bit_offset: 10 + bit_size: 1 + enum: CCOF + - name: CC3OF + description: Capture/Compare %s overcapture flag. + bit_offset: 11 + bit_size: 1 + enum: CCOF + - name: CC4OF + description: Capture/Compare %s overcapture flag. + bit_offset: 12 + bit_size: 1 enum: CCOF enum/ARPE: bit_size: 1 diff --git a/base/STM32WB55/TSC.yaml b/head/STM32WB55/TSC.yaml index 1e302b7..9bcd288 100644 --- a/base/STM32WB55/TSC.yaml +++ b/head/STM32WB55/TSC.yaml @@ -37,14 +37,41 @@ block/TSC: description: I/O group control status register. byte_offset: 48 fieldset: IOGCSR - - name: IOGCR + - name: IOG1CR description: I/O group x counter register. - array: - len: 7 - stride: 4 byte_offset: 52 access: Read fieldset: IOGCR + - name: IOG2CR + description: I/O group x counter register. + byte_offset: 56 + access: Read + fieldset: IOGCR + - name: IOG3CR + description: I/O group x counter register. + byte_offset: 60 + access: Read + fieldset: IOGCR + - name: IOG4CR + description: I/O group x counter register. + byte_offset: 64 + access: Read + fieldset: IOGCR + - name: IOG5CR + description: I/O group x counter register. + byte_offset: 68 + access: Read + fieldset: IOGCR + - name: IOG6CR + description: I/O group x counter register. + byte_offset: 72 + access: Read + fieldset: IOGCR + - name: IOG7CR + description: I/O group x counter register. + byte_offset: 76 + access: Read + fieldset: IOGCR fieldset/CR: description: control register. fields: @@ -129,72 +156,288 @@ fieldset/IER: fieldset/IOASCR: description: I/O analog switch control register. fields: - - name: G_IO1 + - name: G1_IO1 description: G%s_IO1. bit_offset: 0 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOASCR_G_IO1 - - name: G_IO2 + - name: G1_IO2 description: G%s_IO2. bit_offset: 1 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOASCR_G_IO2 - - name: G_IO3 + - name: G1_IO3 description: G%s_IO3. bit_offset: 2 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOASCR_G_IO3 - - name: G_IO4 + - name: G1_IO4 description: G%s_IO4. bit_offset: 3 bit_size: 1 - array: - len: 7 - stride: 4 + enum: IOASCR_G_IO4 + - name: G2_IO1 + description: G%s_IO1. + bit_offset: 4 + bit_size: 1 + enum: IOASCR_G_IO1 + - name: G2_IO2 + description: G%s_IO2. + bit_offset: 5 + bit_size: 1 + enum: IOASCR_G_IO2 + - name: G2_IO3 + description: G%s_IO3. + bit_offset: 6 + bit_size: 1 + enum: IOASCR_G_IO3 + - name: G2_IO4 + description: G%s_IO4. + bit_offset: 7 + bit_size: 1 + enum: IOASCR_G_IO4 + - name: G3_IO1 + description: G%s_IO1. + bit_offset: 8 + bit_size: 1 + enum: IOASCR_G_IO1 + - name: G3_IO2 + description: G%s_IO2. + bit_offset: 9 + bit_size: 1 + enum: IOASCR_G_IO2 + - name: G3_IO3 + description: G%s_IO3. + bit_offset: 10 + bit_size: 1 + enum: IOASCR_G_IO3 + - name: G3_IO4 + description: G%s_IO4. + bit_offset: 11 + bit_size: 1 + enum: IOASCR_G_IO4 + - name: G4_IO1 + description: G%s_IO1. + bit_offset: 12 + bit_size: 1 + enum: IOASCR_G_IO1 + - name: G4_IO2 + description: G%s_IO2. + bit_offset: 13 + bit_size: 1 + enum: IOASCR_G_IO2 + - name: G4_IO3 + description: G%s_IO3. + bit_offset: 14 + bit_size: 1 + enum: IOASCR_G_IO3 + - name: G4_IO4 + description: G%s_IO4. + bit_offset: 15 + bit_size: 1 + enum: IOASCR_G_IO4 + - name: G5_IO1 + description: G%s_IO1. + bit_offset: 16 + bit_size: 1 + enum: IOASCR_G_IO1 + - name: G5_IO2 + description: G%s_IO2. + bit_offset: 17 + bit_size: 1 + enum: IOASCR_G_IO2 + - name: G5_IO3 + description: G%s_IO3. + bit_offset: 18 + bit_size: 1 + enum: IOASCR_G_IO3 + - name: G5_IO4 + description: G%s_IO4. + bit_offset: 19 + bit_size: 1 + enum: IOASCR_G_IO4 + - name: G6_IO1 + description: G%s_IO1. + bit_offset: 20 + bit_size: 1 + enum: IOASCR_G_IO1 + - name: G6_IO2 + description: G%s_IO2. + bit_offset: 21 + bit_size: 1 + enum: IOASCR_G_IO2 + - name: G6_IO3 + description: G%s_IO3. + bit_offset: 22 + bit_size: 1 + enum: IOASCR_G_IO3 + - name: G6_IO4 + description: G%s_IO4. + bit_offset: 23 + bit_size: 1 + enum: IOASCR_G_IO4 + - name: G7_IO1 + description: G%s_IO1. + bit_offset: 24 + bit_size: 1 + enum: IOASCR_G_IO1 + - name: G7_IO2 + description: G%s_IO2. + bit_offset: 25 + bit_size: 1 + enum: IOASCR_G_IO2 + - name: G7_IO3 + description: G%s_IO3. + bit_offset: 26 + bit_size: 1 + enum: IOASCR_G_IO3 + - name: G7_IO4 + description: G%s_IO4. + bit_offset: 27 + bit_size: 1 enum: IOASCR_G_IO4 fieldset/IOCCR: description: I/O channel control register. fields: - - name: G_IO1 + - name: G1_IO1 description: G%s_IO1. bit_offset: 0 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOCCR_G_IO1 - - name: G_IO2 + - name: G1_IO2 description: G%s_IO2. bit_offset: 1 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOCCR_G_IO2 - - name: G_IO3 + - name: G1_IO3 description: G%s_IO3. bit_offset: 2 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOCCR_G_IO3 - - name: G_IO4 + - name: G1_IO4 description: G%s_IO4. bit_offset: 3 bit_size: 1 - array: - len: 7 - stride: 4 + enum: IOCCR_G_IO4 + - name: G2_IO1 + description: G%s_IO1. + bit_offset: 4 + bit_size: 1 + enum: IOCCR_G_IO1 + - name: G2_IO2 + description: G%s_IO2. + bit_offset: 5 + bit_size: 1 + enum: IOCCR_G_IO2 + - name: G2_IO3 + description: G%s_IO3. + bit_offset: 6 + bit_size: 1 + enum: IOCCR_G_IO3 + - name: G2_IO4 + description: G%s_IO4. + bit_offset: 7 + bit_size: 1 + enum: IOCCR_G_IO4 + - name: G3_IO1 + description: G%s_IO1. + bit_offset: 8 + bit_size: 1 + enum: IOCCR_G_IO1 + - name: G3_IO2 + description: G%s_IO2. + bit_offset: 9 + bit_size: 1 + enum: IOCCR_G_IO2 + - name: G3_IO3 + description: G%s_IO3. + bit_offset: 10 + bit_size: 1 + enum: IOCCR_G_IO3 + - name: G3_IO4 + description: G%s_IO4. + bit_offset: 11 + bit_size: 1 + enum: IOCCR_G_IO4 + - name: G4_IO1 + description: G%s_IO1. + bit_offset: 12 + bit_size: 1 + enum: IOCCR_G_IO1 + - name: G4_IO2 + description: G%s_IO2. + bit_offset: 13 + bit_size: 1 + enum: IOCCR_G_IO2 + - name: G4_IO3 + description: G%s_IO3. + bit_offset: 14 + bit_size: 1 + enum: IOCCR_G_IO3 + - name: G4_IO4 + description: G%s_IO4. + bit_offset: 15 + bit_size: 1 + enum: IOCCR_G_IO4 + - name: G5_IO1 + description: G%s_IO1. + bit_offset: 16 + bit_size: 1 + enum: IOCCR_G_IO1 + - name: G5_IO2 + description: G%s_IO2. + bit_offset: 17 + bit_size: 1 + enum: IOCCR_G_IO2 + - name: G5_IO3 + description: G%s_IO3. + bit_offset: 18 + bit_size: 1 + enum: IOCCR_G_IO3 + - name: G5_IO4 + description: G%s_IO4. + bit_offset: 19 + bit_size: 1 + enum: IOCCR_G_IO4 + - name: G6_IO1 + description: G%s_IO1. + bit_offset: 20 + bit_size: 1 + enum: IOCCR_G_IO1 + - name: G6_IO2 + description: G%s_IO2. + bit_offset: 21 + bit_size: 1 + enum: IOCCR_G_IO2 + - name: G6_IO3 + description: G%s_IO3. + bit_offset: 22 + bit_size: 1 + enum: IOCCR_G_IO3 + - name: G6_IO4 + description: G%s_IO4. + bit_offset: 23 + bit_size: 1 + enum: IOCCR_G_IO4 + - name: G7_IO1 + description: G%s_IO1. + bit_offset: 24 + bit_size: 1 + enum: IOCCR_G_IO1 + - name: G7_IO2 + description: G%s_IO2. + bit_offset: 25 + bit_size: 1 + enum: IOCCR_G_IO2 + - name: G7_IO3 + description: G%s_IO3. + bit_offset: 26 + bit_size: 1 + enum: IOCCR_G_IO3 + - name: G7_IO4 + description: G%s_IO4. + bit_offset: 27 + bit_size: 1 enum: IOCCR_G_IO4 fieldset/IOGCR: description: I/O group x counter register. @@ -206,91 +449,361 @@ fieldset/IOGCR: fieldset/IOGCSR: description: I/O group control status register. fields: - - name: GE + - name: G1E description: Analog I/O group x enable. bit_offset: 0 bit_size: 1 - array: - len: 7 - stride: 1 enum: GE - - name: GS + - name: G2E + description: Analog I/O group x enable. + bit_offset: 1 + bit_size: 1 + enum: GE + - name: G3E + description: Analog I/O group x enable. + bit_offset: 2 + bit_size: 1 + enum: GE + - name: G4E + description: Analog I/O group x enable. + bit_offset: 3 + bit_size: 1 + enum: GE + - name: G5E + description: Analog I/O group x enable. + bit_offset: 4 + bit_size: 1 + enum: GE + - name: G6E + description: Analog I/O group x enable. + bit_offset: 5 + bit_size: 1 + enum: GE + - name: G7E + description: Analog I/O group x enable. + bit_offset: 6 + bit_size: 1 + enum: GE + - name: G1S description: Analog I/O group x status. bit_offset: 16 bit_size: 1 - array: - len: 7 - stride: 1 + enum: GS + - name: G2S + description: Analog I/O group x status. + bit_offset: 17 + bit_size: 1 + enum: GS + - name: G3S + description: Analog I/O group x status. + bit_offset: 18 + bit_size: 1 + enum: GS + - name: G4S + description: Analog I/O group x status. + bit_offset: 19 + bit_size: 1 + enum: GS + - name: G5S + description: Analog I/O group x status. + bit_offset: 20 + bit_size: 1 + enum: GS + - name: G6S + description: Analog I/O group x status. + bit_offset: 21 + bit_size: 1 + enum: GS + - name: G7S + description: Analog I/O group x status. + bit_offset: 22 + bit_size: 1 enum: GS fieldset/IOHCR: description: I/O hysteresis control register. fields: - - name: G_IO1 + - name: G1_IO1 description: G%s_IO1. bit_offset: 0 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOHCR_G_IO1 - - name: G_IO2 + - name: G1_IO2 description: G%s_IO2. bit_offset: 1 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOHCR_G_IO2 - - name: G_IO3 + - name: G1_IO3 description: G%s_IO3. bit_offset: 2 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOHCR_G_IO3 - - name: G_IO4 + - name: G1_IO4 description: G%s_IO4. bit_offset: 3 bit_size: 1 - array: - len: 7 - stride: 4 + enum: IOHCR_G_IO4 + - name: G2_IO1 + description: G%s_IO1. + bit_offset: 4 + bit_size: 1 + enum: IOHCR_G_IO1 + - name: G2_IO2 + description: G%s_IO2. + bit_offset: 5 + bit_size: 1 + enum: IOHCR_G_IO2 + - name: G2_IO3 + description: G%s_IO3. + bit_offset: 6 + bit_size: 1 + enum: IOHCR_G_IO3 + - name: G2_IO4 + description: G%s_IO4. + bit_offset: 7 + bit_size: 1 + enum: IOHCR_G_IO4 + - name: G3_IO1 + description: G%s_IO1. + bit_offset: 8 + bit_size: 1 + enum: IOHCR_G_IO1 + - name: G3_IO2 + description: G%s_IO2. + bit_offset: 9 + bit_size: 1 + enum: IOHCR_G_IO2 + - name: G3_IO3 + description: G%s_IO3. + bit_offset: 10 + bit_size: 1 + enum: IOHCR_G_IO3 + - name: G3_IO4 + description: G%s_IO4. + bit_offset: 11 + bit_size: 1 + enum: IOHCR_G_IO4 + - name: G4_IO1 + description: G%s_IO1. + bit_offset: 12 + bit_size: 1 + enum: IOHCR_G_IO1 + - name: G4_IO2 + description: G%s_IO2. + bit_offset: 13 + bit_size: 1 + enum: IOHCR_G_IO2 + - name: G4_IO3 + description: G%s_IO3. + bit_offset: 14 + bit_size: 1 + enum: IOHCR_G_IO3 + - name: G4_IO4 + description: G%s_IO4. + bit_offset: 15 + bit_size: 1 + enum: IOHCR_G_IO4 + - name: G5_IO1 + description: G%s_IO1. + bit_offset: 16 + bit_size: 1 + enum: IOHCR_G_IO1 + - name: G5_IO2 + description: G%s_IO2. + bit_offset: 17 + bit_size: 1 + enum: IOHCR_G_IO2 + - name: G5_IO3 + description: G%s_IO3. + bit_offset: 18 + bit_size: 1 + enum: IOHCR_G_IO3 + - name: G5_IO4 + description: G%s_IO4. + bit_offset: 19 + bit_size: 1 + enum: IOHCR_G_IO4 + - name: G6_IO1 + description: G%s_IO1. + bit_offset: 20 + bit_size: 1 + enum: IOHCR_G_IO1 + - name: G6_IO2 + description: G%s_IO2. + bit_offset: 21 + bit_size: 1 + enum: IOHCR_G_IO2 + - name: G6_IO3 + description: G%s_IO3. + bit_offset: 22 + bit_size: 1 + enum: IOHCR_G_IO3 + - name: G6_IO4 + description: G%s_IO4. + bit_offset: 23 + bit_size: 1 + enum: IOHCR_G_IO4 + - name: G7_IO1 + description: G%s_IO1. + bit_offset: 24 + bit_size: 1 + enum: IOHCR_G_IO1 + - name: G7_IO2 + description: G%s_IO2. + bit_offset: 25 + bit_size: 1 + enum: IOHCR_G_IO2 + - name: G7_IO3 + description: G%s_IO3. + bit_offset: 26 + bit_size: 1 + enum: IOHCR_G_IO3 + - name: G7_IO4 + description: G%s_IO4. + bit_offset: 27 + bit_size: 1 enum: IOHCR_G_IO4 fieldset/IOSCR: description: I/O sampling control register. fields: - - name: G_IO1 + - name: G1_IO1 description: G%s_IO1. bit_offset: 0 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOSCR_G_IO1 - - name: G_IO2 + - name: G1_IO2 description: G%s_IO2. bit_offset: 1 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOSCR_G_IO2 - - name: G_IO3 + - name: G1_IO3 description: G%s_IO3. bit_offset: 2 bit_size: 1 - array: - len: 7 - stride: 4 enum: IOSCR_G_IO3 - - name: G_IO4 + - name: G1_IO4 description: G%s_IO4. bit_offset: 3 bit_size: 1 - array: - len: 7 - stride: 4 + enum: IOSCR_G_IO4 + - name: G2_IO1 + description: G%s_IO1. + bit_offset: 4 + bit_size: 1 + enum: IOSCR_G_IO1 + - name: G2_IO2 + description: G%s_IO2. + bit_offset: 5 + bit_size: 1 + enum: IOSCR_G_IO2 + - name: G2_IO3 + description: G%s_IO3. + bit_offset: 6 + bit_size: 1 + enum: IOSCR_G_IO3 + - name: G2_IO4 + description: G%s_IO4. + bit_offset: 7 + bit_size: 1 + enum: IOSCR_G_IO4 + - name: G3_IO1 + description: G%s_IO1. + bit_offset: 8 + bit_size: 1 + enum: IOSCR_G_IO1 + - name: G3_IO2 + description: G%s_IO2. + bit_offset: 9 + bit_size: 1 + enum: IOSCR_G_IO2 + - name: G3_IO3 + description: G%s_IO3. + bit_offset: 10 + bit_size: 1 + enum: IOSCR_G_IO3 + - name: G3_IO4 + description: G%s_IO4. + bit_offset: 11 + bit_size: 1 + enum: IOSCR_G_IO4 + - name: G4_IO1 + description: G%s_IO1. + bit_offset: 12 + bit_size: 1 + enum: IOSCR_G_IO1 + - name: G4_IO2 + description: G%s_IO2. + bit_offset: 13 + bit_size: 1 + enum: IOSCR_G_IO2 + - name: G4_IO3 + description: G%s_IO3. + bit_offset: 14 + bit_size: 1 + enum: IOSCR_G_IO3 + - name: G4_IO4 + description: G%s_IO4. + bit_offset: 15 + bit_size: 1 + enum: IOSCR_G_IO4 + - name: G5_IO1 + description: G%s_IO1. + bit_offset: 16 + bit_size: 1 + enum: IOSCR_G_IO1 + - name: G5_IO2 + description: G%s_IO2. + bit_offset: 17 + bit_size: 1 + enum: IOSCR_G_IO2 + - name: G5_IO3 + description: G%s_IO3. + bit_offset: 18 + bit_size: 1 + enum: IOSCR_G_IO3 + - name: G5_IO4 + description: G%s_IO4. + bit_offset: 19 + bit_size: 1 + enum: IOSCR_G_IO4 + - name: G6_IO1 + description: G%s_IO1. + bit_offset: 20 + bit_size: 1 + enum: IOSCR_G_IO1 + - name: G6_IO2 + description: G%s_IO2. + bit_offset: 21 + bit_size: 1 + enum: IOSCR_G_IO2 + - name: G6_IO3 + description: G%s_IO3. + bit_offset: 22 + bit_size: 1 + enum: IOSCR_G_IO3 + - name: G6_IO4 + description: G%s_IO4. + bit_offset: 23 + bit_size: 1 + enum: IOSCR_G_IO4 + - name: G7_IO1 + description: G%s_IO1. + bit_offset: 24 + bit_size: 1 + enum: IOSCR_G_IO1 + - name: G7_IO2 + description: G%s_IO2. + bit_offset: 25 + bit_size: 1 + enum: IOSCR_G_IO2 + - name: G7_IO3 + description: G%s_IO3. + bit_offset: 26 + bit_size: 1 + enum: IOSCR_G_IO3 + - name: G7_IO4 + description: G%s_IO4. + bit_offset: 27 + bit_size: 1 enum: IOSCR_G_IO4 fieldset/ISR: description: interrupt status register. diff --git a/base/STM32WB55/USB.yaml b/head/STM32WB55/USB.yaml index c7e4e97..b01d8c5 100644 --- a/base/STM32WB55/USB.yaml +++ b/head/STM32WB55/USB.yaml @@ -1,14 +1,46 @@ block/USB: description: Universal serial bus full-speed device interface. items: - - name: EPR + - name: EP0R description: endpoint %s register. - array: - len: 8 - stride: 4 byte_offset: 0 bit_size: 16 fieldset: EPR + - name: EP1R + description: endpoint %s register. + byte_offset: 4 + bit_size: 16 + fieldset: EPR + - name: EP2R + description: endpoint %s register. + byte_offset: 8 + bit_size: 16 + fieldset: EPR + - name: EP3R + description: endpoint %s register. + byte_offset: 12 + bit_size: 16 + fieldset: EPR + - name: EP4R + description: endpoint %s register. + byte_offset: 16 + bit_size: 16 + fieldset: EPR + - name: EP5R + description: endpoint %s register. + byte_offset: 20 + bit_size: 16 + fieldset: EPR + - name: EP6R + description: endpoint %s register. + byte_offset: 24 + bit_size: 16 + fieldset: EPR + - name: EP7R + description: endpoint %s register. + byte_offset: 28 + bit_size: 16 + fieldset: EPR - name: CNTR description: control register. byte_offset: 64 diff --git a/base/esp32/APB_CTRL.yaml b/head/esp32/APB_CTRL.yaml index a1757a8..638a759 100644 --- a/base/esp32/APB_CTRL.yaml +++ b/head/esp32/APB_CTRL.yaml @@ -22,18 +22,30 @@ block/APB_CTRL: - name: APB_SARADC_FSM byte_offset: 24 fieldset: APB_SARADC_FSM - - name: APB_SARADC_SAR1_PATT_TAB - array: - len: 4 - stride: 4 + - name: APB_SARADC_SAR1_PATT_TAB1 byte_offset: 28 fieldset: APB_SARADC_SAR1_PATT_TAB - - name: APB_SARADC_SAR2_PATT_TAB - array: - len: 4 - stride: 4 + - name: APB_SARADC_SAR1_PATT_TAB2 + byte_offset: 32 + fieldset: APB_SARADC_SAR1_PATT_TAB + - name: APB_SARADC_SAR1_PATT_TAB3 + byte_offset: 36 + fieldset: APB_SARADC_SAR1_PATT_TAB + - name: APB_SARADC_SAR1_PATT_TAB4 + byte_offset: 40 + fieldset: APB_SARADC_SAR1_PATT_TAB + - name: APB_SARADC_SAR2_PATT_TAB1 byte_offset: 44 fieldset: APB_SARADC_SAR2_PATT_TAB + - name: APB_SARADC_SAR2_PATT_TAB2 + byte_offset: 48 + fieldset: APB_SARADC_SAR2_PATT_TAB + - name: APB_SARADC_SAR2_PATT_TAB3 + byte_offset: 52 + fieldset: APB_SARADC_SAR2_PATT_TAB + - name: APB_SARADC_SAR2_PATT_TAB4 + byte_offset: 56 + fieldset: APB_SARADC_SAR2_PATT_TAB - name: APLL_TICK_CONF byte_offset: 60 fieldset: APLL_TICK_CONF diff --git a/base/esp32/FLASH_ENCRYPTION.yaml b/head/esp32/FLASH_ENCRYPTION.yaml index 2d6e48a..a87daa0 100644 --- a/base/esp32/FLASH_ENCRYPTION.yaml +++ b/head/esp32/FLASH_ENCRYPTION.yaml @@ -1,12 +1,6 @@ block/FLASH_ENCRYPTION: description: FLASH_ENCRYPTION Peripheral. items: - - name: BUFFER_ - array: - len: 8 - stride: 4 - byte_offset: 0 - fieldset: BUFFER_ - name: START byte_offset: 32 fieldset: START diff --git a/base/esp32/GPIO.yaml b/head/esp32/GPIO.yaml index b1bb9b3..b816b33 100644 --- a/base/esp32/GPIO.yaml +++ b/head/esp32/GPIO.yaml @@ -100,30 +100,1020 @@ block/GPIO: - name: CPUSDIO_INT1 byte_offset: 132 fieldset: CPUSDIO_INT1 - - name: PIN - array: - len: 40 - stride: 4 + - name: PIN0 byte_offset: 136 fieldset: PIN + - name: PIN1 + byte_offset: 140 + fieldset: PIN + - name: PIN2 + byte_offset: 144 + fieldset: PIN + - name: PIN3 + byte_offset: 148 + fieldset: PIN + - name: PIN4 + byte_offset: 152 + fieldset: PIN + - name: PIN5 + byte_offset: 156 + fieldset: PIN + - name: PIN6 + byte_offset: 160 + fieldset: PIN + - name: PIN7 + byte_offset: 164 + fieldset: PIN + - name: PIN8 + byte_offset: 168 + fieldset: PIN + - name: PIN9 + byte_offset: 172 + fieldset: PIN + - name: PIN10 + byte_offset: 176 + fieldset: PIN + - name: PIN11 + byte_offset: 180 + fieldset: PIN + - name: PIN12 + byte_offset: 184 + fieldset: PIN + - name: PIN13 + byte_offset: 188 + fieldset: PIN + - name: PIN14 + byte_offset: 192 + fieldset: PIN + - name: PIN15 + byte_offset: 196 + fieldset: PIN + - name: PIN16 + byte_offset: 200 + fieldset: PIN + - name: PIN17 + byte_offset: 204 + fieldset: PIN + - name: PIN18 + byte_offset: 208 + fieldset: PIN + - name: PIN19 + byte_offset: 212 + fieldset: PIN + - name: PIN20 + byte_offset: 216 + fieldset: PIN + - name: PIN21 + byte_offset: 220 + fieldset: PIN + - name: PIN22 + byte_offset: 224 + fieldset: PIN + - name: PIN23 + byte_offset: 228 + fieldset: PIN + - name: PIN24 + byte_offset: 232 + fieldset: PIN + - name: PIN25 + byte_offset: 236 + fieldset: PIN + - name: PIN26 + byte_offset: 240 + fieldset: PIN + - name: PIN27 + byte_offset: 244 + fieldset: PIN + - name: PIN28 + byte_offset: 248 + fieldset: PIN + - name: PIN29 + byte_offset: 252 + fieldset: PIN + - name: PIN30 + byte_offset: 256 + fieldset: PIN + - name: PIN31 + byte_offset: 260 + fieldset: PIN + - name: PIN32 + byte_offset: 264 + fieldset: PIN + - name: PIN33 + byte_offset: 268 + fieldset: PIN + - name: PIN34 + byte_offset: 272 + fieldset: PIN + - name: PIN35 + byte_offset: 276 + fieldset: PIN + - name: PIN36 + byte_offset: 280 + fieldset: PIN + - name: PIN37 + byte_offset: 284 + fieldset: PIN + - name: PIN38 + byte_offset: 288 + fieldset: PIN + - name: PIN39 + byte_offset: 292 + fieldset: PIN - name: cali_conf byte_offset: 296 fieldset: cali_conf - name: cali_data byte_offset: 300 fieldset: cali_data - - name: FUNC_IN_SEL_CFG - array: - len: 256 - stride: 4 + - name: FUNC0_IN_SEL_CFG byte_offset: 304 fieldset: FUNC_IN_SEL_CFG - - name: FUNC_OUT_SEL_CFG - array: - len: 40 - stride: 4 + - name: FUNC1_IN_SEL_CFG + byte_offset: 308 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC2_IN_SEL_CFG + byte_offset: 312 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC3_IN_SEL_CFG + byte_offset: 316 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC4_IN_SEL_CFG + byte_offset: 320 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC5_IN_SEL_CFG + byte_offset: 324 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC6_IN_SEL_CFG + byte_offset: 328 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC7_IN_SEL_CFG + byte_offset: 332 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC8_IN_SEL_CFG + byte_offset: 336 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC9_IN_SEL_CFG + byte_offset: 340 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC10_IN_SEL_CFG + byte_offset: 344 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC11_IN_SEL_CFG + byte_offset: 348 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC12_IN_SEL_CFG + byte_offset: 352 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC13_IN_SEL_CFG + byte_offset: 356 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC14_IN_SEL_CFG + byte_offset: 360 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC15_IN_SEL_CFG + byte_offset: 364 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC16_IN_SEL_CFG + byte_offset: 368 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC17_IN_SEL_CFG + byte_offset: 372 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC18_IN_SEL_CFG + byte_offset: 376 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC19_IN_SEL_CFG + byte_offset: 380 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC20_IN_SEL_CFG + byte_offset: 384 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC21_IN_SEL_CFG + byte_offset: 388 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC22_IN_SEL_CFG + byte_offset: 392 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC23_IN_SEL_CFG + byte_offset: 396 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC24_IN_SEL_CFG + byte_offset: 400 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC25_IN_SEL_CFG + byte_offset: 404 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC26_IN_SEL_CFG + byte_offset: 408 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC27_IN_SEL_CFG + byte_offset: 412 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC28_IN_SEL_CFG + byte_offset: 416 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC29_IN_SEL_CFG + byte_offset: 420 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC30_IN_SEL_CFG + byte_offset: 424 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC31_IN_SEL_CFG + byte_offset: 428 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC32_IN_SEL_CFG + byte_offset: 432 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC33_IN_SEL_CFG + byte_offset: 436 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC34_IN_SEL_CFG + byte_offset: 440 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC35_IN_SEL_CFG + byte_offset: 444 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC36_IN_SEL_CFG + byte_offset: 448 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC37_IN_SEL_CFG + byte_offset: 452 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC38_IN_SEL_CFG + byte_offset: 456 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC39_IN_SEL_CFG + byte_offset: 460 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC40_IN_SEL_CFG + byte_offset: 464 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC41_IN_SEL_CFG + byte_offset: 468 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC42_IN_SEL_CFG + byte_offset: 472 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC43_IN_SEL_CFG + byte_offset: 476 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC44_IN_SEL_CFG + byte_offset: 480 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC45_IN_SEL_CFG + byte_offset: 484 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC46_IN_SEL_CFG + byte_offset: 488 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC47_IN_SEL_CFG + byte_offset: 492 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC48_IN_SEL_CFG + byte_offset: 496 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC49_IN_SEL_CFG + byte_offset: 500 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC50_IN_SEL_CFG + byte_offset: 504 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC51_IN_SEL_CFG + byte_offset: 508 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC52_IN_SEL_CFG + byte_offset: 512 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC53_IN_SEL_CFG + byte_offset: 516 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC54_IN_SEL_CFG + byte_offset: 520 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC55_IN_SEL_CFG + byte_offset: 524 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC56_IN_SEL_CFG + byte_offset: 528 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC57_IN_SEL_CFG + byte_offset: 532 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC58_IN_SEL_CFG + byte_offset: 536 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC59_IN_SEL_CFG + byte_offset: 540 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC60_IN_SEL_CFG + byte_offset: 544 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC61_IN_SEL_CFG + byte_offset: 548 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC62_IN_SEL_CFG + byte_offset: 552 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC63_IN_SEL_CFG + byte_offset: 556 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC64_IN_SEL_CFG + byte_offset: 560 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC65_IN_SEL_CFG + byte_offset: 564 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC66_IN_SEL_CFG + byte_offset: 568 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC67_IN_SEL_CFG + byte_offset: 572 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC68_IN_SEL_CFG + byte_offset: 576 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC69_IN_SEL_CFG + byte_offset: 580 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC70_IN_SEL_CFG + byte_offset: 584 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC71_IN_SEL_CFG + byte_offset: 588 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC72_IN_SEL_CFG + byte_offset: 592 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC73_IN_SEL_CFG + byte_offset: 596 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC74_IN_SEL_CFG + byte_offset: 600 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC75_IN_SEL_CFG + byte_offset: 604 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC76_IN_SEL_CFG + byte_offset: 608 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC77_IN_SEL_CFG + byte_offset: 612 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC78_IN_SEL_CFG + byte_offset: 616 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC79_IN_SEL_CFG + byte_offset: 620 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC80_IN_SEL_CFG + byte_offset: 624 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC81_IN_SEL_CFG + byte_offset: 628 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC82_IN_SEL_CFG + byte_offset: 632 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC83_IN_SEL_CFG + byte_offset: 636 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC84_IN_SEL_CFG + byte_offset: 640 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC85_IN_SEL_CFG + byte_offset: 644 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC86_IN_SEL_CFG + byte_offset: 648 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC87_IN_SEL_CFG + byte_offset: 652 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC88_IN_SEL_CFG + byte_offset: 656 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC89_IN_SEL_CFG + byte_offset: 660 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC90_IN_SEL_CFG + byte_offset: 664 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC91_IN_SEL_CFG + byte_offset: 668 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC92_IN_SEL_CFG + byte_offset: 672 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC93_IN_SEL_CFG + byte_offset: 676 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC94_IN_SEL_CFG + byte_offset: 680 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC95_IN_SEL_CFG + byte_offset: 684 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC96_IN_SEL_CFG + byte_offset: 688 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC97_IN_SEL_CFG + byte_offset: 692 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC98_IN_SEL_CFG + byte_offset: 696 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC99_IN_SEL_CFG + byte_offset: 700 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC100_IN_SEL_CFG + byte_offset: 704 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC101_IN_SEL_CFG + byte_offset: 708 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC102_IN_SEL_CFG + byte_offset: 712 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC103_IN_SEL_CFG + byte_offset: 716 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC104_IN_SEL_CFG + byte_offset: 720 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC105_IN_SEL_CFG + byte_offset: 724 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC106_IN_SEL_CFG + byte_offset: 728 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC107_IN_SEL_CFG + byte_offset: 732 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC108_IN_SEL_CFG + byte_offset: 736 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC109_IN_SEL_CFG + byte_offset: 740 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC110_IN_SEL_CFG + byte_offset: 744 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC111_IN_SEL_CFG + byte_offset: 748 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC112_IN_SEL_CFG + byte_offset: 752 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC113_IN_SEL_CFG + byte_offset: 756 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC114_IN_SEL_CFG + byte_offset: 760 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC115_IN_SEL_CFG + byte_offset: 764 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC116_IN_SEL_CFG + byte_offset: 768 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC117_IN_SEL_CFG + byte_offset: 772 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC118_IN_SEL_CFG + byte_offset: 776 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC119_IN_SEL_CFG + byte_offset: 780 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC120_IN_SEL_CFG + byte_offset: 784 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC121_IN_SEL_CFG + byte_offset: 788 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC122_IN_SEL_CFG + byte_offset: 792 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC123_IN_SEL_CFG + byte_offset: 796 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC124_IN_SEL_CFG + byte_offset: 800 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC125_IN_SEL_CFG + byte_offset: 804 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC126_IN_SEL_CFG + byte_offset: 808 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC127_IN_SEL_CFG + byte_offset: 812 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC128_IN_SEL_CFG + byte_offset: 816 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC129_IN_SEL_CFG + byte_offset: 820 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC130_IN_SEL_CFG + byte_offset: 824 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC131_IN_SEL_CFG + byte_offset: 828 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC132_IN_SEL_CFG + byte_offset: 832 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC133_IN_SEL_CFG + byte_offset: 836 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC134_IN_SEL_CFG + byte_offset: 840 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC135_IN_SEL_CFG + byte_offset: 844 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC136_IN_SEL_CFG + byte_offset: 848 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC137_IN_SEL_CFG + byte_offset: 852 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC138_IN_SEL_CFG + byte_offset: 856 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC139_IN_SEL_CFG + byte_offset: 860 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC140_IN_SEL_CFG + byte_offset: 864 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC141_IN_SEL_CFG + byte_offset: 868 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC142_IN_SEL_CFG + byte_offset: 872 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC143_IN_SEL_CFG + byte_offset: 876 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC144_IN_SEL_CFG + byte_offset: 880 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC145_IN_SEL_CFG + byte_offset: 884 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC146_IN_SEL_CFG + byte_offset: 888 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC147_IN_SEL_CFG + byte_offset: 892 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC148_IN_SEL_CFG + byte_offset: 896 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC149_IN_SEL_CFG + byte_offset: 900 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC150_IN_SEL_CFG + byte_offset: 904 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC151_IN_SEL_CFG + byte_offset: 908 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC152_IN_SEL_CFG + byte_offset: 912 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC153_IN_SEL_CFG + byte_offset: 916 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC154_IN_SEL_CFG + byte_offset: 920 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC155_IN_SEL_CFG + byte_offset: 924 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC156_IN_SEL_CFG + byte_offset: 928 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC157_IN_SEL_CFG + byte_offset: 932 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC158_IN_SEL_CFG + byte_offset: 936 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC159_IN_SEL_CFG + byte_offset: 940 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC160_IN_SEL_CFG + byte_offset: 944 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC161_IN_SEL_CFG + byte_offset: 948 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC162_IN_SEL_CFG + byte_offset: 952 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC163_IN_SEL_CFG + byte_offset: 956 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC164_IN_SEL_CFG + byte_offset: 960 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC165_IN_SEL_CFG + byte_offset: 964 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC166_IN_SEL_CFG + byte_offset: 968 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC167_IN_SEL_CFG + byte_offset: 972 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC168_IN_SEL_CFG + byte_offset: 976 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC169_IN_SEL_CFG + byte_offset: 980 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC170_IN_SEL_CFG + byte_offset: 984 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC171_IN_SEL_CFG + byte_offset: 988 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC172_IN_SEL_CFG + byte_offset: 992 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC173_IN_SEL_CFG + byte_offset: 996 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC174_IN_SEL_CFG + byte_offset: 1000 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC175_IN_SEL_CFG + byte_offset: 1004 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC176_IN_SEL_CFG + byte_offset: 1008 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC177_IN_SEL_CFG + byte_offset: 1012 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC178_IN_SEL_CFG + byte_offset: 1016 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC179_IN_SEL_CFG + byte_offset: 1020 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC180_IN_SEL_CFG + byte_offset: 1024 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC181_IN_SEL_CFG + byte_offset: 1028 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC182_IN_SEL_CFG + byte_offset: 1032 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC183_IN_SEL_CFG + byte_offset: 1036 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC184_IN_SEL_CFG + byte_offset: 1040 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC185_IN_SEL_CFG + byte_offset: 1044 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC186_IN_SEL_CFG + byte_offset: 1048 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC187_IN_SEL_CFG + byte_offset: 1052 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC188_IN_SEL_CFG + byte_offset: 1056 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC189_IN_SEL_CFG + byte_offset: 1060 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC190_IN_SEL_CFG + byte_offset: 1064 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC191_IN_SEL_CFG + byte_offset: 1068 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC192_IN_SEL_CFG + byte_offset: 1072 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC193_IN_SEL_CFG + byte_offset: 1076 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC194_IN_SEL_CFG + byte_offset: 1080 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC195_IN_SEL_CFG + byte_offset: 1084 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC196_IN_SEL_CFG + byte_offset: 1088 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC197_IN_SEL_CFG + byte_offset: 1092 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC198_IN_SEL_CFG + byte_offset: 1096 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC199_IN_SEL_CFG + byte_offset: 1100 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC200_IN_SEL_CFG + byte_offset: 1104 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC201_IN_SEL_CFG + byte_offset: 1108 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC202_IN_SEL_CFG + byte_offset: 1112 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC203_IN_SEL_CFG + byte_offset: 1116 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC204_IN_SEL_CFG + byte_offset: 1120 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC205_IN_SEL_CFG + byte_offset: 1124 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC206_IN_SEL_CFG + byte_offset: 1128 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC207_IN_SEL_CFG + byte_offset: 1132 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC208_IN_SEL_CFG + byte_offset: 1136 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC209_IN_SEL_CFG + byte_offset: 1140 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC210_IN_SEL_CFG + byte_offset: 1144 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC211_IN_SEL_CFG + byte_offset: 1148 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC212_IN_SEL_CFG + byte_offset: 1152 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC213_IN_SEL_CFG + byte_offset: 1156 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC214_IN_SEL_CFG + byte_offset: 1160 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC215_IN_SEL_CFG + byte_offset: 1164 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC216_IN_SEL_CFG + byte_offset: 1168 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC217_IN_SEL_CFG + byte_offset: 1172 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC218_IN_SEL_CFG + byte_offset: 1176 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC219_IN_SEL_CFG + byte_offset: 1180 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC220_IN_SEL_CFG + byte_offset: 1184 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC221_IN_SEL_CFG + byte_offset: 1188 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC222_IN_SEL_CFG + byte_offset: 1192 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC223_IN_SEL_CFG + byte_offset: 1196 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC224_IN_SEL_CFG + byte_offset: 1200 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC225_IN_SEL_CFG + byte_offset: 1204 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC226_IN_SEL_CFG + byte_offset: 1208 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC227_IN_SEL_CFG + byte_offset: 1212 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC228_IN_SEL_CFG + byte_offset: 1216 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC229_IN_SEL_CFG + byte_offset: 1220 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC230_IN_SEL_CFG + byte_offset: 1224 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC231_IN_SEL_CFG + byte_offset: 1228 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC232_IN_SEL_CFG + byte_offset: 1232 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC233_IN_SEL_CFG + byte_offset: 1236 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC234_IN_SEL_CFG + byte_offset: 1240 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC235_IN_SEL_CFG + byte_offset: 1244 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC236_IN_SEL_CFG + byte_offset: 1248 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC237_IN_SEL_CFG + byte_offset: 1252 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC238_IN_SEL_CFG + byte_offset: 1256 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC239_IN_SEL_CFG + byte_offset: 1260 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC240_IN_SEL_CFG + byte_offset: 1264 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC241_IN_SEL_CFG + byte_offset: 1268 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC242_IN_SEL_CFG + byte_offset: 1272 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC243_IN_SEL_CFG + byte_offset: 1276 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC244_IN_SEL_CFG + byte_offset: 1280 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC245_IN_SEL_CFG + byte_offset: 1284 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC246_IN_SEL_CFG + byte_offset: 1288 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC247_IN_SEL_CFG + byte_offset: 1292 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC248_IN_SEL_CFG + byte_offset: 1296 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC249_IN_SEL_CFG + byte_offset: 1300 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC250_IN_SEL_CFG + byte_offset: 1304 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC251_IN_SEL_CFG + byte_offset: 1308 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC252_IN_SEL_CFG + byte_offset: 1312 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC253_IN_SEL_CFG + byte_offset: 1316 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC254_IN_SEL_CFG + byte_offset: 1320 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC255_IN_SEL_CFG + byte_offset: 1324 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC0_OUT_SEL_CFG byte_offset: 1328 fieldset: FUNC_OUT_SEL_CFG + - name: FUNC1_OUT_SEL_CFG + byte_offset: 1332 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC2_OUT_SEL_CFG + byte_offset: 1336 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC3_OUT_SEL_CFG + byte_offset: 1340 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC4_OUT_SEL_CFG + byte_offset: 1344 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC5_OUT_SEL_CFG + byte_offset: 1348 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC6_OUT_SEL_CFG + byte_offset: 1352 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC7_OUT_SEL_CFG + byte_offset: 1356 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC8_OUT_SEL_CFG + byte_offset: 1360 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC9_OUT_SEL_CFG + byte_offset: 1364 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC10_OUT_SEL_CFG + byte_offset: 1368 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC11_OUT_SEL_CFG + byte_offset: 1372 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC12_OUT_SEL_CFG + byte_offset: 1376 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC13_OUT_SEL_CFG + byte_offset: 1380 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC14_OUT_SEL_CFG + byte_offset: 1384 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC15_OUT_SEL_CFG + byte_offset: 1388 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC16_OUT_SEL_CFG + byte_offset: 1392 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC17_OUT_SEL_CFG + byte_offset: 1396 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC18_OUT_SEL_CFG + byte_offset: 1400 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC19_OUT_SEL_CFG + byte_offset: 1404 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC20_OUT_SEL_CFG + byte_offset: 1408 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC21_OUT_SEL_CFG + byte_offset: 1412 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC22_OUT_SEL_CFG + byte_offset: 1416 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC23_OUT_SEL_CFG + byte_offset: 1420 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC24_OUT_SEL_CFG + byte_offset: 1424 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC25_OUT_SEL_CFG + byte_offset: 1428 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC26_OUT_SEL_CFG + byte_offset: 1432 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC27_OUT_SEL_CFG + byte_offset: 1436 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC28_OUT_SEL_CFG + byte_offset: 1440 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC29_OUT_SEL_CFG + byte_offset: 1444 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC30_OUT_SEL_CFG + byte_offset: 1448 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC31_OUT_SEL_CFG + byte_offset: 1452 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC32_OUT_SEL_CFG + byte_offset: 1456 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC33_OUT_SEL_CFG + byte_offset: 1460 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC34_OUT_SEL_CFG + byte_offset: 1464 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC35_OUT_SEL_CFG + byte_offset: 1468 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC36_OUT_SEL_CFG + byte_offset: 1472 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC37_OUT_SEL_CFG + byte_offset: 1476 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC38_OUT_SEL_CFG + byte_offset: 1480 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC39_OUT_SEL_CFG + byte_offset: 1484 + fieldset: FUNC_OUT_SEL_CFG fieldset/ACPU_INT: fields: - name: APPCPU_INT diff --git a/base/esp32/GPIO_SD.yaml b/head/esp32/GPIO_SD.yaml index 269101d..50551f6 100644 --- a/base/esp32/GPIO_SD.yaml +++ b/head/esp32/GPIO_SD.yaml @@ -1,12 +1,30 @@ block/GPIO_SD: description: Sigma-Delta Modulation. items: - - name: SIGMADELTA - array: - len: 8 - stride: 4 + - name: SIGMADELTA0 byte_offset: 0 fieldset: SIGMADELTA + - name: SIGMADELTA1 + byte_offset: 4 + fieldset: SIGMADELTA + - name: SIGMADELTA2 + byte_offset: 8 + fieldset: SIGMADELTA + - name: SIGMADELTA3 + byte_offset: 12 + fieldset: SIGMADELTA + - name: SIGMADELTA4 + byte_offset: 16 + fieldset: SIGMADELTA + - name: SIGMADELTA5 + byte_offset: 20 + fieldset: SIGMADELTA + - name: SIGMADELTA6 + byte_offset: 24 + fieldset: SIGMADELTA + - name: SIGMADELTA7 + byte_offset: 28 + fieldset: SIGMADELTA - name: CG byte_offset: 32 fieldset: CG diff --git a/base/esp32/I2C0.yaml b/head/esp32/I2C0.yaml index 2a2558c..5ff34be 100644 --- a/base/esp32/I2C0.yaml +++ b/head/esp32/I2C0.yaml @@ -64,12 +64,54 @@ block/I2C0: - name: SDA_FILTER_CFG byte_offset: 84 fieldset: SDA_FILTER_CFG - - name: COMD - array: - len: 16 - stride: 4 + - name: COMD0 byte_offset: 88 fieldset: COMD + - name: COMD1 + byte_offset: 92 + fieldset: COMD + - name: COMD2 + byte_offset: 96 + fieldset: COMD + - name: COMD3 + byte_offset: 100 + fieldset: COMD + - name: COMD4 + byte_offset: 104 + fieldset: COMD + - name: COMD5 + byte_offset: 108 + fieldset: COMD + - name: COMD6 + byte_offset: 112 + fieldset: COMD + - name: COMD7 + byte_offset: 116 + fieldset: COMD + - name: COMD8 + byte_offset: 120 + fieldset: COMD + - name: COMD9 + byte_offset: 124 + fieldset: COMD + - name: COMD10 + byte_offset: 128 + fieldset: COMD + - name: COMD11 + byte_offset: 132 + fieldset: COMD + - name: COMD12 + byte_offset: 136 + fieldset: COMD + - name: COMD13 + byte_offset: 140 + fieldset: COMD + - name: COMD14 + byte_offset: 144 + fieldset: COMD + - name: COMD15 + byte_offset: 148 + fieldset: COMD - name: DATE byte_offset: 248 fieldset: DATE diff --git a/base/esp32/LEDC.yaml b/head/esp32/LEDC.yaml index 74939cc..b4c7cf0 100644 --- a/base/esp32/LEDC.yaml +++ b/head/esp32/LEDC.yaml @@ -1,90 +1,294 @@ block/LEDC: description: LED Control PWM (Pulse Width Modulation). items: - - name: HSCH_CONF0 - array: - len: 8 - stride: 20 + - name: HSCH0_CONF0 byte_offset: 0 fieldset: HSCH_CONF0 - - name: HSCH_HPOINT - array: - len: 8 - stride: 20 + - name: HSCH0_HPOINT byte_offset: 4 fieldset: HSCH_HPOINT - - name: HSCH_DUTY - array: - len: 8 - stride: 20 + - name: HSCH0_DUTY byte_offset: 8 fieldset: HSCH_DUTY - - name: HSCH_CONF1 - array: - len: 8 - stride: 20 + - name: HSCH0_CONF1 byte_offset: 12 fieldset: HSCH_CONF1 - - name: HSCH_DUTY_R - array: - len: 8 - stride: 20 + - name: HSCH0_DUTY_R byte_offset: 16 fieldset: HSCH_DUTY_R - - name: LSCH_CONF0 - array: - len: 8 - stride: 20 + - name: HSCH1_CONF0 + byte_offset: 20 + fieldset: HSCH_CONF0 + - name: HSCH1_HPOINT + byte_offset: 24 + fieldset: HSCH_HPOINT + - name: HSCH1_DUTY + byte_offset: 28 + fieldset: HSCH_DUTY + - name: HSCH1_CONF1 + byte_offset: 32 + fieldset: HSCH_CONF1 + - name: HSCH1_DUTY_R + byte_offset: 36 + fieldset: HSCH_DUTY_R + - name: HSCH2_CONF0 + byte_offset: 40 + fieldset: HSCH_CONF0 + - name: HSCH2_HPOINT + byte_offset: 44 + fieldset: HSCH_HPOINT + - name: HSCH2_DUTY + byte_offset: 48 + fieldset: HSCH_DUTY + - name: HSCH2_CONF1 + byte_offset: 52 + fieldset: HSCH_CONF1 + - name: HSCH2_DUTY_R + byte_offset: 56 + fieldset: HSCH_DUTY_R + - name: HSCH3_CONF0 + byte_offset: 60 + fieldset: HSCH_CONF0 + - name: HSCH3_HPOINT + byte_offset: 64 + fieldset: HSCH_HPOINT + - name: HSCH3_DUTY + byte_offset: 68 + fieldset: HSCH_DUTY + - name: HSCH3_CONF1 + byte_offset: 72 + fieldset: HSCH_CONF1 + - name: HSCH3_DUTY_R + byte_offset: 76 + fieldset: HSCH_DUTY_R + - name: HSCH4_CONF0 + byte_offset: 80 + fieldset: HSCH_CONF0 + - name: HSCH4_HPOINT + byte_offset: 84 + fieldset: HSCH_HPOINT + - name: HSCH4_DUTY + byte_offset: 88 + fieldset: HSCH_DUTY + - name: HSCH4_CONF1 + byte_offset: 92 + fieldset: HSCH_CONF1 + - name: HSCH4_DUTY_R + byte_offset: 96 + fieldset: HSCH_DUTY_R + - name: HSCH5_CONF0 + byte_offset: 100 + fieldset: HSCH_CONF0 + - name: HSCH5_HPOINT + byte_offset: 104 + fieldset: HSCH_HPOINT + - name: HSCH5_DUTY + byte_offset: 108 + fieldset: HSCH_DUTY + - name: HSCH5_CONF1 + byte_offset: 112 + fieldset: HSCH_CONF1 + - name: HSCH5_DUTY_R + byte_offset: 116 + fieldset: HSCH_DUTY_R + - name: HSCH6_CONF0 + byte_offset: 120 + fieldset: HSCH_CONF0 + - name: HSCH6_HPOINT + byte_offset: 124 + fieldset: HSCH_HPOINT + - name: HSCH6_DUTY + byte_offset: 128 + fieldset: HSCH_DUTY + - name: HSCH6_CONF1 + byte_offset: 132 + fieldset: HSCH_CONF1 + - name: HSCH6_DUTY_R + byte_offset: 136 + fieldset: HSCH_DUTY_R + - name: HSCH7_CONF0 + byte_offset: 140 + fieldset: HSCH_CONF0 + - name: HSCH7_HPOINT + byte_offset: 144 + fieldset: HSCH_HPOINT + - name: HSCH7_DUTY + byte_offset: 148 + fieldset: HSCH_DUTY + - name: HSCH7_CONF1 + byte_offset: 152 + fieldset: HSCH_CONF1 + - name: HSCH7_DUTY_R + byte_offset: 156 + fieldset: HSCH_DUTY_R + - name: LSCH0_CONF0 byte_offset: 160 fieldset: LSCH_CONF0 - - name: LSCH_HPOINT - array: - len: 8 - stride: 20 + - name: LSCH0_HPOINT byte_offset: 164 fieldset: LSCH_HPOINT - - name: LSCH_DUTY - array: - len: 8 - stride: 20 + - name: LSCH0_DUTY byte_offset: 168 fieldset: LSCH_DUTY - - name: LSCH_CONF1 - array: - len: 8 - stride: 20 + - name: LSCH0_CONF1 byte_offset: 172 fieldset: LSCH_CONF1 - - name: LSCH_DUTY_R - array: - len: 8 - stride: 20 + - name: LSCH0_DUTY_R byte_offset: 176 fieldset: LSCH_DUTY_R - - name: HSTIMER_CONF - array: - len: 4 - stride: 8 + - name: LSCH1_CONF0 + byte_offset: 180 + fieldset: LSCH_CONF0 + - name: LSCH1_HPOINT + byte_offset: 184 + fieldset: LSCH_HPOINT + - name: LSCH1_DUTY + byte_offset: 188 + fieldset: LSCH_DUTY + - name: LSCH1_CONF1 + byte_offset: 192 + fieldset: LSCH_CONF1 + - name: LSCH1_DUTY_R + byte_offset: 196 + fieldset: LSCH_DUTY_R + - name: LSCH2_CONF0 + byte_offset: 200 + fieldset: LSCH_CONF0 + - name: LSCH2_HPOINT + byte_offset: 204 + fieldset: LSCH_HPOINT + - name: LSCH2_DUTY + byte_offset: 208 + fieldset: LSCH_DUTY + - name: LSCH2_CONF1 + byte_offset: 212 + fieldset: LSCH_CONF1 + - name: LSCH2_DUTY_R + byte_offset: 216 + fieldset: LSCH_DUTY_R + - name: LSCH3_CONF0 + byte_offset: 220 + fieldset: LSCH_CONF0 + - name: LSCH3_HPOINT + byte_offset: 224 + fieldset: LSCH_HPOINT + - name: LSCH3_DUTY + byte_offset: 228 + fieldset: LSCH_DUTY + - name: LSCH3_CONF1 + byte_offset: 232 + fieldset: LSCH_CONF1 + - name: LSCH3_DUTY_R + byte_offset: 236 + fieldset: LSCH_DUTY_R + - name: LSCH4_CONF0 + byte_offset: 240 + fieldset: LSCH_CONF0 + - name: LSCH4_HPOINT + byte_offset: 244 + fieldset: LSCH_HPOINT + - name: LSCH4_DUTY + byte_offset: 248 + fieldset: LSCH_DUTY + - name: LSCH4_CONF1 + byte_offset: 252 + fieldset: LSCH_CONF1 + - name: LSCH4_DUTY_R + byte_offset: 256 + fieldset: LSCH_DUTY_R + - name: LSCH5_CONF0 + byte_offset: 260 + fieldset: LSCH_CONF0 + - name: LSCH5_HPOINT + byte_offset: 264 + fieldset: LSCH_HPOINT + - name: LSCH5_DUTY + byte_offset: 268 + fieldset: LSCH_DUTY + - name: LSCH5_CONF1 + byte_offset: 272 + fieldset: LSCH_CONF1 + - name: LSCH5_DUTY_R + byte_offset: 276 + fieldset: LSCH_DUTY_R + - name: LSCH6_CONF0 + byte_offset: 280 + fieldset: LSCH_CONF0 + - name: LSCH6_HPOINT + byte_offset: 284 + fieldset: LSCH_HPOINT + - name: LSCH6_DUTY + byte_offset: 288 + fieldset: LSCH_DUTY + - name: LSCH6_CONF1 + byte_offset: 292 + fieldset: LSCH_CONF1 + - name: LSCH6_DUTY_R + byte_offset: 296 + fieldset: LSCH_DUTY_R + - name: LSCH7_CONF0 + byte_offset: 300 + fieldset: LSCH_CONF0 + - name: LSCH7_HPOINT + byte_offset: 304 + fieldset: LSCH_HPOINT + - name: LSCH7_DUTY + byte_offset: 308 + fieldset: LSCH_DUTY + - name: LSCH7_CONF1 + byte_offset: 312 + fieldset: LSCH_CONF1 + - name: LSCH7_DUTY_R + byte_offset: 316 + fieldset: LSCH_DUTY_R + - name: HSTIMER0_CONF byte_offset: 320 fieldset: HSTIMER_CONF - - name: HSTIMER_VALUE - array: - len: 4 - stride: 8 + - name: HSTIMER0_VALUE byte_offset: 324 fieldset: HSTIMER_VALUE - - name: LSTIMER_CONF - array: - len: 4 - stride: 8 + - name: HSTIMER1_CONF + byte_offset: 328 + fieldset: HSTIMER_CONF + - name: HSTIMER1_VALUE + byte_offset: 332 + fieldset: HSTIMER_VALUE + - name: HSTIMER2_CONF + byte_offset: 336 + fieldset: HSTIMER_CONF + - name: HSTIMER2_VALUE + byte_offset: 340 + fieldset: HSTIMER_VALUE + - name: HSTIMER3_CONF + byte_offset: 344 + fieldset: HSTIMER_CONF + - name: HSTIMER3_VALUE + byte_offset: 348 + fieldset: HSTIMER_VALUE + - name: LSTIMER0_CONF byte_offset: 352 fieldset: LSTIMER_CONF - - name: LSTIMER_VALUE - array: - len: 4 - stride: 8 + - name: LSTIMER0_VALUE byte_offset: 356 fieldset: LSTIMER_VALUE + - name: LSTIMER1_CONF + byte_offset: 360 + fieldset: LSTIMER_CONF + - name: LSTIMER1_VALUE + byte_offset: 364 + fieldset: LSTIMER_VALUE + - name: LSTIMER2_CONF + byte_offset: 368 + fieldset: LSTIMER_CONF + - name: LSTIMER2_VALUE + byte_offset: 372 + fieldset: LSTIMER_VALUE + - name: LSTIMER3_CONF + byte_offset: 376 + fieldset: LSTIMER_CONF + - name: LSTIMER3_VALUE + byte_offset: 380 + fieldset: LSTIMER_VALUE - name: INT_RAW byte_offset: 384 fieldset: INT_RAW diff --git a/base/esp32/PCNT.yaml b/head/esp32/PCNT.yaml index 103676c..c620563 100644 --- a/base/esp32/PCNT.yaml +++ b/head/esp32/PCNT.yaml @@ -1,30 +1,102 @@ block/PCNT: description: Pulse Count Controller. items: - - name: U_CONF0 - array: - len: 8 - stride: 12 + - name: U0_CONF0 byte_offset: 0 fieldset: U_CONF0 - - name: U_CONF1 - array: - len: 8 - stride: 12 + - name: U0_CONF1 byte_offset: 4 fieldset: U_CONF1 - - name: U_CONF2 - array: - len: 8 - stride: 12 + - name: U0_CONF2 byte_offset: 8 fieldset: U_CONF2 - - name: U_CNT - array: - len: 8 - stride: 4 + - name: U1_CONF0 + byte_offset: 12 + fieldset: U_CONF0 + - name: U1_CONF1 + byte_offset: 16 + fieldset: U_CONF1 + - name: U1_CONF2 + byte_offset: 20 + fieldset: U_CONF2 + - name: U2_CONF0 + byte_offset: 24 + fieldset: U_CONF0 + - name: U2_CONF1 + byte_offset: 28 + fieldset: U_CONF1 + - name: U2_CONF2 + byte_offset: 32 + fieldset: U_CONF2 + - name: U3_CONF0 + byte_offset: 36 + fieldset: U_CONF0 + - name: U3_CONF1 + byte_offset: 40 + fieldset: U_CONF1 + - name: U3_CONF2 + byte_offset: 44 + fieldset: U_CONF2 + - name: U4_CONF0 + byte_offset: 48 + fieldset: U_CONF0 + - name: U4_CONF1 + byte_offset: 52 + fieldset: U_CONF1 + - name: U4_CONF2 + byte_offset: 56 + fieldset: U_CONF2 + - name: U5_CONF0 + byte_offset: 60 + fieldset: U_CONF0 + - name: U5_CONF1 + byte_offset: 64 + fieldset: U_CONF1 + - name: U5_CONF2 + byte_offset: 68 + fieldset: U_CONF2 + - name: U6_CONF0 + byte_offset: 72 + fieldset: U_CONF0 + - name: U6_CONF1 + byte_offset: 76 + fieldset: U_CONF1 + - name: U6_CONF2 + byte_offset: 80 + fieldset: U_CONF2 + - name: U7_CONF0 + byte_offset: 84 + fieldset: U_CONF0 + - name: U7_CONF1 + byte_offset: 88 + fieldset: U_CONF1 + - name: U7_CONF2 + byte_offset: 92 + fieldset: U_CONF2 + - name: U0_CNT byte_offset: 96 fieldset: U_CNT + - name: U1_CNT + byte_offset: 100 + fieldset: U_CNT + - name: U2_CNT + byte_offset: 104 + fieldset: U_CNT + - name: U3_CNT + byte_offset: 108 + fieldset: U_CNT + - name: U4_CNT + byte_offset: 112 + fieldset: U_CNT + - name: U5_CNT + byte_offset: 116 + fieldset: U_CNT + - name: U6_CNT + byte_offset: 120 + fieldset: U_CNT + - name: U7_CNT + byte_offset: 124 + fieldset: U_CNT - name: INT_RAW byte_offset: 128 fieldset: INT_RAW @@ -37,12 +109,30 @@ block/PCNT: - name: INT_CLR byte_offset: 140 fieldset: INT_CLR - - name: U_STATUS - array: - len: 8 - stride: 4 + - name: U0_STATUS byte_offset: 144 fieldset: U_STATUS + - name: U1_STATUS + byte_offset: 148 + fieldset: U_STATUS + - name: U2_STATUS + byte_offset: 152 + fieldset: U_STATUS + - name: U3_STATUS + byte_offset: 156 + fieldset: U_STATUS + - name: U4_STATUS + byte_offset: 160 + fieldset: U_STATUS + - name: U5_STATUS + byte_offset: 164 + fieldset: U_STATUS + - name: U6_STATUS + byte_offset: 168 + fieldset: U_STATUS + - name: U7_STATUS + byte_offset: 172 + fieldset: U_STATUS - name: CTRL byte_offset: 176 fieldset: CTRL diff --git a/base/esp32/RMT.yaml b/head/esp32/RMT.yaml index a9d8002..6af3d35 100644 --- a/base/esp32/RMT.yaml +++ b/head/esp32/RMT.yaml @@ -1,35 +1,118 @@ block/RMT: description: Remote Control. items: - - name: CHDATA - array: - len: 8 - stride: 4 + - name: CH0DATA byte_offset: 0 - - name: CHCONF0 - array: - len: 8 - stride: 8 + - name: CH1DATA + byte_offset: 4 + - name: CH2DATA + byte_offset: 8 + - name: CH3DATA + byte_offset: 12 + - name: CH4DATA + byte_offset: 16 + - name: CH5DATA + byte_offset: 20 + - name: CH6DATA + byte_offset: 24 + - name: CH7DATA + byte_offset: 28 + - name: CH0CONF0 byte_offset: 32 fieldset: CHCONF0 - - name: CHCONF1 - array: - len: 8 - stride: 8 + - name: CH0CONF1 byte_offset: 36 fieldset: CHCONF1 - - name: CHSTATUS - array: - len: 8 - stride: 4 + - name: CH1CONF0 + byte_offset: 40 + fieldset: CHCONF0 + - name: CH1CONF1 + byte_offset: 44 + fieldset: CHCONF1 + - name: CH2CONF0 + byte_offset: 48 + fieldset: CHCONF0 + - name: CH2CONF1 + byte_offset: 52 + fieldset: CHCONF1 + - name: CH3CONF0 + byte_offset: 56 + fieldset: CHCONF0 + - name: CH3CONF1 + byte_offset: 60 + fieldset: CHCONF1 + - name: CH4CONF0 + byte_offset: 64 + fieldset: CHCONF0 + - name: CH4CONF1 + byte_offset: 68 + fieldset: CHCONF1 + - name: CH5CONF0 + byte_offset: 72 + fieldset: CHCONF0 + - name: CH5CONF1 + byte_offset: 76 + fieldset: CHCONF1 + - name: CH6CONF0 + byte_offset: 80 + fieldset: CHCONF0 + - name: CH6CONF1 + byte_offset: 84 + fieldset: CHCONF1 + - name: CH7CONF0 + byte_offset: 88 + fieldset: CHCONF0 + - name: CH7CONF1 + byte_offset: 92 + fieldset: CHCONF1 + - name: CH0STATUS byte_offset: 96 fieldset: CHSTATUS - - name: CHADDR - array: - len: 8 - stride: 4 + - name: CH1STATUS + byte_offset: 100 + fieldset: CHSTATUS + - name: CH2STATUS + byte_offset: 104 + fieldset: CHSTATUS + - name: CH3STATUS + byte_offset: 108 + fieldset: CHSTATUS + - name: CH4STATUS + byte_offset: 112 + fieldset: CHSTATUS + - name: CH5STATUS + byte_offset: 116 + fieldset: CHSTATUS + - name: CH6STATUS + byte_offset: 120 + fieldset: CHSTATUS + - name: CH7STATUS + byte_offset: 124 + fieldset: CHSTATUS + - name: CH0ADDR byte_offset: 128 fieldset: CHADDR + - name: CH1ADDR + byte_offset: 132 + fieldset: CHADDR + - name: CH2ADDR + byte_offset: 136 + fieldset: CHADDR + - name: CH3ADDR + byte_offset: 140 + fieldset: CHADDR + - name: CH4ADDR + byte_offset: 144 + fieldset: CHADDR + - name: CH5ADDR + byte_offset: 148 + fieldset: CHADDR + - name: CH6ADDR + byte_offset: 152 + fieldset: CHADDR + - name: CH7ADDR + byte_offset: 156 + fieldset: CHADDR - name: INT_RAW byte_offset: 160 fieldset: INT_RAW @@ -42,18 +125,54 @@ block/RMT: - name: INT_CLR byte_offset: 172 fieldset: INT_CLR - - name: CHCARRIER_DUTY - array: - len: 8 - stride: 4 + - name: CH0CARRIER_DUTY byte_offset: 176 fieldset: CHCARRIER_DUTY - - name: CH_TX_LIM - array: - len: 8 - stride: 4 + - name: CH1CARRIER_DUTY + byte_offset: 180 + fieldset: CHCARRIER_DUTY + - name: CH2CARRIER_DUTY + byte_offset: 184 + fieldset: CHCARRIER_DUTY + - name: CH3CARRIER_DUTY + byte_offset: 188 + fieldset: CHCARRIER_DUTY + - name: CH4CARRIER_DUTY + byte_offset: 192 + fieldset: CHCARRIER_DUTY + - name: CH5CARRIER_DUTY + byte_offset: 196 + fieldset: CHCARRIER_DUTY + - name: CH6CARRIER_DUTY + byte_offset: 200 + fieldset: CHCARRIER_DUTY + - name: CH7CARRIER_DUTY + byte_offset: 204 + fieldset: CHCARRIER_DUTY + - name: CH0_TX_LIM byte_offset: 208 fieldset: CH_TX_LIM + - name: CH1_TX_LIM + byte_offset: 212 + fieldset: CH_TX_LIM + - name: CH2_TX_LIM + byte_offset: 216 + fieldset: CH_TX_LIM + - name: CH3_TX_LIM + byte_offset: 220 + fieldset: CH_TX_LIM + - name: CH4_TX_LIM + byte_offset: 224 + fieldset: CH_TX_LIM + - name: CH5_TX_LIM + byte_offset: 228 + fieldset: CH_TX_LIM + - name: CH6_TX_LIM + byte_offset: 232 + fieldset: CH_TX_LIM + - name: CH7_TX_LIM + byte_offset: 236 + fieldset: CH_TX_LIM - name: APB_CONF byte_offset: 240 fieldset: APB_CONF @@ -222,121 +341,521 @@ fieldset/DATE: bit_size: 32 fieldset/INT_CLR: fields: - - name: CH_TX_END + - name: CH0_TX_END description: Set this bit to clear the rmt_ch%s_rx_end_int_raw.. bit_offset: 0 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_RX_END + - name: CH0_RX_END description: Set this bit to clear the rmt_ch%s_tx_end_int_raw. bit_offset: 1 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_ERR + - name: CH0_ERR description: Set this bit to clear the rmt_ch%s_err_int_raw. bit_offset: 2 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_TX_THR_EVENT + - name: CH1_TX_END + description: Set this bit to clear the rmt_ch%s_rx_end_int_raw.. + bit_offset: 3 + bit_size: 1 + - name: CH1_RX_END + description: Set this bit to clear the rmt_ch%s_tx_end_int_raw. + bit_offset: 4 + bit_size: 1 + - name: CH1_ERR + description: Set this bit to clear the rmt_ch%s_err_int_raw. + bit_offset: 5 + bit_size: 1 + - name: CH2_TX_END + description: Set this bit to clear the rmt_ch%s_rx_end_int_raw.. + bit_offset: 6 + bit_size: 1 + - name: CH2_RX_END + description: Set this bit to clear the rmt_ch%s_tx_end_int_raw. + bit_offset: 7 + bit_size: 1 + - name: CH2_ERR + description: Set this bit to clear the rmt_ch%s_err_int_raw. + bit_offset: 8 + bit_size: 1 + - name: CH3_TX_END + description: Set this bit to clear the rmt_ch%s_rx_end_int_raw.. + bit_offset: 9 + bit_size: 1 + - name: CH3_RX_END + description: Set this bit to clear the rmt_ch%s_tx_end_int_raw. + bit_offset: 10 + bit_size: 1 + - name: CH3_ERR + description: Set this bit to clear the rmt_ch%s_err_int_raw. + bit_offset: 11 + bit_size: 1 + - name: CH4_TX_END + description: Set this bit to clear the rmt_ch%s_rx_end_int_raw.. + bit_offset: 12 + bit_size: 1 + - name: CH4_RX_END + description: Set this bit to clear the rmt_ch%s_tx_end_int_raw. + bit_offset: 13 + bit_size: 1 + - name: CH4_ERR + description: Set this bit to clear the rmt_ch%s_err_int_raw. + bit_offset: 14 + bit_size: 1 + - name: CH5_TX_END + description: Set this bit to clear the rmt_ch%s_rx_end_int_raw.. + bit_offset: 15 + bit_size: 1 + - name: CH5_RX_END + description: Set this bit to clear the rmt_ch%s_tx_end_int_raw. + bit_offset: 16 + bit_size: 1 + - name: CH5_ERR + description: Set this bit to clear the rmt_ch%s_err_int_raw. + bit_offset: 17 + bit_size: 1 + - name: CH6_TX_END + description: Set this bit to clear the rmt_ch%s_rx_end_int_raw.. + bit_offset: 18 + bit_size: 1 + - name: CH6_RX_END + description: Set this bit to clear the rmt_ch%s_tx_end_int_raw. + bit_offset: 19 + bit_size: 1 + - name: CH6_ERR + description: Set this bit to clear the rmt_ch%s_err_int_raw. + bit_offset: 20 + bit_size: 1 + - name: CH7_TX_END + description: Set this bit to clear the rmt_ch%s_rx_end_int_raw.. + bit_offset: 21 + bit_size: 1 + - name: CH7_RX_END + description: Set this bit to clear the rmt_ch%s_tx_end_int_raw. + bit_offset: 22 + bit_size: 1 + - name: CH7_ERR + description: Set this bit to clear the rmt_ch%s_err_int_raw. + bit_offset: 23 + bit_size: 1 + - name: CH0_TX_THR_EVENT description: Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. bit_offset: 24 bit_size: 1 - array: - len: 8 - stride: 1 + - name: CH1_TX_THR_EVENT + description: Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. + bit_offset: 25 + bit_size: 1 + - name: CH2_TX_THR_EVENT + description: Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. + bit_offset: 26 + bit_size: 1 + - name: CH3_TX_THR_EVENT + description: Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. + bit_offset: 27 + bit_size: 1 + - name: CH4_TX_THR_EVENT + description: Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. + bit_offset: 28 + bit_size: 1 + - name: CH5_TX_THR_EVENT + description: Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. + bit_offset: 29 + bit_size: 1 + - name: CH6_TX_THR_EVENT + description: Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. + bit_offset: 30 + bit_size: 1 + - name: CH7_TX_THR_EVENT + description: Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. + bit_offset: 31 + bit_size: 1 fieldset/INT_ENA: fields: - - name: CH_TX_END + - name: CH0_TX_END description: Set this bit to enable rmt_ch%s_tx_end_int_st. bit_offset: 0 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_RX_END + - name: CH0_RX_END description: Set this bit to enable rmt_ch%s_rx_end_int_st. bit_offset: 1 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_ERR + - name: CH0_ERR description: Set this bit to enable rmt_ch%s_err_int_st. bit_offset: 2 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_TX_THR_EVENT + - name: CH1_TX_END + description: Set this bit to enable rmt_ch%s_tx_end_int_st. + bit_offset: 3 + bit_size: 1 + - name: CH1_RX_END + description: Set this bit to enable rmt_ch%s_rx_end_int_st. + bit_offset: 4 + bit_size: 1 + - name: CH1_ERR + description: Set this bit to enable rmt_ch%s_err_int_st. + bit_offset: 5 + bit_size: 1 + - name: CH2_TX_END + description: Set this bit to enable rmt_ch%s_tx_end_int_st. + bit_offset: 6 + bit_size: 1 + - name: CH2_RX_END + description: Set this bit to enable rmt_ch%s_rx_end_int_st. + bit_offset: 7 + bit_size: 1 + - name: CH2_ERR + description: Set this bit to enable rmt_ch%s_err_int_st. + bit_offset: 8 + bit_size: 1 + - name: CH3_TX_END + description: Set this bit to enable rmt_ch%s_tx_end_int_st. + bit_offset: 9 + bit_size: 1 + - name: CH3_RX_END + description: Set this bit to enable rmt_ch%s_rx_end_int_st. + bit_offset: 10 + bit_size: 1 + - name: CH3_ERR + description: Set this bit to enable rmt_ch%s_err_int_st. + bit_offset: 11 + bit_size: 1 + - name: CH4_TX_END + description: Set this bit to enable rmt_ch%s_tx_end_int_st. + bit_offset: 12 + bit_size: 1 + - name: CH4_RX_END + description: Set this bit to enable rmt_ch%s_rx_end_int_st. + bit_offset: 13 + bit_size: 1 + - name: CH4_ERR + description: Set this bit to enable rmt_ch%s_err_int_st. + bit_offset: 14 + bit_size: 1 + - name: CH5_TX_END + description: Set this bit to enable rmt_ch%s_tx_end_int_st. + bit_offset: 15 + bit_size: 1 + - name: CH5_RX_END + description: Set this bit to enable rmt_ch%s_rx_end_int_st. + bit_offset: 16 + bit_size: 1 + - name: CH5_ERR + description: Set this bit to enable rmt_ch%s_err_int_st. + bit_offset: 17 + bit_size: 1 + - name: CH6_TX_END + description: Set this bit to enable rmt_ch%s_tx_end_int_st. + bit_offset: 18 + bit_size: 1 + - name: CH6_RX_END + description: Set this bit to enable rmt_ch%s_rx_end_int_st. + bit_offset: 19 + bit_size: 1 + - name: CH6_ERR + description: Set this bit to enable rmt_ch%s_err_int_st. + bit_offset: 20 + bit_size: 1 + - name: CH7_TX_END + description: Set this bit to enable rmt_ch%s_tx_end_int_st. + bit_offset: 21 + bit_size: 1 + - name: CH7_RX_END + description: Set this bit to enable rmt_ch%s_rx_end_int_st. + bit_offset: 22 + bit_size: 1 + - name: CH7_ERR + description: Set this bit to enable rmt_ch%s_err_int_st. + bit_offset: 23 + bit_size: 1 + - name: CH0_TX_THR_EVENT description: Set this bit to enable rmt_ch%s_tx_thr_event_int_st. bit_offset: 24 bit_size: 1 - array: - len: 8 - stride: 1 + - name: CH1_TX_THR_EVENT + description: Set this bit to enable rmt_ch%s_tx_thr_event_int_st. + bit_offset: 25 + bit_size: 1 + - name: CH2_TX_THR_EVENT + description: Set this bit to enable rmt_ch%s_tx_thr_event_int_st. + bit_offset: 26 + bit_size: 1 + - name: CH3_TX_THR_EVENT + description: Set this bit to enable rmt_ch%s_tx_thr_event_int_st. + bit_offset: 27 + bit_size: 1 + - name: CH4_TX_THR_EVENT + description: Set this bit to enable rmt_ch%s_tx_thr_event_int_st. + bit_offset: 28 + bit_size: 1 + - name: CH5_TX_THR_EVENT + description: Set this bit to enable rmt_ch%s_tx_thr_event_int_st. + bit_offset: 29 + bit_size: 1 + - name: CH6_TX_THR_EVENT + description: Set this bit to enable rmt_ch%s_tx_thr_event_int_st. + bit_offset: 30 + bit_size: 1 + - name: CH7_TX_THR_EVENT + description: Set this bit to enable rmt_ch%s_tx_thr_event_int_st. + bit_offset: 31 + bit_size: 1 fieldset/INT_RAW: fields: - - name: CH_TX_END + - name: CH0_TX_END description: The interrupt raw bit for channel %s turns to high level when the transmit process is done. bit_offset: 0 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_RX_END + - name: CH0_RX_END description: The interrupt raw bit for channel %s turns to high level when the receive process is done. bit_offset: 1 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_ERR + - name: CH0_ERR description: The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. bit_offset: 2 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_TX_THR_EVENT + - name: CH1_TX_END + description: The interrupt raw bit for channel %s turns to high level when the transmit process is done. + bit_offset: 3 + bit_size: 1 + - name: CH1_RX_END + description: The interrupt raw bit for channel %s turns to high level when the receive process is done. + bit_offset: 4 + bit_size: 1 + - name: CH1_ERR + description: The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. + bit_offset: 5 + bit_size: 1 + - name: CH2_TX_END + description: The interrupt raw bit for channel %s turns to high level when the transmit process is done. + bit_offset: 6 + bit_size: 1 + - name: CH2_RX_END + description: The interrupt raw bit for channel %s turns to high level when the receive process is done. + bit_offset: 7 + bit_size: 1 + - name: CH2_ERR + description: The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. + bit_offset: 8 + bit_size: 1 + - name: CH3_TX_END + description: The interrupt raw bit for channel %s turns to high level when the transmit process is done. + bit_offset: 9 + bit_size: 1 + - name: CH3_RX_END + description: The interrupt raw bit for channel %s turns to high level when the receive process is done. + bit_offset: 10 + bit_size: 1 + - name: CH3_ERR + description: The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. + bit_offset: 11 + bit_size: 1 + - name: CH4_TX_END + description: The interrupt raw bit for channel %s turns to high level when the transmit process is done. + bit_offset: 12 + bit_size: 1 + - name: CH4_RX_END + description: The interrupt raw bit for channel %s turns to high level when the receive process is done. + bit_offset: 13 + bit_size: 1 + - name: CH4_ERR + description: The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. + bit_offset: 14 + bit_size: 1 + - name: CH5_TX_END + description: The interrupt raw bit for channel %s turns to high level when the transmit process is done. + bit_offset: 15 + bit_size: 1 + - name: CH5_RX_END + description: The interrupt raw bit for channel %s turns to high level when the receive process is done. + bit_offset: 16 + bit_size: 1 + - name: CH5_ERR + description: The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. + bit_offset: 17 + bit_size: 1 + - name: CH6_TX_END + description: The interrupt raw bit for channel %s turns to high level when the transmit process is done. + bit_offset: 18 + bit_size: 1 + - name: CH6_RX_END + description: The interrupt raw bit for channel %s turns to high level when the receive process is done. + bit_offset: 19 + bit_size: 1 + - name: CH6_ERR + description: The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. + bit_offset: 20 + bit_size: 1 + - name: CH7_TX_END + description: The interrupt raw bit for channel %s turns to high level when the transmit process is done. + bit_offset: 21 + bit_size: 1 + - name: CH7_RX_END + description: The interrupt raw bit for channel %s turns to high level when the receive process is done. + bit_offset: 22 + bit_size: 1 + - name: CH7_ERR + description: The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. + bit_offset: 23 + bit_size: 1 + - name: CH0_TX_THR_EVENT description: The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. bit_offset: 24 bit_size: 1 - array: - len: 8 - stride: 1 + - name: CH1_TX_THR_EVENT + description: The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. + bit_offset: 25 + bit_size: 1 + - name: CH2_TX_THR_EVENT + description: The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. + bit_offset: 26 + bit_size: 1 + - name: CH3_TX_THR_EVENT + description: The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. + bit_offset: 27 + bit_size: 1 + - name: CH4_TX_THR_EVENT + description: The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. + bit_offset: 28 + bit_size: 1 + - name: CH5_TX_THR_EVENT + description: The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. + bit_offset: 29 + bit_size: 1 + - name: CH6_TX_THR_EVENT + description: The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. + bit_offset: 30 + bit_size: 1 + - name: CH7_TX_THR_EVENT + description: The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. + bit_offset: 31 + bit_size: 1 fieldset/INT_ST: fields: - - name: CH_TX_END + - name: CH0_TX_END description: The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s. bit_offset: 0 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_RX_END + - name: CH0_RX_END description: The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s. bit_offset: 1 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_ERR + - name: CH0_ERR description: The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s. bit_offset: 2 bit_size: 1 - array: - len: 8 - stride: 3 - - name: CH_TX_THR_EVENT + - name: CH1_TX_END + description: The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s. + bit_offset: 3 + bit_size: 1 + - name: CH1_RX_END + description: The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s. + bit_offset: 4 + bit_size: 1 + - name: CH1_ERR + description: The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s. + bit_offset: 5 + bit_size: 1 + - name: CH2_TX_END + description: The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s. + bit_offset: 6 + bit_size: 1 + - name: CH2_RX_END + description: The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s. + bit_offset: 7 + bit_size: 1 + - name: CH2_ERR + description: The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s. + bit_offset: 8 + bit_size: 1 + - name: CH3_TX_END + description: The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s. + bit_offset: 9 + bit_size: 1 + - name: CH3_RX_END + description: The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s. + bit_offset: 10 + bit_size: 1 + - name: CH3_ERR + description: The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s. + bit_offset: 11 + bit_size: 1 + - name: CH4_TX_END + description: The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s. + bit_offset: 12 + bit_size: 1 + - name: CH4_RX_END + description: The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s. + bit_offset: 13 + bit_size: 1 + - name: CH4_ERR + description: The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s. + bit_offset: 14 + bit_size: 1 + - name: CH5_TX_END + description: The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s. + bit_offset: 15 + bit_size: 1 + - name: CH5_RX_END + description: The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s. + bit_offset: 16 + bit_size: 1 + - name: CH5_ERR + description: The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s. + bit_offset: 17 + bit_size: 1 + - name: CH6_TX_END + description: The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s. + bit_offset: 18 + bit_size: 1 + - name: CH6_RX_END + description: The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s. + bit_offset: 19 + bit_size: 1 + - name: CH6_ERR + description: The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s. + bit_offset: 20 + bit_size: 1 + - name: CH7_TX_END + description: The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s. + bit_offset: 21 + bit_size: 1 + - name: CH7_RX_END + description: The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s. + bit_offset: 22 + bit_size: 1 + - name: CH7_ERR + description: The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s. + bit_offset: 23 + bit_size: 1 + - name: CH0_TX_THR_EVENT description: The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1. bit_offset: 24 bit_size: 1 - array: - len: 8 - stride: 1 + - name: CH1_TX_THR_EVENT + description: The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1. + bit_offset: 25 + bit_size: 1 + - name: CH2_TX_THR_EVENT + description: The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1. + bit_offset: 26 + bit_size: 1 + - name: CH3_TX_THR_EVENT + description: The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1. + bit_offset: 27 + bit_size: 1 + - name: CH4_TX_THR_EVENT + description: The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1. + bit_offset: 28 + bit_size: 1 + - name: CH5_TX_THR_EVENT + description: The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1. + bit_offset: 29 + bit_size: 1 + - name: CH6_TX_THR_EVENT + description: The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1. + bit_offset: 30 + bit_size: 1 + - name: CH7_TX_THR_EVENT + description: The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1. + bit_offset: 31 + bit_size: 1 diff --git a/base/esp32/RTC_IO.yaml b/head/esp32/RTC_IO.yaml index b0c896a..10f4167 100644 --- a/base/esp32/RTC_IO.yaml +++ b/head/esp32/RTC_IO.yaml @@ -31,12 +31,60 @@ block/RTC_IO: - name: IN byte_offset: 36 fieldset: IN - - name: PIN - array: - len: 18 - stride: 4 + - name: PIN0 byte_offset: 40 fieldset: PIN + - name: PIN1 + byte_offset: 44 + fieldset: PIN + - name: PIN2 + byte_offset: 48 + fieldset: PIN + - name: PIN3 + byte_offset: 52 + fieldset: PIN + - name: PIN4 + byte_offset: 56 + fieldset: PIN + - name: PIN5 + byte_offset: 60 + fieldset: PIN + - name: PIN6 + byte_offset: 64 + fieldset: PIN + - name: PIN7 + byte_offset: 68 + fieldset: PIN + - name: PIN8 + byte_offset: 72 + fieldset: PIN + - name: PIN9 + byte_offset: 76 + fieldset: PIN + - name: PIN10 + byte_offset: 80 + fieldset: PIN + - name: PIN11 + byte_offset: 84 + fieldset: PIN + - name: PIN12 + byte_offset: 88 + fieldset: PIN + - name: PIN13 + byte_offset: 92 + fieldset: PIN + - name: PIN14 + byte_offset: 96 + fieldset: PIN + - name: PIN15 + byte_offset: 100 + fieldset: PIN + - name: PIN16 + byte_offset: 104 + fieldset: PIN + - name: PIN17 + byte_offset: 108 + fieldset: PIN - name: RTC_DEBUG_SEL byte_offset: 112 fieldset: RTC_DEBUG_SEL diff --git a/base/esp32/SHA.yaml b/head/esp32/SHA.yaml index e234c49..ed40bb6 100644 --- a/base/esp32/SHA.yaml +++ b/head/esp32/SHA.yaml @@ -1,12 +1,6 @@ block/SHA: description: SHA (Secure Hash Algorithm) Accelerator. items: - - name: TEXT - array: - len: 32 - stride: 4 - byte_offset: 0 - fieldset: TEXT - name: SHA1_START byte_offset: 128 fieldset: SHA1_START diff --git a/base/esp32c3/DMA.yaml b/head/esp32c3/DMA.yaml index e52a46e..4cd1013 100644 --- a/base/esp32c3/DMA.yaml +++ b/head/esp32c3/DMA.yaml @@ -1,39 +1,54 @@ block/DMA: description: DMA (Direct Memory Access) Controller. items: - - name: INT_RAW_CH + - name: INT_RAW_CH0 description: DMA_INT_RAW_CH%s_REG. - array: - len: 3 - stride: 16 byte_offset: 0 fieldset: INT_RAW_CH - name: INT_ST_CH0 description: DMA_INT_ST_CH0_REG. byte_offset: 4 fieldset: INT_ST_CH0 - - name: INT_ENA_CH + - name: INT_ENA_CH0 description: DMA_INT_ENA_CH%s_REG. - array: - len: 3 - stride: 16 byte_offset: 8 fieldset: INT_ENA_CH - - name: INT_CLR_CH + - name: INT_CLR_CH0 description: DMA_INT_CLR_CH%s_REG. - array: - len: 3 - stride: 16 byte_offset: 12 fieldset: INT_CLR_CH + - name: INT_RAW_CH1 + description: DMA_INT_RAW_CH%s_REG. + byte_offset: 16 + fieldset: INT_RAW_CH - name: INT_ST_CH1 description: DMA_INT_ST_CH1_REG. byte_offset: 20 fieldset: INT_ST_CH1 + - name: INT_ENA_CH1 + description: DMA_INT_ENA_CH%s_REG. + byte_offset: 24 + fieldset: INT_ENA_CH + - name: INT_CLR_CH1 + description: DMA_INT_CLR_CH%s_REG. + byte_offset: 28 + fieldset: INT_CLR_CH + - name: INT_RAW_CH2 + description: DMA_INT_RAW_CH%s_REG. + byte_offset: 32 + fieldset: INT_RAW_CH - name: INT_ST_CH2 description: DMA_INT_ST_CH2_REG. byte_offset: 36 fieldset: INT_ST_CH2 + - name: INT_ENA_CH2 + description: DMA_INT_ENA_CH%s_REG. + byte_offset: 40 + fieldset: INT_ENA_CH + - name: INT_CLR_CH2 + description: DMA_INT_CLR_CH%s_REG. + byte_offset: 44 + fieldset: INT_CLR_CH - name: AHB_TEST description: DMA_AHB_TEST_REG. byte_offset: 64 @@ -46,11 +61,8 @@ block/DMA: description: DMA_DATE_REG. byte_offset: 72 fieldset: DATE - - name: IN_CONF0_CH + - name: IN_CONF0_CH0 description: DMA_IN_CONF%s_CH%s_REG. - array: - len: 3 - stride: 192 byte_offset: 112 fieldset: IN_CONF0_CH - name: IN_CONF1_CH0 @@ -65,11 +77,8 @@ block/DMA: description: DMA_IN_POP_CH0_REG. byte_offset: 124 fieldset: IN_POP_CH0 - - name: IN_LINK_CH + - name: IN_LINK_CH0 description: DMA_IN_LINK_CH%s_REG. - array: - len: 3 - stride: 192 byte_offset: 128 fieldset: IN_LINK_CH - name: IN_STATE_CH0 @@ -88,43 +97,28 @@ block/DMA: description: DMA_IN_DSCR_CH0_REG. byte_offset: 144 fieldset: IN_DSCR_CH0 - - name: IN_DSCR_BF0_CH + - name: IN_DSCR_BF0_CH0 description: DMA_IN_DSCR_BF%s_CH%s_REG. - array: - len: 3 - stride: 192 byte_offset: 148 fieldset: IN_DSCR_BF0_CH - name: IN_DSCR_BF1_CH0 description: DMA_IN_DSCR_BF1_CH0_REG. byte_offset: 152 fieldset: IN_DSCR_BF1_CH0 - - name: IN_PRI_CH + - name: IN_PRI_CH0 description: DMA_IN_PRI_CH%s_REG. - array: - len: 3 - stride: 192 byte_offset: 156 fieldset: IN_PRI_CH - - name: IN_PERI_SEL_CH + - name: IN_PERI_SEL_CH0 description: DMA_IN_PERI_SEL_CH%s_REG. - array: - len: 3 - stride: 192 byte_offset: 160 fieldset: IN_PERI_SEL_CH - - name: OUT_CONF0_CH + - name: OUT_CONF0_CH0 description: DMA_OUT_CONF%s_CH%s_REG. - array: - len: 3 - stride: 192 byte_offset: 208 fieldset: OUT_CONF0_CH - - name: OUT_CONF1_CH + - name: OUT_CONF1_CH0 description: DMA_OUT_CONF1_CH%s_REG. - array: - len: 3 - stride: 192 byte_offset: 212 fieldset: OUT_CONF1_CH - name: OUTFIFO_STATUS_CH0 @@ -135,22 +129,16 @@ block/DMA: description: DMA_OUT_PUSH_CH0_REG. byte_offset: 220 fieldset: OUT_PUSH_CH0 - - name: OUT_LINK_CH + - name: OUT_LINK_CH0 description: DMA_OUT_LINK_CH%s_REG. - array: - len: 3 - stride: 192 byte_offset: 224 fieldset: OUT_LINK_CH - name: OUT_STATE_CH0 description: DMA_OUT_STATE_CH0_REG. byte_offset: 228 fieldset: OUT_STATE_CH0 - - name: OUT_EOF_DES_ADDR_CH + - name: OUT_EOF_DES_ADDR_CH0 description: DMA_OUT_EOF_DES_ADDR_CH%s_REG. - array: - len: 3 - stride: 192 byte_offset: 232 fieldset: OUT_EOF_DES_ADDR_CH - name: OUT_EOF_BFR_DES_ADDR_CH0 @@ -169,20 +157,18 @@ block/DMA: description: DMA_OUT_DSCR_BF1_CH0_REG. byte_offset: 248 fieldset: OUT_DSCR_BF1_CH0 - - name: OUT_PRI_CH + - name: OUT_PRI_CH0 description: DMA_OUT_PRI_CH%s_REG. - array: - len: 3 - stride: 192 byte_offset: 252 fieldset: OUT_PRI_CH - - name: OUT_PERI_SEL_CH + - name: OUT_PERI_SEL_CH0 description: DMA_OUT_PERI_SEL_CH%s_REG. - array: - len: 3 - stride: 192 byte_offset: 256 fieldset: OUT_PERI_SEL_CH + - name: IN_CONF0_CH1 + description: DMA_IN_CONF%s_CH%s_REG. + byte_offset: 304 + fieldset: IN_CONF0_CH - name: IN_CONF1_CH1 description: DMA_IN_CONF1_CH1_REG. byte_offset: 308 @@ -195,6 +181,10 @@ block/DMA: description: DMA_IN_POP_CH1_REG. byte_offset: 316 fieldset: IN_POP_CH1 + - name: IN_LINK_CH1 + description: DMA_IN_LINK_CH%s_REG. + byte_offset: 320 + fieldset: IN_LINK_CH - name: IN_STATE_CH1 description: DMA_IN_STATE_CH1_REG. byte_offset: 324 @@ -211,10 +201,30 @@ block/DMA: description: DMA_IN_DSCR_CH1_REG. byte_offset: 336 fieldset: IN_DSCR_CH1 + - name: IN_DSCR_BF0_CH1 + description: DMA_IN_DSCR_BF%s_CH%s_REG. + byte_offset: 340 + fieldset: IN_DSCR_BF0_CH - name: IN_DSCR_BF1_CH1 description: DMA_IN_DSCR_BF1_CH1_REG. byte_offset: 344 fieldset: IN_DSCR_BF1_CH1 + - name: IN_PRI_CH1 + description: DMA_IN_PRI_CH%s_REG. + byte_offset: 348 + fieldset: IN_PRI_CH + - name: IN_PERI_SEL_CH1 + description: DMA_IN_PERI_SEL_CH%s_REG. + byte_offset: 352 + fieldset: IN_PERI_SEL_CH + - name: OUT_CONF0_CH1 + description: DMA_OUT_CONF%s_CH%s_REG. + byte_offset: 400 + fieldset: OUT_CONF0_CH + - name: OUT_CONF1_CH1 + description: DMA_OUT_CONF1_CH%s_REG. + byte_offset: 404 + fieldset: OUT_CONF1_CH - name: OUTFIFO_STATUS_CH1 description: DMA_OUTFIFO_STATUS_CH1_REG. byte_offset: 408 @@ -223,10 +233,18 @@ block/DMA: description: DMA_OUT_PUSH_CH1_REG. byte_offset: 412 fieldset: OUT_PUSH_CH1 + - name: OUT_LINK_CH1 + description: DMA_OUT_LINK_CH%s_REG. + byte_offset: 416 + fieldset: OUT_LINK_CH - name: OUT_STATE_CH1 description: DMA_OUT_STATE_CH1_REG. byte_offset: 420 fieldset: OUT_STATE_CH1 + - name: OUT_EOF_DES_ADDR_CH1 + description: DMA_OUT_EOF_DES_ADDR_CH%s_REG. + byte_offset: 424 + fieldset: OUT_EOF_DES_ADDR_CH - name: OUT_EOF_BFR_DES_ADDR_CH1 description: DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. byte_offset: 428 @@ -243,6 +261,18 @@ block/DMA: description: DMA_OUT_DSCR_BF1_CH1_REG. byte_offset: 440 fieldset: OUT_DSCR_BF1_CH1 + - name: OUT_PRI_CH1 + description: DMA_OUT_PRI_CH%s_REG. + byte_offset: 444 + fieldset: OUT_PRI_CH + - name: OUT_PERI_SEL_CH1 + description: DMA_OUT_PERI_SEL_CH%s_REG. + byte_offset: 448 + fieldset: OUT_PERI_SEL_CH + - name: IN_CONF0_CH2 + description: DMA_IN_CONF%s_CH%s_REG. + byte_offset: 496 + fieldset: IN_CONF0_CH - name: IN_CONF1_CH2 description: DMA_IN_CONF1_CH2_REG. byte_offset: 500 @@ -255,6 +285,10 @@ block/DMA: description: DMA_IN_POP_CH2_REG. byte_offset: 508 fieldset: IN_POP_CH2 + - name: IN_LINK_CH2 + description: DMA_IN_LINK_CH%s_REG. + byte_offset: 512 + fieldset: IN_LINK_CH - name: IN_STATE_CH2 description: DMA_IN_STATE_CH2_REG. byte_offset: 516 @@ -271,10 +305,30 @@ block/DMA: description: DMA_IN_DSCR_CH2_REG. byte_offset: 528 fieldset: IN_DSCR_CH2 + - name: IN_DSCR_BF0_CH2 + description: DMA_IN_DSCR_BF%s_CH%s_REG. + byte_offset: 532 + fieldset: IN_DSCR_BF0_CH - name: IN_DSCR_BF1_CH2 description: DMA_IN_DSCR_BF1_CH2_REG. byte_offset: 536 fieldset: IN_DSCR_BF1_CH2 + - name: IN_PRI_CH2 + description: DMA_IN_PRI_CH%s_REG. + byte_offset: 540 + fieldset: IN_PRI_CH + - name: IN_PERI_SEL_CH2 + description: DMA_IN_PERI_SEL_CH%s_REG. + byte_offset: 544 + fieldset: IN_PERI_SEL_CH + - name: OUT_CONF0_CH2 + description: DMA_OUT_CONF%s_CH%s_REG. + byte_offset: 592 + fieldset: OUT_CONF0_CH + - name: OUT_CONF1_CH2 + description: DMA_OUT_CONF1_CH%s_REG. + byte_offset: 596 + fieldset: OUT_CONF1_CH - name: OUTFIFO_STATUS_CH2 description: DMA_OUTFIFO_STATUS_CH2_REG. byte_offset: 600 @@ -283,10 +337,18 @@ block/DMA: description: DMA_OUT_PUSH_CH2_REG. byte_offset: 604 fieldset: OUT_PUSH_CH2 + - name: OUT_LINK_CH2 + description: DMA_OUT_LINK_CH%s_REG. + byte_offset: 608 + fieldset: OUT_LINK_CH - name: OUT_STATE_CH2 description: DMA_OUT_STATE_CH2_REG. byte_offset: 612 fieldset: OUT_STATE_CH2 + - name: OUT_EOF_DES_ADDR_CH2 + description: DMA_OUT_EOF_DES_ADDR_CH%s_REG. + byte_offset: 616 + fieldset: OUT_EOF_DES_ADDR_CH - name: OUT_EOF_BFR_DES_ADDR_CH2 description: DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. byte_offset: 620 @@ -303,6 +365,14 @@ block/DMA: description: DMA_OUT_DSCR_BF1_CH2_REG. byte_offset: 632 fieldset: OUT_DSCR_BF1_CH2 + - name: OUT_PRI_CH2 + description: DMA_OUT_PRI_CH%s_REG. + byte_offset: 636 + fieldset: OUT_PRI_CH + - name: OUT_PERI_SEL_CH2 + description: DMA_OUT_PERI_SEL_CH%s_REG. + byte_offset: 640 + fieldset: OUT_PERI_SEL_CH fieldset/AHB_TEST: description: DMA_AHB_TEST_REG. fields: diff --git a/base/esp32c3/GPIO.yaml b/head/esp32c3/GPIO.yaml index 785da05..73f4204 100644 --- a/base/esp32c3/GPIO.yaml +++ b/head/esp32c3/GPIO.yaml @@ -65,31 +65,730 @@ block/GPIO: description: GPIO CPUSDIO interrupt status register. byte_offset: 100 fieldset: CPUSDIO_INT - - name: PIN + - name: PIN0 description: GPIO pin configuration register. - array: - len: 26 - stride: 4 byte_offset: 116 fieldset: PIN + - name: PIN1 + description: GPIO pin configuration register. + byte_offset: 120 + fieldset: PIN + - name: PIN2 + description: GPIO pin configuration register. + byte_offset: 124 + fieldset: PIN + - name: PIN3 + description: GPIO pin configuration register. + byte_offset: 128 + fieldset: PIN + - name: PIN4 + description: GPIO pin configuration register. + byte_offset: 132 + fieldset: PIN + - name: PIN5 + description: GPIO pin configuration register. + byte_offset: 136 + fieldset: PIN + - name: PIN6 + description: GPIO pin configuration register. + byte_offset: 140 + fieldset: PIN + - name: PIN7 + description: GPIO pin configuration register. + byte_offset: 144 + fieldset: PIN + - name: PIN8 + description: GPIO pin configuration register. + byte_offset: 148 + fieldset: PIN + - name: PIN9 + description: GPIO pin configuration register. + byte_offset: 152 + fieldset: PIN + - name: PIN10 + description: GPIO pin configuration register. + byte_offset: 156 + fieldset: PIN + - name: PIN11 + description: GPIO pin configuration register. + byte_offset: 160 + fieldset: PIN + - name: PIN12 + description: GPIO pin configuration register. + byte_offset: 164 + fieldset: PIN + - name: PIN13 + description: GPIO pin configuration register. + byte_offset: 168 + fieldset: PIN + - name: PIN14 + description: GPIO pin configuration register. + byte_offset: 172 + fieldset: PIN + - name: PIN15 + description: GPIO pin configuration register. + byte_offset: 176 + fieldset: PIN + - name: PIN16 + description: GPIO pin configuration register. + byte_offset: 180 + fieldset: PIN + - name: PIN17 + description: GPIO pin configuration register. + byte_offset: 184 + fieldset: PIN + - name: PIN18 + description: GPIO pin configuration register. + byte_offset: 188 + fieldset: PIN + - name: PIN19 + description: GPIO pin configuration register. + byte_offset: 192 + fieldset: PIN + - name: PIN20 + description: GPIO pin configuration register. + byte_offset: 196 + fieldset: PIN + - name: PIN21 + description: GPIO pin configuration register. + byte_offset: 200 + fieldset: PIN + - name: PIN22 + description: GPIO pin configuration register. + byte_offset: 204 + fieldset: PIN + - name: PIN23 + description: GPIO pin configuration register. + byte_offset: 208 + fieldset: PIN + - name: PIN24 + description: GPIO pin configuration register. + byte_offset: 212 + fieldset: PIN + - name: PIN25 + description: GPIO pin configuration register. + byte_offset: 216 + fieldset: PIN - name: STATUS_NEXT description: GPIO interrupt source register. byte_offset: 332 fieldset: STATUS_NEXT - - name: FUNC_IN_SEL_CFG + - name: FUNC0_IN_SEL_CFG description: GPIO input function configuration register. - array: - len: 128 - stride: 4 byte_offset: 340 fieldset: FUNC_IN_SEL_CFG - - name: FUNC_OUT_SEL_CFG + - name: FUNC1_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 344 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC2_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 348 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC3_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 352 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC4_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 356 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC5_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 360 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC6_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 364 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC7_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 368 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC8_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 372 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC9_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 376 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC10_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 380 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC11_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 384 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC12_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 388 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC13_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 392 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC14_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 396 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC15_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 400 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC16_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 404 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC17_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 408 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC18_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 412 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC19_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 416 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC20_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 420 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC21_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 424 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC22_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 428 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC23_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 432 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC24_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 436 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC25_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 440 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC26_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 444 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC27_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 448 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC28_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 452 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC29_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 456 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC30_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 460 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC31_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 464 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC32_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 468 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC33_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 472 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC34_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 476 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC35_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 480 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC36_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 484 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC37_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 488 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC38_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 492 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC39_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 496 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC40_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 500 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC41_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 504 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC42_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 508 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC43_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 512 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC44_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 516 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC45_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 520 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC46_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 524 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC47_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 528 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC48_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 532 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC49_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 536 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC50_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 540 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC51_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 544 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC52_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 548 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC53_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 552 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC54_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 556 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC55_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 560 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC56_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 564 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC57_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 568 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC58_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 572 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC59_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 576 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC60_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 580 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC61_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 584 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC62_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 588 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC63_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 592 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC64_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 596 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC65_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 600 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC66_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 604 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC67_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 608 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC68_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 612 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC69_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 616 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC70_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 620 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC71_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 624 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC72_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 628 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC73_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 632 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC74_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 636 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC75_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 640 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC76_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 644 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC77_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 648 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC78_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 652 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC79_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 656 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC80_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 660 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC81_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 664 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC82_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 668 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC83_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 672 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC84_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 676 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC85_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 680 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC86_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 684 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC87_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 688 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC88_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 692 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC89_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 696 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC90_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 700 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC91_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 704 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC92_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 708 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC93_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 712 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC94_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 716 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC95_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 720 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC96_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 724 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC97_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 728 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC98_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 732 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC99_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 736 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC100_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 740 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC101_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 744 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC102_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 748 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC103_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 752 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC104_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 756 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC105_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 760 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC106_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 764 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC107_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 768 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC108_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 772 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC109_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 776 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC110_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 780 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC111_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 784 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC112_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 788 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC113_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 792 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC114_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 796 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC115_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 800 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC116_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 804 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC117_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 808 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC118_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 812 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC119_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 816 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC120_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 820 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC121_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 824 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC122_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 828 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC123_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 832 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC124_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 836 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC125_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 840 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC126_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 844 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC127_IN_SEL_CFG + description: GPIO input function configuration register. + byte_offset: 848 + fieldset: FUNC_IN_SEL_CFG + - name: FUNC0_OUT_SEL_CFG description: GPIO output function select register. - array: - len: 26 - stride: 4 byte_offset: 1364 fieldset: FUNC_OUT_SEL_CFG + - name: FUNC1_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1368 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC2_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1372 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC3_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1376 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC4_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1380 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC5_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1384 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC6_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1388 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC7_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1392 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC8_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1396 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC9_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1400 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC10_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1404 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC11_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1408 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC12_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1412 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC13_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1416 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC14_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1420 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC15_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1424 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC16_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1428 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC17_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1432 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC18_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1436 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC19_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1440 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC20_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1444 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC21_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1448 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC22_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1452 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC23_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1456 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC24_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1460 + fieldset: FUNC_OUT_SEL_CFG + - name: FUNC25_OUT_SEL_CFG + description: GPIO output function select register. + byte_offset: 1464 + fieldset: FUNC_OUT_SEL_CFG - name: CLOCK_GATE description: GPIO clock gate register. byte_offset: 1580 diff --git a/base/esp32c3/GPIO_SD.yaml b/head/esp32c3/GPIO_SD.yaml index 812cc17..3dcd09d 100644 --- a/base/esp32c3/GPIO_SD.yaml +++ b/head/esp32c3/GPIO_SD.yaml @@ -1,13 +1,6 @@ block/GPIO_SD: description: Sigma-Delta Modulation. items: - - name: SIGMADELTA - description: Duty Cycle Configure Register of SDM%s. - array: - len: 4 - stride: 4 - byte_offset: 0 - fieldset: SIGMADELTA - name: SIGMADELTA_CG description: Clock Gating Configure Register. byte_offset: 32 diff --git a/base/esp32c3/I2C0.yaml b/head/esp32c3/I2C0.yaml index 671726a..824db34 100644 --- a/base/esp32c3/I2C0.yaml +++ b/head/esp32c3/I2C0.yaml @@ -85,13 +85,38 @@ block/I2C0: description: I2C_CLK_CONF_REG. byte_offset: 84 fieldset: CLK_CONF - - name: COMD + - name: COMD0 description: I2C_COMD%s_REG. - array: - len: 8 - stride: 4 byte_offset: 88 fieldset: COMD + - name: COMD1 + description: I2C_COMD%s_REG. + byte_offset: 92 + fieldset: COMD + - name: COMD2 + description: I2C_COMD%s_REG. + byte_offset: 96 + fieldset: COMD + - name: COMD3 + description: I2C_COMD%s_REG. + byte_offset: 100 + fieldset: COMD + - name: COMD4 + description: I2C_COMD%s_REG. + byte_offset: 104 + fieldset: COMD + - name: COMD5 + description: I2C_COMD%s_REG. + byte_offset: 108 + fieldset: COMD + - name: COMD6 + description: I2C_COMD%s_REG. + byte_offset: 112 + fieldset: COMD + - name: COMD7 + description: I2C_COMD%s_REG. + byte_offset: 116 + fieldset: COMD - name: SCL_ST_TIME_OUT description: I2C_SCL_ST_TIME_OUT_REG. byte_offset: 120 diff --git a/base/esp32c3/IO_MUX.yaml b/head/esp32c3/IO_MUX.yaml index 36bdd80..607ee10 100644 --- a/base/esp32c3/IO_MUX.yaml +++ b/head/esp32c3/IO_MUX.yaml @@ -5,13 +5,6 @@ block/IO_MUX: description: Clock Output Configuration Register. byte_offset: 0 fieldset: PIN_CTRL - - name: GPIO - description: IO MUX Configure Register for pad XTAL_32K_P. - array: - len: 22 - stride: 4 - byte_offset: 4 - fieldset: GPIO - name: DATE description: IO MUX Version Control Register. byte_offset: 252 diff --git a/base/esp32c3/LEDC.yaml b/head/esp32c3/LEDC.yaml index 70f99f0..d263116 100644 --- a/base/esp32c3/LEDC.yaml +++ b/head/esp32c3/LEDC.yaml @@ -1,55 +1,158 @@ block/LEDC: description: LED Control PWM (Pulse Width Modulation). items: - - name: CH_CONF0 + - name: CH0_CONF0 description: LEDC_LSCH%s_CONF%s. - array: - len: 6 - stride: 20 byte_offset: 0 fieldset: CH_CONF0 - - name: CH_HPOINT + - name: CH0_HPOINT description: LEDC_LSCH%s_HPOINT. - array: - len: 6 - stride: 20 byte_offset: 4 fieldset: CH_HPOINT - - name: CH_DUTY + - name: CH0_DUTY description: LEDC_LSCH%s_DUTY. - array: - len: 6 - stride: 20 byte_offset: 8 fieldset: CH_DUTY - - name: CH_CONF1 + - name: CH0_CONF1 description: LEDC_LSCH%s_CONF1. - array: - len: 6 - stride: 20 byte_offset: 12 fieldset: CH_CONF1 - - name: CH_DUTY_R + - name: CH0_DUTY_R description: LEDC_LSCH%s_DUTY_R. - array: - len: 6 - stride: 20 byte_offset: 16 fieldset: CH_DUTY_R - - name: TIMER_CONF + - name: CH1_CONF0 + description: LEDC_LSCH%s_CONF%s. + byte_offset: 20 + fieldset: CH_CONF0 + - name: CH1_HPOINT + description: LEDC_LSCH%s_HPOINT. + byte_offset: 24 + fieldset: CH_HPOINT + - name: CH1_DUTY + description: LEDC_LSCH%s_DUTY. + byte_offset: 28 + fieldset: CH_DUTY + - name: CH1_CONF1 + description: LEDC_LSCH%s_CONF1. + byte_offset: 32 + fieldset: CH_CONF1 + - name: CH1_DUTY_R + description: LEDC_LSCH%s_DUTY_R. + byte_offset: 36 + fieldset: CH_DUTY_R + - name: CH2_CONF0 + description: LEDC_LSCH%s_CONF%s. + byte_offset: 40 + fieldset: CH_CONF0 + - name: CH2_HPOINT + description: LEDC_LSCH%s_HPOINT. + byte_offset: 44 + fieldset: CH_HPOINT + - name: CH2_DUTY + description: LEDC_LSCH%s_DUTY. + byte_offset: 48 + fieldset: CH_DUTY + - name: CH2_CONF1 + description: LEDC_LSCH%s_CONF1. + byte_offset: 52 + fieldset: CH_CONF1 + - name: CH2_DUTY_R + description: LEDC_LSCH%s_DUTY_R. + byte_offset: 56 + fieldset: CH_DUTY_R + - name: CH3_CONF0 + description: LEDC_LSCH%s_CONF%s. + byte_offset: 60 + fieldset: CH_CONF0 + - name: CH3_HPOINT + description: LEDC_LSCH%s_HPOINT. + byte_offset: 64 + fieldset: CH_HPOINT + - name: CH3_DUTY + description: LEDC_LSCH%s_DUTY. + byte_offset: 68 + fieldset: CH_DUTY + - name: CH3_CONF1 + description: LEDC_LSCH%s_CONF1. + byte_offset: 72 + fieldset: CH_CONF1 + - name: CH3_DUTY_R + description: LEDC_LSCH%s_DUTY_R. + byte_offset: 76 + fieldset: CH_DUTY_R + - name: CH4_CONF0 + description: LEDC_LSCH%s_CONF%s. + byte_offset: 80 + fieldset: CH_CONF0 + - name: CH4_HPOINT + description: LEDC_LSCH%s_HPOINT. + byte_offset: 84 + fieldset: CH_HPOINT + - name: CH4_DUTY + description: LEDC_LSCH%s_DUTY. + byte_offset: 88 + fieldset: CH_DUTY + - name: CH4_CONF1 + description: LEDC_LSCH%s_CONF1. + byte_offset: 92 + fieldset: CH_CONF1 + - name: CH4_DUTY_R + description: LEDC_LSCH%s_DUTY_R. + byte_offset: 96 + fieldset: CH_DUTY_R + - name: CH5_CONF0 + description: LEDC_LSCH%s_CONF%s. + byte_offset: 100 + fieldset: CH_CONF0 + - name: CH5_HPOINT + description: LEDC_LSCH%s_HPOINT. + byte_offset: 104 + fieldset: CH_HPOINT + - name: CH5_DUTY + description: LEDC_LSCH%s_DUTY. + byte_offset: 108 + fieldset: CH_DUTY + - name: CH5_CONF1 + description: LEDC_LSCH%s_CONF1. + byte_offset: 112 + fieldset: CH_CONF1 + - name: CH5_DUTY_R + description: LEDC_LSCH%s_DUTY_R. + byte_offset: 116 + fieldset: CH_DUTY_R + - name: TIMER0_CONF description: LEDC_LSTIMER%s_CONF. - array: - len: 4 - stride: 8 byte_offset: 160 fieldset: TIMER_CONF - - name: TIMER_VALUE + - name: TIMER0_VALUE description: LEDC_LSTIMER%s_VALUE. - array: - len: 4 - stride: 8 byte_offset: 164 fieldset: TIMER_VALUE + - name: TIMER1_CONF + description: LEDC_LSTIMER%s_CONF. + byte_offset: 168 + fieldset: TIMER_CONF + - name: TIMER1_VALUE + description: LEDC_LSTIMER%s_VALUE. + byte_offset: 172 + fieldset: TIMER_VALUE + - name: TIMER2_CONF + description: LEDC_LSTIMER%s_CONF. + byte_offset: 176 + fieldset: TIMER_CONF + - name: TIMER2_VALUE + description: LEDC_LSTIMER%s_VALUE. + byte_offset: 180 + fieldset: TIMER_VALUE + - name: TIMER3_CONF + description: LEDC_LSTIMER%s_CONF. + byte_offset: 184 + fieldset: TIMER_CONF + - name: TIMER3_VALUE + description: LEDC_LSTIMER%s_VALUE. + byte_offset: 188 + fieldset: TIMER_VALUE - name: INT_RAW description: LEDC_INT_RAW. byte_offset: 192 diff --git a/base/esp32c3/RMT.yaml b/head/esp32c3/RMT.yaml index 79cd9a3..f365154 100644 --- a/base/esp32c3/RMT.yaml +++ b/head/esp32c3/RMT.yaml @@ -1,48 +1,62 @@ block/RMT: description: Remote Control. items: - - name: CHDATA + - name: CH0DATA description: RMT_CH%sDATA_REG. - array: - len: 4 - stride: 4 byte_offset: 0 fieldset: CHDATA - - name: CH_TX_CONF0 + - name: CH1DATA + description: RMT_CH%sDATA_REG. + byte_offset: 4 + fieldset: CHDATA + - name: CH2DATA + description: RMT_CH%sDATA_REG. + byte_offset: 8 + fieldset: CHDATA + - name: CH3DATA + description: RMT_CH%sDATA_REG. + byte_offset: 12 + fieldset: CHDATA + - name: CH0_TX_CONF0 description: RMT_CH%sCONF%s_REG. - array: - len: 2 - stride: 4 byte_offset: 16 fieldset: CH_TX_CONF0 - - name: CH_RX_CONF0 + - name: CH1_TX_CONF0 + description: RMT_CH%sCONF%s_REG. + byte_offset: 20 + fieldset: CH_TX_CONF0 + - name: CH2_RX_CONF0 description: RMT_CH2CONF0_REG. - array: - len: 2 - stride: 8 byte_offset: 24 fieldset: CH_RX_CONF0 - - name: CH_RX_CONF1 + - name: CH2_RX_CONF1 description: RMT_CH2CONF1_REG. - array: - len: 2 - stride: 8 byte_offset: 28 fieldset: CH_RX_CONF1 - - name: CH_TX_STATUS + - name: CH3_RX_CONF0 + description: RMT_CH2CONF0_REG. + byte_offset: 32 + fieldset: CH_RX_CONF0 + - name: CH3_RX_CONF1 + description: RMT_CH2CONF1_REG. + byte_offset: 36 + fieldset: CH_RX_CONF1 + - name: CH0_TX_STATUS description: RMT_CH%sSTATUS_REG. - array: - len: 2 - stride: 4 byte_offset: 40 fieldset: CH_TX_STATUS - - name: CH_RX_STATUS + - name: CH1_TX_STATUS + description: RMT_CH%sSTATUS_REG. + byte_offset: 44 + fieldset: CH_TX_STATUS + - name: CH2_RX_STATUS description: RMT_CH2STATUS_REG. - array: - len: 2 - stride: 4 byte_offset: 48 fieldset: CH_RX_STATUS + - name: CH3_RX_STATUS + description: RMT_CH2STATUS_REG. + byte_offset: 52 + fieldset: CH_RX_STATUS - name: INT_RAW description: RMT_INT_RAW_REG. byte_offset: 56 @@ -59,34 +73,38 @@ block/RMT: description: RMT_INT_CLR_REG. byte_offset: 68 fieldset: INT_CLR - - name: CHCARRIER_DUTY + - name: CH0CARRIER_DUTY description: RMT_CH%sCARRIER_DUTY_REG. - array: - len: 2 - stride: 4 byte_offset: 72 fieldset: CHCARRIER_DUTY - - name: CH_RX_CARRIER_RM + - name: CH1CARRIER_DUTY + description: RMT_CH%sCARRIER_DUTY_REG. + byte_offset: 76 + fieldset: CHCARRIER_DUTY + - name: CH2_RX_CARRIER_RM description: RMT_CH2_RX_CARRIER_RM_REG. - array: - len: 2 - stride: 4 byte_offset: 80 fieldset: CH_RX_CARRIER_RM - - name: CH_TX_LIM + - name: CH3_RX_CARRIER_RM + description: RMT_CH2_RX_CARRIER_RM_REG. + byte_offset: 84 + fieldset: CH_RX_CARRIER_RM + - name: CH0_TX_LIM description: RMT_CH%s_TX_LIM_REG. - array: - len: 2 - stride: 4 byte_offset: 88 fieldset: CH_TX_LIM - - name: CH_RX_LIM + - name: CH1_TX_LIM + description: RMT_CH%s_TX_LIM_REG. + byte_offset: 92 + fieldset: CH_TX_LIM + - name: CH2_RX_LIM description: RMT_CH2_RX_LIM_REG. - array: - len: 2 - stride: 4 byte_offset: 96 fieldset: CH_RX_LIM + - name: CH3_RX_LIM + description: RMT_CH2_RX_LIM_REG. + byte_offset: 100 + fieldset: CH_RX_LIM - name: SYS_CONF description: RMT_SYS_CONF_REG. byte_offset: 104 @@ -351,211 +369,239 @@ fieldset/DATE: fieldset/INT_CLR: description: RMT_INT_CLR_REG. fields: - - name: CH_TX_END + - name: CH0_TX_END description: reg_ch%s_tx_end_int_clr. bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_END + - name: CH1_TX_END + description: reg_ch%s_tx_end_int_clr. + bit_offset: 1 + bit_size: 1 + - name: CH2_RX_END description: reg_ch2_rx_end_int_clr. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_ERR + - name: CH3_RX_END + description: reg_ch2_rx_end_int_clr. + bit_offset: 3 + bit_size: 1 + - name: CH0_TX_ERR description: reg_ch%s_err_int_clr. bit_offset: 4 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_ERR + - name: CH1_TX_ERR + description: reg_ch%s_err_int_clr. + bit_offset: 5 + bit_size: 1 + - name: CH2_RX_ERR description: reg_ch2_err_int_clr. bit_offset: 6 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_THR_EVENT + - name: CH3_RX_ERR + description: reg_ch2_err_int_clr. + bit_offset: 7 + bit_size: 1 + - name: CH0_TX_THR_EVENT description: reg_ch%s_tx_thr_event_int_clr. bit_offset: 8 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_THR_EVENT + - name: CH1_TX_THR_EVENT + description: reg_ch%s_tx_thr_event_int_clr. + bit_offset: 9 + bit_size: 1 + - name: CH2_RX_THR_EVENT description: reg_ch2_rx_thr_event_int_clr. bit_offset: 10 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_LOOP + - name: CH3_RX_THR_EVENT + description: reg_ch2_rx_thr_event_int_clr. + bit_offset: 11 + bit_size: 1 + - name: CH0_TX_LOOP description: reg_ch%s_tx_loop_int_clr. bit_offset: 12 bit_size: 1 - array: - len: 2 - stride: 1 + - name: CH1_TX_LOOP + description: reg_ch%s_tx_loop_int_clr. + bit_offset: 13 + bit_size: 1 fieldset/INT_ENA: description: RMT_INT_ENA_REG. fields: - - name: CH_TX_END + - name: CH0_TX_END description: reg_ch%s_tx_end_int_ena. bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_END + - name: CH1_TX_END + description: reg_ch%s_tx_end_int_ena. + bit_offset: 1 + bit_size: 1 + - name: CH2_RX_END description: reg_ch2_rx_end_int_ena. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_ERR + - name: CH3_RX_END + description: reg_ch2_rx_end_int_ena. + bit_offset: 3 + bit_size: 1 + - name: CH0_TX_ERR description: reg_ch%s_err_int_ena. bit_offset: 4 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_ERR + - name: CH1_TX_ERR + description: reg_ch%s_err_int_ena. + bit_offset: 5 + bit_size: 1 + - name: CH2_RX_ERR description: reg_ch2_err_int_ena. bit_offset: 6 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_THR_EVENT + - name: CH3_RX_ERR + description: reg_ch2_err_int_ena. + bit_offset: 7 + bit_size: 1 + - name: CH0_TX_THR_EVENT description: reg_ch%s_tx_thr_event_int_ena. bit_offset: 8 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_THR_EVENT + - name: CH1_TX_THR_EVENT + description: reg_ch%s_tx_thr_event_int_ena. + bit_offset: 9 + bit_size: 1 + - name: CH2_RX_THR_EVENT description: reg_ch2_rx_thr_event_int_ena. bit_offset: 10 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_LOOP + - name: CH3_RX_THR_EVENT + description: reg_ch2_rx_thr_event_int_ena. + bit_offset: 11 + bit_size: 1 + - name: CH0_TX_LOOP description: reg_ch%s_tx_loop_int_ena. bit_offset: 12 bit_size: 1 - array: - len: 2 - stride: 1 + - name: CH1_TX_LOOP + description: reg_ch%s_tx_loop_int_ena. + bit_offset: 13 + bit_size: 1 fieldset/INT_RAW: description: RMT_INT_RAW_REG. fields: - - name: CH_TX_END + - name: CH0_TX_END description: reg_ch%s_tx_end_int_raw. bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_END + - name: CH1_TX_END + description: reg_ch%s_tx_end_int_raw. + bit_offset: 1 + bit_size: 1 + - name: CH2_RX_END description: reg_ch2_rx_end_int_raw. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_ERR + - name: CH3_RX_END + description: reg_ch2_rx_end_int_raw. + bit_offset: 3 + bit_size: 1 + - name: CH0_TX_ERR description: reg_ch%s_err_int_raw. bit_offset: 4 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_ERR + - name: CH1_TX_ERR + description: reg_ch%s_err_int_raw. + bit_offset: 5 + bit_size: 1 + - name: CH2_RX_ERR description: reg_ch2_err_int_raw. bit_offset: 6 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_THR_EVENT + - name: CH3_RX_ERR + description: reg_ch2_err_int_raw. + bit_offset: 7 + bit_size: 1 + - name: CH0_TX_THR_EVENT description: reg_ch%s_tx_thr_event_int_raw. bit_offset: 8 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_THR_EVENT + - name: CH1_TX_THR_EVENT + description: reg_ch%s_tx_thr_event_int_raw. + bit_offset: 9 + bit_size: 1 + - name: CH2_RX_THR_EVENT description: reg_ch2_rx_thr_event_int_raw. bit_offset: 10 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_LOOP + - name: CH3_RX_THR_EVENT + description: reg_ch2_rx_thr_event_int_raw. + bit_offset: 11 + bit_size: 1 + - name: CH0_TX_LOOP description: reg_ch%s_tx_loop_int_raw. bit_offset: 12 bit_size: 1 - array: - len: 2 - stride: 1 + - name: CH1_TX_LOOP + description: reg_ch%s_tx_loop_int_raw. + bit_offset: 13 + bit_size: 1 fieldset/INT_ST: description: RMT_INT_ST_REG. fields: - - name: CH_TX_END + - name: CH0_TX_END description: reg_ch%s_tx_end_int_st. bit_offset: 0 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_END + - name: CH1_TX_END + description: reg_ch%s_tx_end_int_st. + bit_offset: 1 + bit_size: 1 + - name: CH2_RX_END description: reg_ch2_rx_end_int_st. bit_offset: 2 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_ERR + - name: CH3_RX_END + description: reg_ch2_rx_end_int_st. + bit_offset: 3 + bit_size: 1 + - name: CH0_TX_ERR description: reg_ch%s_err_int_st. bit_offset: 4 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_ERR + - name: CH1_TX_ERR + description: reg_ch%s_err_int_st. + bit_offset: 5 + bit_size: 1 + - name: CH2_RX_ERR description: reg_ch2_err_int_st. bit_offset: 6 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_THR_EVENT + - name: CH3_RX_ERR + description: reg_ch2_err_int_st. + bit_offset: 7 + bit_size: 1 + - name: CH0_TX_THR_EVENT description: reg_ch%s_tx_thr_event_int_st. bit_offset: 8 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_RX_THR_EVENT + - name: CH1_TX_THR_EVENT + description: reg_ch%s_tx_thr_event_int_st. + bit_offset: 9 + bit_size: 1 + - name: CH2_RX_THR_EVENT description: reg_ch2_rx_thr_event_int_st. bit_offset: 10 bit_size: 1 - array: - len: 2 - stride: 1 - - name: CH_TX_LOOP + - name: CH3_RX_THR_EVENT + description: reg_ch2_rx_thr_event_int_st. + bit_offset: 11 + bit_size: 1 + - name: CH0_TX_LOOP description: reg_ch%s_tx_loop_int_st. bit_offset: 12 bit_size: 1 - array: - len: 2 - stride: 1 + - name: CH1_TX_LOOP + description: reg_ch%s_tx_loop_int_st. + bit_offset: 13 + bit_size: 1 fieldset/REF_CNT_RST: description: RMT_REF_CNT_RST_REG. fields: diff --git a/base/va108xx/SYSCONFIG.yaml b/head/va108xx/SYSCONFIG.yaml index f511836..2a880cb 100644 --- a/base/va108xx/SYSCONFIG.yaml +++ b/head/va108xx/SYSCONFIG.yaml @@ -32,12 +32,27 @@ block/SYSCONFIG: description: IO Configuration Clock Divider Register. byte_offset: 72 access: Read - - name: IOCONFIG_CLKDIV + - name: IOCONFIG_CLKDIV1 description: IO Configuration Clock Divider Register. - array: - len: 7 - stride: 4 byte_offset: 76 + - name: IOCONFIG_CLKDIV2 + description: IO Configuration Clock Divider Register. + byte_offset: 80 + - name: IOCONFIG_CLKDIV3 + description: IO Configuration Clock Divider Register. + byte_offset: 84 + - name: IOCONFIG_CLKDIV4 + description: IO Configuration Clock Divider Register. + byte_offset: 88 + - name: IOCONFIG_CLKDIV5 + description: IO Configuration Clock Divider Register. + byte_offset: 92 + - name: IOCONFIG_CLKDIV6 + description: IO Configuration Clock Divider Register. + byte_offset: 96 + - name: IOCONFIG_CLKDIV7 + description: IO Configuration Clock Divider Register. + byte_offset: 100 - name: ROM_RETRIES description: ROM BOOT Retry count. byte_offset: 104