diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index a4cb63a..9fa8f18 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -10316,8 +10316,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index 340d8a8..989ea1d 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -10316,8 +10316,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index f648bb3..a823007 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -9312,8 +9312,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index 0c2babb..a113856 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -9312,8 +9312,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index f530119..0e79a3e 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -6490,8 +6490,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index 37fa1c9..9e57315 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -6490,8 +6490,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index ebeb28c..f14ef41 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -8283,8 +8283,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index be3bf3d..2dd4889 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -8283,8 +8283,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index ceef69e..d26e0e4 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -10502,8 +10502,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index 8202f91..c1528ab 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -10502,8 +10502,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index 15f4844..1273b51 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -10022,8 +10022,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index 8abcc6e..053abfb 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -10125,8 +10125,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index 890c08b..eb814ee 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -10125,8 +10125,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index 83a4333..cab7398 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -7776,8 +7776,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index e737ed8..87b752b 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -8551,8 +8551,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index c6a0e8e..1b50b96 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -9957,8 +9957,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index 13738c5..7837b7a 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -9957,8 +9957,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index d601ab3..46a75d8 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -10478,8 +10478,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5A5QI.json b/data/chips/STM32U5A5QI.json index b08f293..a69aeb9 100644 --- a/data/chips/STM32U5A5QI.json +++ b/data/chips/STM32U5A5QI.json @@ -8586,8 +8586,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index 7a93c9e..bacd232 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -9474,8 +9474,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index 7241e45..7548031 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -6652,8 +6652,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index 6c86526..f52d847 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -8445,8 +8445,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 025a592..3cbfdc8 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -10664,8 +10664,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 1acd576..3715e93 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -10184,8 +10184,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index cbc2b69..4fe05fb 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -10287,8 +10287,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 1b45b71..a182c0b 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -7938,8 +7938,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index a22e4ab..e44bd05 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -10119,8 +10119,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5F7VI.json b/data/chips/STM32U5F7VI.json index 78110ac..8796a4d 100644 --- a/data/chips/STM32U5F7VI.json +++ b/data/chips/STM32U5F7VI.json @@ -8673,8 +8673,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5F7VJ.json b/data/chips/STM32U5F7VJ.json index 13c5ada..127b433 100644 --- a/data/chips/STM32U5F7VJ.json +++ b/data/chips/STM32U5F7VJ.json @@ -8673,8 +8673,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5F9BJ.json b/data/chips/STM32U5F9BJ.json index d47c04f..856cb38 100644 --- a/data/chips/STM32U5F9BJ.json +++ b/data/chips/STM32U5F9BJ.json @@ -10111,8 +10111,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5F9NJ.json b/data/chips/STM32U5F9NJ.json index e6bf487..852e00f 100644 --- a/data/chips/STM32U5F9NJ.json +++ b/data/chips/STM32U5F9NJ.json @@ -10309,8 +10309,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5F9VI.json b/data/chips/STM32U5F9VI.json index 9cd9960..5c33f15 100644 --- a/data/chips/STM32U5F9VI.json +++ b/data/chips/STM32U5F9VI.json @@ -7007,8 +7007,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5F9VJ.json b/data/chips/STM32U5F9VJ.json index 0206730..fc0a0e4 100644 --- a/data/chips/STM32U5F9VJ.json +++ b/data/chips/STM32U5F9VJ.json @@ -7007,8 +7007,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5F9ZI.json b/data/chips/STM32U5F9ZI.json index 9af9ff1..e4c16f1 100644 --- a/data/chips/STM32U5F9ZI.json +++ b/data/chips/STM32U5F9ZI.json @@ -9666,8 +9666,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5F9ZJ.json b/data/chips/STM32U5F9ZJ.json index 1f87480..a9cdbfe 100644 --- a/data/chips/STM32U5F9ZJ.json +++ b/data/chips/STM32U5F9ZJ.json @@ -9666,8 +9666,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5G7VJ.json b/data/chips/STM32U5G7VJ.json index ce87bf9..b9326a0 100644 --- a/data/chips/STM32U5G7VJ.json +++ b/data/chips/STM32U5G7VJ.json @@ -8808,8 +8808,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5G9BJ.json b/data/chips/STM32U5G9BJ.json index 00e9c4a..ce17a0c 100644 --- a/data/chips/STM32U5G9BJ.json +++ b/data/chips/STM32U5G9BJ.json @@ -10273,8 +10273,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5G9NJ.json b/data/chips/STM32U5G9NJ.json index 2c04e9f..70cf85c 100644 --- a/data/chips/STM32U5G9NJ.json +++ b/data/chips/STM32U5G9NJ.json @@ -10471,8 +10471,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5G9VJ.json b/data/chips/STM32U5G9VJ.json index 88da611..ce468d4 100644 --- a/data/chips/STM32U5G9VJ.json +++ b/data/chips/STM32U5G9VJ.json @@ -7142,8 +7142,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1", diff --git a/data/chips/STM32U5G9ZJ.json b/data/chips/STM32U5G9ZJ.json index cf3902a..c5bed1e 100644 --- a/data/chips/STM32U5G9ZJ.json +++ b/data/chips/STM32U5G9ZJ.json @@ -9801,8 +9801,8 @@ "rcc": { "bus_clock": "HCLK2", "kernel_clock": { - "register": "CCIPR1", - "field": "ICLKSEL" + "register": "CCIPR2", + "field": "OTGHSSEL" }, "enable": { "register": "AHB2ENR1",