diff --git a/data/chips/STM32G431C6.json b/data/chips/STM32G431C6.json index 28823df..c906dea 100644 --- a/data/chips/STM32G431C6.json +++ b/data/chips/STM32G431C6.json @@ -2024,7 +2024,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431C8.json b/data/chips/STM32G431C8.json index 7ea4ce4..147f42f 100644 --- a/data/chips/STM32G431C8.json +++ b/data/chips/STM32G431C8.json @@ -2024,7 +2024,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431CB.json b/data/chips/STM32G431CB.json index 8ff6f2d..261a177 100644 --- a/data/chips/STM32G431CB.json +++ b/data/chips/STM32G431CB.json @@ -2028,7 +2028,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431K6.json b/data/chips/STM32G431K6.json index ff90919..6c38236 100644 --- a/data/chips/STM32G431K6.json +++ b/data/chips/STM32G431K6.json @@ -1820,7 +1820,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431K8.json b/data/chips/STM32G431K8.json index e57ef3d..ae18ce4 100644 --- a/data/chips/STM32G431K8.json +++ b/data/chips/STM32G431K8.json @@ -1820,7 +1820,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431KB.json b/data/chips/STM32G431KB.json index c588b3e..685c2bf 100644 --- a/data/chips/STM32G431KB.json +++ b/data/chips/STM32G431KB.json @@ -1820,7 +1820,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431M6.json b/data/chips/STM32G431M6.json index 6cff356..22c9ad6 100644 --- a/data/chips/STM32G431M6.json +++ b/data/chips/STM32G431M6.json @@ -2151,7 +2151,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431M8.json b/data/chips/STM32G431M8.json index 6567aa3..8f4f1c6 100644 --- a/data/chips/STM32G431M8.json +++ b/data/chips/STM32G431M8.json @@ -2151,7 +2151,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431MB.json b/data/chips/STM32G431MB.json index 51e526e..1f701e9 100644 --- a/data/chips/STM32G431MB.json +++ b/data/chips/STM32G431MB.json @@ -2151,7 +2151,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431R6.json b/data/chips/STM32G431R6.json index b42a726..02456c6 100644 --- a/data/chips/STM32G431R6.json +++ b/data/chips/STM32G431R6.json @@ -2137,7 +2137,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431R8.json b/data/chips/STM32G431R8.json index 839816b..1835b82 100644 --- a/data/chips/STM32G431R8.json +++ b/data/chips/STM32G431R8.json @@ -2137,7 +2137,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431RB.json b/data/chips/STM32G431RB.json index dfb8bd1..1fbd1ff 100644 --- a/data/chips/STM32G431RB.json +++ b/data/chips/STM32G431RB.json @@ -2137,7 +2137,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431V6.json b/data/chips/STM32G431V6.json index 60aa271..3cbda48 100644 --- a/data/chips/STM32G431V6.json +++ b/data/chips/STM32G431V6.json @@ -2168,7 +2168,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431V8.json b/data/chips/STM32G431V8.json index 763a01f..b7881f4 100644 --- a/data/chips/STM32G431V8.json +++ b/data/chips/STM32G431V8.json @@ -2168,7 +2168,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431VB.json b/data/chips/STM32G431VB.json index c1d682d..28cc23f 100644 --- a/data/chips/STM32G431VB.json +++ b/data/chips/STM32G431VB.json @@ -2168,7 +2168,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G441CB.json b/data/chips/STM32G441CB.json index 1182a98..8b00835 100644 --- a/data/chips/STM32G441CB.json +++ b/data/chips/STM32G441CB.json @@ -2061,7 +2061,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G441KB.json b/data/chips/STM32G441KB.json index 9ec3d7c..69278d8 100644 --- a/data/chips/STM32G441KB.json +++ b/data/chips/STM32G441KB.json @@ -1853,7 +1853,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G441MB.json b/data/chips/STM32G441MB.json index bce50dc..371d3eb 100644 --- a/data/chips/STM32G441MB.json +++ b/data/chips/STM32G441MB.json @@ -2184,7 +2184,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G441RB.json b/data/chips/STM32G441RB.json index 9aa4558..8e748bd 100644 --- a/data/chips/STM32G441RB.json +++ b/data/chips/STM32G441RB.json @@ -2170,7 +2170,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G441VB.json b/data/chips/STM32G441VB.json index 6cd4e77..8982da9 100644 --- a/data/chips/STM32G441VB.json +++ b/data/chips/STM32G441VB.json @@ -2201,7 +2201,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471CC.json b/data/chips/STM32G471CC.json index 2efff08..064b0b9 100644 --- a/data/chips/STM32G471CC.json +++ b/data/chips/STM32G471CC.json @@ -2095,7 +2095,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471CE.json b/data/chips/STM32G471CE.json index bc755ce..741cb98 100644 --- a/data/chips/STM32G471CE.json +++ b/data/chips/STM32G471CE.json @@ -2095,7 +2095,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471MC.json b/data/chips/STM32G471MC.json index e46ba1a..be3067c 100644 --- a/data/chips/STM32G471MC.json +++ b/data/chips/STM32G471MC.json @@ -2313,7 +2313,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471ME.json b/data/chips/STM32G471ME.json index 0beda81..c3e114d 100644 --- a/data/chips/STM32G471ME.json +++ b/data/chips/STM32G471ME.json @@ -2317,7 +2317,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471QC.json b/data/chips/STM32G471QC.json index 5a17cbf..d6afd7c 100644 --- a/data/chips/STM32G471QC.json +++ b/data/chips/STM32G471QC.json @@ -2477,7 +2477,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471QE.json b/data/chips/STM32G471QE.json index de495b2..16f3675 100644 --- a/data/chips/STM32G471QE.json +++ b/data/chips/STM32G471QE.json @@ -2477,7 +2477,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471RC.json b/data/chips/STM32G471RC.json index 3e3157e..5736e83 100644 --- a/data/chips/STM32G471RC.json +++ b/data/chips/STM32G471RC.json @@ -2224,7 +2224,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471RE.json b/data/chips/STM32G471RE.json index b331949..d6dce89 100644 --- a/data/chips/STM32G471RE.json +++ b/data/chips/STM32G471RE.json @@ -2224,7 +2224,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471VC.json b/data/chips/STM32G471VC.json index b816976..96139b9 100644 --- a/data/chips/STM32G471VC.json +++ b/data/chips/STM32G471VC.json @@ -2385,7 +2385,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471VE.json b/data/chips/STM32G471VE.json index 06ab6c8..88c00c2 100644 --- a/data/chips/STM32G471VE.json +++ b/data/chips/STM32G471VE.json @@ -2385,7 +2385,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473CB.json b/data/chips/STM32G473CB.json index dba82ce..efccbeb 100644 --- a/data/chips/STM32G473CB.json +++ b/data/chips/STM32G473CB.json @@ -2812,7 +2812,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473CC.json b/data/chips/STM32G473CC.json index 2e0831c..bc147f4 100644 --- a/data/chips/STM32G473CC.json +++ b/data/chips/STM32G473CC.json @@ -2812,7 +2812,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473CE.json b/data/chips/STM32G473CE.json index 89b6799..4d2dfb2 100644 --- a/data/chips/STM32G473CE.json +++ b/data/chips/STM32G473CE.json @@ -2812,7 +2812,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473MB.json b/data/chips/STM32G473MB.json index 74ad31d..cc8f26e 100644 --- a/data/chips/STM32G473MB.json +++ b/data/chips/STM32G473MB.json @@ -3156,7 +3156,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473MC.json b/data/chips/STM32G473MC.json index a9292de..86a518d 100644 --- a/data/chips/STM32G473MC.json +++ b/data/chips/STM32G473MC.json @@ -3156,7 +3156,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473ME.json b/data/chips/STM32G473ME.json index 2f4da32..f11b3a3 100644 --- a/data/chips/STM32G473ME.json +++ b/data/chips/STM32G473ME.json @@ -3160,7 +3160,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473PB.json b/data/chips/STM32G473PB.json index 0ab3fc0..2ff37c0 100644 --- a/data/chips/STM32G473PB.json +++ b/data/chips/STM32G473PB.json @@ -3689,7 +3689,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473PC.json b/data/chips/STM32G473PC.json index 140be87..9e6aa38 100644 --- a/data/chips/STM32G473PC.json +++ b/data/chips/STM32G473PC.json @@ -3689,7 +3689,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473PE.json b/data/chips/STM32G473PE.json index f901343..3fe4a79 100644 --- a/data/chips/STM32G473PE.json +++ b/data/chips/STM32G473PE.json @@ -3689,7 +3689,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473QB.json b/data/chips/STM32G473QB.json index 623ba19..7d4cecf 100644 --- a/data/chips/STM32G473QB.json +++ b/data/chips/STM32G473QB.json @@ -3765,7 +3765,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473QC.json b/data/chips/STM32G473QC.json index 5039bec..4425601 100644 --- a/data/chips/STM32G473QC.json +++ b/data/chips/STM32G473QC.json @@ -3765,7 +3765,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473QE.json b/data/chips/STM32G473QE.json index 40dc310..5698751 100644 --- a/data/chips/STM32G473QE.json +++ b/data/chips/STM32G473QE.json @@ -3765,7 +3765,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473RB.json b/data/chips/STM32G473RB.json index e45df2c..ff6abbc 100644 --- a/data/chips/STM32G473RB.json +++ b/data/chips/STM32G473RB.json @@ -2959,7 +2959,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473RC.json b/data/chips/STM32G473RC.json index 129a223..bc1ab90 100644 --- a/data/chips/STM32G473RC.json +++ b/data/chips/STM32G473RC.json @@ -2959,7 +2959,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473RE.json b/data/chips/STM32G473RE.json index 3857611..b71e425 100644 --- a/data/chips/STM32G473RE.json +++ b/data/chips/STM32G473RE.json @@ -2959,7 +2959,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473VB.json b/data/chips/STM32G473VB.json index 9c4ca3b..6efe182 100644 --- a/data/chips/STM32G473VB.json +++ b/data/chips/STM32G473VB.json @@ -3564,7 +3564,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473VC.json b/data/chips/STM32G473VC.json index 2ab54f6..6436252 100644 --- a/data/chips/STM32G473VC.json +++ b/data/chips/STM32G473VC.json @@ -3564,7 +3564,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473VE.json b/data/chips/STM32G473VE.json index 85c12de..4a35028 100644 --- a/data/chips/STM32G473VE.json +++ b/data/chips/STM32G473VE.json @@ -3564,7 +3564,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474CB.json b/data/chips/STM32G474CB.json index 40eb094..c9ca00c 100644 --- a/data/chips/STM32G474CB.json +++ b/data/chips/STM32G474CB.json @@ -3058,7 +3058,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474CC.json b/data/chips/STM32G474CC.json index 37ce659..b3faf18 100644 --- a/data/chips/STM32G474CC.json +++ b/data/chips/STM32G474CC.json @@ -3058,7 +3058,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474CE.json b/data/chips/STM32G474CE.json index aed6c3e..a21ba75 100644 --- a/data/chips/STM32G474CE.json +++ b/data/chips/STM32G474CE.json @@ -3058,7 +3058,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474MB.json b/data/chips/STM32G474MB.json index c317b6c..caf0769 100644 --- a/data/chips/STM32G474MB.json +++ b/data/chips/STM32G474MB.json @@ -3432,7 +3432,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474MC.json b/data/chips/STM32G474MC.json index ca0f93e..a02d9be 100644 --- a/data/chips/STM32G474MC.json +++ b/data/chips/STM32G474MC.json @@ -3432,7 +3432,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474ME.json b/data/chips/STM32G474ME.json index 60112dd..8635b95 100644 --- a/data/chips/STM32G474ME.json +++ b/data/chips/STM32G474ME.json @@ -3436,7 +3436,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474PB.json b/data/chips/STM32G474PB.json index 6f594ee..19b1fed 100644 --- a/data/chips/STM32G474PB.json +++ b/data/chips/STM32G474PB.json @@ -3953,7 +3953,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474PC.json b/data/chips/STM32G474PC.json index 6f31d5a..dd595ba 100644 --- a/data/chips/STM32G474PC.json +++ b/data/chips/STM32G474PC.json @@ -3953,7 +3953,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474PE.json b/data/chips/STM32G474PE.json index 1640277..988193a 100644 --- a/data/chips/STM32G474PE.json +++ b/data/chips/STM32G474PE.json @@ -3953,7 +3953,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474QB.json b/data/chips/STM32G474QB.json index eb2428e..b4f4917 100644 --- a/data/chips/STM32G474QB.json +++ b/data/chips/STM32G474QB.json @@ -4041,7 +4041,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474QC.json b/data/chips/STM32G474QC.json index d2c8f35..22dd9d3 100644 --- a/data/chips/STM32G474QC.json +++ b/data/chips/STM32G474QC.json @@ -4041,7 +4041,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474QE.json b/data/chips/STM32G474QE.json index 504dc30..0507f45 100644 --- a/data/chips/STM32G474QE.json +++ b/data/chips/STM32G474QE.json @@ -4041,7 +4041,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474RB.json b/data/chips/STM32G474RB.json index eb49d22..3169699 100644 --- a/data/chips/STM32G474RB.json +++ b/data/chips/STM32G474RB.json @@ -3235,7 +3235,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474RC.json b/data/chips/STM32G474RC.json index 4acb7d5..9d35ade 100644 --- a/data/chips/STM32G474RC.json +++ b/data/chips/STM32G474RC.json @@ -3235,7 +3235,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474RE.json b/data/chips/STM32G474RE.json index 7540bb6..db62679 100644 --- a/data/chips/STM32G474RE.json +++ b/data/chips/STM32G474RE.json @@ -3235,7 +3235,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474VB.json b/data/chips/STM32G474VB.json index d10a997..af9db76 100644 --- a/data/chips/STM32G474VB.json +++ b/data/chips/STM32G474VB.json @@ -3840,7 +3840,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474VC.json b/data/chips/STM32G474VC.json index f7659f3..f55cbd3 100644 --- a/data/chips/STM32G474VC.json +++ b/data/chips/STM32G474VC.json @@ -3840,7 +3840,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474VE.json b/data/chips/STM32G474VE.json index 0853e8a..1b16019 100644 --- a/data/chips/STM32G474VE.json +++ b/data/chips/STM32G474VE.json @@ -3840,7 +3840,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483CE.json b/data/chips/STM32G483CE.json index aa62782..35debc6 100644 --- a/data/chips/STM32G483CE.json +++ b/data/chips/STM32G483CE.json @@ -2851,7 +2851,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483ME.json b/data/chips/STM32G483ME.json index da30fd9..c1773de 100644 --- a/data/chips/STM32G483ME.json +++ b/data/chips/STM32G483ME.json @@ -3199,7 +3199,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483PE.json b/data/chips/STM32G483PE.json index 15fc71e..883d246 100644 --- a/data/chips/STM32G483PE.json +++ b/data/chips/STM32G483PE.json @@ -3728,7 +3728,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483QE.json b/data/chips/STM32G483QE.json index e3855e5..801bf0c 100644 --- a/data/chips/STM32G483QE.json +++ b/data/chips/STM32G483QE.json @@ -3804,7 +3804,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483RE.json b/data/chips/STM32G483RE.json index 2727541..a8b7922 100644 --- a/data/chips/STM32G483RE.json +++ b/data/chips/STM32G483RE.json @@ -2998,7 +2998,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483VE.json b/data/chips/STM32G483VE.json index 2aba5d7..82d344e 100644 --- a/data/chips/STM32G483VE.json +++ b/data/chips/STM32G483VE.json @@ -3603,7 +3603,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484CE.json b/data/chips/STM32G484CE.json index 4dc0dd1..e5d0195 100644 --- a/data/chips/STM32G484CE.json +++ b/data/chips/STM32G484CE.json @@ -3091,7 +3091,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484ME.json b/data/chips/STM32G484ME.json index d0afcfd..a7e054d 100644 --- a/data/chips/STM32G484ME.json +++ b/data/chips/STM32G484ME.json @@ -3469,7 +3469,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484PE.json b/data/chips/STM32G484PE.json index b72102f..98eaff9 100644 --- a/data/chips/STM32G484PE.json +++ b/data/chips/STM32G484PE.json @@ -3992,7 +3992,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484QE.json b/data/chips/STM32G484QE.json index 066c5eb..f775ad5 100644 --- a/data/chips/STM32G484QE.json +++ b/data/chips/STM32G484QE.json @@ -4074,7 +4074,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484RE.json b/data/chips/STM32G484RE.json index c06333b..3dde6ea 100644 --- a/data/chips/STM32G484RE.json +++ b/data/chips/STM32G484RE.json @@ -3268,7 +3268,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484VE.json b/data/chips/STM32G484VE.json index 1b7825c..03ccf39 100644 --- a/data/chips/STM32G484VE.json +++ b/data/chips/STM32G484VE.json @@ -3873,7 +3873,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491CC.json b/data/chips/STM32G491CC.json index 0b585b7..ff66d55 100644 --- a/data/chips/STM32G491CC.json +++ b/data/chips/STM32G491CC.json @@ -2290,7 +2290,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491CE.json b/data/chips/STM32G491CE.json index 2fd3bec..a0b481d 100644 --- a/data/chips/STM32G491CE.json +++ b/data/chips/STM32G491CE.json @@ -2290,7 +2290,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491KC.json b/data/chips/STM32G491KC.json index 2b6a67a..9bc7654 100644 --- a/data/chips/STM32G491KC.json +++ b/data/chips/STM32G491KC.json @@ -2007,7 +2007,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491KE.json b/data/chips/STM32G491KE.json index 37600a3..0807b9b 100644 --- a/data/chips/STM32G491KE.json +++ b/data/chips/STM32G491KE.json @@ -2007,7 +2007,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491MC.json b/data/chips/STM32G491MC.json index 7a23336..48f50a3 100644 --- a/data/chips/STM32G491MC.json +++ b/data/chips/STM32G491MC.json @@ -2506,7 +2506,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491ME.json b/data/chips/STM32G491ME.json index 272a049..2f75bc7 100644 --- a/data/chips/STM32G491ME.json +++ b/data/chips/STM32G491ME.json @@ -2506,7 +2506,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491RC.json b/data/chips/STM32G491RC.json index fcf053e..1c73c11 100644 --- a/data/chips/STM32G491RC.json +++ b/data/chips/STM32G491RC.json @@ -2418,7 +2418,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491RE.json b/data/chips/STM32G491RE.json index b599152..fccac73 100644 --- a/data/chips/STM32G491RE.json +++ b/data/chips/STM32G491RE.json @@ -2422,7 +2422,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491VC.json b/data/chips/STM32G491VC.json index 363056a..cbcc082 100644 --- a/data/chips/STM32G491VC.json +++ b/data/chips/STM32G491VC.json @@ -2570,7 +2570,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491VE.json b/data/chips/STM32G491VE.json index 91a07c3..779d717 100644 --- a/data/chips/STM32G491VE.json +++ b/data/chips/STM32G491VE.json @@ -2570,7 +2570,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G4A1CE.json b/data/chips/STM32G4A1CE.json index 955cba0..5eab502 100644 --- a/data/chips/STM32G4A1CE.json +++ b/data/chips/STM32G4A1CE.json @@ -2329,7 +2329,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G4A1KE.json b/data/chips/STM32G4A1KE.json index 2f2cc14..d102dd8 100644 --- a/data/chips/STM32G4A1KE.json +++ b/data/chips/STM32G4A1KE.json @@ -2046,7 +2046,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G4A1ME.json b/data/chips/STM32G4A1ME.json index 14b0a4f..fea3b34 100644 --- a/data/chips/STM32G4A1ME.json +++ b/data/chips/STM32G4A1ME.json @@ -2545,7 +2545,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G4A1RE.json b/data/chips/STM32G4A1RE.json index 1f61b2b..82183c2 100644 --- a/data/chips/STM32G4A1RE.json +++ b/data/chips/STM32G4A1RE.json @@ -2461,7 +2461,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G4A1VE.json b/data/chips/STM32G4A1VE.json index 9b2f3a9..cabc5d1 100644 --- a/data/chips/STM32G4A1VE.json +++ b/data/chips/STM32G4A1VE.json @@ -2609,7 +2609,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index 3ef2b31..72884ac 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -4194,6 +4194,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4398,6 +4403,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index c338eb7..a2326f7 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -4205,6 +4205,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4409,6 +4414,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index 3685ff0..53b9884 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -4238,6 +4238,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4442,6 +4447,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index de15725..0468fb2 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -4249,6 +4249,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4453,6 +4458,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index b75974e..b56c96b 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -2803,6 +2803,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -2917,6 +2922,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index 7b5bd33..5c529cf 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -2814,6 +2814,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -2928,6 +2933,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index 6965733..eb3c55a 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -3347,6 +3347,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3516,6 +3521,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index 6bc60f7..cc7bdcb 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -3358,6 +3358,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3527,6 +3532,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index 8d9a304..8cdde7e 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -3871,6 +3871,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4075,6 +4080,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index 9e6b0a7..7a426a7 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -3882,6 +3882,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4086,6 +4091,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index 49da115..cd9c08c 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -4467,6 +4467,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4671,6 +4676,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index 240f5ac..b569ee4 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -4507,6 +4507,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4711,6 +4716,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 2d46837..1e340c0 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -4516,6 +4516,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4720,6 +4725,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index f9b0018..bc5ade8 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -4535,6 +4535,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4739,6 +4744,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index ce0d4d6..9846835 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -3142,6 +3142,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3246,6 +3251,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index b688ed3..3e09907 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -3021,6 +3021,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3135,6 +3140,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index f3deba4..391c347 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -3032,6 +3032,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3146,6 +3151,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index 2b0e826..1fe62fe 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -3570,6 +3570,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3739,6 +3744,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index 27b2164..74c9117 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -3600,6 +3600,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3769,6 +3774,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index 4bac43e..349d3e1 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -4119,6 +4119,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4323,6 +4328,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index 703912a..93ac4e9 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -4174,6 +4174,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4378,6 +4383,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index a8ed64c..1ae36ac 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -4649,6 +4649,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4853,6 +4858,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index 1be47ef..f7b6ad3 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -4677,6 +4677,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4881,6 +4886,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index d074222..5f88740 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -3284,6 +3284,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3388,6 +3393,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index c6a7fd4..1ab169b 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -3174,6 +3174,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3288,6 +3293,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index b9d185f..626f115 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -3742,6 +3742,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3911,6 +3916,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index a0d3c29..62f6341 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -4316,6 +4316,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4520,6 +4525,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H723VE.json b/data/chips/STM32H723VE.json index 6b88f5c..e4adde8 100644 --- a/data/chips/STM32H723VE.json +++ b/data/chips/STM32H723VE.json @@ -4421,7 +4421,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4545,7 +4545,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H723VG.json b/data/chips/STM32H723VG.json index 13f0323..5716d74 100644 --- a/data/chips/STM32H723VG.json +++ b/data/chips/STM32H723VG.json @@ -4421,7 +4421,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4545,7 +4545,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H723ZE.json b/data/chips/STM32H723ZE.json index ea97d94..e442db4 100644 --- a/data/chips/STM32H723ZE.json +++ b/data/chips/STM32H723ZE.json @@ -5057,7 +5057,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5211,7 +5211,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H723ZG.json b/data/chips/STM32H723ZG.json index 3200e6f..7648316 100644 --- a/data/chips/STM32H723ZG.json +++ b/data/chips/STM32H723ZG.json @@ -5057,7 +5057,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5211,7 +5211,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725AE.json b/data/chips/STM32H725AE.json index 985d6af..1e5b1bc 100644 --- a/data/chips/STM32H725AE.json +++ b/data/chips/STM32H725AE.json @@ -5243,7 +5243,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5397,7 +5397,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725AG.json b/data/chips/STM32H725AG.json index 065559f..0c65100 100644 --- a/data/chips/STM32H725AG.json +++ b/data/chips/STM32H725AG.json @@ -5249,7 +5249,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5403,7 +5403,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725IE.json b/data/chips/STM32H725IE.json index 90aa732..9da2e8d 100644 --- a/data/chips/STM32H725IE.json +++ b/data/chips/STM32H725IE.json @@ -5448,7 +5448,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5602,7 +5602,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725IG.json b/data/chips/STM32H725IG.json index dd7f1e9..a58c5c1 100644 --- a/data/chips/STM32H725IG.json +++ b/data/chips/STM32H725IG.json @@ -5454,7 +5454,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5608,7 +5608,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725RE.json b/data/chips/STM32H725RE.json index 564fc16..017ea30 100644 --- a/data/chips/STM32H725RE.json +++ b/data/chips/STM32H725RE.json @@ -3157,7 +3157,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725RG.json b/data/chips/STM32H725RG.json index 960dcc4..676aacc 100644 --- a/data/chips/STM32H725RG.json +++ b/data/chips/STM32H725RG.json @@ -3163,7 +3163,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725VE.json b/data/chips/STM32H725VE.json index 60f0114..f631c4d 100644 --- a/data/chips/STM32H725VE.json +++ b/data/chips/STM32H725VE.json @@ -4306,7 +4306,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4430,7 +4430,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725VG.json b/data/chips/STM32H725VG.json index 667bfae..cc8f36b 100644 --- a/data/chips/STM32H725VG.json +++ b/data/chips/STM32H725VG.json @@ -4316,7 +4316,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4440,7 +4440,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725ZE.json b/data/chips/STM32H725ZE.json index 67eef17..b08bfdb 100644 --- a/data/chips/STM32H725ZE.json +++ b/data/chips/STM32H725ZE.json @@ -4790,7 +4790,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4944,7 +4944,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725ZG.json b/data/chips/STM32H725ZG.json index 0312bd2..b22a198 100644 --- a/data/chips/STM32H725ZG.json +++ b/data/chips/STM32H725ZG.json @@ -4796,7 +4796,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4950,7 +4950,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index 9b524ba..56c0f3c 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -5342,7 +5342,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5496,7 +5496,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index a4590ef..a5bfad4 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -5547,7 +5547,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5701,7 +5701,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index 22ad249..a8285e2 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -4514,7 +4514,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4638,7 +4638,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index 8204227..9127c80 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -5150,7 +5150,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5304,7 +5304,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index 34c06c1..65e11c7 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -4514,7 +4514,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4638,7 +4638,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index c699301..40a58f1 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -5150,7 +5150,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5304,7 +5304,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index f461eb0..079ef12 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -5342,7 +5342,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5496,7 +5496,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index 2b2c623..b0c790e 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -5547,7 +5547,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5701,7 +5701,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index 4b7346c..ad81bda 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -4409,7 +4409,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4533,7 +4533,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index f7cbc24..6742a47 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -4889,7 +4889,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5043,7 +5043,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742AG.json b/data/chips/STM32H742AG.json index 9a55637..647cd42 100644 --- a/data/chips/STM32H742AG.json +++ b/data/chips/STM32H742AG.json @@ -4310,7 +4310,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4464,7 +4464,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4610,7 +4610,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4691,7 +4691,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742AI.json b/data/chips/STM32H742AI.json index d6ab9bb..1d84eb2 100644 --- a/data/chips/STM32H742AI.json +++ b/data/chips/STM32H742AI.json @@ -4321,7 +4321,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4475,7 +4475,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4621,7 +4621,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4702,7 +4702,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742BG.json b/data/chips/STM32H742BG.json index d23aeb4..47ae28c 100644 --- a/data/chips/STM32H742BG.json +++ b/data/chips/STM32H742BG.json @@ -4463,7 +4463,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4617,7 +4617,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4773,7 +4773,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4854,7 +4854,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742BI.json b/data/chips/STM32H742BI.json index a8aa8ce..b9f46e5 100644 --- a/data/chips/STM32H742BI.json +++ b/data/chips/STM32H742BI.json @@ -4474,7 +4474,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4628,7 +4628,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4784,7 +4784,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4865,7 +4865,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742IG.json b/data/chips/STM32H742IG.json index 59aa221..219ee3c 100644 --- a/data/chips/STM32H742IG.json +++ b/data/chips/STM32H742IG.json @@ -4467,7 +4467,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4621,7 +4621,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4777,7 +4777,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4858,7 +4858,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742II.json b/data/chips/STM32H742II.json index 1b1c0d4..d414ffc 100644 --- a/data/chips/STM32H742II.json +++ b/data/chips/STM32H742II.json @@ -4478,7 +4478,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4632,7 +4632,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4788,7 +4788,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4869,7 +4869,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742VG.json b/data/chips/STM32H742VG.json index 2120427..8bd19a8 100644 --- a/data/chips/STM32H742VG.json +++ b/data/chips/STM32H742VG.json @@ -3707,7 +3707,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -3831,7 +3831,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -3942,7 +3942,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4023,7 +4023,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742VI.json b/data/chips/STM32H742VI.json index 31456e5..ff2dbba 100644 --- a/data/chips/STM32H742VI.json +++ b/data/chips/STM32H742VI.json @@ -3718,7 +3718,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -3842,7 +3842,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -3953,7 +3953,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4034,7 +4034,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742XG.json b/data/chips/STM32H742XG.json index a666be1..692dea9 100644 --- a/data/chips/STM32H742XG.json +++ b/data/chips/STM32H742XG.json @@ -4527,7 +4527,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4681,7 +4681,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4837,7 +4837,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4918,7 +4918,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742XI.json b/data/chips/STM32H742XI.json index 72607a8..5e3cdbd 100644 --- a/data/chips/STM32H742XI.json +++ b/data/chips/STM32H742XI.json @@ -4538,7 +4538,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4692,7 +4692,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4848,7 +4848,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4929,7 +4929,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742ZG.json b/data/chips/STM32H742ZG.json index 2b8e44e..4d76898 100644 --- a/data/chips/STM32H742ZG.json +++ b/data/chips/STM32H742ZG.json @@ -4123,7 +4123,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4277,7 +4277,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4403,7 +4403,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4484,7 +4484,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742ZI.json b/data/chips/STM32H742ZI.json index 540452e..766aeb0 100644 --- a/data/chips/STM32H742ZI.json +++ b/data/chips/STM32H742ZI.json @@ -4134,7 +4134,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4288,7 +4288,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4414,7 +4414,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4495,7 +4495,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743AG.json b/data/chips/STM32H743AG.json index 94137e3..d3d3f94 100644 --- a/data/chips/STM32H743AG.json +++ b/data/chips/STM32H743AG.json @@ -4735,7 +4735,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4889,7 +4889,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5035,7 +5035,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5116,7 +5116,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743AI.json b/data/chips/STM32H743AI.json index 3a28649..ba608df 100644 --- a/data/chips/STM32H743AI.json +++ b/data/chips/STM32H743AI.json @@ -4746,7 +4746,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4900,7 +4900,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5046,7 +5046,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5127,7 +5127,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743BG.json b/data/chips/STM32H743BG.json index a879de0..db7eb1e 100644 --- a/data/chips/STM32H743BG.json +++ b/data/chips/STM32H743BG.json @@ -5068,7 +5068,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5222,7 +5222,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5378,7 +5378,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5459,7 +5459,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743BI.json b/data/chips/STM32H743BI.json index 2e4a749..986a435 100644 --- a/data/chips/STM32H743BI.json +++ b/data/chips/STM32H743BI.json @@ -5079,7 +5079,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5233,7 +5233,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5389,7 +5389,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5470,7 +5470,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743IG.json b/data/chips/STM32H743IG.json index d30c78f..c8a1fb6 100644 --- a/data/chips/STM32H743IG.json +++ b/data/chips/STM32H743IG.json @@ -4912,7 +4912,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5066,7 +5066,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5222,7 +5222,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5303,7 +5303,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743II.json b/data/chips/STM32H743II.json index c1d49e3..236bcc1 100644 --- a/data/chips/STM32H743II.json +++ b/data/chips/STM32H743II.json @@ -4923,7 +4923,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5077,7 +5077,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5233,7 +5233,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5314,7 +5314,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743VG.json b/data/chips/STM32H743VG.json index 13df3a6..fda46f6 100644 --- a/data/chips/STM32H743VG.json +++ b/data/chips/STM32H743VG.json @@ -3987,7 +3987,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4111,7 +4111,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4222,7 +4222,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4303,7 +4303,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743VI.json b/data/chips/STM32H743VI.json index 99f9501..70be932 100644 --- a/data/chips/STM32H743VI.json +++ b/data/chips/STM32H743VI.json @@ -3998,7 +3998,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4122,7 +4122,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4233,7 +4233,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4314,7 +4314,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743XG.json b/data/chips/STM32H743XG.json index 0beb3d6..b958a0b 100644 --- a/data/chips/STM32H743XG.json +++ b/data/chips/STM32H743XG.json @@ -5132,7 +5132,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5286,7 +5286,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5442,7 +5442,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5523,7 +5523,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743XI.json b/data/chips/STM32H743XI.json index e3a1807..4fdc09f 100644 --- a/data/chips/STM32H743XI.json +++ b/data/chips/STM32H743XI.json @@ -5143,7 +5143,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5297,7 +5297,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5453,7 +5453,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5534,7 +5534,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743ZG.json b/data/chips/STM32H743ZG.json index cb4a58c..e8fc61a 100644 --- a/data/chips/STM32H743ZG.json +++ b/data/chips/STM32H743ZG.json @@ -4458,7 +4458,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4612,7 +4612,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4738,7 +4738,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4819,7 +4819,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743ZI.json b/data/chips/STM32H743ZI.json index 587dc35..3c0c459 100644 --- a/data/chips/STM32H743ZI.json +++ b/data/chips/STM32H743ZI.json @@ -4469,7 +4469,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4623,7 +4623,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4749,7 +4749,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4830,7 +4830,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745BG.json b/data/chips/STM32H745BG.json index d01321a..ff3911f 100644 --- a/data/chips/STM32H745BG.json +++ b/data/chips/STM32H745BG.json @@ -4954,7 +4954,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5108,7 +5108,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5264,7 +5264,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5345,7 +5345,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14752,7 +14752,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14906,7 +14906,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15062,7 +15062,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15143,7 +15143,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745BI.json b/data/chips/STM32H745BI.json index 6b7b2c9..a0ae6fe 100644 --- a/data/chips/STM32H745BI.json +++ b/data/chips/STM32H745BI.json @@ -4965,7 +4965,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5119,7 +5119,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5275,7 +5275,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5356,7 +5356,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14763,7 +14763,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14917,7 +14917,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15073,7 +15073,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15154,7 +15154,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745IG.json b/data/chips/STM32H745IG.json index da802f3..ae269b2 100644 --- a/data/chips/STM32H745IG.json +++ b/data/chips/STM32H745IG.json @@ -4840,7 +4840,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4994,7 +4994,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5130,7 +5130,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5211,7 +5211,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14380,7 +14380,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14534,7 +14534,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14670,7 +14670,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14751,7 +14751,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745II.json b/data/chips/STM32H745II.json index 1872c6a..acb7064 100644 --- a/data/chips/STM32H745II.json +++ b/data/chips/STM32H745II.json @@ -4851,7 +4851,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5005,7 +5005,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5141,7 +5141,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5222,7 +5222,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14391,7 +14391,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14545,7 +14545,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14681,7 +14681,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14762,7 +14762,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745XG.json b/data/chips/STM32H745XG.json index 9a045b9..9f2eac6 100644 --- a/data/chips/STM32H745XG.json +++ b/data/chips/STM32H745XG.json @@ -5123,7 +5123,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5277,7 +5277,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5433,7 +5433,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5514,7 +5514,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15090,7 +15090,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15244,7 +15244,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15400,7 +15400,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15481,7 +15481,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745XI.json b/data/chips/STM32H745XI.json index 8e86422..3866df3 100644 --- a/data/chips/STM32H745XI.json +++ b/data/chips/STM32H745XI.json @@ -5134,7 +5134,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5288,7 +5288,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5444,7 +5444,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5525,7 +5525,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15101,7 +15101,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15255,7 +15255,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15411,7 +15411,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15492,7 +15492,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745ZG.json b/data/chips/STM32H745ZG.json index f82195e..54b6eb5 100644 --- a/data/chips/STM32H745ZG.json +++ b/data/chips/STM32H745ZG.json @@ -4294,7 +4294,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4448,7 +4448,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4574,7 +4574,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4655,7 +4655,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13027,7 +13027,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13181,7 +13181,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13307,7 +13307,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13388,7 +13388,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745ZI.json b/data/chips/STM32H745ZI.json index be03630..683cd5e 100644 --- a/data/chips/STM32H745ZI.json +++ b/data/chips/STM32H745ZI.json @@ -4305,7 +4305,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4459,7 +4459,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4585,7 +4585,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4666,7 +4666,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13038,7 +13038,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13192,7 +13192,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13318,7 +13318,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13399,7 +13399,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index e464638..1e70863 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -4455,7 +4455,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4609,7 +4609,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4735,7 +4735,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4816,7 +4816,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13407,7 +13407,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13561,7 +13561,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13687,7 +13687,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13768,7 +13768,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index 10f16b9..3a9a159 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -4466,7 +4466,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4620,7 +4620,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4746,7 +4746,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4827,7 +4827,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13418,7 +13418,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13572,7 +13572,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13698,7 +13698,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13779,7 +13779,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index 84f23e9..9a7bb0c 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -4915,7 +4915,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5069,7 +5069,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5225,7 +5225,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5306,7 +5306,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14542,7 +14542,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14696,7 +14696,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14852,7 +14852,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14933,7 +14933,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index 36d7440..f25b4fa 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -4926,7 +4926,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5080,7 +5080,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5236,7 +5236,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5317,7 +5317,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14553,7 +14553,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14707,7 +14707,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14863,7 +14863,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14944,7 +14944,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index 09473ea..a2251dc 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -4455,7 +4455,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4609,7 +4609,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4735,7 +4735,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4816,7 +4816,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13407,7 +13407,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13561,7 +13561,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13687,7 +13687,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13768,7 +13768,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index 5340956..eb2b3c4 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -4466,7 +4466,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4620,7 +4620,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4746,7 +4746,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4827,7 +4827,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13418,7 +13418,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13572,7 +13572,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13698,7 +13698,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13779,7 +13779,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index 88f6309..2ace5fd 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -5129,7 +5129,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5283,7 +5283,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5439,7 +5439,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5520,7 +5520,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15100,7 +15100,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15254,7 +15254,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15410,7 +15410,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15491,7 +15491,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index 37f6ec9..2de9617 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -5140,7 +5140,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5294,7 +5294,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5450,7 +5450,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5531,7 +5531,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15111,7 +15111,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15265,7 +15265,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15421,7 +15421,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15502,7 +15502,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index 7cb92aa..b6b1cf8 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -4204,7 +4204,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4328,7 +4328,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4444,7 +4444,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4525,7 +4525,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12613,7 +12613,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12737,7 +12737,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12853,7 +12853,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12934,7 +12934,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H750IB.json b/data/chips/STM32H750IB.json index cadbb2b..a5e579e 100644 --- a/data/chips/STM32H750IB.json +++ b/data/chips/STM32H750IB.json @@ -4961,7 +4961,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5115,7 +5115,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5271,7 +5271,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5352,7 +5352,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H750VB.json b/data/chips/STM32H750VB.json index 99e5382..94b17dd 100644 --- a/data/chips/STM32H750VB.json +++ b/data/chips/STM32H750VB.json @@ -4032,7 +4032,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4156,7 +4156,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4267,7 +4267,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4348,7 +4348,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H750XB.json b/data/chips/STM32H750XB.json index a9887d1..db4665b 100644 --- a/data/chips/STM32H750XB.json +++ b/data/chips/STM32H750XB.json @@ -5181,7 +5181,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5335,7 +5335,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5491,7 +5491,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5572,7 +5572,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H750ZB.json b/data/chips/STM32H750ZB.json index b9b0628..75b238a 100644 --- a/data/chips/STM32H750ZB.json +++ b/data/chips/STM32H750ZB.json @@ -4495,7 +4495,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4649,7 +4649,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4775,7 +4775,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4856,7 +4856,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753AI.json b/data/chips/STM32H753AI.json index 1e2c673..4b2677e 100644 --- a/data/chips/STM32H753AI.json +++ b/data/chips/STM32H753AI.json @@ -4813,7 +4813,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4967,7 +4967,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5113,7 +5113,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5194,7 +5194,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753BI.json b/data/chips/STM32H753BI.json index d6fecbc..930ded6 100644 --- a/data/chips/STM32H753BI.json +++ b/data/chips/STM32H753BI.json @@ -5146,7 +5146,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5300,7 +5300,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5456,7 +5456,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5537,7 +5537,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753II.json b/data/chips/STM32H753II.json index 69c32f8..f54a32a 100644 --- a/data/chips/STM32H753II.json +++ b/data/chips/STM32H753II.json @@ -4990,7 +4990,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5144,7 +5144,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5300,7 +5300,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5381,7 +5381,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753VI.json b/data/chips/STM32H753VI.json index 1cb935b..d3ee432 100644 --- a/data/chips/STM32H753VI.json +++ b/data/chips/STM32H753VI.json @@ -4065,7 +4065,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4189,7 +4189,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4300,7 +4300,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4381,7 +4381,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753XI.json b/data/chips/STM32H753XI.json index 67f0845..d222ab3 100644 --- a/data/chips/STM32H753XI.json +++ b/data/chips/STM32H753XI.json @@ -5210,7 +5210,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5364,7 +5364,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5520,7 +5520,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5601,7 +5601,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753ZI.json b/data/chips/STM32H753ZI.json index 33bc0a0..79207d6 100644 --- a/data/chips/STM32H753ZI.json +++ b/data/chips/STM32H753ZI.json @@ -4536,7 +4536,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4690,7 +4690,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4816,7 +4816,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4897,7 +4897,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index 6084b01..59e2ae0 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -5032,7 +5032,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5186,7 +5186,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5342,7 +5342,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5423,7 +5423,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14895,7 +14895,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15049,7 +15049,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15205,7 +15205,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15286,7 +15286,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index d4c258d..73df4be 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -4918,7 +4918,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5072,7 +5072,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5208,7 +5208,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5289,7 +5289,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14523,7 +14523,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14677,7 +14677,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14813,7 +14813,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14894,7 +14894,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index 234ea37..272f463 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -5201,7 +5201,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5355,7 +5355,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5511,7 +5511,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5592,7 +5592,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15233,7 +15233,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15387,7 +15387,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15543,7 +15543,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15624,7 +15624,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index 7cf0cb2..e1b2949 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -4372,7 +4372,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4526,7 +4526,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4652,7 +4652,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4733,7 +4733,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13170,7 +13170,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13324,7 +13324,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13450,7 +13450,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13531,7 +13531,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index a9f89e2..7709506 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -4533,7 +4533,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4687,7 +4687,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4813,7 +4813,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4894,7 +4894,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13550,7 +13550,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13704,7 +13704,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13830,7 +13830,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13911,7 +13911,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index fd3579f..5c078c8 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -4993,7 +4993,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5147,7 +5147,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5303,7 +5303,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5384,7 +5384,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14685,7 +14685,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14839,7 +14839,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14995,7 +14995,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15076,7 +15076,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 717e943..fb519d0 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -4533,7 +4533,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4687,7 +4687,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4813,7 +4813,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4894,7 +4894,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13550,7 +13550,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13704,7 +13704,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13830,7 +13830,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13911,7 +13911,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 6515bab..f1904bb 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -5207,7 +5207,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5361,7 +5361,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5517,7 +5517,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5598,7 +5598,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15243,7 +15243,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15397,7 +15397,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15553,7 +15553,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15634,7 +15634,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index c41cb96..5a4fe23 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -4271,7 +4271,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4395,7 +4395,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4511,7 +4511,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4592,7 +4592,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12745,7 +12745,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12869,7 +12869,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12985,7 +12985,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13066,7 +13066,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index 16b80ac..2455878 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -4761,7 +4761,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4915,7 +4915,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index 52add67..00673d7 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -4772,7 +4772,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4926,7 +4926,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index fe485f0..666bf3f 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -5174,7 +5174,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5328,7 +5328,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index 05f1718..ad15f10 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -5185,7 +5185,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5339,7 +5339,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index a9b3465..4754652 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -5326,7 +5326,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5480,7 +5480,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index 83d5d44..71dd1c4 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -5343,7 +5343,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5497,7 +5497,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index c1b7b32..53c11c5 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -5288,7 +5288,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5442,7 +5442,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index 4bff280..c082a7d 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -5299,7 +5299,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5453,7 +5453,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index 42d4074..f90d06b 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -4238,7 +4238,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4352,7 +4352,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3RG.json b/data/chips/STM32H7A3RG.json index 7b5de51..972646e 100644 --- a/data/chips/STM32H7A3RG.json +++ b/data/chips/STM32H7A3RG.json @@ -3205,7 +3205,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3RI.json b/data/chips/STM32H7A3RI.json index ac99cce..4dc0665 100644 --- a/data/chips/STM32H7A3RI.json +++ b/data/chips/STM32H7A3RI.json @@ -3216,7 +3216,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index 49e9eb5..1c9cf3f 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -4091,7 +4091,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4215,7 +4215,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index a6a33e8..8840b91 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -4102,7 +4102,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4226,7 +4226,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index 4a208d0..be45af4 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -4571,7 +4571,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4725,7 +4725,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index 8d56785..9562fee 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -4582,7 +4582,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4736,7 +4736,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index 33ef74d..b4e0e39 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -4848,7 +4848,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5002,7 +5002,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index f95f23c..35c733c 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -5218,7 +5218,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5372,7 +5372,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index 46837aa..1ab9a59 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -3282,7 +3282,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index e34733c..de64143 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -4156,7 +4156,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4280,7 +4280,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index 197df25..ed8b535 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -4654,7 +4654,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4808,7 +4808,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index 63fa7ed..068dcec 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -4865,7 +4865,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5019,7 +5019,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index ae4c547..2b12c49 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -5278,7 +5278,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5432,7 +5432,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index dfb7d10..153a1ec 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -5436,7 +5436,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5590,7 +5590,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index ceecbf0..5cd11d6 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -5392,7 +5392,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5546,7 +5546,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index 3a1be90..36a6bd6 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -4321,7 +4321,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4435,7 +4435,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 4c40136..ccd2317 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -3299,7 +3299,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index c737122..509c7c2 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -4185,7 +4185,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4309,7 +4309,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index f5bf6b2..55ee9a8 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -4675,7 +4675,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4829,7 +4829,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32L552CC.json b/data/chips/STM32L552CC.json index d72b327..92c5cba 100644 --- a/data/chips/STM32L552CC.json +++ b/data/chips/STM32L552CC.json @@ -2000,6 +2000,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2141,6 +2146,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552CE.json b/data/chips/STM32L552CE.json index 7ac364c..0006c5c 100644 --- a/data/chips/STM32L552CE.json +++ b/data/chips/STM32L552CE.json @@ -2008,6 +2008,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2149,6 +2154,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552ME.json b/data/chips/STM32L552ME.json index 88c1dee..8e32931 100644 --- a/data/chips/STM32L552ME.json +++ b/data/chips/STM32L552ME.json @@ -2194,6 +2194,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2350,6 +2355,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552QC.json b/data/chips/STM32L552QC.json index a0a9027..c672ee3 100644 --- a/data/chips/STM32L552QC.json +++ b/data/chips/STM32L552QC.json @@ -2782,6 +2782,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3028,6 +3033,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552QE.json b/data/chips/STM32L552QE.json index e6db8d8..9e28264 100644 --- a/data/chips/STM32L552QE.json +++ b/data/chips/STM32L552QE.json @@ -2790,6 +2790,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3036,6 +3041,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552RC.json b/data/chips/STM32L552RC.json index 3616ca0..3efd295 100644 --- a/data/chips/STM32L552RC.json +++ b/data/chips/STM32L552RC.json @@ -2151,6 +2151,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2312,6 +2317,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552RE.json b/data/chips/STM32L552RE.json index 76ae26b..8e32e09 100644 --- a/data/chips/STM32L552RE.json +++ b/data/chips/STM32L552RE.json @@ -2159,6 +2159,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2320,6 +2325,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552VC.json b/data/chips/STM32L552VC.json index f06651e..d86aed8 100644 --- a/data/chips/STM32L552VC.json +++ b/data/chips/STM32L552VC.json @@ -2532,6 +2532,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2768,6 +2773,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552VE.json b/data/chips/STM32L552VE.json index b8980d1..a04d158 100644 --- a/data/chips/STM32L552VE.json +++ b/data/chips/STM32L552VE.json @@ -2536,6 +2536,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2772,6 +2777,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552ZC.json b/data/chips/STM32L552ZC.json index c29bac0..ed3523e 100644 --- a/data/chips/STM32L552ZC.json +++ b/data/chips/STM32L552ZC.json @@ -2807,6 +2807,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3078,6 +3083,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552ZE.json b/data/chips/STM32L552ZE.json index e50b790..5f79cee 100644 --- a/data/chips/STM32L552ZE.json +++ b/data/chips/STM32L552ZE.json @@ -2811,6 +2811,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3082,6 +3087,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index aff4647..01e4028 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -2091,6 +2091,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2232,6 +2237,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index 3c21f3c..a0f34d2 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -2277,6 +2277,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2433,6 +2438,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index c36a96b..254fd29 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -2873,6 +2873,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3119,6 +3124,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index e825ed9..93afb69 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -2242,6 +2242,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2403,6 +2408,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index 56cdd63..11a1eb3 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -2619,6 +2619,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2855,6 +2860,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index 0074271..73a79a7 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -2894,6 +2894,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3165,6 +3170,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index b219df4..c1e2c8a 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -2155,6 +2155,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index 57a2fdc..8f86931 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -2155,6 +2155,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index 409980d..fc8dd95 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -2155,6 +2155,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index 7d507df..4d51ce8 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -2256,6 +2256,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index bf146bd..a042e48 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -2122,6 +2122,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index 9f770aa..8937f1d 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -2122,6 +2122,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index db444cc..22a78be 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -2362,6 +2362,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index e11e4e3..17dc8d8 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -2362,6 +2362,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index ea540e5..ebd8caa 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -2362,6 +2362,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index 92cc9ae..da1ec39 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -2932,6 +2932,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index bd6708b..7767f6d 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -2932,6 +2932,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index c28cad5..edf302d 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -2275,6 +2275,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index 59af698..d8e786c 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -2376,6 +2376,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index f0e2408..71f38a2 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -2242,6 +2242,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index 7661b41..1cf2500 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -2482,6 +2482,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index ecaa6f8..c06b515 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -3052,6 +3052,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575AG.json b/data/chips/STM32U575AG.json index 984af62..e1e6e90 100644 --- a/data/chips/STM32U575AG.json +++ b/data/chips/STM32U575AG.json @@ -4634,6 +4634,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4898,6 +4903,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575AI.json b/data/chips/STM32U575AI.json index ec79a37..f174689 100644 --- a/data/chips/STM32U575AI.json +++ b/data/chips/STM32U575AI.json @@ -4634,6 +4634,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4898,6 +4903,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575CG.json b/data/chips/STM32U575CG.json index becf4c3..923def3 100644 --- a/data/chips/STM32U575CG.json +++ b/data/chips/STM32U575CG.json @@ -2748,6 +2748,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575CI.json b/data/chips/STM32U575CI.json index 27a1cdb..58ef3ef 100644 --- a/data/chips/STM32U575CI.json +++ b/data/chips/STM32U575CI.json @@ -2748,6 +2748,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575OG.json b/data/chips/STM32U575OG.json index 3b4a3c6..51c221c 100644 --- a/data/chips/STM32U575OG.json +++ b/data/chips/STM32U575OG.json @@ -3521,6 +3521,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575OI.json b/data/chips/STM32U575OI.json index b08b95d..9d9eaf8 100644 --- a/data/chips/STM32U575OI.json +++ b/data/chips/STM32U575OI.json @@ -3521,6 +3521,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575QG.json b/data/chips/STM32U575QG.json index f28a7f1..f9c78ef 100644 --- a/data/chips/STM32U575QG.json +++ b/data/chips/STM32U575QG.json @@ -4244,6 +4244,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4483,6 +4488,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575QI.json b/data/chips/STM32U575QI.json index 77203c3..101a54c 100644 --- a/data/chips/STM32U575QI.json +++ b/data/chips/STM32U575QI.json @@ -4244,6 +4244,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4483,6 +4488,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575RG.json b/data/chips/STM32U575RG.json index f1829ab..1aab7aa 100644 --- a/data/chips/STM32U575RG.json +++ b/data/chips/STM32U575RG.json @@ -3215,6 +3215,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575RI.json b/data/chips/STM32U575RI.json index 810ceec..6a3d590 100644 --- a/data/chips/STM32U575RI.json +++ b/data/chips/STM32U575RI.json @@ -3215,6 +3215,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575VG.json b/data/chips/STM32U575VG.json index 2648201..caa5446 100644 --- a/data/chips/STM32U575VG.json +++ b/data/chips/STM32U575VG.json @@ -3854,6 +3854,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4083,6 +4088,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575VI.json b/data/chips/STM32U575VI.json index 517ebbe..942c1f5 100644 --- a/data/chips/STM32U575VI.json +++ b/data/chips/STM32U575VI.json @@ -3854,6 +3854,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4083,6 +4088,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575ZG.json b/data/chips/STM32U575ZG.json index 6d4a258..c9e5acb 100644 --- a/data/chips/STM32U575ZG.json +++ b/data/chips/STM32U575ZG.json @@ -4324,6 +4324,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4588,6 +4593,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575ZI.json b/data/chips/STM32U575ZI.json index 3abaf1d..9cd0d32 100644 --- a/data/chips/STM32U575ZI.json +++ b/data/chips/STM32U575ZI.json @@ -4324,6 +4324,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4588,6 +4593,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index b76e9a7..9f79d9c 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -4782,6 +4782,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5046,6 +5051,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index 7342ec6..ec615ce 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -2896,6 +2896,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index c9631b9..76d6e85 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -3669,6 +3669,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index 65a429e..ce77bd0 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -4392,6 +4392,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4631,6 +4636,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index 484fd62..bdc04bc 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -3363,6 +3363,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index 3f7ee46..5ca2fc6 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -4002,6 +4002,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4231,6 +4236,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index e686778..f17048c 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -4472,6 +4472,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4736,6 +4741,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index dc83dab..a605316 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -4547,6 +4547,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4811,6 +4816,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index a01f045..6b24ce6 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -4547,6 +4547,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4811,6 +4816,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index 62f65df..9e9c7c1 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -4142,6 +4142,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4381,6 +4386,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index 45fc172..ccfce18 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -4142,6 +4142,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4381,6 +4386,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index 67d414e..60086d8 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -2961,6 +2961,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index 974439a..6af30d3 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -2961,6 +2961,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index 976e7d8..00485e7 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -3717,6 +3717,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3946,6 +3951,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index 882835b..b51dcfc 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -3717,6 +3717,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3946,6 +3951,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index 9a551f6..07847fb 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -4226,6 +4226,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4490,6 +4495,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index 2cf047d..d7446f8 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -4226,6 +4226,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4490,6 +4495,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index 1d5b681..a038997 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -4983,6 +4983,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5247,6 +5252,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index 36f1ef7..ba1d96f 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -5008,6 +5008,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5272,6 +5277,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index bcb2a8c..d36ffbe 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -5008,6 +5008,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5272,6 +5277,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index badfc70..567be41 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -3875,6 +3875,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4099,6 +4104,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index 7bea3ff..de39174 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -3980,6 +3980,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4209,6 +4214,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index 479ae83..eb587f0 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -4515,6 +4515,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4779,6 +4784,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index 0438d2a..441bd80 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -4515,6 +4515,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4779,6 +4784,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index 4014c80..471d615 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -4689,6 +4689,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4953,6 +4958,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index 2600e90..dc20f50 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -4284,6 +4284,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4523,6 +4528,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index d820537..c719a3a 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -3103,6 +3103,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index 6351aea..6402180 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -3859,6 +3859,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4088,6 +4093,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 36664b8..33dd6ac 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -4368,6 +4368,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4632,6 +4637,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 0d9b620..7baa74e 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -5125,6 +5125,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5389,6 +5394,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index bcb6b06..b4134aa 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -5150,6 +5150,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5414,6 +5419,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index e2e9817..7afacc4 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -4017,6 +4017,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4241,6 +4246,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index c962e83..92e88a5 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -4657,6 +4657,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4921,6 +4926,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/registers/sai_v3_2pdm.json b/data/registers/sai_v3_2pdm.json new file mode 100644 index 0000000..dbe4698 --- /dev/null +++ b/data/registers/sai_v3_2pdm.json @@ -0,0 +1,916 @@ +{ + "block/CH": { + "description": "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR", + "items": [ + { + "name": "CR1", + "description": "Configuration register 1", + "byte_offset": 0, + "fieldset": "CR1" + }, + { + "name": "CR2", + "description": "Configuration register 2", + "byte_offset": 4, + "fieldset": "CR2" + }, + { + "name": "FRCR", + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "byte_offset": 8, + "fieldset": "FRCR" + }, + { + "name": "SLOTR", + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "byte_offset": 12, + "fieldset": "SLOTR" + }, + { + "name": "IM", + "description": "Interrupt mask register 2", + "byte_offset": 16, + "fieldset": "IM" + }, + { + "name": "SR", + "description": "Status register", + "byte_offset": 20, + "access": "Read", + "fieldset": "SR" + }, + { + "name": "CLRFR", + "description": "Clear flag register", + "byte_offset": 24, + "access": "Write", + "fieldset": "CLRFR" + }, + { + "name": "DR", + "description": "Data register", + "byte_offset": 28, + "fieldset": "DR" + } + ] + }, + "block/SAI": { + "description": "Serial audio interface", + "items": [ + { + "name": "GCR", + "description": "Global configuration register", + "byte_offset": 0, + "fieldset": "GCR" + }, + { + "name": "CH", + "description": "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR", + "array": { + "len": 2, + "stride": 32 + }, + "byte_offset": 4, + "block": "CH" + }, + { + "name": "PDMCR", + "description": "PDM control register", + "byte_offset": 68, + "fieldset": "PDMCR" + }, + { + "name": "PDMDLY", + "description": "PDM delay register", + "byte_offset": 72, + "fieldset": "PDMDLY" + } + ] + }, + "fieldset/CLRFR": { + "description": "Clear flag register", + "fields": [ + { + "name": "COVRUDR", + "description": "Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CMUTEDET", + "description": "Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CWCKCFG", + "description": "Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CCNRDY", + "description": "Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "CAFSDET", + "description": "Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CLFSDET", + "description": "Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/CR1": { + "description": "Configuration register 1", + "fields": [ + { + "name": "MODE", + "description": "SAIx audio block mode immediately", + "bit_offset": 0, + "bit_size": 2, + "enum": "MODE" + }, + { + "name": "PRTCFG", + "description": "Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled.", + "bit_offset": 2, + "bit_size": 2, + "enum": "PRTCFG" + }, + { + "name": "DS", + "description": "Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled.", + "bit_offset": 5, + "bit_size": 3, + "enum": "DS" + }, + { + "name": "LSBFIRST", + "description": "Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first.", + "bit_offset": 8, + "bit_size": 1, + "enum": "LSBFIRST" + }, + { + "name": "CKSTR", + "description": "Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol.", + "bit_offset": 9, + "bit_size": 1, + "enum": "CKSTR" + }, + { + "name": "SYNCEN", + "description": "Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.", + "bit_offset": 10, + "bit_size": 2, + "enum": "SYNCEN" + }, + { + "name": "MONO", + "description": "Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details.", + "bit_offset": 12, + "bit_size": 1, + "enum": "MONO" + }, + { + "name": "OUTDRIV", + "description": "Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration.", + "bit_offset": 13, + "bit_size": 1, + "enum": "OUTDRIV" + }, + { + "name": "SAIEN", + "description": "Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "DMAEN", + "description": "DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "NODIV", + "description": "No fixed divider between MCLK and FS", + "bit_offset": 19, + "bit_size": 1, + "enum": "NODIV" + }, + { + "name": "MCKDIV", + "description": "Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:", + "bit_offset": 20, + "bit_size": 6 + }, + { + "name": "OSR", + "description": "Oversampling ratio for master clock", + "bit_offset": 26, + "bit_size": 1 + } + ] + }, + "fieldset/CR2": { + "description": "Configuration register 2", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold. This bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 3, + "enum": "FTH" + }, + { + "name": "FFLUSH", + "description": "FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TRIS", + "description": "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "MUTE", + "description": "Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "MUTEVAL", + "description": "Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.", + "bit_offset": 6, + "bit_size": 1, + "enum": "MUTEVAL" + }, + { + "name": "MUTECNT", + "description": "Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details.", + "bit_offset": 7, + "bit_size": 6 + }, + { + "name": "CPL", + "description": "Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm.", + "bit_offset": 13, + "bit_size": 1, + "enum": "CPL" + }, + { + "name": "COMP", + "description": "Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected.", + "bit_offset": 14, + "bit_size": 2, + "enum": "COMP" + } + ] + }, + "fieldset/DR": { + "description": "Data register", + "fields": [ + { + "name": "DATA", + "description": "Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/FRCR": { + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "fields": [ + { + "name": "FRL", + "description": "Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "FSALL", + "description": "Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled.", + "bit_offset": 8, + "bit_size": 7 + }, + { + "name": "FSDEF", + "description": "Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "FSPOL", + "description": "Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.", + "bit_offset": 17, + "bit_size": 1, + "enum": "FSPOL" + }, + { + "name": "FSOFF", + "description": "Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.", + "bit_offset": 18, + "bit_size": 1, + "enum": "FSOFF" + } + ] + }, + "fieldset/GCR": { + "description": "Global configuration register", + "fields": [ + { + "name": "SYNCIN", + "description": "Synchronization inputs", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "SYNCOUT", + "description": "Synchronization outputs These bits are set and cleared by software.", + "bit_offset": 4, + "bit_size": 2 + } + ] + }, + "fieldset/IM": { + "description": "Interrupt mask register 2", + "fields": [ + { + "name": "OVRUDRIE", + "description": "Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MUTEDETIE", + "description": "Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "WCKCFGIE", + "description": "Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "FREQIE", + "description": "FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CNRDYIE", + "description": "Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AFSDETIE", + "description": "Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LFSDETIE", + "description": "Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/PDMCR": { + "description": "PDM control register", + "fields": [ + { + "name": "PDMEN", + "description": "PDM enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MICNBR", + "description": "Number of microphones", + "bit_offset": 4, + "bit_size": 2 + }, + { + "name": "CKEN", + "description": "Clock enable of bitstream clock number 1", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + } + ] + }, + "fieldset/PDMDLY": { + "description": "PDM delay register", + "fields": [ + { + "name": "DLYML", + "description": "Delay line adjust for first microphone of pair 1", + "bit_offset": 0, + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } + }, + { + "name": "DLYMR", + "description": "Delay line adjust for second microphone of pair 1", + "bit_offset": 4, + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } + } + ] + }, + "fieldset/SLOTR": { + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "fields": [ + { + "name": "FBOFF", + "description": "First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 0, + "bit_size": 5 + }, + { + "name": "SLOTSZ", + "description": "Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 6, + "bit_size": 2, + "enum": "SLOTSZ" + }, + { + "name": "NBSLOT", + "description": "Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SLOTEN", + "description": "Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 16, + "bit_size": 16, + "enum": "SLOTEN" + } + ] + }, + "fieldset/SR": { + "description": "Status register", + "fields": [ + { + "name": "OVRUDR", + "description": "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MUTEDET", + "description": "Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register.", + "bit_offset": 2, + "bit_size": 1, + "enum": "WCKCFG" + }, + { + "name": "FREQ", + "description": "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CNRDY", + "description": "Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register.", + "bit_offset": 4, + "bit_size": 1, + "enum": "CNRDY" + }, + { + "name": "AFSDET", + "description": "Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LFSDET", + "description": "Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "FLVL", + "description": "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:", + "bit_offset": 16, + "bit_size": 3, + "enum": "FLVL" + } + ] + }, + "enum/CKSTR": { + "bit_size": 1, + "variants": [ + { + "name": "FallingEdge", + "description": "Data strobing edge is falling edge of SCK", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "Data strobing edge is rising edge of SCK", + "value": 1 + } + ] + }, + "enum/CNRDY": { + "bit_size": 1, + "variants": [ + { + "name": "Ready", + "description": "External AC’97 Codec is ready", + "value": 0 + }, + { + "name": "NotReady", + "description": "External AC’97 Codec is not ready", + "value": 1 + } + ] + }, + "enum/COMP": { + "bit_size": 2, + "variants": [ + { + "name": "NoCompanding", + "description": "No companding algorithm", + "value": 0 + }, + { + "name": "MuLaw", + "description": "μ-Law algorithm", + "value": 2 + }, + { + "name": "ALaw", + "description": "A-Law algorithm", + "value": 3 + } + ] + }, + "enum/CPL": { + "bit_size": 1, + "variants": [ + { + "name": "OnesComplement", + "description": "1’s complement representation", + "value": 0 + }, + { + "name": "TwosComplement", + "description": "2’s complement representation", + "value": 1 + } + ] + }, + "enum/DS": { + "bit_size": 3, + "variants": [ + { + "name": "Bit8", + "description": "8 bits", + "value": 2 + }, + { + "name": "Bit10", + "description": "10 bits", + "value": 3 + }, + { + "name": "Bit16", + "description": "16 bits", + "value": 4 + }, + { + "name": "Bit20", + "description": "20 bits", + "value": 5 + }, + { + "name": "Bit24", + "description": "24 bits", + "value": 6 + }, + { + "name": "Bit32", + "description": "32 bits", + "value": 7 + } + ] + }, + "enum/FLVL": { + "bit_size": 3, + "variants": [ + { + "name": "Empty", + "description": "FIFO empty", + "value": 0 + }, + { + "name": "Quarter1", + "description": "FIFO <= 1⁄4 but not empty", + "value": 1 + }, + { + "name": "Quarter2", + "description": "1⁄4 < FIFO <= 1⁄2", + "value": 2 + }, + { + "name": "Quarter3", + "description": "1⁄2 < FIFO <= 3⁄4", + "value": 3 + }, + { + "name": "Quarter4", + "description": "3⁄4 < FIFO but not full", + "value": 4 + }, + { + "name": "Full", + "description": "FIFO full", + "value": 5 + } + ] + }, + "enum/FSOFF": { + "bit_size": 1, + "variants": [ + { + "name": "OnFirst", + "description": "FS is asserted on the first bit of the slot 0", + "value": 0 + }, + { + "name": "BeforeFirst", + "description": "FS is asserted one bit before the first bit of the slot 0", + "value": 1 + } + ] + }, + "enum/FSPOL": { + "bit_size": 1, + "variants": [ + { + "name": "FallingEdge", + "description": "FS is active low (falling edge)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "FS is active high (rising edge)", + "value": 1 + } + ] + }, + "enum/FTH": { + "bit_size": 3, + "variants": [ + { + "name": "Empty", + "description": "FIFO empty", + "value": 0 + }, + { + "name": "Quarter1", + "description": "1⁄4 FIFO", + "value": 1 + }, + { + "name": "Quarter2", + "description": "1⁄2 FIFO", + "value": 2 + }, + { + "name": "Quarter3", + "description": "3⁄4 FIFO", + "value": 3 + }, + { + "name": "Full", + "description": "FIFO full", + "value": 4 + } + ] + }, + "enum/LSBFIRST": { + "bit_size": 1, + "variants": [ + { + "name": "MsbFirst", + "description": "Data are transferred with MSB first", + "value": 0 + }, + { + "name": "LsbFirst", + "description": "Data are transferred with LSB first", + "value": 1 + } + ] + }, + "enum/MODE": { + "bit_size": 2, + "variants": [ + { + "name": "MasterTx", + "description": "Master transmitter", + "value": 0 + }, + { + "name": "MasterRx", + "description": "Master receiver", + "value": 1 + }, + { + "name": "SlaveTx", + "description": "Slave transmitter", + "value": 2 + }, + { + "name": "SlaveRx", + "description": "Slave receiver", + "value": 3 + } + ] + }, + "enum/MONO": { + "bit_size": 1, + "variants": [ + { + "name": "Stereo", + "description": "Stereo mode", + "value": 0 + }, + { + "name": "Mono", + "description": "Mono mode", + "value": 1 + } + ] + }, + "enum/MUTEVAL": { + "bit_size": 1, + "variants": [ + { + "name": "SendZero", + "description": "Bit value 0 is sent during the mute mode", + "value": 0 + }, + { + "name": "SendLast", + "description": "Last values are sent during the mute mode", + "value": 1 + } + ] + }, + "enum/NODIV": { + "bit_size": 1, + "variants": [ + { + "name": "MasterClock", + "description": "MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value", + "value": 0 + }, + { + "name": "NoDiv", + "description": "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.", + "value": 1 + } + ] + }, + "enum/OUTDRIV": { + "bit_size": 1, + "variants": [ + { + "name": "OnStart", + "description": "Audio block output driven when SAIEN is set", + "value": 0 + }, + { + "name": "Immediately", + "description": "Audio block output driven immediately after the setting of this bit", + "value": 1 + } + ] + }, + "enum/PRTCFG": { + "bit_size": 2, + "variants": [ + { + "name": "Free", + "description": "Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol", + "value": 0 + }, + { + "name": "Spdif", + "description": "SPDIF protocol", + "value": 1 + }, + { + "name": "Ac97", + "description": "AC’97 protocol", + "value": 2 + } + ] + }, + "enum/SLOTEN": { + "bit_size": 16, + "variants": [ + { + "name": "Inactive", + "description": "Inactive slot", + "value": 0 + }, + { + "name": "Active", + "description": "Active slot", + "value": 1 + } + ] + }, + "enum/SLOTSZ": { + "bit_size": 2, + "variants": [ + { + "name": "DataSize", + "description": "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)", + "value": 0 + }, + { + "name": "Bit16", + "description": "16-bit", + "value": 1 + }, + { + "name": "Bit32", + "description": "32-bit", + "value": 2 + } + ] + }, + "enum/SYNCEN": { + "bit_size": 2, + "variants": [ + { + "name": "Asynchronous", + "description": "audio sub-block in asynchronous mode", + "value": 0 + }, + { + "name": "Internal", + "description": "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode", + "value": 1 + }, + { + "name": "External", + "description": "audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode", + "value": 2 + } + ] + }, + "enum/WCKCFG": { + "bit_size": 1, + "variants": [ + { + "name": "Correct", + "description": "Clock configuration is correct", + "value": 0 + }, + { + "name": "Wrong", + "description": "Clock configuration does not respect the rule concerning the frame length specification", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/sai_v3_4pdm.json b/data/registers/sai_v3_4pdm.json new file mode 100644 index 0000000..cf40008 --- /dev/null +++ b/data/registers/sai_v3_4pdm.json @@ -0,0 +1,916 @@ +{ + "block/CH": { + "description": "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR", + "items": [ + { + "name": "CR1", + "description": "Configuration register 1", + "byte_offset": 0, + "fieldset": "CR1" + }, + { + "name": "CR2", + "description": "Configuration register 2", + "byte_offset": 4, + "fieldset": "CR2" + }, + { + "name": "FRCR", + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "byte_offset": 8, + "fieldset": "FRCR" + }, + { + "name": "SLOTR", + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "byte_offset": 12, + "fieldset": "SLOTR" + }, + { + "name": "IM", + "description": "Interrupt mask register 2", + "byte_offset": 16, + "fieldset": "IM" + }, + { + "name": "SR", + "description": "Status register", + "byte_offset": 20, + "access": "Read", + "fieldset": "SR" + }, + { + "name": "CLRFR", + "description": "Clear flag register", + "byte_offset": 24, + "access": "Write", + "fieldset": "CLRFR" + }, + { + "name": "DR", + "description": "Data register", + "byte_offset": 28, + "fieldset": "DR" + } + ] + }, + "block/SAI": { + "description": "Serial audio interface", + "items": [ + { + "name": "GCR", + "description": "Global configuration register", + "byte_offset": 0, + "fieldset": "GCR" + }, + { + "name": "CH", + "description": "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR", + "array": { + "len": 2, + "stride": 32 + }, + "byte_offset": 4, + "block": "CH" + }, + { + "name": "PDMCR", + "description": "PDM control register", + "byte_offset": 68, + "fieldset": "PDMCR" + }, + { + "name": "PDMDLY", + "description": "PDM delay register", + "byte_offset": 72, + "fieldset": "PDMDLY" + } + ] + }, + "fieldset/CLRFR": { + "description": "Clear flag register", + "fields": [ + { + "name": "COVRUDR", + "description": "Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CMUTEDET", + "description": "Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CWCKCFG", + "description": "Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CCNRDY", + "description": "Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "CAFSDET", + "description": "Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CLFSDET", + "description": "Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/CR1": { + "description": "Configuration register 1", + "fields": [ + { + "name": "MODE", + "description": "SAIx audio block mode immediately", + "bit_offset": 0, + "bit_size": 2, + "enum": "MODE" + }, + { + "name": "PRTCFG", + "description": "Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled.", + "bit_offset": 2, + "bit_size": 2, + "enum": "PRTCFG" + }, + { + "name": "DS", + "description": "Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled.", + "bit_offset": 5, + "bit_size": 3, + "enum": "DS" + }, + { + "name": "LSBFIRST", + "description": "Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first.", + "bit_offset": 8, + "bit_size": 1, + "enum": "LSBFIRST" + }, + { + "name": "CKSTR", + "description": "Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol.", + "bit_offset": 9, + "bit_size": 1, + "enum": "CKSTR" + }, + { + "name": "SYNCEN", + "description": "Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.", + "bit_offset": 10, + "bit_size": 2, + "enum": "SYNCEN" + }, + { + "name": "MONO", + "description": "Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details.", + "bit_offset": 12, + "bit_size": 1, + "enum": "MONO" + }, + { + "name": "OUTDRIV", + "description": "Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration.", + "bit_offset": 13, + "bit_size": 1, + "enum": "OUTDRIV" + }, + { + "name": "SAIEN", + "description": "Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "DMAEN", + "description": "DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "NODIV", + "description": "No fixed divider between MCLK and FS", + "bit_offset": 19, + "bit_size": 1, + "enum": "NODIV" + }, + { + "name": "MCKDIV", + "description": "Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:", + "bit_offset": 20, + "bit_size": 6 + }, + { + "name": "OSR", + "description": "Oversampling ratio for master clock", + "bit_offset": 26, + "bit_size": 1 + } + ] + }, + "fieldset/CR2": { + "description": "Configuration register 2", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold. This bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 3, + "enum": "FTH" + }, + { + "name": "FFLUSH", + "description": "FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TRIS", + "description": "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "MUTE", + "description": "Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "MUTEVAL", + "description": "Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.", + "bit_offset": 6, + "bit_size": 1, + "enum": "MUTEVAL" + }, + { + "name": "MUTECNT", + "description": "Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details.", + "bit_offset": 7, + "bit_size": 6 + }, + { + "name": "CPL", + "description": "Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm.", + "bit_offset": 13, + "bit_size": 1, + "enum": "CPL" + }, + { + "name": "COMP", + "description": "Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected.", + "bit_offset": 14, + "bit_size": 2, + "enum": "COMP" + } + ] + }, + "fieldset/DR": { + "description": "Data register", + "fields": [ + { + "name": "DATA", + "description": "Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/FRCR": { + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "fields": [ + { + "name": "FRL", + "description": "Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "FSALL", + "description": "Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled.", + "bit_offset": 8, + "bit_size": 7 + }, + { + "name": "FSDEF", + "description": "Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "FSPOL", + "description": "Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.", + "bit_offset": 17, + "bit_size": 1, + "enum": "FSPOL" + }, + { + "name": "FSOFF", + "description": "Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.", + "bit_offset": 18, + "bit_size": 1, + "enum": "FSOFF" + } + ] + }, + "fieldset/GCR": { + "description": "Global configuration register", + "fields": [ + { + "name": "SYNCIN", + "description": "Synchronization inputs", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "SYNCOUT", + "description": "Synchronization outputs These bits are set and cleared by software.", + "bit_offset": 4, + "bit_size": 2 + } + ] + }, + "fieldset/IM": { + "description": "Interrupt mask register 2", + "fields": [ + { + "name": "OVRUDRIE", + "description": "Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MUTEDETIE", + "description": "Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "WCKCFGIE", + "description": "Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "FREQIE", + "description": "FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CNRDYIE", + "description": "Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AFSDETIE", + "description": "Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LFSDETIE", + "description": "Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/PDMCR": { + "description": "PDM control register", + "fields": [ + { + "name": "PDMEN", + "description": "PDM enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MICNBR", + "description": "Number of microphones", + "bit_offset": 4, + "bit_size": 2 + }, + { + "name": "CKEN", + "description": "Clock enable of bitstream clock number 1", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } + } + ] + }, + "fieldset/PDMDLY": { + "description": "PDM delay register", + "fields": [ + { + "name": "DLYML", + "description": "Delay line adjust for first microphone of pair 1", + "bit_offset": 0, + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } + }, + { + "name": "DLYMR", + "description": "Delay line adjust for second microphone of pair 1", + "bit_offset": 4, + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } + } + ] + }, + "fieldset/SLOTR": { + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "fields": [ + { + "name": "FBOFF", + "description": "First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 0, + "bit_size": 5 + }, + { + "name": "SLOTSZ", + "description": "Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 6, + "bit_size": 2, + "enum": "SLOTSZ" + }, + { + "name": "NBSLOT", + "description": "Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SLOTEN", + "description": "Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 16, + "bit_size": 16, + "enum": "SLOTEN" + } + ] + }, + "fieldset/SR": { + "description": "Status register", + "fields": [ + { + "name": "OVRUDR", + "description": "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MUTEDET", + "description": "Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register.", + "bit_offset": 2, + "bit_size": 1, + "enum": "WCKCFG" + }, + { + "name": "FREQ", + "description": "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CNRDY", + "description": "Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register.", + "bit_offset": 4, + "bit_size": 1, + "enum": "CNRDY" + }, + { + "name": "AFSDET", + "description": "Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LFSDET", + "description": "Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "FLVL", + "description": "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:", + "bit_offset": 16, + "bit_size": 3, + "enum": "FLVL" + } + ] + }, + "enum/CKSTR": { + "bit_size": 1, + "variants": [ + { + "name": "FallingEdge", + "description": "Data strobing edge is falling edge of SCK", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "Data strobing edge is rising edge of SCK", + "value": 1 + } + ] + }, + "enum/CNRDY": { + "bit_size": 1, + "variants": [ + { + "name": "Ready", + "description": "External AC’97 Codec is ready", + "value": 0 + }, + { + "name": "NotReady", + "description": "External AC’97 Codec is not ready", + "value": 1 + } + ] + }, + "enum/COMP": { + "bit_size": 2, + "variants": [ + { + "name": "NoCompanding", + "description": "No companding algorithm", + "value": 0 + }, + { + "name": "MuLaw", + "description": "μ-Law algorithm", + "value": 2 + }, + { + "name": "ALaw", + "description": "A-Law algorithm", + "value": 3 + } + ] + }, + "enum/CPL": { + "bit_size": 1, + "variants": [ + { + "name": "OnesComplement", + "description": "1’s complement representation", + "value": 0 + }, + { + "name": "TwosComplement", + "description": "2’s complement representation", + "value": 1 + } + ] + }, + "enum/DS": { + "bit_size": 3, + "variants": [ + { + "name": "Bit8", + "description": "8 bits", + "value": 2 + }, + { + "name": "Bit10", + "description": "10 bits", + "value": 3 + }, + { + "name": "Bit16", + "description": "16 bits", + "value": 4 + }, + { + "name": "Bit20", + "description": "20 bits", + "value": 5 + }, + { + "name": "Bit24", + "description": "24 bits", + "value": 6 + }, + { + "name": "Bit32", + "description": "32 bits", + "value": 7 + } + ] + }, + "enum/FLVL": { + "bit_size": 3, + "variants": [ + { + "name": "Empty", + "description": "FIFO empty", + "value": 0 + }, + { + "name": "Quarter1", + "description": "FIFO <= 1⁄4 but not empty", + "value": 1 + }, + { + "name": "Quarter2", + "description": "1⁄4 < FIFO <= 1⁄2", + "value": 2 + }, + { + "name": "Quarter3", + "description": "1⁄2 < FIFO <= 3⁄4", + "value": 3 + }, + { + "name": "Quarter4", + "description": "3⁄4 < FIFO but not full", + "value": 4 + }, + { + "name": "Full", + "description": "FIFO full", + "value": 5 + } + ] + }, + "enum/FSOFF": { + "bit_size": 1, + "variants": [ + { + "name": "OnFirst", + "description": "FS is asserted on the first bit of the slot 0", + "value": 0 + }, + { + "name": "BeforeFirst", + "description": "FS is asserted one bit before the first bit of the slot 0", + "value": 1 + } + ] + }, + "enum/FSPOL": { + "bit_size": 1, + "variants": [ + { + "name": "FallingEdge", + "description": "FS is active low (falling edge)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "FS is active high (rising edge)", + "value": 1 + } + ] + }, + "enum/FTH": { + "bit_size": 3, + "variants": [ + { + "name": "Empty", + "description": "FIFO empty", + "value": 0 + }, + { + "name": "Quarter1", + "description": "1⁄4 FIFO", + "value": 1 + }, + { + "name": "Quarter2", + "description": "1⁄2 FIFO", + "value": 2 + }, + { + "name": "Quarter3", + "description": "3⁄4 FIFO", + "value": 3 + }, + { + "name": "Full", + "description": "FIFO full", + "value": 4 + } + ] + }, + "enum/LSBFIRST": { + "bit_size": 1, + "variants": [ + { + "name": "MsbFirst", + "description": "Data are transferred with MSB first", + "value": 0 + }, + { + "name": "LsbFirst", + "description": "Data are transferred with LSB first", + "value": 1 + } + ] + }, + "enum/MODE": { + "bit_size": 2, + "variants": [ + { + "name": "MasterTx", + "description": "Master transmitter", + "value": 0 + }, + { + "name": "MasterRx", + "description": "Master receiver", + "value": 1 + }, + { + "name": "SlaveTx", + "description": "Slave transmitter", + "value": 2 + }, + { + "name": "SlaveRx", + "description": "Slave receiver", + "value": 3 + } + ] + }, + "enum/MONO": { + "bit_size": 1, + "variants": [ + { + "name": "Stereo", + "description": "Stereo mode", + "value": 0 + }, + { + "name": "Mono", + "description": "Mono mode", + "value": 1 + } + ] + }, + "enum/MUTEVAL": { + "bit_size": 1, + "variants": [ + { + "name": "SendZero", + "description": "Bit value 0 is sent during the mute mode", + "value": 0 + }, + { + "name": "SendLast", + "description": "Last values are sent during the mute mode", + "value": 1 + } + ] + }, + "enum/NODIV": { + "bit_size": 1, + "variants": [ + { + "name": "MasterClock", + "description": "MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value", + "value": 0 + }, + { + "name": "NoDiv", + "description": "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.", + "value": 1 + } + ] + }, + "enum/OUTDRIV": { + "bit_size": 1, + "variants": [ + { + "name": "OnStart", + "description": "Audio block output driven when SAIEN is set", + "value": 0 + }, + { + "name": "Immediately", + "description": "Audio block output driven immediately after the setting of this bit", + "value": 1 + } + ] + }, + "enum/PRTCFG": { + "bit_size": 2, + "variants": [ + { + "name": "Free", + "description": "Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol", + "value": 0 + }, + { + "name": "Spdif", + "description": "SPDIF protocol", + "value": 1 + }, + { + "name": "Ac97", + "description": "AC’97 protocol", + "value": 2 + } + ] + }, + "enum/SLOTEN": { + "bit_size": 16, + "variants": [ + { + "name": "Inactive", + "description": "Inactive slot", + "value": 0 + }, + { + "name": "Active", + "description": "Active slot", + "value": 1 + } + ] + }, + "enum/SLOTSZ": { + "bit_size": 2, + "variants": [ + { + "name": "DataSize", + "description": "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)", + "value": 0 + }, + { + "name": "Bit16", + "description": "16-bit", + "value": 1 + }, + { + "name": "Bit32", + "description": "32-bit", + "value": 2 + } + ] + }, + "enum/SYNCEN": { + "bit_size": 2, + "variants": [ + { + "name": "Asynchronous", + "description": "audio sub-block in asynchronous mode", + "value": 0 + }, + { + "name": "Internal", + "description": "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode", + "value": 1 + }, + { + "name": "External", + "description": "audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode", + "value": 2 + } + ] + }, + "enum/WCKCFG": { + "bit_size": 1, + "variants": [ + { + "name": "Correct", + "description": "Clock configuration is correct", + "value": 0 + }, + { + "name": "Wrong", + "description": "Clock configuration does not respect the rule concerning the frame length specification", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/sai_v3.json b/data/registers/sai_v4_2pdm.json similarity index 95% rename from data/registers/sai_v3.json rename to data/registers/sai_v4_2pdm.json index 16f3967..a6ad251 100644 --- a/data/registers/sai_v3.json +++ b/data/registers/sai_v4_2pdm.json @@ -217,6 +217,12 @@ "description": "Oversampling ratio for master clock", "bit_offset": 26, "bit_size": 1 + }, + { + "name": "MCKEN", + "description": "Master clock generation enable", + "bit_offset": 27, + "bit_size": 1 } ] }, @@ -405,28 +411,14 @@ "bit_size": 2 }, { - "name": "CKEN1", + "name": "CKEN", "description": "Clock enable of bitstream clock number 1", "bit_offset": 8, - "bit_size": 1 - }, - { - "name": "CKEN2", - "description": "Clock enable of bitstream clock number 2", - "bit_offset": 9, - "bit_size": 1 - }, - { - "name": "CKEN3", - "description": "Clock enable of bitstream clock number 3", - "bit_offset": 10, - "bit_size": 1 - }, - { - "name": "CKEN4", - "description": "Clock enable of bitstream clock number 4", - "bit_offset": 11, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } } ] }, @@ -434,52 +426,24 @@ "description": "PDM delay register", "fields": [ { - "name": "DLYM1L", + "name": "DLYML", "description": "Delay line adjust for first microphone of pair 1", "bit_offset": 0, - "bit_size": 3 + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } }, { - "name": "DLYM1R", + "name": "DLYMR", "description": "Delay line adjust for second microphone of pair 1", "bit_offset": 4, - "bit_size": 3 - }, - { - "name": "DLYM2L", - "description": "Delay line for first microphone of pair 2", - "bit_offset": 8, - "bit_size": 3 - }, - { - "name": "DLYM2R", - "description": "Delay line for second microphone of pair 2", - "bit_offset": 12, - "bit_size": 3 - }, - { - "name": "DLYM3L", - "description": "Delay line for first microphone of pair 3", - "bit_offset": 16, - "bit_size": 3 - }, - { - "name": "DLYM3R", - "description": "Delay line for second microphone of pair 3", - "bit_offset": 20, - "bit_size": 3 - }, - { - "name": "DLYM4L", - "description": "Delay line for first microphone of pair 4", - "bit_offset": 24, - "bit_size": 3 - }, - { - "name": "DLYM4R", - "description": "Delay line for second microphone of pair 4", - "bit_offset": 28, - "bit_size": 3 + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } } ] }, diff --git a/data/registers/sai_v4.json b/data/registers/sai_v4_4pdm.json similarity index 95% rename from data/registers/sai_v4.json rename to data/registers/sai_v4_4pdm.json index c8731e6..26f6f1a 100644 --- a/data/registers/sai_v4.json +++ b/data/registers/sai_v4_4pdm.json @@ -411,28 +411,14 @@ "bit_size": 2 }, { - "name": "CKEN1", + "name": "CKEN", "description": "Clock enable of bitstream clock number 1", "bit_offset": 8, - "bit_size": 1 - }, - { - "name": "CKEN2", - "description": "Clock enable of bitstream clock number 2", - "bit_offset": 9, - "bit_size": 1 - }, - { - "name": "CKEN3", - "description": "Clock enable of bitstream clock number 3", - "bit_offset": 10, - "bit_size": 1 - }, - { - "name": "CKEN4", - "description": "Clock enable of bitstream clock number 4", - "bit_offset": 11, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } } ] }, @@ -440,52 +426,24 @@ "description": "PDM delay register", "fields": [ { - "name": "DLYM1L", + "name": "DLYML", "description": "Delay line adjust for first microphone of pair 1", "bit_offset": 0, - "bit_size": 3 + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } }, { - "name": "DLYM1R", + "name": "DLYMR", "description": "Delay line adjust for second microphone of pair 1", "bit_offset": 4, - "bit_size": 3 - }, - { - "name": "DLYM2L", - "description": "Delay line for first microphone of pair 2", - "bit_offset": 8, - "bit_size": 3 - }, - { - "name": "DLYM2R", - "description": "Delay line for second microphone of pair 2", - "bit_offset": 12, - "bit_size": 3 - }, - { - "name": "DLYM3L", - "description": "Delay line for first microphone of pair 3", - "bit_offset": 16, - "bit_size": 3 - }, - { - "name": "DLYM3R", - "description": "Delay line for second microphone of pair 3", - "bit_offset": 20, - "bit_size": 3 - }, - { - "name": "DLYM4L", - "description": "Delay line for first microphone of pair 4", - "bit_offset": 24, - "bit_size": 3 - }, - { - "name": "DLYM4R", - "description": "Delay line for second microphone of pair 4", - "bit_offset": 28, - "bit_size": 3 + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } } ] },