diff --git a/data/chips/STM32H503CB.json b/data/chips/STM32H503CB.json index b251164..fbefc3c 100644 --- a/data/chips/STM32H503CB.json +++ b/data/chips/STM32H503CB.json @@ -76,7 +76,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC1EN" @@ -295,7 +298,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H503EB.json b/data/chips/STM32H503EB.json index 7055afa..a181494 100644 --- a/data/chips/STM32H503EB.json +++ b/data/chips/STM32H503EB.json @@ -72,7 +72,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC1EN" @@ -242,7 +245,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H503KB.json b/data/chips/STM32H503KB.json index 1ee646c..2646762 100644 --- a/data/chips/STM32H503KB.json +++ b/data/chips/STM32H503KB.json @@ -72,7 +72,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC1EN" @@ -287,7 +290,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H503RB.json b/data/chips/STM32H503RB.json index 561f827..a7abe33 100644 --- a/data/chips/STM32H503RB.json +++ b/data/chips/STM32H503RB.json @@ -72,7 +72,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC1EN" @@ -340,7 +343,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index 544a570..19e7bf8 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -61,7 +61,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -210,7 +213,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -490,7 +496,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index 2def6db..8091019 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -72,7 +72,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -221,7 +224,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -501,7 +507,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index 9aaab1e..23a5abc 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -65,7 +65,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -214,7 +217,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -494,7 +500,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index 0365fd6..ba0c379 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -76,7 +76,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -225,7 +228,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -505,7 +511,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index 7bc37a1..781f923 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -65,7 +65,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -202,7 +205,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -470,7 +476,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index d5462c7..d6f922a 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -76,7 +76,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -213,7 +216,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -481,7 +487,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index 96a67b5..ebde387 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -61,7 +61,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -198,7 +201,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -466,7 +472,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index fce894d..f619f19 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -72,7 +72,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -209,7 +212,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -477,7 +483,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index 7937328..44536a8 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -61,7 +61,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -210,7 +213,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -490,7 +496,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index d35dffa..3337199 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -72,7 +72,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -221,7 +224,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -501,7 +507,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index f6893ac..a591b7d 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -61,7 +61,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -210,7 +213,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -490,7 +496,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index f5c7430..6092598 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -76,7 +76,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -225,7 +228,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -505,7 +511,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 6bf9108..88f8d00 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -65,7 +65,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -214,7 +217,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -494,7 +500,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index d7bb03a..9f26c10 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -84,7 +84,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -233,7 +236,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -513,7 +519,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index 9770905..e93d8fd 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -72,7 +72,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -209,7 +212,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -477,7 +483,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index 5a5a5c8..445c61b 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -65,7 +65,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -202,7 +205,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -470,7 +476,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index 3d659e6..de93dd1 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -76,7 +76,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -213,7 +216,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -481,7 +487,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index fafc4d8..8597be5 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -61,7 +61,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -198,7 +201,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -466,7 +472,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index ff443d5..cf791fb 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -76,7 +76,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -213,7 +216,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -481,7 +487,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index 9b704f1..59c3032 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -61,7 +61,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -210,7 +213,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -490,7 +496,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index 3ee3d1b..4a54094 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -76,7 +76,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -225,7 +228,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -505,7 +511,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 0a02b71..6d8bd7b 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -76,7 +76,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -225,7 +228,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -554,7 +560,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index c5cc10e..9494755 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -84,7 +84,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -233,7 +236,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -562,7 +568,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index 728d662..8a03d19 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -72,7 +72,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -209,7 +212,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -526,7 +532,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index c378f36..3386f3b 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -76,7 +76,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -213,7 +216,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -530,7 +536,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index 9bb5ee2..69a5bb5 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -76,7 +76,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -213,7 +216,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -530,7 +536,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index b30aaa5..c3105bb 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -76,7 +76,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -225,7 +228,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "ADC12EN" @@ -554,7 +560,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR", "field": "DAC1EN" diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index ca5d0bf..0a4f668 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -68,7 +68,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -143,7 +146,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index b34a1a1..2dfff7f 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -68,7 +68,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -143,7 +146,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index 0a13e48..46f028b 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -68,7 +68,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -143,7 +146,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index d9904c6..f07371c 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -135,7 +138,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index f5aefeb..9f2331d 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -131,7 +134,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index 2037ef6..599cf78 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -131,7 +134,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index 748fe2d..6f0269e 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -68,7 +68,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -167,7 +170,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index 614a0f6..36748a6 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -68,7 +68,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -167,7 +170,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index 623a8b1..332d5c1 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -68,7 +68,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -167,7 +170,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index 7ad507c..0b2cff5 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -68,7 +68,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -167,7 +170,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index 7eec627..1a94e6a 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -68,7 +68,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -167,7 +170,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index 24f1fba..ff17a20 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -68,7 +68,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -143,7 +146,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index 14c3e55..d4dea65 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -135,7 +138,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 1a45f3f..cb40780 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -131,7 +134,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index 322c6f7..02cff9f 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -68,7 +68,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -167,7 +170,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index 5f481a8..e8dbe29 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -68,7 +68,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -167,7 +170,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575AG.json b/data/chips/STM32U575AG.json index 4bbe459..b73a092 100644 --- a/data/chips/STM32U575AG.json +++ b/data/chips/STM32U575AG.json @@ -427,7 +427,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -526,7 +529,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575AI.json b/data/chips/STM32U575AI.json index e8a62cf..9d4f070 100644 --- a/data/chips/STM32U575AI.json +++ b/data/chips/STM32U575AI.json @@ -427,7 +427,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -526,7 +529,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575CG.json b/data/chips/STM32U575CG.json index 553a01d..568bee9 100644 --- a/data/chips/STM32U575CG.json +++ b/data/chips/STM32U575CG.json @@ -435,7 +435,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -510,7 +513,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575CI.json b/data/chips/STM32U575CI.json index 0d8ae41..47a152d 100644 --- a/data/chips/STM32U575CI.json +++ b/data/chips/STM32U575CI.json @@ -435,7 +435,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -510,7 +513,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575OG.json b/data/chips/STM32U575OG.json index a98bd87..acdd6ee 100644 --- a/data/chips/STM32U575OG.json +++ b/data/chips/STM32U575OG.json @@ -423,7 +423,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -518,7 +521,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575OI.json b/data/chips/STM32U575OI.json index 8e64e1b..ae95df5 100644 --- a/data/chips/STM32U575OI.json +++ b/data/chips/STM32U575OI.json @@ -423,7 +423,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -518,7 +521,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575QG.json b/data/chips/STM32U575QG.json index 3d93029..3a0fab2 100644 --- a/data/chips/STM32U575QG.json +++ b/data/chips/STM32U575QG.json @@ -427,7 +427,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -526,7 +529,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575QI.json b/data/chips/STM32U575QI.json index 7dc1ea8..009db96 100644 --- a/data/chips/STM32U575QI.json +++ b/data/chips/STM32U575QI.json @@ -427,7 +427,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -526,7 +529,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575RG.json b/data/chips/STM32U575RG.json index 6c36ce2..e050919 100644 --- a/data/chips/STM32U575RG.json +++ b/data/chips/STM32U575RG.json @@ -427,7 +427,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -526,7 +529,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575RI.json b/data/chips/STM32U575RI.json index 9a3939d..86e02fe 100644 --- a/data/chips/STM32U575RI.json +++ b/data/chips/STM32U575RI.json @@ -427,7 +427,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -526,7 +529,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575VG.json b/data/chips/STM32U575VG.json index 4a17b11..cb04404 100644 --- a/data/chips/STM32U575VG.json +++ b/data/chips/STM32U575VG.json @@ -427,7 +427,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -526,7 +529,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575VI.json b/data/chips/STM32U575VI.json index 9d60d5e..ae3cd9f 100644 --- a/data/chips/STM32U575VI.json +++ b/data/chips/STM32U575VI.json @@ -427,7 +427,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -526,7 +529,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575ZG.json b/data/chips/STM32U575ZG.json index b40246e..fb4f7a9 100644 --- a/data/chips/STM32U575ZG.json +++ b/data/chips/STM32U575ZG.json @@ -427,7 +427,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -526,7 +529,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U575ZI.json b/data/chips/STM32U575ZI.json index 3c3ea42..7823604 100644 --- a/data/chips/STM32U575ZI.json +++ b/data/chips/STM32U575ZI.json @@ -427,7 +427,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -526,7 +529,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index e6c47f5..ea630c2 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -433,7 +433,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -532,7 +535,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index ad6fbb9..b73922b 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -441,7 +441,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -516,7 +519,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index 316b689..9d9e09f 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -429,7 +429,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -524,7 +527,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index 97354b3..81e1856 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -433,7 +433,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -532,7 +535,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index de2bfae..682e89c 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -433,7 +433,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -532,7 +535,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index ada36cd..cbf51ff 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -433,7 +433,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -532,7 +535,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index 2d426e7..d5ab318 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -433,7 +433,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -532,7 +535,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index 22e1c82..aa9e326 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index 0f5c2a1..671335b 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index 85c37b9..e555bc3 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index 84cc5ae..a5575ed 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index 7775e7b..14a0e29 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index 531df44..996dc26 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index e94c4e0..3637f2d 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index 734ce00..416ced9 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index 731a0e1..1d6babb 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -64,7 +64,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -163,7 +166,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -255,7 +261,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index 25264b1..1558964 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -64,7 +64,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -163,7 +166,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -255,7 +261,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index 88d495d..fd58ebe 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -155,7 +158,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -247,7 +253,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index cbb50e9..6f02592 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -155,7 +158,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -247,7 +253,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index e4eb455..8530431 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -155,7 +158,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -247,7 +253,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index 4bdb205..e64241f 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -147,7 +150,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -231,7 +237,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index 3e34aa4..e47fadd 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index de8dc73..069d80c 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index fb4711c..73c528d 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index 56993ec..1e2ad61 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index 6b3d9a4..b4b53ae 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index 4a42edb..a25fef8 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index 300675a..bfc3fb1 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index bebc33d..082b4b8 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -64,7 +64,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -163,7 +166,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -255,7 +261,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 824ec33..194e883 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -155,7 +158,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -247,7 +253,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index c6e7702..21ee0eb 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -155,7 +158,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -247,7 +253,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 6d3d4c4..df5e26b 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -56,7 +56,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -147,7 +150,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -231,7 +237,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index df9c309..14c743b 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -60,7 +60,10 @@ "address": 1107460096, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -159,7 +162,10 @@ "address": 1107460352, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB2ENR1", "field": "ADC12EN" @@ -251,7 +257,10 @@ "address": 1174540288, "rcc": { "bus_clock": "HCLK3", - "kernel_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR3", + "field": "ADCDACSEL" + }, "enable": { "register": "AHB3ENR", "field": "ADC4EN" diff --git a/data/registers/rcc_h5.json b/data/registers/rcc_h5.json index 70f36a3..9923d3c 100644 --- a/data/registers/rcc_h5.json +++ b/data/registers/rcc_h5.json @@ -3153,7 +3153,7 @@ "bit_size": 3, "variants": [ { - "name": "HCLK1", + "name": "HCLK2", "description": "rcc_hclk selected as kernel clock (default after reset)", "value": 0 }, diff --git a/data/registers/rcc_h50.json b/data/registers/rcc_h50.json index 6e09f1d..18d33df 100644 --- a/data/registers/rcc_h50.json +++ b/data/registers/rcc_h50.json @@ -1995,7 +1995,7 @@ "bit_size": 3, "variants": [ { - "name": "HCLK1", + "name": "HCLK2", "description": "rcc_hclk selected as kernel clock (default after reset)", "value": 0 },