block/UHCI0: description: Universal Host Controller Interface 0. items: - name: CONF0 byte_offset: 0 fieldset: CONF0 - name: INT_RAW byte_offset: 4 fieldset: INT_RAW - name: INT_ST byte_offset: 8 fieldset: INT_ST - name: INT_ENA byte_offset: 12 fieldset: INT_ENA - name: INT_CLR byte_offset: 16 fieldset: INT_CLR - name: DMA_OUT_STATUS byte_offset: 20 fieldset: DMA_OUT_STATUS - name: DMA_OUT_PUSH byte_offset: 24 fieldset: DMA_OUT_PUSH - name: DMA_IN_STATUS byte_offset: 28 fieldset: DMA_IN_STATUS - name: DMA_IN_POP byte_offset: 32 fieldset: DMA_IN_POP - name: DMA_OUT_LINK byte_offset: 36 fieldset: DMA_OUT_LINK - name: DMA_IN_LINK byte_offset: 40 fieldset: DMA_IN_LINK - name: CONF1 byte_offset: 44 fieldset: CONF1 - name: STATE0 byte_offset: 48 fieldset: STATE0 - name: STATE1 byte_offset: 52 fieldset: STATE1 - name: DMA_OUT_EOF_DES_ADDR byte_offset: 56 fieldset: DMA_OUT_EOF_DES_ADDR - name: DMA_IN_SUC_EOF_DES_ADDR byte_offset: 60 fieldset: DMA_IN_SUC_EOF_DES_ADDR - name: DMA_IN_ERR_EOF_DES_ADDR byte_offset: 64 fieldset: DMA_IN_ERR_EOF_DES_ADDR - name: DMA_OUT_EOF_BFR_DES_ADDR byte_offset: 68 fieldset: DMA_OUT_EOF_BFR_DES_ADDR - name: AHB_TEST byte_offset: 72 fieldset: AHB_TEST - name: DMA_IN_DSCR byte_offset: 76 fieldset: DMA_IN_DSCR - name: DMA_IN_DSCR_BF0 byte_offset: 80 fieldset: DMA_IN_DSCR_BF0 - name: DMA_IN_DSCR_BF1 byte_offset: 84 fieldset: DMA_IN_DSCR_BF1 - name: DMA_OUT_DSCR byte_offset: 88 fieldset: DMA_OUT_DSCR - name: DMA_OUT_DSCR_BF0 byte_offset: 92 fieldset: DMA_OUT_DSCR_BF0 - name: DMA_OUT_DSCR_BF1 byte_offset: 96 fieldset: DMA_OUT_DSCR_BF1 - name: ESCAPE_CONF byte_offset: 100 fieldset: ESCAPE_CONF - name: HUNG_CONF byte_offset: 104 fieldset: HUNG_CONF - name: ACK_NUM byte_offset: 108 - name: RX_HEAD byte_offset: 112 fieldset: RX_HEAD - name: QUICK_SENT byte_offset: 116 fieldset: QUICK_SENT - name: Q0_WORD0 byte_offset: 120 fieldset: Q0_WORD0 - name: Q0_WORD1 byte_offset: 124 fieldset: Q0_WORD1 - name: Q1_WORD0 byte_offset: 128 fieldset: Q1_WORD0 - name: Q1_WORD1 byte_offset: 132 fieldset: Q1_WORD1 - name: Q2_WORD0 byte_offset: 136 fieldset: Q2_WORD0 - name: Q2_WORD1 byte_offset: 140 fieldset: Q2_WORD1 - name: Q3_WORD0 byte_offset: 144 fieldset: Q3_WORD0 - name: Q3_WORD1 byte_offset: 148 fieldset: Q3_WORD1 - name: Q4_WORD0 byte_offset: 152 fieldset: Q4_WORD0 - name: Q4_WORD1 byte_offset: 156 fieldset: Q4_WORD1 - name: Q5_WORD0 byte_offset: 160 fieldset: Q5_WORD0 - name: Q5_WORD1 byte_offset: 164 fieldset: Q5_WORD1 - name: Q6_WORD0 byte_offset: 168 fieldset: Q6_WORD0 - name: Q6_WORD1 byte_offset: 172 fieldset: Q6_WORD1 - name: ESC_CONF0 byte_offset: 176 fieldset: ESC_CONF0 - name: ESC_CONF1 byte_offset: 180 fieldset: ESC_CONF1 - name: ESC_CONF2 byte_offset: 184 fieldset: ESC_CONF2 - name: ESC_CONF3 byte_offset: 188 fieldset: ESC_CONF3 - name: PKT_THRES byte_offset: 192 fieldset: PKT_THRES - name: DATE byte_offset: 252 fieldset: DATE fieldset/AHB_TEST: fields: - name: AHB_TESTMODE description: bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0). bit_offset: 0 bit_size: 3 - name: AHB_TESTADDR description: The two bits represent ahb bus address bit[20:19]. bit_offset: 4 bit_size: 2 fieldset/CONF0: fields: - name: IN_RST description: Set this bit to reset in link operations. bit_offset: 0 bit_size: 1 - name: OUT_RST description: Set this bit to reset out link operations. bit_offset: 1 bit_size: 1 - name: AHBM_FIFO_RST description: Set this bit to reset dma ahb fifo. bit_offset: 2 bit_size: 1 - name: AHBM_RST description: Set this bit to reset dma ahb interface. bit_offset: 3 bit_size: 1 - name: IN_LOOP_TEST description: Set this bit to enable loop test for in links. bit_offset: 4 bit_size: 1 - name: OUT_LOOP_TEST description: Set this bit to enable loop test for out links. bit_offset: 5 bit_size: 1 - name: OUT_AUTO_WRBACK description: when in link's length is 0 go on to use the next in link automatically. bit_offset: 6 bit_size: 1 - name: OUT_NO_RESTART_CLR description: don't use. bit_offset: 7 bit_size: 1 - name: OUT_EOF_MODE description: Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data. bit_offset: 8 bit_size: 1 - name: UART0_CE description: Set this bit to use UART to transmit or receive data. bit_offset: 9 bit_size: 1 - name: UART1_CE description: Set this bit to use UART1 to transmit or receive data. bit_offset: 10 bit_size: 1 - name: UART2_CE description: Set this bit to use UART2 to transmit or receive data. bit_offset: 11 bit_size: 1 - name: OUTDSCR_BURST_EN description: Set this bit to enable DMA in links to use burst mode. bit_offset: 12 bit_size: 1 - name: INDSCR_BURST_EN description: Set this bit to enable DMA out links to use burst mode. bit_offset: 13 bit_size: 1 - name: OUT_DATA_BURST_EN description: Set this bit to enable DMA burst MODE. bit_offset: 14 bit_size: 1 - name: MEM_TRANS_EN bit_offset: 15 bit_size: 1 - name: SEPER_EN description: Set this bit to use special char to separate the data frame. bit_offset: 16 bit_size: 1 - name: HEAD_EN description: Set this bit to enable to use head packet before the data frame. bit_offset: 17 bit_size: 1 - name: CRC_REC_EN description: Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame. bit_offset: 18 bit_size: 1 - name: UART_IDLE_EOF_EN description: Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame. bit_offset: 19 bit_size: 1 - name: LEN_EOF_EN description: Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame. bit_offset: 20 bit_size: 1 - name: ENCODE_CRC_EN description: Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1. bit_offset: 21 bit_size: 1 - name: CLK_EN description: Set this bit to enable clock-gating for read or write registers. bit_offset: 22 bit_size: 1 - name: UART_RX_BRK_EOF_EN description: Set this bit to enable to use brk char as the end of a data frame. bit_offset: 23 bit_size: 1 fieldset/CONF1: fields: - name: CHECK_SUM_EN description: Set this bit to enable decoder to check check_sum in packet header. bit_offset: 0 bit_size: 1 - name: CHECK_SEQ_EN description: Set this bit to enable decoder to check seq num in packet header. bit_offset: 1 bit_size: 1 - name: CRC_DISABLE description: Set this bit to disable crc calculation. bit_offset: 2 bit_size: 1 - name: SAVE_HEAD description: Set this bit to save packet header. bit_offset: 3 bit_size: 1 - name: TX_CHECK_SUM_RE description: Set this bit to enable hardware replace check_sum in packet header automatically. bit_offset: 4 bit_size: 1 - name: TX_ACK_NUM_RE description: Set this bit to enable hardware replace ack num in packet header automatically. bit_offset: 5 bit_size: 1 - name: CHECK_OWNER description: Set this bit to check the owner bit in link descriptor. bit_offset: 6 bit_size: 1 - name: WAIT_SW_START description: Set this bit to enable software way to add packet header. bit_offset: 7 bit_size: 1 - name: SW_START description: Set this bit to start inserting the packet header. bit_offset: 8 bit_size: 1 - name: DMA_INFIFO_FULL_THRS description: when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt. bit_offset: 9 bit_size: 12 fieldset/DATE: fields: - name: DATE description: version information. bit_offset: 0 bit_size: 32 fieldset/DMA_IN_DSCR: fields: - name: INLINK_DSCR description: The content of current in link descriptor's third dword. bit_offset: 0 bit_size: 32 fieldset/DMA_IN_DSCR_BF0: fields: - name: INLINK_DSCR_BF0 description: The content of current in link descriptor's first dword. bit_offset: 0 bit_size: 32 fieldset/DMA_IN_DSCR_BF1: fields: - name: INLINK_DSCR_BF1 description: The content of current in link descriptor's second dword. bit_offset: 0 bit_size: 32 fieldset/DMA_IN_ERR_EOF_DES_ADDR: fields: - name: IN_ERR_EOF_DES_ADDR description: This register stores the address of in link descriptor when there are some errors in this descriptor. bit_offset: 0 bit_size: 32 fieldset/DMA_IN_LINK: fields: - name: INLINK_ADDR description: This register stores the least 20 bits of the first in link descriptor's address. bit_offset: 0 bit_size: 20 - name: INLINK_AUTO_RET description: 1:when a packet is wrong in link descriptor returns to the descriptor which is lately used. bit_offset: 20 bit_size: 1 - name: INLINK_STOP description: Set this bit to stop dealing with the in link descriptors. bit_offset: 28 bit_size: 1 - name: INLINK_START description: Set this bit to start dealing with the in link descriptors. bit_offset: 29 bit_size: 1 - name: INLINK_RESTART description: Set this bit to mount on new in link descriptors. bit_offset: 30 bit_size: 1 - name: INLINK_PARK description: 1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working. bit_offset: 31 bit_size: 1 fieldset/DMA_IN_POP: fields: - name: INFIFO_RDATA description: This register stores the data pop from in link descriptor's fifo. bit_offset: 0 bit_size: 12 - name: INFIFO_POP description: Set this bit to pop data in in link descriptor's fifo. bit_offset: 16 bit_size: 1 fieldset/DMA_IN_STATUS: fields: - name: IN_FULL bit_offset: 0 bit_size: 1 - name: IN_EMPTY bit_offset: 1 bit_size: 1 - name: RX_ERR_CAUSE description: This register stores the errors caused in out link descriptor's data packet. bit_offset: 4 bit_size: 3 fieldset/DMA_IN_SUC_EOF_DES_ADDR: fields: - name: IN_SUC_EOF_DES_ADDR description: This register stores the address of in link descriptor when eof bit in this descriptor is 1. bit_offset: 0 bit_size: 32 fieldset/DMA_OUT_DSCR: fields: - name: OUTLINK_DSCR description: The content of current out link descriptor's third dword. bit_offset: 0 bit_size: 32 fieldset/DMA_OUT_DSCR_BF0: fields: - name: OUTLINK_DSCR_BF0 description: The content of current out link descriptor's first dword. bit_offset: 0 bit_size: 32 fieldset/DMA_OUT_DSCR_BF1: fields: - name: OUTLINK_DSCR_BF1 description: The content of current out link descriptor's second dword. bit_offset: 0 bit_size: 32 fieldset/DMA_OUT_EOF_BFR_DES_ADDR: fields: - name: OUT_EOF_BFR_DES_ADDR description: This register stores the address of out link descriptor when there are some errors in this descriptor. bit_offset: 0 bit_size: 32 fieldset/DMA_OUT_EOF_DES_ADDR: fields: - name: OUT_EOF_DES_ADDR description: This register stores the address of out link descriptoir when eof bit in this descriptor is 1. bit_offset: 0 bit_size: 32 fieldset/DMA_OUT_LINK: fields: - name: OUTLINK_ADDR description: This register stores the least 20 bits of the first out link descriptor's address. bit_offset: 0 bit_size: 20 - name: OUTLINK_STOP description: Set this bit to stop dealing with the out link descriptors. bit_offset: 28 bit_size: 1 - name: OUTLINK_START description: Set this bit to start dealing with the out link descriptors. bit_offset: 29 bit_size: 1 - name: OUTLINK_RESTART description: Set this bit to mount on new out link descriptors. bit_offset: 30 bit_size: 1 - name: OUTLINK_PARK description: 1£º the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working. bit_offset: 31 bit_size: 1 fieldset/DMA_OUT_PUSH: fields: - name: OUTFIFO_WDATA description: This is the data need to be pushed into out link descriptor's fifo. bit_offset: 0 bit_size: 9 - name: OUTFIFO_PUSH description: Set this bit to push data in out link descriptor's fifo. bit_offset: 16 bit_size: 1 fieldset/DMA_OUT_STATUS: fields: - name: OUT_FULL description: 1:DMA out link descriptor's fifo is full. bit_offset: 0 bit_size: 1 - name: OUT_EMPTY description: 1:DMA in link descriptor's fifo is empty. bit_offset: 1 bit_size: 1 fieldset/ESCAPE_CONF: fields: - name: TX_C0_ESC_EN description: Set this bit to enable 0xc0 char decode when DMA receives data. bit_offset: 0 bit_size: 1 - name: TX_DB_ESC_EN description: Set this bit to enable 0xdb char decode when DMA receives data. bit_offset: 1 bit_size: 1 - name: TX_11_ESC_EN description: Set this bit to enable flow control char 0x11 decode when DMA receives data. bit_offset: 2 bit_size: 1 - name: TX_13_ESC_EN description: Set this bit to enable flow control char 0x13 decode when DMA receives data. bit_offset: 3 bit_size: 1 - name: RX_C0_ESC_EN description: Set this bit to enable 0xc0 char replace when DMA sends data. bit_offset: 4 bit_size: 1 - name: RX_DB_ESC_EN description: Set this bit to enable 0xdb char replace when DMA sends data. bit_offset: 5 bit_size: 1 - name: RX_11_ESC_EN description: Set this bit to enable flow control char 0x11 replace when DMA sends data. bit_offset: 6 bit_size: 1 - name: RX_13_ESC_EN description: Set this bit to enable flow control char 0x13 replace when DMA sends data. bit_offset: 7 bit_size: 1 fieldset/ESC_CONF0: fields: - name: SEPER_CHAR description: This register stores the seperator char seperator char is used to seperate the data frame. bit_offset: 0 bit_size: 8 - name: SEPER_ESC_CHAR0 description: This register stores thee first char used to replace seperator char in data. bit_offset: 8 bit_size: 8 - name: SEPER_ESC_CHAR1 description: This register stores the second char used to replace seperator char in data . 0xdc 0xdb replace 0xc0 by default. bit_offset: 16 bit_size: 8 fieldset/ESC_CONF1: fields: - name: ESC_SEQ0 description: This register stores the first substitute char used to replace the seperator char. bit_offset: 0 bit_size: 8 - name: ESC_SEQ0_CHAR0 description: This register stores the first char used to replace reg_esc_seq0 in data. bit_offset: 8 bit_size: 8 - name: ESC_SEQ0_CHAR1 description: This register stores the second char used to replace the reg_esc_seq0 in data. bit_offset: 16 bit_size: 8 fieldset/ESC_CONF2: fields: - name: ESC_SEQ1 description: This register stores the flow control char to turn on the flow_control. bit_offset: 0 bit_size: 8 - name: ESC_SEQ1_CHAR0 description: This register stores the first char used to replace the reg_esc_seq1 in data. bit_offset: 8 bit_size: 8 - name: ESC_SEQ1_CHAR1 description: This register stores the second char used to replace the reg_esc_seq1 in data. bit_offset: 16 bit_size: 8 fieldset/ESC_CONF3: fields: - name: ESC_SEQ2 description: This register stores the flow_control char to turn off the flow_control. bit_offset: 0 bit_size: 8 - name: ESC_SEQ2_CHAR0 description: This register stores the first char used to replace the reg_esc_seq2 in data. bit_offset: 8 bit_size: 8 - name: ESC_SEQ2_CHAR1 description: This register stores the second char used to replace the reg_esc_seq2 in data. bit_offset: 16 bit_size: 8 fieldset/HUNG_CONF: fields: - name: TXFIFO_TIMEOUT description: This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt. bit_offset: 0 bit_size: 8 - name: TXFIFO_TIMEOUT_SHIFT description: The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift). bit_offset: 8 bit_size: 3 - name: TXFIFO_TIMEOUT_ENA description: The enable bit for txfifo receive data timeout. bit_offset: 11 bit_size: 1 - name: RXFIFO_TIMEOUT description: This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt. bit_offset: 12 bit_size: 8 - name: RXFIFO_TIMEOUT_SHIFT description: The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift). bit_offset: 20 bit_size: 3 - name: RXFIFO_TIMEOUT_ENA description: This is the enable bit for DMA send data timeout. bit_offset: 23 bit_size: 1 fieldset/INT_CLR: fields: - name: RX_START_INT_CLR bit_offset: 0 bit_size: 1 - name: TX_START_INT_CLR bit_offset: 1 bit_size: 1 - name: RX_HUNG_INT_CLR bit_offset: 2 bit_size: 1 - name: TX_HUNG_INT_CLR bit_offset: 3 bit_size: 1 - name: IN_DONE_INT_CLR bit_offset: 4 bit_size: 1 - name: IN_SUC_EOF_INT_CLR bit_offset: 5 bit_size: 1 - name: IN_ERR_EOF_INT_CLR bit_offset: 6 bit_size: 1 - name: OUT_DONE_INT_CLR bit_offset: 7 bit_size: 1 - name: OUT_EOF_INT_CLR bit_offset: 8 bit_size: 1 - name: IN_DSCR_ERR_INT_CLR bit_offset: 9 bit_size: 1 - name: OUT_DSCR_ERR_INT_CLR bit_offset: 10 bit_size: 1 - name: IN_DSCR_EMPTY_INT_CLR bit_offset: 11 bit_size: 1 - name: OUTLINK_EOF_ERR_INT_CLR bit_offset: 12 bit_size: 1 - name: OUT_TOTAL_EOF_INT_CLR bit_offset: 13 bit_size: 1 - name: SEND_S_Q_INT_CLR bit_offset: 14 bit_size: 1 - name: SEND_A_Q_INT_CLR bit_offset: 15 bit_size: 1 - name: DMA_INFIFO_FULL_WM_INT_CLR bit_offset: 16 bit_size: 1 fieldset/INT_ENA: fields: - name: RX_START_INT_ENA bit_offset: 0 bit_size: 1 - name: TX_START_INT_ENA bit_offset: 1 bit_size: 1 - name: RX_HUNG_INT_ENA bit_offset: 2 bit_size: 1 - name: TX_HUNG_INT_ENA bit_offset: 3 bit_size: 1 - name: IN_DONE_INT_ENA bit_offset: 4 bit_size: 1 - name: IN_SUC_EOF_INT_ENA bit_offset: 5 bit_size: 1 - name: IN_ERR_EOF_INT_ENA bit_offset: 6 bit_size: 1 - name: OUT_DONE_INT_ENA bit_offset: 7 bit_size: 1 - name: OUT_EOF_INT_ENA bit_offset: 8 bit_size: 1 - name: IN_DSCR_ERR_INT_ENA bit_offset: 9 bit_size: 1 - name: OUT_DSCR_ERR_INT_ENA bit_offset: 10 bit_size: 1 - name: IN_DSCR_EMPTY_INT_ENA bit_offset: 11 bit_size: 1 - name: OUTLINK_EOF_ERR_INT_ENA bit_offset: 12 bit_size: 1 - name: OUT_TOTAL_EOF_INT_ENA bit_offset: 13 bit_size: 1 - name: SEND_S_Q_INT_ENA bit_offset: 14 bit_size: 1 - name: SEND_A_Q_INT_ENA bit_offset: 15 bit_size: 1 - name: DMA_INFIFO_FULL_WM_INT_ENA bit_offset: 16 bit_size: 1 fieldset/INT_RAW: fields: - name: RX_START_INT_RAW description: when a separator char has been send it will produce uhci_rx_start_int interrupt. bit_offset: 0 bit_size: 1 - name: TX_START_INT_RAW description: when DMA detects a separator char it will produce uhci_tx_start_int interrupt. bit_offset: 1 bit_size: 1 - name: RX_HUNG_INT_RAW description: when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt. bit_offset: 2 bit_size: 1 - name: TX_HUNG_INT_RAW description: when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt. bit_offset: 3 bit_size: 1 - name: IN_DONE_INT_RAW description: when a in link descriptor has been completed it will produce uhci_in_done_int interrupt. bit_offset: 4 bit_size: 1 - name: IN_SUC_EOF_INT_RAW description: when a data packet has been received it will produce uhci_in_suc_eof_int interrupt. bit_offset: 5 bit_size: 1 - name: IN_ERR_EOF_INT_RAW description: when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt. bit_offset: 6 bit_size: 1 - name: OUT_DONE_INT_RAW description: when a out link descriptor is completed it will produce uhci_out_done_int interrupt. bit_offset: 7 bit_size: 1 - name: OUT_EOF_INT_RAW description: when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt. bit_offset: 8 bit_size: 1 - name: IN_DSCR_ERR_INT_RAW description: when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt. bit_offset: 9 bit_size: 1 - name: OUT_DSCR_ERR_INT_RAW description: when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt. bit_offset: 10 bit_size: 1 - name: IN_DSCR_EMPTY_INT_RAW description: when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt. bit_offset: 11 bit_size: 1 - name: OUTLINK_EOF_ERR_INT_RAW description: when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt. bit_offset: 12 bit_size: 1 - name: OUT_TOTAL_EOF_INT_RAW description: When all data have been send it will produce uhci_out_total_eof_int interrupt. bit_offset: 13 bit_size: 1 - name: SEND_S_Q_INT_RAW description: When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet. bit_offset: 14 bit_size: 1 - name: SEND_A_Q_INT_RAW description: When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet. bit_offset: 15 bit_size: 1 - name: DMA_INFIFO_FULL_WM_INT_RAW bit_offset: 16 bit_size: 1 fieldset/INT_ST: fields: - name: RX_START_INT_ST bit_offset: 0 bit_size: 1 - name: TX_START_INT_ST bit_offset: 1 bit_size: 1 - name: RX_HUNG_INT_ST bit_offset: 2 bit_size: 1 - name: TX_HUNG_INT_ST bit_offset: 3 bit_size: 1 - name: IN_DONE_INT_ST bit_offset: 4 bit_size: 1 - name: IN_SUC_EOF_INT_ST bit_offset: 5 bit_size: 1 - name: IN_ERR_EOF_INT_ST bit_offset: 6 bit_size: 1 - name: OUT_DONE_INT_ST bit_offset: 7 bit_size: 1 - name: OUT_EOF_INT_ST bit_offset: 8 bit_size: 1 - name: IN_DSCR_ERR_INT_ST bit_offset: 9 bit_size: 1 - name: OUT_DSCR_ERR_INT_ST bit_offset: 10 bit_size: 1 - name: IN_DSCR_EMPTY_INT_ST bit_offset: 11 bit_size: 1 - name: OUTLINK_EOF_ERR_INT_ST bit_offset: 12 bit_size: 1 - name: OUT_TOTAL_EOF_INT_ST bit_offset: 13 bit_size: 1 - name: SEND_S_Q_INT_ST bit_offset: 14 bit_size: 1 - name: SEND_A_Q_INT_ST bit_offset: 15 bit_size: 1 - name: DMA_INFIFO_FULL_WM_INT_ST bit_offset: 16 bit_size: 1 fieldset/PKT_THRES: fields: - name: PKT_THRS description: when the amount of packet payload is greater than this value the process of receiving data is done. bit_offset: 0 bit_size: 13 fieldset/Q0_WORD0: fields: - name: SEND_Q0_WORD0 description: This register stores the content of short packet's first dword. bit_offset: 0 bit_size: 32 fieldset/Q0_WORD1: fields: - name: SEND_Q0_WORD1 description: This register stores the content of short packet's second dword. bit_offset: 0 bit_size: 32 fieldset/Q1_WORD0: fields: - name: SEND_Q1_WORD0 description: This register stores the content of short packet's first dword. bit_offset: 0 bit_size: 32 fieldset/Q1_WORD1: fields: - name: SEND_Q1_WORD1 description: This register stores the content of short packet's second dword. bit_offset: 0 bit_size: 32 fieldset/Q2_WORD0: fields: - name: SEND_Q2_WORD0 description: This register stores the content of short packet's first dword. bit_offset: 0 bit_size: 32 fieldset/Q2_WORD1: fields: - name: SEND_Q2_WORD1 description: This register stores the content of short packet's second dword. bit_offset: 0 bit_size: 32 fieldset/Q3_WORD0: fields: - name: SEND_Q3_WORD0 description: This register stores the content of short packet's first dword. bit_offset: 0 bit_size: 32 fieldset/Q3_WORD1: fields: - name: SEND_Q3_WORD1 description: This register stores the content of short packet's second dword. bit_offset: 0 bit_size: 32 fieldset/Q4_WORD0: fields: - name: SEND_Q4_WORD0 description: This register stores the content of short packet's first dword. bit_offset: 0 bit_size: 32 fieldset/Q4_WORD1: fields: - name: SEND_Q4_WORD1 description: This register stores the content of short packet's second dword. bit_offset: 0 bit_size: 32 fieldset/Q5_WORD0: fields: - name: SEND_Q5_WORD0 description: This register stores the content of short packet's first dword. bit_offset: 0 bit_size: 32 fieldset/Q5_WORD1: fields: - name: SEND_Q5_WORD1 description: This register stores the content of short packet's second dword. bit_offset: 0 bit_size: 32 fieldset/Q6_WORD0: fields: - name: SEND_Q6_WORD0 description: This register stores the content of short packet's first dword. bit_offset: 0 bit_size: 32 fieldset/Q6_WORD1: fields: - name: SEND_Q6_WORD1 description: This register stores the content of short packet's second dword. bit_offset: 0 bit_size: 32 fieldset/QUICK_SENT: fields: - name: SINGLE_SEND_NUM description: The bits are used to choose which short packet. bit_offset: 0 bit_size: 3 - name: SINGLE_SEND_EN description: Set this bit to enable send a short packet. bit_offset: 3 bit_size: 1 - name: ALWAYS_SEND_NUM description: The bits are used to choose which short packet. bit_offset: 4 bit_size: 3 - name: ALWAYS_SEND_EN description: Set this bit to enable continuously send the same short packet. bit_offset: 7 bit_size: 1 fieldset/RX_HEAD: fields: - name: RX_HEAD description: This register stores the packet header received by DMA. bit_offset: 0 bit_size: 32 fieldset/STATE0: fields: - name: STATE0 bit_offset: 0 bit_size: 32 fieldset/STATE1: fields: - name: STATE1 bit_offset: 0 bit_size: 32