block/TIMG0: description: Timer Group 0. items: - name: T0CONFIG byte_offset: 0 fieldset: T0CONFIG - name: T0LO byte_offset: 4 fieldset: T0LO - name: T0HI byte_offset: 8 fieldset: T0HI - name: T0UPDATE byte_offset: 12 fieldset: T0UPDATE - name: T0ALARMLO byte_offset: 16 fieldset: T0ALARMLO - name: T0ALARMHI byte_offset: 20 fieldset: T0ALARMHI - name: T0LOADLO byte_offset: 24 fieldset: T0LOADLO - name: T0LOADHI byte_offset: 28 fieldset: T0LOADHI - name: T0LOAD byte_offset: 32 fieldset: T0LOAD - name: T1CONFIG byte_offset: 36 fieldset: T1CONFIG - name: T1LO byte_offset: 40 fieldset: T1LO - name: T1HI byte_offset: 44 fieldset: T1HI - name: T1UPDATE byte_offset: 48 fieldset: T1UPDATE - name: T1ALARMLO byte_offset: 52 fieldset: T1ALARMLO - name: T1ALARMHI byte_offset: 56 fieldset: T1ALARMHI - name: T1LOADLO byte_offset: 60 fieldset: T1LOADLO - name: T1LOADHI byte_offset: 64 fieldset: T1LOADHI - name: T1LOAD byte_offset: 68 fieldset: T1LOAD - name: WDTCONFIG0 byte_offset: 72 fieldset: WDTCONFIG0 - name: WDTCONFIG1 byte_offset: 76 fieldset: WDTCONFIG1 - name: WDTCONFIG2 byte_offset: 80 fieldset: WDTCONFIG2 - name: WDTCONFIG3 byte_offset: 84 fieldset: WDTCONFIG3 - name: WDTCONFIG4 byte_offset: 88 fieldset: WDTCONFIG4 - name: WDTCONFIG5 byte_offset: 92 fieldset: WDTCONFIG5 - name: WDTFEED byte_offset: 96 fieldset: WDTFEED - name: WDTWPROTECT byte_offset: 100 fieldset: WDTWPROTECT - name: RTCCALICFG byte_offset: 104 fieldset: RTCCALICFG - name: RTCCALICFG1 byte_offset: 108 fieldset: RTCCALICFG1 - name: LACTCONFIG byte_offset: 112 fieldset: LACTCONFIG - name: LACTRTC byte_offset: 116 fieldset: LACTRTC - name: LACTLO byte_offset: 120 fieldset: LACTLO - name: LACTHI byte_offset: 124 fieldset: LACTHI - name: LACTUPDATE byte_offset: 128 fieldset: LACTUPDATE - name: LACTALARMLO byte_offset: 132 fieldset: LACTALARMLO - name: LACTALARMHI byte_offset: 136 fieldset: LACTALARMHI - name: LACTLOADLO byte_offset: 140 fieldset: LACTLOADLO - name: LACTLOADHI byte_offset: 144 fieldset: LACTLOADHI - name: LACTLOAD byte_offset: 148 fieldset: LACTLOAD - name: INT_ENA_TIMERS byte_offset: 152 fieldset: INT_ENA_TIMERS - name: INT_RAW_TIMERS byte_offset: 156 fieldset: INT_RAW_TIMERS - name: INT_ST_TIMERS byte_offset: 160 fieldset: INT_ST_TIMERS - name: INT_CLR_TIMERS byte_offset: 164 fieldset: INT_CLR_TIMERS - name: NTIMERS_DATE byte_offset: 248 fieldset: NTIMERS_DATE - name: TIMGCLK byte_offset: 252 fieldset: TIMGCLK fieldset/INT_CLR_TIMERS: fields: - name: T0_INT_CLR description: interrupt when timer0 alarm. bit_offset: 0 bit_size: 1 - name: T1_INT_CLR description: interrupt when timer1 alarm. bit_offset: 1 bit_size: 1 - name: WDT_INT_CLR description: Interrupt when an interrupt stage timeout. bit_offset: 2 bit_size: 1 - name: LACT_INT_CLR bit_offset: 3 bit_size: 1 fieldset/INT_ENA_TIMERS: fields: - name: T0_INT_ENA description: interrupt when timer0 alarm. bit_offset: 0 bit_size: 1 - name: T1_INT_ENA description: interrupt when timer1 alarm. bit_offset: 1 bit_size: 1 - name: WDT_INT_ENA description: Interrupt when an interrupt stage timeout. bit_offset: 2 bit_size: 1 - name: LACT_INT_ENA bit_offset: 3 bit_size: 1 fieldset/INT_RAW_TIMERS: fields: - name: T0_INT_RAW description: interrupt when timer0 alarm. bit_offset: 0 bit_size: 1 - name: T1_INT_RAW description: interrupt when timer1 alarm. bit_offset: 1 bit_size: 1 - name: WDT_INT_RAW description: Interrupt when an interrupt stage timeout. bit_offset: 2 bit_size: 1 - name: LACT_INT_RAW bit_offset: 3 bit_size: 1 fieldset/INT_ST_TIMERS: fields: - name: T0_INT_ST description: interrupt when timer0 alarm. bit_offset: 0 bit_size: 1 - name: T1_INT_ST description: interrupt when timer1 alarm. bit_offset: 1 bit_size: 1 - name: WDT_INT_ST description: Interrupt when an interrupt stage timeout. bit_offset: 2 bit_size: 1 - name: LACT_INT_ST bit_offset: 3 bit_size: 1 fieldset/LACTALARMHI: fields: - name: LACT_ALARM_HI bit_offset: 0 bit_size: 32 fieldset/LACTALARMLO: fields: - name: LACT_ALARM_LO bit_offset: 0 bit_size: 32 fieldset/LACTCONFIG: fields: - name: LACT_RTC_ONLY bit_offset: 7 bit_size: 1 - name: LACT_CPST_EN bit_offset: 8 bit_size: 1 - name: LACT_LAC_EN bit_offset: 9 bit_size: 1 - name: LACT_ALARM_EN bit_offset: 10 bit_size: 1 - name: LACT_LEVEL_INT_EN bit_offset: 11 bit_size: 1 - name: LACT_EDGE_INT_EN bit_offset: 12 bit_size: 1 - name: LACT_DIVIDER bit_offset: 13 bit_size: 16 - name: LACT_AUTORELOAD bit_offset: 29 bit_size: 1 - name: LACT_INCREASE bit_offset: 30 bit_size: 1 - name: LACT_EN bit_offset: 31 bit_size: 1 fieldset/LACTHI: fields: - name: LACT_HI bit_offset: 0 bit_size: 32 fieldset/LACTLO: fields: - name: LACT_LO bit_offset: 0 bit_size: 32 fieldset/LACTLOAD: fields: - name: LACT_LOAD bit_offset: 0 bit_size: 32 fieldset/LACTLOADHI: fields: - name: LACT_LOAD_HI bit_offset: 0 bit_size: 32 fieldset/LACTLOADLO: fields: - name: LACT_LOAD_LO bit_offset: 0 bit_size: 32 fieldset/LACTRTC: fields: - name: LACT_RTC_STEP_LEN bit_offset: 6 bit_size: 26 fieldset/LACTUPDATE: fields: - name: LACT_UPDATE bit_offset: 0 bit_size: 32 fieldset/NTIMERS_DATE: fields: - name: NTIMERS_DATE description: Version of this regfile. bit_offset: 0 bit_size: 28 fieldset/RTCCALICFG: fields: - name: RTC_CALI_START_CYCLING bit_offset: 12 bit_size: 1 - name: RTC_CALI_CLK_SEL bit_offset: 13 bit_size: 2 - name: RTC_CALI_RDY bit_offset: 15 bit_size: 1 - name: RTC_CALI_MAX bit_offset: 16 bit_size: 15 - name: RTC_CALI_START bit_offset: 31 bit_size: 1 fieldset/RTCCALICFG1: fields: - name: RTC_CALI_VALUE bit_offset: 7 bit_size: 25 fieldset/T0ALARMHI: fields: - name: ALARM_HI description: Timer 0 time-base counter value higher 32 bits that will trigger the alarm. bit_offset: 0 bit_size: 32 fieldset/T0ALARMLO: fields: - name: ALARM_LO description: Timer 0 time-base counter value lower 32 bits that will trigger the alarm. bit_offset: 0 bit_size: 32 fieldset/T0CONFIG: fields: - name: ALARM_EN description: When set alarm is enabled. bit_offset: 10 bit_size: 1 - name: LEVEL_INT_EN description: When set level type interrupt will be generated during alarm. bit_offset: 11 bit_size: 1 - name: EDGE_INT_EN description: When set edge type interrupt will be generated during alarm. bit_offset: 12 bit_size: 1 - name: DIVIDER description: Timer 0 clock (T0_clk) prescale value. bit_offset: 13 bit_size: 16 - name: AUTORELOAD description: When set timer 0 auto-reload at alarming is enabled. bit_offset: 29 bit_size: 1 - name: INCREASE description: When set timer 0 time-base counter increment. When cleared timer 0 time-base counter decrement. bit_offset: 30 bit_size: 1 - name: EN description: When set timer 0 time-base counter is enabled. bit_offset: 31 bit_size: 1 fieldset/T0HI: fields: - name: HI description: Register to store timer 0 time-base counter current value higher 32 bits. bit_offset: 0 bit_size: 32 fieldset/T0LO: fields: - name: LO description: Register to store timer 0 time-base counter current value lower 32 bits. bit_offset: 0 bit_size: 32 fieldset/T0LOAD: fields: - name: LOAD description: Write any value will trigger timer 0 time-base counter reload. bit_offset: 0 bit_size: 32 fieldset/T0LOADHI: fields: - name: LOAD_HI description: higher 32 bits of the value that will load into timer 0 time-base counter. bit_offset: 0 bit_size: 32 fieldset/T0LOADLO: fields: - name: LOAD_LO description: Lower 32 bits of the value that will load into timer 0 time-base counter. bit_offset: 0 bit_size: 32 fieldset/T0UPDATE: fields: - name: UPDATE description: Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above). bit_offset: 0 bit_size: 32 fieldset/T1ALARMHI: fields: - name: ALARM_HI description: Timer 1 time-base counter value higher 32 bits that will trigger the alarm. bit_offset: 0 bit_size: 32 fieldset/T1ALARMLO: fields: - name: ALARM_LO description: Timer 1 time-base counter value lower 32 bits that will trigger the alarm. bit_offset: 0 bit_size: 32 fieldset/T1CONFIG: fields: - name: ALARM_EN description: When set alarm is enabled. bit_offset: 10 bit_size: 1 - name: LEVEL_INT_EN description: When set level type interrupt will be generated during alarm. bit_offset: 11 bit_size: 1 - name: EDGE_INT_EN description: When set edge type interrupt will be generated during alarm. bit_offset: 12 bit_size: 1 - name: DIVIDER description: Timer 1 clock (T1_clk) prescale value. bit_offset: 13 bit_size: 16 - name: AUTORELOAD description: When set timer 1 auto-reload at alarming is enabled. bit_offset: 29 bit_size: 1 - name: INCREASE description: When set timer 1 time-base counter increment. When cleared timer 1 time-base counter decrement. bit_offset: 30 bit_size: 1 - name: EN description: When set timer 1 time-base counter is enabled. bit_offset: 31 bit_size: 1 fieldset/T1HI: fields: - name: HI description: Register to store timer 1 time-base counter current value higher 32 bits. bit_offset: 0 bit_size: 32 fieldset/T1LO: fields: - name: LO description: Register to store timer 1 time-base counter current value lower 32 bits. bit_offset: 0 bit_size: 32 fieldset/T1LOAD: fields: - name: LOAD description: Write any value will trigger timer 1 time-base counter reload. bit_offset: 0 bit_size: 32 fieldset/T1LOADHI: fields: - name: LOAD_HI description: higher 32 bits of the value that will load into timer 1 time-base counter. bit_offset: 0 bit_size: 32 fieldset/T1LOADLO: fields: - name: LOAD_LO description: Lower 32 bits of the value that will load into timer 1 time-base counter. bit_offset: 0 bit_size: 32 fieldset/T1UPDATE: fields: - name: UPDATE description: Write any value will trigger a timer 1 time-base counter value update (timer 1 current value will be stored in registers above). bit_offset: 0 bit_size: 32 fieldset/TIMGCLK: fields: - name: CLK_EN description: Force clock enable for this regfile. bit_offset: 31 bit_size: 1 fieldset/WDTCONFIG0: fields: - name: WDT_FLASHBOOT_MOD_EN description: When set flash boot protection is enabled. bit_offset: 14 bit_size: 1 - name: WDT_SYS_RESET_LENGTH description: 'length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us.' bit_offset: 15 bit_size: 3 enum: WDT_SYS_RESET_LENGTH - name: WDT_CPU_RESET_LENGTH description: 'length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us.' bit_offset: 18 bit_size: 3 enum: WDT_CPU_RESET_LENGTH - name: WDT_LEVEL_INT_EN description: When set level type interrupt generation is enabled. bit_offset: 21 bit_size: 1 - name: WDT_EDGE_INT_EN description: When set edge type interrupt generation is enabled. bit_offset: 22 bit_size: 1 - name: WDT_STG3 description: 'Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system.' bit_offset: 23 bit_size: 2 enum: WDT_STG3 - name: WDT_STG2 description: 'Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system.' bit_offset: 25 bit_size: 2 enum: WDT_STG2 - name: WDT_STG1 description: 'Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system.' bit_offset: 27 bit_size: 2 enum: WDT_STG1 - name: WDT_STG0 description: 'Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system.' bit_offset: 29 bit_size: 2 enum: WDT_STG0 - name: WDT_EN description: When set SWDT is enabled. bit_offset: 31 bit_size: 1 fieldset/WDTCONFIG1: fields: - name: WDT_CLK_PRESCALE description: SWDT clock prescale value. Period = 12.5ns * value stored in this register. bit_offset: 16 bit_size: 16 fieldset/WDTCONFIG2: fields: - name: WDT_STG0_HOLD description: Stage 0 timeout value in SWDT clock cycles. bit_offset: 0 bit_size: 32 fieldset/WDTCONFIG3: fields: - name: WDT_STG1_HOLD description: Stage 1 timeout value in SWDT clock cycles. bit_offset: 0 bit_size: 32 fieldset/WDTCONFIG4: fields: - name: WDT_STG2_HOLD description: Stage 2 timeout value in SWDT clock cycles. bit_offset: 0 bit_size: 32 fieldset/WDTCONFIG5: fields: - name: WDT_STG3_HOLD description: Stage 3 timeout value in SWDT clock cycles. bit_offset: 0 bit_size: 32 fieldset/WDTFEED: fields: - name: WDT_FEED description: Write any value will feed SWDT. bit_offset: 0 bit_size: 32 fieldset/WDTWPROTECT: fields: - name: WDT_WKEY description: If change its value from default then write protection is on. bit_offset: 0 bit_size: 32 enum/WDT_CPU_RESET_LENGTH: bit_size: 3 variants: - name: NS100 description: 100ns. value: 0 - name: NS200 description: 200ns. value: 1 - name: NS300 description: 300ns. value: 2 - name: NS400 description: 400ns. value: 3 - name: NS500 description: 500ns. value: 4 - name: NS800 description: 800ns. value: 5 - name: NS1600 description: 1.6us. value: 6 - name: NS3200 description: 3.2us. value: 7 enum/WDT_STG0: bit_size: 2 variants: - name: OFF description: Off. value: 0 - name: INTERRUPT description: Interrupt. value: 1 - name: RESET description: Reset CPU. value: 2 - name: RESET_SYS description: Reset system. value: 3 enum/WDT_STG1: bit_size: 2 variants: - name: OFF description: Off. value: 0 - name: INTERRUPT description: Interrupt. value: 1 - name: RESET description: Reset CPU. value: 2 - name: RESET_SYS description: Reset system. value: 3 enum/WDT_STG2: bit_size: 2 variants: - name: OFF description: Off. value: 0 - name: INTERRUPT description: Interrupt. value: 1 - name: RESET description: Reset CPU. value: 2 - name: RESET_SYS description: Reset system. value: 3 enum/WDT_STG3: bit_size: 2 variants: - name: OFF description: Off. value: 0 - name: INTERRUPT description: Interrupt. value: 1 - name: RESET description: Reset CPU. value: 2 - name: RESET_SYS description: Reset system. value: 3 enum/WDT_SYS_RESET_LENGTH: bit_size: 3 variants: - name: NS100 description: 100ns. value: 0 - name: NS200 description: 200ns. value: 1 - name: NS300 description: 300ns. value: 2 - name: NS400 description: 400ns. value: 3 - name: NS500 description: 500ns. value: 4 - name: NS800 description: 800ns. value: 5 - name: NS1600 description: 1.6us. value: 6 - name: NS3200 description: 3.2us. value: 7