block/TIM2:
  description: General-purpose-timers.
  items:
  - name: CR1
    description: control register 1.
    byte_offset: 0
    bit_size: 16
    fieldset: CR1
  - name: CR2
    description: control register 2.
    byte_offset: 4
    bit_size: 16
    fieldset: CR2
  - name: SMCR
    description: slave mode control register.
    byte_offset: 8
    fieldset: SMCR
  - name: DIER
    description: DMA/Interrupt enable register.
    byte_offset: 12
    bit_size: 16
    fieldset: DIER
  - name: SR
    description: status register.
    byte_offset: 16
    bit_size: 16
    fieldset: SR
  - name: EGR
    description: event generation register.
    byte_offset: 20
    access: Write
    bit_size: 16
    fieldset: EGR
  - name: CCMR1_Input
    description: capture/compare mode register 1 (input mode).
    byte_offset: 24
    fieldset: CCMR1_Input
  - name: CCMR1_Output
    description: capture/compare mode register 1 (output mode).
    byte_offset: 24
    fieldset: CCMR1_Output
  - name: CCMR2_Input
    description: capture/compare mode register 2 (input mode).
    byte_offset: 28
    fieldset: CCMR2_Input
  - name: CCMR2_Output
    description: capture/compare mode register 2 (output mode).
    byte_offset: 28
    fieldset: CCMR2_Output
  - name: CCER
    description: capture/compare enable register.
    byte_offset: 32
    bit_size: 16
    fieldset: CCER
  - name: CNT
    description: counter.
    byte_offset: 36
    fieldset: CNT
  - name: CNT32
    description: 32-bit counter register.
    byte_offset: 36
    fieldset: CNT32
  - name: PSC
    description: prescaler.
    byte_offset: 40
    bit_size: 16
    fieldset: PSC
  - name: ARR
    description: auto-reload register.
    byte_offset: 44
    fieldset: ARR
  - name: CCR
    description: capture/compare register.
    array:
      len: 4
      stride: 4
    byte_offset: 52
    fieldset: CCR
  - name: DCR
    description: DMA control register.
    byte_offset: 72
    bit_size: 16
    fieldset: DCR
  - name: DMAR
    description: DMA address for full transfer.
    byte_offset: 76
    bit_size: 16
    fieldset: DMAR
  - name: OR
    description: TIM2 option register.
    byte_offset: 80
    fieldset: OR
  - name: AF
    description: TIM2 alternate function option register 1.
    byte_offset: 96
    fieldset: AF
fieldset/AF:
  description: TIM2 alternate function option register 1.
  fields:
  - name: ETRSEL
    description: External trigger source selection.
    bit_offset: 14
    bit_size: 3
fieldset/ARR:
  description: auto-reload register.
  fields:
  - name: ARR
    description: Auto-reload value.
    bit_offset: 0
    bit_size: 32
fieldset/CCER:
  description: capture/compare enable register.
  bit_size: 16
  fields:
  - name: CCE
    description: Capture/Compare %s output enable.
    bit_offset: 0
    bit_size: 1
    array:
      len: 4
      stride: 4
    enum: CCE
  - name: CCP
    description: Capture/Compare %s output Polarity.
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 4
    enum: CCP
  - name: CCNP
    description: Capture/Compare %s output Polarity.
    bit_offset: 3
    bit_size: 1
    array:
      len: 4
      stride: 4
fieldset/CCMR1_Input:
  description: capture/compare mode register 1 (input mode).
  fields:
  - name: CC1S
    description: Capture/Compare 1 selection.
    bit_offset: 0
    bit_size: 2
    enum: CC1S
  - name: ICPSC
    description: Input capture %s prescaler.
    bit_offset: 2
    bit_size: 2
    array:
      len: 2
      stride: 8
    enum: ICPSC
  - name: ICF
    description: Input capture %s filter.
    bit_offset: 4
    bit_size: 4
    array:
      len: 2
      stride: 8
    enum: ICF
  - name: CC2S
    description: Capture/compare 2 selection.
    bit_offset: 8
    bit_size: 2
    enum: CC2S
fieldset/CCMR1_Output:
  description: capture/compare mode register 1 (output mode).
  fields:
  - name: CCS
    description: Capture/Compare %s selection.
    bit_offset: 0
    bit_size: 2
    array:
      len: 2
      stride: 8
    enum: CCS
  - name: OCFE
    description: Output compare %s fast enable.
    bit_offset: 2
    bit_size: 1
    array:
      len: 2
      stride: 8
    enum: OCFE
  - name: OCPE
    description: Output compare %s preload enable.
    bit_offset: 3
    bit_size: 1
    array:
      len: 2
      stride: 8
    enum: OCPE
  - name: OCM
    description: Output compare %s mode.
    bit_offset: 4
    bit_size: 3
    array:
      len: 2
      stride: 8
    enum: OCM
  - name: OCCE
    description: Output compare %s clear enable.
    bit_offset: 7
    bit_size: 1
    array:
      len: 2
      stride: 8
  - name: OCM_3
    description: Output compare %s mode, bit 3.
    bit_offset: 16
    bit_size: 1
    array:
      len: 2
      stride: 8
    enum: OCM_3
fieldset/CCMR2_Input:
  description: capture/compare mode register 2 (input mode).
  fields:
  - name: CC3S
    description: Capture/Compare 3 selection.
    bit_offset: 0
    bit_size: 2
    enum: CC3S
  - name: CC4S
    description: Capture/Compare 4 selection.
    bit_offset: 8
    bit_size: 2
    enum: CC4S
fieldset/CCMR2_Output:
  description: capture/compare mode register 2 (output mode).
  fields: []
fieldset/CCR:
  description: capture/compare register.
  fields:
  - name: CCR
    description: Capture/Compare value.
    bit_offset: 0
    bit_size: 32
fieldset/CNT:
  description: counter.
  fields:
  - name: CNT
    description: Counter value.
    bit_offset: 0
    bit_size: 32
  - name: UIFREMAP_CNT
    description: Counter value when CR1.UIFREMAP=1.
    bit_offset: 0
    bit_size: 31
  - name: UIFCPY
    description: Copy of ISR.UIF when CR1.UIFREMAP=1.
    bit_offset: 31
    bit_size: 1
fieldset/CNT32:
  description: 32-bit counter register.
  fields:
  - name: CNT
    description: counter value.
    bit_offset: 0
    bit_size: 32
fieldset/CR1:
  description: control register 1.
  bit_size: 16
  fields:
  - name: CEN
    description: Counter enable.
    bit_offset: 0
    bit_size: 1
    enum: CEN
  - name: UDIS
    description: Update disable.
    bit_offset: 1
    bit_size: 1
    enum: UDIS
  - name: URS
    description: Update request source.
    bit_offset: 2
    bit_size: 1
    enum: URS
  - name: OPM
    description: One-pulse mode.
    bit_offset: 3
    bit_size: 1
    enum: OPM
  - name: DIR
    description: Direction.
    bit_offset: 4
    bit_size: 1
    enum: DIR
  - name: CMS
    description: Center-aligned mode selection.
    bit_offset: 5
    bit_size: 2
    enum: CMS
  - name: ARPE
    description: Auto-reload preload enable.
    bit_offset: 7
    bit_size: 1
    enum: ARPE
  - name: CKD
    description: Clock division.
    bit_offset: 8
    bit_size: 2
    enum: CKD
  - name: UIFREMAP
    description: UIF status bit remapping.
    bit_offset: 11
    bit_size: 1
fieldset/CR2:
  description: control register 2.
  bit_size: 16
  fields:
  - name: CCDS
    description: Capture/compare DMA selection.
    bit_offset: 3
    bit_size: 1
  - name: MMS
    description: Master mode selection.
    bit_offset: 4
    bit_size: 3
  - name: TI1S
    description: TI1 selection.
    bit_offset: 7
    bit_size: 1
fieldset/DCR:
  description: DMA control register.
  bit_size: 16
  fields:
  - name: DBA
    description: DMA base address.
    bit_offset: 0
    bit_size: 5
  - name: DBL
    description: DMA burst length.
    bit_offset: 8
    bit_size: 5
fieldset/DIER:
  description: DMA/Interrupt enable register.
  bit_size: 16
  fields:
  - name: UIE
    description: Update interrupt enable.
    bit_offset: 0
    bit_size: 1
    enum: UIE
  - name: CCIE
    description: Capture/Compare %s interrupt enable.
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
    enum: CCIE
  - name: TIE
    description: Trigger interrupt enable.
    bit_offset: 6
    bit_size: 1
  - name: UDE
    description: Update DMA request enable.
    bit_offset: 8
    bit_size: 1
  - name: CCDE
    description: Capture/Compare %s DMA request enable.
    bit_offset: 9
    bit_size: 1
    array:
      len: 4
      stride: 1
    enum: CCDE
fieldset/DMAR:
  description: DMA address for full transfer.
  bit_size: 16
  fields:
  - name: DMAB
    description: DMA register for burst accesses.
    bit_offset: 0
    bit_size: 16
fieldset/EGR:
  description: event generation register.
  bit_size: 16
  fields:
  - name: UG
    description: Update generation.
    bit_offset: 0
    bit_size: 1
    enum: UG
  - name: CCG
    description: Capture/compare %s generation.
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
    enum: CCG
  - name: TG
    description: Trigger generation.
    bit_offset: 6
    bit_size: 1
fieldset/OR:
  description: TIM2 option register.
  fields:
  - name: ITR_RMP
    description: Internal trigger remap.
    bit_offset: 0
    bit_size: 1
  - name: ETR_RMP
    description: External trigger remap.
    bit_offset: 1
    bit_size: 1
  - name: TI4_RMP
    description: Input capture 4 remap.
    bit_offset: 2
    bit_size: 2
fieldset/PSC:
  description: prescaler.
  bit_size: 16
  fields:
  - name: PSC
    description: Prescaler value.
    bit_offset: 0
    bit_size: 16
fieldset/SMCR:
  description: slave mode control register.
  fields:
  - name: SMS
    description: Slave mode selection.
    bit_offset: 0
    bit_size: 3
  - name: OCCS
    description: OCREF clear selection.
    bit_offset: 3
    bit_size: 1
  - name: TS
    description: Trigger selection.
    bit_offset: 4
    bit_size: 3
  - name: MSM
    description: Master/Slave mode.
    bit_offset: 7
    bit_size: 1
  - name: ETF
    description: External trigger filter.
    bit_offset: 8
    bit_size: 4
  - name: ETPS
    description: External trigger prescaler.
    bit_offset: 12
    bit_size: 2
  - name: ECE
    description: External clock enable.
    bit_offset: 14
    bit_size: 1
  - name: ETP
    description: External trigger polarity.
    bit_offset: 15
    bit_size: 1
  - name: SMS_3
    description: Slave mode selection - bit 3.
    bit_offset: 16
    bit_size: 1
fieldset/SR:
  description: status register.
  bit_size: 16
  fields:
  - name: UIF
    description: Update interrupt flag.
    bit_offset: 0
    bit_size: 1
    enum: UIF
  - name: CCIF
    description: Capture/compare %s interrupt flag.
    bit_offset: 1
    bit_size: 1
    array:
      len: 4
      stride: 1
    enum: CCIF
  - name: TIF
    description: Trigger interrupt flag.
    bit_offset: 6
    bit_size: 1
  - name: CCOF
    description: Capture/Compare %s overcapture flag.
    bit_offset: 9
    bit_size: 1
    array:
      len: 4
      stride: 1
    enum: CCOF
enum/ARPE:
  bit_size: 1
  variants:
  - name: Disabled
    description: TIMx_APRR register is not buffered.
    value: 0
  - name: Enabled
    description: TIMx_APRR register is buffered.
    value: 1
enum/CC1S:
  bit_size: 2
  variants:
  - name: TI1
    description: CC1 channel is configured as input, IC1 is mapped on TI1.
    value: 1
  - name: TI2
    description: CC1 channel is configured as input, IC1 is mapped on TI2.
    value: 2
  - name: TRC
    description: CC1 channel is configured as input, IC1 is mapped on TRC.
    value: 3
enum/CC2S:
  bit_size: 2
  variants:
  - name: TI2
    description: CC2 channel is configured as input, IC2 is mapped on TI2.
    value: 1
  - name: TI1
    description: CC2 channel is configured as input, IC2 is mapped on TI1.
    value: 2
  - name: TRC
    description: CC2 channel is configured as input, IC2 is mapped on TRC.
    value: 3
enum/CC3S:
  bit_size: 2
  variants:
  - name: TI3
    description: CC3 channel is configured as input, IC3 is mapped on TI3.
    value: 1
  - name: TI4
    description: CC3 channel is configured as input, IC3 is mapped on TI4.
    value: 2
  - name: TRC
    description: CC3 channel is configured as input, IC3 is mapped on TRC.
    value: 3
enum/CC4S:
  bit_size: 2
  variants:
  - name: TI4
    description: CC4 channel is configured as input, IC4 is mapped on TI4.
    value: 1
  - name: TI3
    description: CC4 channel is configured as input, IC4 is mapped on TI3.
    value: 2
  - name: TRC
    description: CC4 channel is configured as input, IC4 is mapped on TRC.
    value: 3
enum/CCDE:
  bit_size: 1
  variants:
  - name: Disabled
    description: CCx DMA request disabled.
    value: 0
  - name: Enabled
    description: CCx DMA request enabled.
    value: 1
enum/CCE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Capture disabled.
    value: 0
  - name: Enabled
    description: Capture enabled.
    value: 1
enum/CCG:
  bit_size: 1
  variants:
  - name: Trigger
    description: 'If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.'
    value: 1
enum/CCIE:
  bit_size: 1
  variants:
  - name: Disabled
    description: CCx interrupt disabled.
    value: 0
  - name: Enabled
    description: CCx interrupt enabled.
    value: 1
enum/CCIF:
  bit_size: 1
  variants:
  - name: R_NoMatch_W_Clear
    description: No campture/compare has been detected.
    value: 0
  - name: Match
    description: 'If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.'
    value: 1
enum/CCOF:
  bit_size: 1
  variants:
  - name: R_NoOvercapture_W_Clear
    description: No overcapture has been detected.
    value: 0
  - name: Overcapture
    description: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set.
    value: 1
enum/CCP:
  bit_size: 1
  variants:
  - name: RisingEdge
    description: Noninverted/rising edge.
    value: 0
  - name: FallingEdge
    description: Inverted/falling edge.
    value: 1
enum/CCS:
  bit_size: 2
  variants:
  - name: Output
    description: CCx channel is configured as output.
    value: 0
enum/CEN:
  bit_size: 1
  variants:
  - name: Disabled
    description: Counter disabled.
    value: 0
  - name: Enabled
    description: Counter enabled.
    value: 1
enum/CKD:
  bit_size: 2
  variants:
  - name: Div1
    description: t_DTS = t_CK_INT.
    value: 0
  - name: Div2
    description: t_DTS = 2 × t_CK_INT.
    value: 1
  - name: Div4
    description: t_DTS = 4 × t_CK_INT.
    value: 2
enum/CMS:
  bit_size: 2
  variants:
  - name: EdgeAligned
    description: The counter counts up or down depending on the direction bit.
    value: 0
  - name: CenterAligned1
    description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
    value: 1
  - name: CenterAligned2
    description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
    value: 2
  - name: CenterAligned3
    description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
    value: 3
enum/DIR:
  bit_size: 1
  variants:
  - name: Up
    description: Counter used as upcounter.
    value: 0
  - name: Down
    description: Counter used as downcounter.
    value: 1
enum/ICF:
  bit_size: 4
  variants:
  - name: NoFilter
    description: No filter, sampling is done at fDTS.
    value: 0
  - name: FCK_INT_N2
    description: fSAMPLING=fCK_INT, N=2.
    value: 1
  - name: FCK_INT_N4
    description: fSAMPLING=fCK_INT, N=4.
    value: 2
  - name: FCK_INT_N8
    description: fSAMPLING=fCK_INT, N=8.
    value: 3
  - name: FDTS_Div2_N6
    description: fSAMPLING=fDTS/2, N=6.
    value: 4
  - name: FDTS_Div2_N8
    description: fSAMPLING=fDTS/2, N=8.
    value: 5
  - name: FDTS_Div4_N6
    description: fSAMPLING=fDTS/4, N=6.
    value: 6
  - name: FDTS_Div4_N8
    description: fSAMPLING=fDTS/4, N=8.
    value: 7
  - name: FDTS_Div8_N6
    description: fSAMPLING=fDTS/8, N=6.
    value: 8
  - name: FDTS_Div8_N8
    description: fSAMPLING=fDTS/8, N=8.
    value: 9
  - name: FDTS_Div16_N5
    description: fSAMPLING=fDTS/16, N=5.
    value: 10
  - name: FDTS_Div16_N6
    description: fSAMPLING=fDTS/16, N=6.
    value: 11
  - name: FDTS_Div16_N8
    description: fSAMPLING=fDTS/16, N=8.
    value: 12
  - name: FDTS_Div32_N5
    description: fSAMPLING=fDTS/32, N=5.
    value: 13
  - name: FDTS_Div32_N6
    description: fSAMPLING=fDTS/32, N=6.
    value: 14
  - name: FDTS_Div32_N8
    description: fSAMPLING=fDTS/32, N=8.
    value: 15
enum/ICPSC:
  bit_size: 2
  variants:
  - name: NoPrescaler
    description: No prescaler, capture is done each time an edge is detected on the capture input.
    value: 0
  - name: TwoEvents
    description: Capture is done once every 2 events.
    value: 1
  - name: FourEvents
    description: Capture is done once every 4 events.
    value: 2
  - name: EightEvents
    description: Capture is done once every 8 events.
    value: 3
enum/OCFE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Fast output disabled.
    value: 0
  - name: Enabled
    description: Fast output enabled.
    value: 1
enum/OCM:
  bit_size: 3
  variants:
  - name: Frozen
    description: 'The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive.'
    value: 0
  - name: ActiveOnMatch
    description: 'Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1.'
    value: 1
  - name: InactiveOnMatch
    description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved.
    value: 2
  - name: Toggle
    description: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved.
    value: 3
  - name: ForceInactive
    description: 'OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF.'
    value: 4
  - name: ForceActive
    description: 'OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF.'
    value: 5
  - name: PwmMode1
    description: 'In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down.'
    value: 6
  - name: PwmMode2
    description: 'Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1.'
    value: 7
enum/OCM_3:
  bit_size: 1
  variants:
  - name: Normal
    description: Normal output compare mode (modes 0-7).
    value: 0
  - name: Extended
    description: Extended output compare mode (modes 7-15).
    value: 1
enum/OCPE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately.
    value: 0
  - name: Enabled
    description: Preload register on CCRx enabled. Preload value is loaded into active register on each update event.
    value: 1
enum/OPM:
  bit_size: 1
  variants:
  - name: Disabled
    description: Counter is not stopped at update event.
    value: 0
  - name: Enabled
    description: Counter stops counting at the next update event (clearing the CEN bit).
    value: 1
enum/UDIS:
  bit_size: 1
  variants:
  - name: Enabled
    description: Update event enabled.
    value: 0
  - name: Disabled
    description: Update event disabled.
    value: 1
enum/UG:
  bit_size: 1
  variants:
  - name: Update
    description: Re-initializes the timer counter and generates an update of the registers.
    value: 1
enum/UIE:
  bit_size: 1
  variants:
  - name: Disabled
    description: Update interrupt disabled.
    value: 0
  - name: Enabled
    description: Update interrupt enabled.
    value: 1
enum/UIF:
  bit_size: 1
  variants:
  - name: R_NoUpdateOccurred_W_Clear
    description: No update occurred.
    value: 0
  - name: UpdatePending
    description: Update interrupt pending.
    value: 1
enum/URS:
  bit_size: 1
  variants:
  - name: AnyEvent
    description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request.
    value: 0
  - name: CounterOnly
    description: Only counter overflow/underflow generates an update interrupt or DMA request.
    value: 1