block/RCC: description: Reset and clock control. items: - name: CR description: Clock control register. byte_offset: 0 fieldset: CR - name: ICSCR description: Internal clock sources calibration register. byte_offset: 4 fieldset: ICSCR - name: CFGR description: Clock configuration register. byte_offset: 8 fieldset: CFGR - name: PLLCFGR description: PLLSYS configuration register. byte_offset: 12 fieldset: PLLCFGR - name: PLLSAI1CFGR description: PLLSAI1 configuration register. byte_offset: 16 fieldset: PLLSAI1CFGR - name: CIER description: Clock interrupt enable register. byte_offset: 24 fieldset: CIER - name: CIFR description: Clock interrupt flag register. byte_offset: 28 access: Read fieldset: CIFR - name: CICR description: Clock interrupt clear register. byte_offset: 32 access: Write fieldset: CICR - name: SMPSCR description: Step Down converter control register. byte_offset: 36 fieldset: SMPSCR - name: AHB1RSTR description: AHB1 peripheral reset register. byte_offset: 40 fieldset: AHB1RSTR - name: AHB2RSTR description: AHB2 peripheral reset register. byte_offset: 44 fieldset: AHB2RSTR - name: AHB3RSTR description: AHB3 peripheral reset register. byte_offset: 48 fieldset: AHB3RSTR - name: APB1RSTR1 description: APB1 peripheral reset register 1. byte_offset: 56 fieldset: APB1RSTR1 - name: APB1RSTR2 description: APB1 peripheral reset register 2. byte_offset: 60 fieldset: APB1RSTR2 - name: APB2RSTR description: APB2 peripheral reset register. byte_offset: 64 fieldset: APB2RSTR - name: APB3RSTR description: APB3 peripheral reset register. byte_offset: 68 fieldset: APB3RSTR - name: AHB1ENR description: AHB1 peripheral clock enable register. byte_offset: 72 fieldset: AHB1ENR - name: AHB2ENR description: AHB2 peripheral clock enable register. byte_offset: 76 fieldset: AHB2ENR - name: AHB3ENR description: AHB3 peripheral clock enable register. byte_offset: 80 fieldset: AHB3ENR - name: APB1ENR1 description: APB1ENR1. byte_offset: 88 fieldset: APB1ENR1 - name: APB1ENR2 description: APB1 peripheral clock enable register 2. byte_offset: 92 fieldset: APB1ENR2 - name: APB2ENR description: APB2ENR. byte_offset: 96 fieldset: APB2ENR - name: AHB1SMENR description: AHB1 peripheral clocks enable in Sleep and Stop modes register. byte_offset: 104 fieldset: AHB1SMENR - name: AHB2SMENR description: AHB2 peripheral clocks enable in Sleep and Stop modes register. byte_offset: 108 fieldset: AHB2SMENR - name: AHB3SMENR description: AHB3 peripheral clocks enable in Sleep and Stop modes register. byte_offset: 112 fieldset: AHB3SMENR - name: APB1SMENR1 description: APB1SMENR1. byte_offset: 120 fieldset: APB1SMENR1 - name: APB1SMENR2 description: APB1 peripheral clocks enable in Sleep and Stop modes register 2. byte_offset: 124 fieldset: APB1SMENR2 - name: APB2SMENR description: APB2SMENR. byte_offset: 128 fieldset: APB2SMENR - name: CCIPR description: CCIPR. byte_offset: 136 fieldset: CCIPR - name: BDCR description: BDCR. byte_offset: 144 fieldset: BDCR - name: CSR description: CSR. byte_offset: 148 fieldset: CSR - name: CRRCR description: Clock recovery RC register. byte_offset: 152 fieldset: CRRCR - name: HSECR description: Clock HSE register. byte_offset: 156 fieldset: HSECR - name: HSECR_KEY byte_offset: 156 access: Write fieldset: HSECR_KEY - name: EXTCFGR description: Extended clock recovery register. byte_offset: 264 fieldset: EXTCFGR - name: C2AHB1ENR description: CPU2 AHB1 peripheral clock enable register. byte_offset: 328 fieldset: C2AHB1ENR - name: C2AHB2ENR description: CPU2 AHB2 peripheral clock enable register. byte_offset: 332 fieldset: C2AHB2ENR - name: C2AHB3ENR description: CPU2 AHB3 peripheral clock enable register. byte_offset: 336 fieldset: C2AHB3ENR - name: C2APB1ENR1 description: CPU2 APB1ENR1. byte_offset: 344 fieldset: C2APB1ENR1 - name: C2APB1ENR2 description: CPU2 APB1 peripheral clock enable register 2. byte_offset: 348 fieldset: C2APB1ENR2 - name: C2APB2ENR description: CPU2 APB2ENR. byte_offset: 352 fieldset: C2APB2ENR - name: C2APB3ENR description: CPU2 APB3ENR. byte_offset: 356 fieldset: C2APB3ENR - name: C2AHB1SMENR description: CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register. byte_offset: 360 fieldset: C2AHB1SMENR - name: C2AHB2SMENR description: CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register. byte_offset: 364 fieldset: C2AHB2SMENR - name: C2AHB3SMENR description: CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register. byte_offset: 368 fieldset: C2AHB3SMENR - name: C2APB1SMENR1 description: CPU2 APB1SMENR1. byte_offset: 376 fieldset: C2APB1SMENR1 - name: C2APB1SMENR2 description: CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2. byte_offset: 380 fieldset: C2APB1SMENR2 - name: C2APB2SMENR description: CPU2 APB2SMENR. byte_offset: 384 fieldset: C2APB2SMENR - name: C2APB3SMENR description: CPU2 APB3SMENR. byte_offset: 388 fieldset: C2APB3SMENR fieldset/AHB1ENR: description: AHB1 peripheral clock enable register. fields: - name: DMA1EN description: DMA1 clock enable. bit_offset: 0 bit_size: 1 enum: AHB1ENR_DMA1EN - name: DMA2EN description: DMA2 clock enable. bit_offset: 1 bit_size: 1 enum: AHB1ENR_DMA2EN - name: DMAMUXEN description: DMAMUX clock enable. bit_offset: 2 bit_size: 1 enum: AHB1ENR_DMAMUXEN - name: CRCEN description: CPU1 CRC clock enable. bit_offset: 12 bit_size: 1 enum: AHB1ENR_CRCEN - name: TSCEN description: Touch Sensing Controller clock enable. bit_offset: 16 bit_size: 1 enum: AHB1ENR_TSCEN fieldset/AHB1RSTR: description: AHB1 peripheral reset register. fields: - name: DMA1RST description: DMA1 reset. bit_offset: 0 bit_size: 1 enum: DMA1RST - name: DMA2RST description: DMA2 reset. bit_offset: 1 bit_size: 1 enum: DMA2RST - name: DMAMUXRST description: DMAMUX reset. bit_offset: 2 bit_size: 1 enum: DMAMUXRST - name: CRCRST description: CRC reset. bit_offset: 12 bit_size: 1 enum: CRCRST - name: TSCRST description: Touch Sensing Controller reset. bit_offset: 16 bit_size: 1 enum: TSCRST fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep and Stop modes register. fields: - name: DMA1SMEN description: CPU1 DMA1 clocks enable during Sleep and Stop modes. bit_offset: 0 bit_size: 1 - name: DMA2SMEN description: CPU1 DMA2 clocks enable during Sleep and Stop modes. bit_offset: 1 bit_size: 1 - name: DMAMUXSMEN description: CPU1 DMAMUX clocks enable during Sleep and Stop modes. bit_offset: 2 bit_size: 1 - name: SRAM1SMEN description: CPU1 SRAM1 interface clocks enable during Sleep and Stop modes. bit_offset: 9 bit_size: 1 - name: CRCSMEN description: CPU1 CRCSMEN. bit_offset: 12 bit_size: 1 - name: TSCSMEN description: CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes. bit_offset: 16 bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register. fields: - name: GPIOAEN description: IO port A clock enable. bit_offset: 0 bit_size: 1 enum: AHB2ENR_GPIOAEN - name: GPIOBEN description: IO port B clock enable. bit_offset: 1 bit_size: 1 enum: AHB2ENR_GPIOBEN - name: GPIOCEN description: IO port C clock enable. bit_offset: 2 bit_size: 1 enum: AHB2ENR_GPIOCEN - name: GPIODEN description: IO port D clock enable. bit_offset: 3 bit_size: 1 enum: AHB2ENR_GPIODEN - name: GPIOEEN description: IO port E clock enable. bit_offset: 4 bit_size: 1 enum: AHB2ENR_GPIOEEN - name: GPIOHEN description: IO port H clock enable. bit_offset: 7 bit_size: 1 enum: AHB2ENR_GPIOHEN - name: ADCEN description: ADC clock enable. bit_offset: 13 bit_size: 1 enum: AHB2ENR_ADCEN - name: AES1EN description: AES1 accelerator clock enable. bit_offset: 16 bit_size: 1 enum: AHB2ENR_AES1EN fieldset/AHB2RSTR: description: AHB2 peripheral reset register. fields: - name: GPIOARST description: IO port A reset. bit_offset: 0 bit_size: 1 enum: GPIOARST - name: GPIOBRST description: IO port B reset. bit_offset: 1 bit_size: 1 enum: GPIOBRST - name: GPIOCRST description: IO port C reset. bit_offset: 2 bit_size: 1 enum: GPIOCRST - name: GPIODRST description: IO port D reset. bit_offset: 3 bit_size: 1 enum: GPIODRST - name: GPIOERST description: IO port E reset. bit_offset: 4 bit_size: 1 enum: GPIOERST - name: GPIOHRST description: IO port H reset. bit_offset: 7 bit_size: 1 enum: GPIOHRST - name: ADCRST description: ADC reset. bit_offset: 13 bit_size: 1 enum: ADCRST - name: AES1RST description: AES1 hardware accelerator reset. bit_offset: 16 bit_size: 1 enum: AES1RST fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep and Stop modes register. fields: - name: GPIOASMEN description: CPU1 IO port A clocks enable during Sleep and Stop modes. bit_offset: 0 bit_size: 1 - name: GPIOBSMEN description: CPU1 IO port B clocks enable during Sleep and Stop modes. bit_offset: 1 bit_size: 1 - name: GPIOCSMEN description: CPU1 IO port C clocks enable during Sleep and Stop modes. bit_offset: 2 bit_size: 1 - name: GPIODSMEN description: CPU1 IO port D clocks enable during Sleep and Stop modes. bit_offset: 3 bit_size: 1 - name: GPIOESMEN description: CPU1 IO port E clocks enable during Sleep and Stop modes. bit_offset: 4 bit_size: 1 - name: GPIOHSMEN description: CPU1 IO port H clocks enable during Sleep and Stop modes. bit_offset: 7 bit_size: 1 - name: ADCFSSMEN description: CPU1 ADC clocks enable during Sleep and Stop modes. bit_offset: 13 bit_size: 1 - name: AES1SMEN description: CPU1 AES1 accelerator clocks enable during Sleep and Stop modes. bit_offset: 16 bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register. fields: - name: QSPIEN description: QSPIEN. bit_offset: 8 bit_size: 1 enum: QSPIEN - name: PKAEN description: PKAEN. bit_offset: 16 bit_size: 1 enum: AHB3ENR_PKAEN - name: AES2EN description: AES2EN. bit_offset: 17 bit_size: 1 enum: AHB3ENR_AES2EN - name: RNGEN description: RNGEN. bit_offset: 18 bit_size: 1 enum: AHB3ENR_RNGEN - name: HSEMEN description: HSEMEN. bit_offset: 19 bit_size: 1 enum: AHB3ENR_HSEMEN - name: IPCCEN description: IPCCEN. bit_offset: 20 bit_size: 1 enum: AHB3ENR_IPCCEN - name: FLASHEN description: FLASHEN. bit_offset: 25 bit_size: 1 enum: AHB3ENR_FLASHEN fieldset/AHB3RSTR: description: AHB3 peripheral reset register. fields: - name: QSPIRST description: Quad SPI memory interface reset. bit_offset: 8 bit_size: 1 enum: QSPIRST - name: PKARST description: PKA interface reset. bit_offset: 16 bit_size: 1 enum: PKARST - name: AES2RST description: AES2 interface reset. bit_offset: 17 bit_size: 1 enum: AES2RST - name: RNGRST description: RNG interface reset. bit_offset: 18 bit_size: 1 enum: RNGRST - name: HSEMRST description: HSEM interface reset. bit_offset: 19 bit_size: 1 enum: HSEMRST - name: IPCCRST description: IPCC interface reset. bit_offset: 20 bit_size: 1 enum: IPCCRST - name: FLASHRST description: Flash interface reset. bit_offset: 25 bit_size: 1 enum: FLASHRST fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register. fields: - name: QSPISMEN description: QSPISMEN. bit_offset: 8 bit_size: 1 - name: PKASMEN description: PKA accelerator clocks enable during CPU1 sleep mode. bit_offset: 16 bit_size: 1 - name: AES2SMEN description: AES2 accelerator clocks enable during CPU1 sleep mode. bit_offset: 17 bit_size: 1 - name: RNGSMEN description: True RNG clocks enable during CPU1 sleep mode. bit_offset: 18 bit_size: 1 - name: SRAM2SMEN description: SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode. bit_offset: 24 bit_size: 1 - name: FLASHSMEN description: Flash interface clocks enable during CPU1 sleep mode. bit_offset: 25 bit_size: 1 fieldset/APB1ENR1: description: APB1ENR1. fields: - name: TIM2EN description: CPU1 TIM2 timer clock enable. bit_offset: 0 bit_size: 1 enum: APB1ENR1_TIM2EN - name: LCDEN description: CPU1 LCD clock enable. bit_offset: 9 bit_size: 1 enum: APB1ENR1_LCDEN - name: RTCAPBEN description: CPU1 RTC APB clock enable. bit_offset: 10 bit_size: 1 enum: APB1ENR1_RTCAPBEN - name: WWDGEN description: CPU1 Window watchdog clock enable. bit_offset: 11 bit_size: 1 enum: WWDGEN - name: SPI2EN description: CPU1 SPI2 clock enable. bit_offset: 14 bit_size: 1 enum: APB1ENR1_SPI2EN - name: I2C1EN description: CPU1 I2C1 clock enable. bit_offset: 21 bit_size: 1 enum: APB1ENR1_I2C1EN - name: I2C3EN description: CPU1 I2C3 clock enable. bit_offset: 23 bit_size: 1 enum: APB1ENR1_I2C3EN - name: CRSEN description: CPU1 CRS clock enable. bit_offset: 24 bit_size: 1 enum: APB1ENR1_CRSEN - name: USBEN description: CPU1 USB clock enable. bit_offset: 26 bit_size: 1 enum: APB1ENR1_USBEN - name: LPTIM1EN description: CPU1 Low power timer 1 clock enable. bit_offset: 31 bit_size: 1 enum: APB1ENR1_LPTIM1EN fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2. fields: - name: LPUART1EN description: CPU1 Low power UART 1 clock enable. bit_offset: 0 bit_size: 1 enum: APB1ENR2_LPUART1EN - name: LPTIM2EN description: CPU1 LPTIM2EN. bit_offset: 5 bit_size: 1 enum: APB1ENR2_LPTIM2EN fieldset/APB1RSTR1: description: APB1 peripheral reset register 1. fields: - name: TIM2RST description: TIM2 timer reset. bit_offset: 0 bit_size: 1 enum: TIM2RST - name: LCDRST description: LCD interface reset. bit_offset: 9 bit_size: 1 enum: LCDRST - name: SPI2RST description: SPI2 reset. bit_offset: 14 bit_size: 1 enum: SPI2RST - name: I2C1RST description: I2C1 reset. bit_offset: 21 bit_size: 1 enum: I2C1RST - name: I2C3RST description: I2C3 reset. bit_offset: 23 bit_size: 1 enum: I2C3RST - name: CRSRST description: CRS reset. bit_offset: 24 bit_size: 1 enum: CRSRST - name: USBFSRST description: USB FS reset. bit_offset: 26 bit_size: 1 enum: USBFSRST - name: LPTIM1RST description: Low Power Timer 1 reset. bit_offset: 31 bit_size: 1 enum: LPTIM1RST fieldset/APB1RSTR2: description: APB1 peripheral reset register 2. fields: - name: LPUART1RST description: Low-power UART 1 reset. bit_offset: 0 bit_size: 1 enum: LPUART1RST - name: LPTIM2RST description: Low-power timer 2 reset. bit_offset: 5 bit_size: 1 enum: LPTIM2RST fieldset/APB1SMENR1: description: APB1SMENR1. fields: - name: TIM2SMEN description: TIM2 timer clocks enable during CPU1 Sleep mode. bit_offset: 0 bit_size: 1 enum: APB1SMENR1_TIM2SMEN - name: LCDSMEN description: LCD clocks enable during CPU1 Sleep mode. bit_offset: 9 bit_size: 1 enum: APB1SMENR1_LCDSMEN - name: RTCAPBSMEN description: RTC APB clocks enable during CPU1 Sleep mode. bit_offset: 10 bit_size: 1 enum: APB1SMENR1_RTCAPBSMEN - name: WWDGSMEN description: Window watchdog clocks enable during CPU1 Sleep mode. bit_offset: 11 bit_size: 1 enum: WWDGSMEN - name: SPI2SMEN description: SPI2 clocks enable during CPU1 Sleep mode. bit_offset: 14 bit_size: 1 enum: APB1SMENR1_SPI2SMEN - name: I2C1SMEN description: I2C1 clocks enable during CPU1 Sleep mode. bit_offset: 21 bit_size: 1 enum: APB1SMENR1_I2C1SMEN - name: I2C3SMEN description: I2C3 clocks enable during CPU1 Sleep mode. bit_offset: 23 bit_size: 1 enum: APB1SMENR1_I2C3SMEN - name: CRSMEN description: CRS clocks enable during CPU1 Sleep mode. bit_offset: 24 bit_size: 1 enum: APB1SMENR1_CRSMEN - name: USBSMEN description: USB FS clocks enable during CPU1 Sleep mode. bit_offset: 26 bit_size: 1 enum: APB1SMENR1_USBSMEN - name: LPTIM1SMEN description: Low power timer 1 clocks enable during CPU1 Sleep mode. bit_offset: 31 bit_size: 1 enum: APB1SMENR1_LPTIM1SMEN fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep and Stop modes register 2. fields: - name: LPUART1SMEN description: Low power UART 1 clocks enable during CPU1 Sleep mode. bit_offset: 0 bit_size: 1 enum: APB1SMENR2_LPUART1SMEN - name: LPTIM2SMEN description: Low power timer 2 clocks enable during CPU1 Sleep mode. bit_offset: 5 bit_size: 1 enum: APB1SMENR2_LPTIM2SMEN fieldset/APB2ENR: description: APB2ENR. fields: - name: TIM1EN description: CPU1 TIM1 timer clock enable. bit_offset: 11 bit_size: 1 enum: APB2ENR_TIM1EN - name: SPI1EN description: CPU1 SPI1 clock enable. bit_offset: 12 bit_size: 1 enum: APB2ENR_SPI1EN - name: USART1EN description: CPU1 USART1clock enable. bit_offset: 14 bit_size: 1 enum: APB2ENR_USART1EN - name: TIM16EN description: CPU1 TIM16 timer clock enable. bit_offset: 17 bit_size: 1 enum: APB2ENR_TIM16EN - name: TIM17EN description: CPU1 TIM17 timer clock enable. bit_offset: 18 bit_size: 1 enum: APB2ENR_TIM17EN - name: SAI1EN description: CPU1 SAI1 clock enable. bit_offset: 21 bit_size: 1 enum: APB2ENR_SAI1EN fieldset/APB2RSTR: description: APB2 peripheral reset register. fields: - name: TIM1RST description: TIM1 timer reset. bit_offset: 11 bit_size: 1 - name: SPI1RST description: SPI1 reset. bit_offset: 12 bit_size: 1 - name: USART1RST description: USART1 reset. bit_offset: 14 bit_size: 1 - name: TIM16RST description: TIM16 timer reset. bit_offset: 17 bit_size: 1 - name: TIM17RST description: TIM17 timer reset. bit_offset: 18 bit_size: 1 - name: SAI1RST description: Serial audio interface 1 (SAI1) reset. bit_offset: 21 bit_size: 1 fieldset/APB2SMENR: description: APB2SMENR. fields: - name: TIM1SMEN description: TIM1 timer clocks enable during CPU1 Sleep mode. bit_offset: 11 bit_size: 1 - name: SPI1SMEN description: SPI1 clocks enable during CPU1 Sleep mode. bit_offset: 12 bit_size: 1 - name: USART1SMEN description: USART1clocks enable during CPU1 Sleep mode. bit_offset: 14 bit_size: 1 - name: TIM16SMEN description: TIM16 timer clocks enable during CPU1 Sleep mode. bit_offset: 17 bit_size: 1 - name: TIM17SMEN description: TIM17 timer clocks enable during CPU1 Sleep mode. bit_offset: 18 bit_size: 1 - name: SAI1SMEN description: SAI1 clocks enable during CPU1 Sleep mode. bit_offset: 21 bit_size: 1 fieldset/APB3RSTR: description: APB3 peripheral reset register. fields: - name: RFRST description: Radio system BLE reset. bit_offset: 0 bit_size: 1 fieldset/BDCR: description: BDCR. fields: - name: LSEON description: LSE oscillator enable. bit_offset: 0 bit_size: 1 enum: LSEON - name: LSERDY description: LSE oscillator ready. bit_offset: 1 bit_size: 1 enum: LSERDY - name: LSEBYP description: LSE oscillator bypass. bit_offset: 2 bit_size: 1 enum: LSEBYP - name: LSEDRV description: SE oscillator drive capability. bit_offset: 3 bit_size: 2 enum: LSEDRV - name: LSECSSON description: LSECSSON. bit_offset: 5 bit_size: 1 enum: LSECSSON - name: LSECSSD description: CSS on LSE failure detection. bit_offset: 6 bit_size: 1 enum: LSECSSD - name: RTCSEL description: RTC clock source selection. bit_offset: 8 bit_size: 2 enum: RTCSEL - name: RTCEN description: RTC clock enable. bit_offset: 15 bit_size: 1 enum: RTCEN - name: BDRST description: Backup domain software reset. bit_offset: 16 bit_size: 1 enum: BDRST - name: LSCOEN description: Low speed clock output enable. bit_offset: 24 bit_size: 1 enum: LSCOEN - name: LSCOSEL description: Low speed clock output selection. bit_offset: 25 bit_size: 1 enum: LSCOSEL fieldset/C2AHB1ENR: description: CPU2 AHB1 peripheral clock enable register. fields: - name: DMA1EN description: CPU2 DMA1 clock enable. bit_offset: 0 bit_size: 1 enum: C2AHB1ENR_DMA1EN - name: DMA2EN description: CPU2 DMA2 clock enable. bit_offset: 1 bit_size: 1 enum: C2AHB1ENR_DMA2EN - name: DMAMUXEN description: CPU2 DMAMUX clock enable. bit_offset: 2 bit_size: 1 enum: C2AHB1ENR_DMAMUXEN - name: SRAM1EN description: CPU2 SRAM1 clock enable. bit_offset: 9 bit_size: 1 enum: SRAM1EN - name: CRCEN description: CPU2 CRC clock enable. bit_offset: 12 bit_size: 1 enum: C2AHB1ENR_CRCEN - name: TSCEN description: CPU2 Touch Sensing Controller clock enable. bit_offset: 16 bit_size: 1 enum: C2AHB1ENR_TSCEN fieldset/C2AHB1SMENR: description: CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register. fields: - name: DMA1SMEN description: CPU2 DMA1 clocks enable during Sleep and Stop modes. bit_offset: 0 bit_size: 1 enum: DMA1SMEN - name: DMA2SMEN description: CPU2 DMA2 clocks enable during Sleep and Stop modes. bit_offset: 1 bit_size: 1 enum: DMA2SMEN - name: DMAMUXSMEN description: CPU2 DMAMUX clocks enable during Sleep and Stop modes. bit_offset: 2 bit_size: 1 enum: DMAMUXSMEN - name: SRAM1SMEN description: SRAM1 interface clock enable during CPU1 CSleep mode. bit_offset: 9 bit_size: 1 enum: SRAM1SMEN - name: CRCSMEN description: CPU2 CRCSMEN. bit_offset: 12 bit_size: 1 enum: CRCSMEN - name: TSCSMEN description: CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes. bit_offset: 16 bit_size: 1 enum: TSCSMEN fieldset/C2AHB2ENR: description: CPU2 AHB2 peripheral clock enable register. fields: - name: GPIOAEN description: CPU2 IO port A clock enable. bit_offset: 0 bit_size: 1 enum: C2AHB2ENR_GPIOAEN - name: GPIOBEN description: CPU2 IO port B clock enable. bit_offset: 1 bit_size: 1 enum: C2AHB2ENR_GPIOBEN - name: GPIOCEN description: CPU2 IO port C clock enable. bit_offset: 2 bit_size: 1 enum: C2AHB2ENR_GPIOCEN - name: GPIODEN description: CPU2 IO port D clock enable. bit_offset: 3 bit_size: 1 enum: C2AHB2ENR_GPIODEN - name: GPIOEEN description: CPU2 IO port E clock enable. bit_offset: 4 bit_size: 1 enum: C2AHB2ENR_GPIOEEN - name: GPIOHEN description: CPU2 IO port H clock enable. bit_offset: 7 bit_size: 1 enum: C2AHB2ENR_GPIOHEN - name: ADCEN description: CPU2 ADC clock enable. bit_offset: 13 bit_size: 1 enum: C2AHB2ENR_ADCEN - name: AES1EN description: CPU2 AES1 accelerator clock enable. bit_offset: 16 bit_size: 1 enum: C2AHB2ENR_AES1EN fieldset/C2AHB2SMENR: description: CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register. fields: - name: GPIOASMEN description: CPU2 IO port A clocks enable during Sleep and Stop modes. bit_offset: 0 bit_size: 1 enum: GPIOASMEN - name: GPIOBSMEN description: CPU2 IO port B clocks enable during Sleep and Stop modes. bit_offset: 1 bit_size: 1 enum: GPIOBSMEN - name: GPIOCSMEN description: CPU2 IO port C clocks enable during Sleep and Stop modes. bit_offset: 2 bit_size: 1 enum: GPIOCSMEN - name: GPIODSMEN description: CPU2 IO port D clocks enable during Sleep and Stop modes. bit_offset: 3 bit_size: 1 enum: GPIODSMEN - name: GPIOESMEN description: CPU2 IO port E clocks enable during Sleep and Stop modes. bit_offset: 4 bit_size: 1 enum: GPIOESMEN - name: GPIOHSMEN description: CPU2 IO port H clocks enable during Sleep and Stop modes. bit_offset: 7 bit_size: 1 enum: GPIOHSMEN - name: ADCFSSMEN description: CPU2 ADC clocks enable during Sleep and Stop modes. bit_offset: 13 bit_size: 1 enum: ADCFSSMEN - name: AES1SMEN description: CPU2 AES1 accelerator clocks enable during Sleep and Stop modes. bit_offset: 16 bit_size: 1 enum: AES1SMEN fieldset/C2AHB3ENR: description: CPU2 AHB3 peripheral clock enable register. fields: - name: PKAEN description: CPU2 PKAEN. bit_offset: 16 bit_size: 1 enum: C2AHB3ENR_PKAEN - name: AES2EN description: CPU2 AES2EN. bit_offset: 17 bit_size: 1 enum: C2AHB3ENR_AES2EN - name: RNGEN description: CPU2 RNGEN. bit_offset: 18 bit_size: 1 enum: C2AHB3ENR_RNGEN - name: HSEMEN description: CPU2 HSEMEN. bit_offset: 19 bit_size: 1 enum: C2AHB3ENR_HSEMEN - name: IPCCEN description: CPU2 IPCCEN. bit_offset: 20 bit_size: 1 enum: C2AHB3ENR_IPCCEN - name: FLASHEN description: CPU2 FLASHEN. bit_offset: 25 bit_size: 1 enum: C2AHB3ENR_FLASHEN fieldset/C2AHB3SMENR: description: CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register. fields: - name: PKASMEN description: PKA accelerator clocks enable during CPU2 sleep modes. bit_offset: 16 bit_size: 1 enum: PKASMEN - name: AES2SMEN description: AES2 accelerator clocks enable during CPU2 sleep modes. bit_offset: 17 bit_size: 1 enum: AES2SMEN - name: RNGSMEN description: True RNG clocks enable during CPU2 sleep modes. bit_offset: 18 bit_size: 1 enum: RNGSMEN - name: SRAM2SMEN description: SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes. bit_offset: 24 bit_size: 1 enum: SRAM2SMEN - name: FLASHSMEN description: Flash interface clocks enable during CPU2 sleep modes. bit_offset: 25 bit_size: 1 enum: FLASHSMEN fieldset/C2APB1ENR1: description: CPU2 APB1ENR1. fields: - name: TIM2EN description: CPU2 TIM2 timer clock enable. bit_offset: 0 bit_size: 1 enum: C2APB1ENR1_TIM2EN - name: LCDEN description: CPU2 LCD clock enable. bit_offset: 9 bit_size: 1 enum: C2APB1ENR1_LCDEN - name: RTCAPBEN description: CPU2 RTC APB clock enable. bit_offset: 10 bit_size: 1 enum: C2APB1ENR1_RTCAPBEN - name: SPI2EN description: CPU2 SPI2 clock enable. bit_offset: 14 bit_size: 1 enum: C2APB1ENR1_SPI2EN - name: I2C1EN description: CPU2 I2C1 clock enable. bit_offset: 21 bit_size: 1 enum: C2APB1ENR1_I2C1EN - name: I2C3EN description: CPU2 I2C3 clock enable. bit_offset: 23 bit_size: 1 enum: C2APB1ENR1_I2C3EN - name: CRSEN description: CPU2 CRS clock enable. bit_offset: 24 bit_size: 1 enum: C2APB1ENR1_CRSEN - name: USBEN description: CPU2 USB clock enable. bit_offset: 26 bit_size: 1 enum: C2APB1ENR1_USBEN - name: LPTIM1EN description: CPU2 Low power timer 1 clock enable. bit_offset: 31 bit_size: 1 enum: C2APB1ENR1_LPTIM1EN fieldset/C2APB1ENR2: description: CPU2 APB1 peripheral clock enable register 2. fields: - name: LPUART1EN description: CPU2 Low power UART 1 clock enable. bit_offset: 0 bit_size: 1 enum: C2APB1ENR2_LPUART1EN - name: LPTIM2EN description: CPU2 LPTIM2EN. bit_offset: 5 bit_size: 1 enum: C2APB1ENR2_LPTIM2EN fieldset/C2APB1SMENR1: description: CPU2 APB1SMENR1. fields: - name: TIM2SMEN description: TIM2 timer clocks enable during CPU2 Sleep mode. bit_offset: 0 bit_size: 1 enum: C2APB1SMENR1_TIM2SMEN - name: LCDSMEN description: LCD clocks enable during CPU2 Sleep mode. bit_offset: 9 bit_size: 1 enum: C2APB1SMENR1_LCDSMEN - name: RTCAPBSMEN description: RTC APB clocks enable during CPU2 Sleep mode. bit_offset: 10 bit_size: 1 enum: C2APB1SMENR1_RTCAPBSMEN - name: SPI2SMEN description: SPI2 clocks enable during CPU2 Sleep mode. bit_offset: 14 bit_size: 1 enum: C2APB1SMENR1_SPI2SMEN - name: I2C1SMEN description: I2C1 clocks enable during CPU2 Sleep mode. bit_offset: 21 bit_size: 1 enum: C2APB1SMENR1_I2C1SMEN - name: I2C3SMEN description: I2C3 clocks enable during CPU2 Sleep mode. bit_offset: 23 bit_size: 1 enum: C2APB1SMENR1_I2C3SMEN - name: CRSMEN description: CRS clocks enable during CPU2 Sleep mode. bit_offset: 24 bit_size: 1 enum: C2APB1SMENR1_CRSMEN - name: USBSMEN description: USB FS clocks enable during CPU2 Sleep mode. bit_offset: 26 bit_size: 1 enum: C2APB1SMENR1_USBSMEN - name: LPTIM1SMEN description: Low power timer 1 clocks enable during CPU2 Sleep mode. bit_offset: 31 bit_size: 1 enum: C2APB1SMENR1_LPTIM1SMEN fieldset/C2APB1SMENR2: description: CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2. fields: - name: LPUART1SMEN description: Low power UART 1 clocks enable during CPU2 Sleep mode. bit_offset: 0 bit_size: 1 enum: C2APB1SMENR2_LPUART1SMEN - name: LPTIM2SMEN description: Low power timer 2 clocks enable during CPU2 Sleep mode. bit_offset: 5 bit_size: 1 enum: C2APB1SMENR2_LPTIM2SMEN fieldset/C2APB2ENR: description: CPU2 APB2ENR. fields: - name: TIM1EN description: CPU2 TIM1 timer clock enable. bit_offset: 11 bit_size: 1 enum: C2APB2ENR_TIM1EN - name: SPI1EN description: CPU2 SPI1 clock enable. bit_offset: 12 bit_size: 1 enum: C2APB2ENR_SPI1EN - name: USART1EN description: CPU2 USART1clock enable. bit_offset: 14 bit_size: 1 enum: C2APB2ENR_USART1EN - name: TIM16EN description: CPU2 TIM16 timer clock enable. bit_offset: 17 bit_size: 1 enum: C2APB2ENR_TIM16EN - name: TIM17EN description: CPU2 TIM17 timer clock enable. bit_offset: 18 bit_size: 1 enum: C2APB2ENR_TIM17EN - name: SAI1EN description: CPU2 SAI1 clock enable. bit_offset: 21 bit_size: 1 enum: C2APB2ENR_SAI1EN fieldset/C2APB2SMENR: description: CPU2 APB2SMENR. fields: - name: TIM1SMEN description: TIM1 timer clocks enable during CPU2 Sleep mode. bit_offset: 11 bit_size: 1 enum: TIM1SMEN - name: SPI1SMEN description: SPI1 clocks enable during CPU2 Sleep mode. bit_offset: 12 bit_size: 1 enum: SPI1SMEN - name: USART1SMEN description: USART1clocks enable during CPU2 Sleep mode. bit_offset: 14 bit_size: 1 enum: USART1SMEN - name: TIM16SMEN description: TIM16 timer clocks enable during CPU2 Sleep mode. bit_offset: 17 bit_size: 1 enum: TIM16SMEN - name: TIM17SMEN description: TIM17 timer clocks enable during CPU2 Sleep mode. bit_offset: 18 bit_size: 1 enum: TIM17SMEN - name: SAI1SMEN description: SAI1 clocks enable during CPU2 Sleep mode. bit_offset: 21 bit_size: 1 enum: SAI1SMEN fieldset/C2APB3ENR: description: CPU2 APB3ENR. fields: - name: BLEEN description: CPU2 BLE interface clock enable. bit_offset: 0 bit_size: 1 enum: BLEEN - name: EN802 description: CPU2 802.15.4 interface clock enable. bit_offset: 1 bit_size: 1 enum: EN802 fieldset/C2APB3SMENR: description: CPU2 APB3SMENR. fields: - name: BLESMEN description: BLE interface clocks enable during CPU2 Sleep mode. bit_offset: 0 bit_size: 1 enum: BLESMEN - name: SMEN802 description: 802.15.4 interface clocks enable during CPU2 Sleep modes. bit_offset: 1 bit_size: 1 enum: SMEN802 fieldset/CCIPR: description: CCIPR. fields: - name: USART1SEL description: USART1 clock source selection. bit_offset: 0 bit_size: 2 enum: USART1SEL - name: LPUART1SEL description: LPUART1 clock source selection. bit_offset: 10 bit_size: 2 enum: LPUART1SEL - name: I2C1SEL description: I2C1 clock source selection. bit_offset: 12 bit_size: 2 enum: I2C1SEL - name: I2C3SEL description: I2C3 clock source selection. bit_offset: 16 bit_size: 2 enum: I2C3SEL - name: LPTIM1SEL description: Low power timer 1 clock source selection. bit_offset: 18 bit_size: 2 enum: LPTIM1SEL - name: LPTIM2SEL description: Low power timer 2 clock source selection. bit_offset: 20 bit_size: 2 enum: LPTIM2SEL - name: SAI1SEL description: SAI1 clock source selection. bit_offset: 22 bit_size: 2 enum: SAI1SEL - name: CLK48SEL description: 48 MHz clock source selection. bit_offset: 26 bit_size: 2 enum: CLK48SEL - name: ADCSEL description: ADCs clock source selection. bit_offset: 28 bit_size: 2 enum: ADCSEL - name: RNGSEL description: RNG clock source selection. bit_offset: 30 bit_size: 2 enum: RNGSEL fieldset/CFGR: description: Clock configuration register. fields: - name: SW description: System clock switch. bit_offset: 0 bit_size: 2 enum: SW - name: SWS description: System clock switch status. bit_offset: 2 bit_size: 2 enum: SWS - name: HPRE description: AHB prescaler. bit_offset: 4 bit_size: 4 enum: HPRE - name: PPRE1 description: PB low-speed prescaler (APB1). bit_offset: 8 bit_size: 3 enum: PPRE1 - name: PPRE2 description: APB high-speed prescaler (APB2). bit_offset: 11 bit_size: 3 enum: PPRE2 - name: STOPWUCK description: Wakeup from Stop and CSS backup clock selection. bit_offset: 15 bit_size: 1 enum: STOPWUCK - name: HPREF description: AHB prescaler flag. bit_offset: 16 bit_size: 1 enum: HPREF - name: PPRE1F description: APB1 prescaler flag. bit_offset: 17 bit_size: 1 enum: PPRE1F - name: PPRE2F description: APB2 prescaler flag. bit_offset: 18 bit_size: 1 enum: PPRE2F - name: MCOSEL description: Microcontroller clock output. bit_offset: 24 bit_size: 4 enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler. bit_offset: 28 bit_size: 3 enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register. fields: - name: LSI1RDYC description: LSI1 ready interrupt clear. bit_offset: 0 bit_size: 1 enum: LSI1RDYC - name: LSERDYC description: LSE ready interrupt clear. bit_offset: 1 bit_size: 1 enum: LSERDYC - name: MSIRDYC description: MSI ready interrupt clear. bit_offset: 2 bit_size: 1 enum: MSIRDYC - name: HSIRDYC description: HSI ready interrupt clear. bit_offset: 3 bit_size: 1 enum: HSIRDYC - name: HSERDYC description: HSE ready interrupt clear. bit_offset: 4 bit_size: 1 enum: HSERDYC - name: PLLRDYC description: PLL ready interrupt clear. bit_offset: 5 bit_size: 1 enum: PLLRDYC - name: PLLSAI1RDYC description: PLLSAI1 ready interrupt clear. bit_offset: 6 bit_size: 1 enum: PLLSAI1RDYC - name: CSSC description: HSE Clock security system interrupt clear. bit_offset: 8 bit_size: 1 enum: CSSC - name: LSECSSC description: LSE Clock security system interrupt clear. bit_offset: 9 bit_size: 1 enum: LSECSSC - name: HSI48RDYC description: HSI48 ready interrupt clear. bit_offset: 10 bit_size: 1 enum: HSI48RDYC - name: LSI2RDYC description: LSI2 ready interrupt clear. bit_offset: 11 bit_size: 1 enum: LSI2RDYC fieldset/CIER: description: Clock interrupt enable register. fields: - name: LSI1RDYIE description: LSI1 ready interrupt enable. bit_offset: 0 bit_size: 1 enum: LSI1RDYIE - name: LSERDYIE description: LSE ready interrupt enable. bit_offset: 1 bit_size: 1 enum: LSERDYIE - name: MSIRDYIE description: MSI ready interrupt enable. bit_offset: 2 bit_size: 1 enum: MSIRDYIE - name: HSIRDYIE description: HSI ready interrupt enable. bit_offset: 3 bit_size: 1 enum: HSIRDYIE - name: HSERDYIE description: HSE ready interrupt enable. bit_offset: 4 bit_size: 1 enum: HSERDYIE - name: PLLRDYIE description: PLLSYS ready interrupt enable. bit_offset: 5 bit_size: 1 enum: PLLRDYIE - name: PLLSAI1RDYIE description: PLLSAI1 ready interrupt enable. bit_offset: 6 bit_size: 1 enum: PLLSAI1RDYIE - name: LSECSSIE description: LSE clock security system interrupt enable. bit_offset: 9 bit_size: 1 enum: LSECSSIE - name: HSI48RDYIE description: HSI48 ready interrupt enable. bit_offset: 10 bit_size: 1 enum: HSI48RDYIE - name: LSI2RDYIE description: LSI2 ready interrupt enable. bit_offset: 11 bit_size: 1 enum: LSI2RDYIE fieldset/CIFR: description: Clock interrupt flag register. fields: - name: LSI1RDYF description: LSI1 ready interrupt flag. bit_offset: 0 bit_size: 1 enum: LSI1RDYF - name: LSERDYF description: LSE ready interrupt flag. bit_offset: 1 bit_size: 1 enum: LSERDYF - name: MSIRDYF description: MSI ready interrupt flag. bit_offset: 2 bit_size: 1 enum: MSIRDYF - name: HSIRDYF description: HSI ready interrupt flag. bit_offset: 3 bit_size: 1 enum: HSIRDYF - name: HSERDYF description: HSE ready interrupt flag. bit_offset: 4 bit_size: 1 enum: HSERDYF - name: PLLRDYF description: PLL ready interrupt flag. bit_offset: 5 bit_size: 1 enum: PLLRDYF - name: PLLSAI1RDYF description: PLLSAI1 ready interrupt flag. bit_offset: 6 bit_size: 1 enum: PLLSAI1RDYF - name: CSSF description: HSE Clock security system interrupt flag. bit_offset: 8 bit_size: 1 enum: CSSF - name: LSECSSF description: LSE Clock security system interrupt flag. bit_offset: 9 bit_size: 1 enum: LSECSSF - name: HSI48RDYF description: HSI48 ready interrupt flag. bit_offset: 10 bit_size: 1 enum: HSI48RDYF - name: LSI2RDYF description: LSI2 ready interrupt flag. bit_offset: 11 bit_size: 1 enum: LSI2RDYF fieldset/CR: description: Clock control register. fields: - name: MSION description: MSI clock enable. bit_offset: 0 bit_size: 1 enum: MSION - name: MSIRDY description: MSI clock ready flag. bit_offset: 1 bit_size: 1 enum: MSIRDY - name: MSIPLLEN description: MSI clock PLL enable. bit_offset: 2 bit_size: 1 enum: MSIPLLEN - name: MSIRANGE description: MSI clock ranges. bit_offset: 4 bit_size: 4 enum: MSIRANGE - name: HSION description: HSI clock enabled. bit_offset: 8 bit_size: 1 enum: HSION - name: HSIKERON description: HSI always enable for peripheral kernels. bit_offset: 9 bit_size: 1 enum: HSIKERON - name: HSIRDY description: HSI clock ready flag. bit_offset: 10 bit_size: 1 enum: HSIRDY - name: HSIASFS description: HSI automatic start from Stop. bit_offset: 11 bit_size: 1 enum: HSIASFS - name: HSIKERDY description: HSI kernel clock ready flag for peripherals requests. bit_offset: 12 bit_size: 1 enum: HSIKERDY - name: HSEON description: HSE clock enabled. bit_offset: 16 bit_size: 1 enum: HSEON - name: HSERDY description: HSE clock ready flag. bit_offset: 17 bit_size: 1 enum: HSERDY - name: HSEBYP description: HSE crystal oscillator bypass. bit_offset: 18 bit_size: 1 - name: CSSON description: HSE Clock security system enable. bit_offset: 19 bit_size: 1 enum: CSSON - name: HSEPRE description: HSE sysclk and PLL M divider prescaler. bit_offset: 20 bit_size: 1 enum: HSEPRE - name: PLLON description: Main PLL enable. bit_offset: 24 bit_size: 1 enum: PLLON - name: PLLRDY description: Main PLL clock ready flag. bit_offset: 25 bit_size: 1 enum: PLLRDY - name: PLLSAI1ON description: SAI1 PLL enable. bit_offset: 26 bit_size: 1 enum: PLLSAI1ON - name: PLLSAI1RDY description: SAI1 PLL clock ready flag. bit_offset: 27 bit_size: 1 enum: PLLSAI1RDY fieldset/CRRCR: description: Clock recovery RC register. fields: - name: HSI48ON description: HSI48 oscillator enabled. bit_offset: 0 bit_size: 1 enum: HSI48ON - name: HSI48RDY description: HSI48 clock ready. bit_offset: 1 bit_size: 1 enum: HSI48RDY - name: HSI48CAL description: HSI48 clock calibration. bit_offset: 7 bit_size: 9 fieldset/CSR: description: CSR. fields: - name: LSI1ON description: LSI1 oscillator enabled. bit_offset: 0 bit_size: 1 enum: LSI1ON - name: LSI1RDY description: LSI1 oscillator ready. bit_offset: 1 bit_size: 1 enum: LSI1RDY - name: LSI2ON description: LSI2 oscillator enabled. bit_offset: 2 bit_size: 1 enum: LSI2ON - name: LSI2RDY description: LSI2 oscillator ready. bit_offset: 3 bit_size: 1 enum: LSI2RDY - name: LSI2TRIMEN description: LSI2 oscillator trimming enable. bit_offset: 4 bit_size: 1 - name: LSI2TRIMOK description: LSI2 oscillator trim OK. bit_offset: 5 bit_size: 1 - name: LSI2BW description: LSI2 oscillator bias configuration. bit_offset: 8 bit_size: 4 - name: RFWKPSEL description: RF system wakeup clock source selection. bit_offset: 14 bit_size: 2 enum: RFWKPSEL - name: RFRSTS description: Radio system BLE and 802.15.4 reset status. bit_offset: 16 bit_size: 1 enum: RFRSTS - name: RMVF description: Remove reset flag. bit_offset: 23 bit_size: 1 enum: RMVF - name: OBLRSTF description: Option byte loader reset flag. bit_offset: 25 bit_size: 1 enum: OBLRSTF - name: PINRSTF description: Pin reset flag. bit_offset: 26 bit_size: 1 enum: PINRSTF - name: BORRSTF description: BOR flag. bit_offset: 27 bit_size: 1 enum: BORRSTF - name: SFTRSTF description: Software reset flag. bit_offset: 28 bit_size: 1 enum: SFTRSTF - name: IWDGRSTF description: Independent window watchdog reset flag. bit_offset: 29 bit_size: 1 enum: IWDGRSTF - name: WWDGRSTF description: Window watchdog reset flag. bit_offset: 30 bit_size: 1 enum: WWDGRSTF - name: LPWRRSTF description: Low-power reset flag. bit_offset: 31 bit_size: 1 enum: LPWRRSTF fieldset/EXTCFGR: description: Extended clock recovery register. fields: - name: SHDHPRE description: Shared AHB prescaler. bit_offset: 0 bit_size: 4 enum: SHDHPRE - name: C2HPRE description: CPU2 AHB prescaler. bit_offset: 4 bit_size: 4 enum: C2HPRE - name: SHDHPREF description: Shared AHB prescaler flag. bit_offset: 16 bit_size: 1 enum: SHDHPREF - name: C2HPREF description: CPU2 AHB prescaler flag. bit_offset: 17 bit_size: 1 enum: C2HPREF - name: RFCSS description: RF clock source selected. bit_offset: 20 bit_size: 1 enum: RFCSS fieldset/HSECR: description: Clock HSE register. fields: - name: UNLOCKED description: Register lock system. bit_offset: 0 bit_size: 1 - name: HSES description: HSE Sense amplifier threshold. bit_offset: 3 bit_size: 1 enum: HSES - name: HSEGMC description: HSE current control. bit_offset: 4 bit_size: 3 enum: HSEGMC - name: HSETUNE description: HSE capacitor tuning. bit_offset: 8 bit_size: 6 fieldset/HSECR_KEY: fields: - name: KEY bit_offset: 0 bit_size: 32 enum: KEY fieldset/ICSCR: description: Internal clock sources calibration register. fields: - name: MSICAL description: MSI clock calibration. bit_offset: 0 bit_size: 8 - name: MSITRIM description: MSI clock trimming. bit_offset: 8 bit_size: 8 - name: HSICAL description: HSI clock calibration. bit_offset: 16 bit_size: 8 - name: HSITRIM description: HSI clock trimming. bit_offset: 24 bit_size: 7 fieldset/PLLCFGR: description: PLLSYS configuration register. fields: - name: PLLSRC description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source. bit_offset: 0 bit_size: 2 enum: PLLSRC - name: PLLM description: Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock. bit_offset: 4 bit_size: 3 enum: PLLM - name: PLLN description: Main PLLSYS multiplication factor N. bit_offset: 8 bit_size: 7 - name: PLLPEN description: Main PLLSYSP output enable. bit_offset: 16 bit_size: 1 enum: PLLCFGR_PLLPEN - name: PLLP description: Main PLL division factor P for PPLSYSSAICLK. bit_offset: 17 bit_size: 5 enum: PLLCFGR_PLLP - name: PLLQEN description: Main PLLSYSQ output enable. bit_offset: 24 bit_size: 1 enum: PLLCFGR_PLLQEN - name: PLLQ description: Main PLLSYS division factor Q for PLLSYSUSBCLK. bit_offset: 25 bit_size: 3 enum: PLLCFGR_PLLQ - name: PLLREN description: Main PLLSYSR PLLCLK output enable. bit_offset: 28 bit_size: 1 enum: PLLCFGR_PLLREN - name: PLLR description: Main PLLSYS division factor R for SYSCLK (system clock). bit_offset: 29 bit_size: 3 enum: PLLCFGR_PLLR fieldset/PLLSAI1CFGR: description: PLLSAI1 configuration register. fields: - name: PLLN description: SAIPLL multiplication factor for VCO. bit_offset: 8 bit_size: 7 - name: PLLPEN description: SAIPLL PLLSAI1CLK output enable. bit_offset: 16 bit_size: 1 enum: PLLSAI1CFGR_PLLPEN - name: PLLP description: SAI1PLL division factor P for PLLSAICLK (SAI1clock). bit_offset: 17 bit_size: 5 enum: PLLSAI1CFGR_PLLP - name: PLLQEN description: SAIPLL PLLSAIUSBCLK output enable. bit_offset: 24 bit_size: 1 enum: PLLSAI1CFGR_PLLQEN - name: PLLQ description: SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock). bit_offset: 25 bit_size: 3 enum: PLLSAI1CFGR_PLLQ - name: PLLREN description: PLLSAI PLLADC1CLK output enable. bit_offset: 28 bit_size: 1 enum: PLLSAI1CFGR_PLLREN - name: PLLR description: PLLSAI division factor R for PLLADC1CLK (ADC clock). bit_offset: 29 bit_size: 3 enum: PLLSAI1CFGR_PLLR fieldset/SMPSCR: description: Step Down converter control register. fields: - name: SMPSSEL description: Step Down converter clock selection. bit_offset: 0 bit_size: 2 enum: SMPSSEL - name: SMPSDIV description: Step Down converter clock prescaler. bit_offset: 4 bit_size: 2 - name: SMPSSWS description: Step Down converter clock switch status. bit_offset: 8 bit_size: 2 enum: SMPSSWS enum/ADCFSSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/ADCRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/ADCSEL: bit_size: 2 variants: - name: NoClock description: No clock selected. value: 0 - name: PLLSAI1 description: PLLSAI1R clock selected. value: 1 - name: PLL description: PLLP clock selected. value: 2 - name: SYSCLK description: SYSCLK clock selected. value: 3 enum/AES1RST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/AES1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AES2RST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/AES2SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB1ENR_CRCEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB1ENR_DMA1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB1ENR_DMA2EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB1ENR_DMAMUXEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB1ENR_TSCEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB2ENR_ADCEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB2ENR_AES1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB2ENR_GPIOAEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB2ENR_GPIOBEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB2ENR_GPIOCEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB2ENR_GPIODEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB2ENR_GPIOEEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB2ENR_GPIOHEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB3ENR_AES2EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB3ENR_FLASHEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB3ENR_HSEMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB3ENR_IPCCEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB3ENR_PKAEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/AHB3ENR_RNGEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1ENR1_CRSEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1ENR1_I2C1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1ENR1_I2C3EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1ENR1_LCDEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1ENR1_LPTIM1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1ENR1_RTCAPBEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1ENR1_SPI2EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1ENR1_TIM2EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1ENR1_USBEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1ENR2_LPTIM2EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1ENR2_LPUART1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1SMENR1_CRSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1SMENR1_I2C1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1SMENR1_I2C3SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1SMENR1_LCDSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1SMENR1_LPTIM1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1SMENR1_RTCAPBSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1SMENR1_SPI2SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1SMENR1_TIM2SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1SMENR1_USBSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1SMENR2_LPTIM2SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB1SMENR2_LPUART1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB2ENR_SAI1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB2ENR_SPI1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB2ENR_TIM16EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB2ENR_TIM17EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB2ENR_TIM1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/APB2ENR_USART1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/BDRST: bit_size: 1 variants: - name: NotActive description: Reset not activated. value: 0 - name: Reset description: Entire Backup domain reset. value: 1 enum/BLEEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/BLESMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/BORRSTF: bit_size: 1 variants: - name: NoReset description: No reset occurred. value: 0 - name: Reset description: Reset occurred. value: 1 enum/C2AHB1ENR_CRCEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB1ENR_DMA1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB1ENR_DMA2EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB1ENR_DMAMUXEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB1ENR_TSCEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB2ENR_ADCEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB2ENR_AES1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB2ENR_GPIOAEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB2ENR_GPIOBEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB2ENR_GPIOCEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB2ENR_GPIODEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB2ENR_GPIOEEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB2ENR_GPIOHEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB3ENR_AES2EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB3ENR_FLASHEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB3ENR_HSEMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB3ENR_IPCCEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB3ENR_PKAEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2AHB3ENR_RNGEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1ENR1_CRSEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1ENR1_I2C1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1ENR1_I2C3EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1ENR1_LCDEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1ENR1_LPTIM1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1ENR1_RTCAPBEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1ENR1_SPI2EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1ENR1_TIM2EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1ENR1_USBEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1ENR2_LPTIM2EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1ENR2_LPUART1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1SMENR1_CRSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1SMENR1_I2C1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1SMENR1_I2C3SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1SMENR1_LCDSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1SMENR1_LPTIM1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1SMENR1_RTCAPBSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1SMENR1_SPI2SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1SMENR1_TIM2SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1SMENR1_USBSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1SMENR2_LPTIM2SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB1SMENR2_LPUART1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB2ENR_SAI1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB2ENR_SPI1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB2ENR_TIM16EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB2ENR_TIM17EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB2ENR_TIM1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2APB2ENR_USART1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/C2HPRE: bit_size: 4 variants: - name: Div1 description: SYSCLK not divided. value: 0 - name: Div3 description: SYSCLK divided by 3. value: 1 - name: Div5 description: SYSCLK divided by 5. value: 2 - name: Div6 description: SYSCLK divided by 6. value: 5 - name: Div10 description: SYSCLK divided by 10. value: 6 - name: Div32 description: SYSCLK divided by 32. value: 7 - name: Div2 description: SYSCLK divided by 2. value: 8 - name: Div4 description: SYSCLK divided by 4. value: 9 - name: Div8 description: SYSCLK divided by 8. value: 10 - name: Div16 description: SYSCLK divided by 16. value: 11 - name: Div64 description: SYSCLK divided by 64. value: 12 - name: Div128 description: SYSCLK divided by 128. value: 13 - name: Div256 description: SYSCLK divided by 256. value: 14 - name: Div512 description: SYSCLK divided by 512. value: 15 enum/C2HPREF: bit_size: 1 variants: - name: NotApplied description: HCLK2 prescaler value not yet applied. value: 0 - name: Applied description: HCLK2 prescaler value applied. value: 1 enum/CLK48SEL: bit_size: 2 variants: - name: HSI48 description: HSI48 clock selected. value: 0 - name: PLLSAI1 description: PLLSAI1Q clock selected. value: 1 - name: PLL description: PLLQ clock selected. value: 2 - name: MSI description: MSI clock selected. value: 3 enum/CRCRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/CRCSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/CRSRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/CSSC: bit_size: 1 variants: - name: Clear description: Clear interrupt flag. value: 1 enum/CSSF: bit_size: 1 variants: - name: NotInterrupted description: Not interrupted. value: 0 - name: Interrupted description: Interrupted. value: 1 enum/CSSON: bit_size: 1 variants: - name: Disabled description: HSE32 CSS off. value: 0 - name: Enabled description: HSE32 CSS on if the HSE32 oscillator is stable and off if not. value: 1 enum/DMA1RST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/DMA1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/DMA2RST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/DMA2SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/DMAMUXRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/DMAMUXSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/EN802: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/FLASHRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/FLASHSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/GPIOARST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/GPIOASMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/GPIOBRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/GPIOBSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/GPIOCRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/GPIOCSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/GPIODRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/GPIODSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/GPIOERST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/GPIOESMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/GPIOHRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/GPIOHSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/HPRE: bit_size: 4 variants: - name: Div3 description: SYSCLK divided by 3. value: 1 - name: Div5 description: SYSCLK divided by 5. value: 2 - name: Div6 description: SYSCLK divided by 6. value: 5 - name: Div10 description: SYSCLK divided by 10. value: 6 - name: Div32 description: SYSCLK divided by 32. value: 7 - name: Div2 description: SYSCLK divided by 2. value: 8 - name: Div4 description: SYSCLK divided by 4. value: 9 - name: Div8 description: SYSCLK divided by 8. value: 10 - name: Div16 description: SYSCLK divided by 16. value: 11 - name: Div64 description: SYSCLK divided by 64. value: 12 - name: Div128 description: SYSCLK divided by 128. value: 13 - name: Div256 description: SYSCLK divided by 256. value: 14 - name: Div512 description: SYSCLK divided by 512. value: 15 enum/HPREF: bit_size: 1 variants: - name: NotApplied description: HCLK1 prescaler value not yet applied. value: 0 - name: Applied description: HCLK1 prescaler value applied. value: 1 enum/HSEGMC: bit_size: 3 variants: - name: Max0_18 description: Current max limit 0.18 mA/V. value: 0 - name: Max0_57 description: Current max limit 0.57 mA/V. value: 1 - name: Max0_78 description: Current max limit 0.78 mA/V. value: 2 - name: Max1_13 description: Current max limit 1.13 mA/V. value: 3 - name: Max0_61 description: Current max limit 0.61 mA/V. value: 4 - name: Max1_65 description: Current max limit 1.65 mA/V. value: 5 - name: Max2_12 description: Current max limit 2.12 mA/V. value: 6 - name: Max2_84 description: Current max limit 2.84 mA/V. value: 7 enum/HSEMRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/HSEON: bit_size: 1 variants: - name: Disabled description: HSE32 oscillator for CPU disabled. value: 0 - name: Enabled description: HSE32 oscillator for CPU enabled. value: 1 enum/HSEPRE: bit_size: 1 variants: - name: Div1 description: SYSCLK not divided (HSE32). value: 0 - name: Div2 description: SYSCLK divided by two (HSE32/2). value: 1 enum/HSERDY: bit_size: 1 variants: - name: NotReady description: HSE32 oscillator not ready. value: 0 - name: Ready description: HSE32 oscillator ready. value: 1 enum/HSERDYC: bit_size: 1 variants: - name: Clear description: Clear interrupt flag. value: 1 enum/HSERDYF: bit_size: 1 variants: - name: NotInterrupted description: Not interrupted. value: 0 - name: Interrupted description: Interrupted. value: 1 enum/HSERDYIE: bit_size: 1 variants: - name: Disabled description: Interrupt disabled. value: 0 - name: Enabled description: Interrupt enabled. value: 1 enum/HSES: bit_size: 1 variants: - name: OneHalf description: HSE bias current factor 1/2. value: 0 - name: ThreeQuarter description: HSE bias current factor 3/4. value: 1 enum/HSI48ON: bit_size: 1 variants: - name: Off description: HSI48 oscillator off. value: 0 - name: On description: HSI48 oscillator on. value: 1 enum/HSI48RDY: bit_size: 1 variants: - name: NotReady description: HSI48 oscillator not ready. value: 0 - name: Ready description: HSI48 oscillator ready. value: 1 enum/HSI48RDYC: bit_size: 1 variants: - name: Clear description: Clear interrupt flag. value: 1 enum/HSI48RDYF: bit_size: 1 variants: - name: NotInterrupted description: Not interrupted. value: 0 - name: Interrupted description: Interrupted. value: 1 enum/HSI48RDYIE: bit_size: 1 variants: - name: Disabled description: Interrupt disabled. value: 0 - name: Enabled description: Interrupt enabled. value: 1 enum/HSIASFS: bit_size: 1 variants: - name: Disabled description: HSI16 not enabled by hardware when exiting Stop modes with MSI as wakeup clock. value: 0 - name: Enabled description: HSI16 enabled by hardware when exiting Stop mode with MSI as wakeup clock. value: 1 enum/HSIKERDY: bit_size: 1 variants: - name: NotReady description: HSI16 oscillator not ready. value: 0 - name: Ready description: HSI16 oscillator ready. value: 1 enum/HSIKERON: bit_size: 1 variants: - name: NotForced description: No effect on HSI16 oscillator. value: 0 - name: Forced description: HSI16 oscillator forced on even in Stop modes. value: 1 enum/HSION: bit_size: 1 variants: - name: Disabled description: HSI16 oscillator off. value: 0 - name: Enabled description: HSI16 oscillator on. value: 1 enum/HSIRDY: bit_size: 1 variants: - name: NotReady description: HSI16 oscillator not ready. value: 0 - name: Ready description: HSI16 oscillator ready. value: 1 enum/HSIRDYC: bit_size: 1 variants: - name: Clear description: Clear interrupt flag. value: 1 enum/HSIRDYF: bit_size: 1 variants: - name: NotInterrupted description: Not interrupted. value: 0 - name: Interrupted description: Interrupted. value: 1 enum/HSIRDYIE: bit_size: 1 variants: - name: Disabled description: Interrupt disabled. value: 0 - name: Enabled description: Interrupt enabled. value: 1 enum/I2C1RST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/I2C1SEL: bit_size: 2 variants: - name: PCLK description: PCLK clock selected. value: 0 - name: SYSCLK description: SYSCLK clock selected. value: 1 - name: HSI16 description: HSI16 clock selected. value: 2 enum/I2C3RST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/I2C3SEL: bit_size: 2 variants: - name: PCLK description: PCLK clock selected. value: 0 - name: SYSCLK description: SYSCLK clock selected. value: 1 - name: HSI16 description: HSI16 clock selected. value: 2 enum/IPCCRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/IWDGRSTF: bit_size: 1 variants: - name: NoReset description: No reset occurred. value: 0 - name: Reset description: Reset occurred. value: 1 enum/KEY: bit_size: 32 variants: - name: Unlock description: Write enable key. value: 3405695742 enum/LCDRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/LPTIM1RST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/LPTIM1SEL: bit_size: 2 variants: - name: PCLK description: PCLK clock selected. value: 0 - name: LSI description: LSI clock selected. value: 1 - name: HSI16 description: HSI16 clock selected. value: 2 - name: LSE description: LSE clock selected. value: 3 enum/LPTIM2RST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/LPTIM2SEL: bit_size: 2 variants: - name: PCLK description: PCLK clock selected. value: 0 - name: LSI description: LSI clock selected. value: 1 - name: HSI16 description: HSI16 clock selected. value: 2 - name: LSE description: LSE clock selected. value: 3 enum/LPUART1RST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/LPUART1SEL: bit_size: 2 variants: - name: PCLK description: PCLK clock selected. value: 0 - name: SYSCLK description: SYSCLK clock selected. value: 1 - name: HSI16 description: HSI16 clock selected. value: 2 - name: LSE description: LSE clock selected. value: 3 enum/LPWRRSTF: bit_size: 1 variants: - name: NoReset description: No reset occurred. value: 0 - name: Reset description: Reset occurred. value: 1 enum/LSCOEN: bit_size: 1 variants: - name: Disabled description: LSCO disabled. value: 0 - name: Enabled description: LSCO enabled. value: 1 enum/LSCOSEL: bit_size: 1 variants: - name: LSI description: LSI clock selected. value: 0 - name: LSE description: LSE clock selected. value: 1 enum/LSEBYP: bit_size: 1 variants: - name: Disabled description: LSE oscillator not bypassed. value: 0 - name: Enabled description: LSE oscillator bypassed. value: 1 enum/LSECSSC: bit_size: 1 variants: - name: Clear description: Clear interrupt flag. value: 1 enum/LSECSSD: bit_size: 1 variants: - name: NoFailure description: No failure detected on LSE. value: 0 - name: Failure description: Failure detected on LSE. value: 1 enum/LSECSSF: bit_size: 1 variants: - name: NotInterrupted description: Not interrupted. value: 0 - name: Interrupted description: Interrupted. value: 1 enum/LSECSSIE: bit_size: 1 variants: - name: Disabled description: Interrupt disabled. value: 0 - name: Enabled description: Interrupt enabled. value: 1 enum/LSECSSON: bit_size: 1 variants: - name: Disabled description: CSS on LSE disabled. value: 0 - name: Enabled description: CSS on LSE enabled. value: 1 enum/LSEDRV: bit_size: 2 variants: - name: Low description: Xtal mode lower driving capability. value: 0 - name: MedLow description: Xtal mode medium-low driving capability. value: 1 - name: MedHigh description: Xtal mode medium-high driving capability. value: 2 - name: High description: Xtal mode higher driving capability. value: 3 enum/LSEON: bit_size: 1 variants: - name: Off description: LSE oscillator off. value: 0 - name: On description: LSE oscillator on. value: 1 enum/LSERDY: bit_size: 1 variants: - name: NotReady description: LSE oscillator not ready. value: 0 - name: Ready description: LSE oscillator ready. value: 1 enum/LSERDYC: bit_size: 1 variants: - name: Clear description: Clear interrupt flag. value: 1 enum/LSERDYF: bit_size: 1 variants: - name: NotInterrupted description: Not interrupted. value: 0 - name: Interrupted description: Interrupted. value: 1 enum/LSERDYIE: bit_size: 1 variants: - name: Disabled description: Interrupt disabled. value: 0 - name: Enabled description: Interrupt enabled. value: 1 enum/LSI1ON: bit_size: 1 variants: - name: Off description: LSI oscillator off. value: 0 - name: On description: LSI oscillator on. value: 1 enum/LSI1RDY: bit_size: 1 variants: - name: NotReady description: LSI oscillator not ready. value: 0 - name: Ready description: LSI oscillator ready. value: 1 enum/LSI1RDYC: bit_size: 1 variants: - name: Clear description: Clear interrupt flag. value: 1 enum/LSI1RDYF: bit_size: 1 variants: - name: NotInterrupted description: Not interrupted. value: 0 - name: Interrupted description: Interrupted. value: 1 enum/LSI1RDYIE: bit_size: 1 variants: - name: Disabled description: Interrupt disabled. value: 0 - name: Enabled description: Interrupt enabled. value: 1 enum/LSI2ON: bit_size: 1 variants: - name: Off description: LSI oscillator off. value: 0 - name: On description: LSI oscillator on. value: 1 enum/LSI2RDY: bit_size: 1 variants: - name: NotReady description: LSI oscillator not ready. value: 0 - name: Ready description: LSI oscillator ready. value: 1 enum/LSI2RDYC: bit_size: 1 variants: - name: Clear description: Clear interrupt flag. value: 1 enum/LSI2RDYF: bit_size: 1 variants: - name: NotInterrupted description: Not interrupted. value: 0 - name: Interrupted description: Interrupted. value: 1 enum/LSI2RDYIE: bit_size: 1 variants: - name: Disabled description: Interrupt disabled. value: 0 - name: Enabled description: Interrupt enabled. value: 1 enum/MCOPRE: bit_size: 3 variants: - name: Div1 description: No division. value: 0 - name: Div2 description: Division by 2. value: 1 - name: Div4 description: Division by 4. value: 2 - name: Div8 description: Division by 8. value: 3 - name: Div16 description: Division by 16. value: 4 enum/MCOSEL: bit_size: 4 variants: - name: NoClock description: No clock. value: 0 - name: SYSCLK description: SYSCLK clock selected. value: 1 - name: MSI description: MSI oscillator clock selected. value: 2 - name: HSI16 description: HSI16 oscillator clock selected. value: 3 - name: HSE32 description: HSE32 oscillator clock selected. value: 4 - name: PLLR description: Main PLLRCLK clock selected. value: 5 - name: LSI description: LSI oscillator clock selected. value: 6 - name: LSE description: LSE oscillator clock selected. value: 8 - name: PLLP description: Main PLLPCLK clock selected. value: 13 - name: PLLQ description: Main PLLQCLK clock selected. value: 14 enum/MSION: bit_size: 1 variants: - name: Disabled description: MSI oscillator off. value: 0 - name: Enabled description: MSI oscillator on. value: 1 enum/MSIPLLEN: bit_size: 1 variants: - name: Off description: MSI PLL Off. value: 0 - name: On description: MSI PLL On. value: 1 enum/MSIRANGE: bit_size: 4 variants: - name: Range100K description: range 0 around 100 kHz. value: 0 - name: Range200K description: range 1 around 200 kHz. value: 1 - name: Range400K description: range 2 around 400 kHz. value: 2 - name: Range800K description: range 3 around 800 kHz. value: 3 - name: Range1M description: range 4 around 1 MHz. value: 4 - name: Range2M description: range 5 around 2 MHz. value: 5 - name: Range4M description: range 6 around 4 MHz (reset value). value: 6 - name: Range8M description: range 7 around 8 MHz. value: 7 - name: Range16M description: range 8 around 16 MHz. value: 8 - name: Range24M description: range 9 around 24 MHz. value: 9 - name: Range32M description: range 10 around 32 MHz. value: 10 - name: Range48M description: range 11 around 48 MHz. value: 11 enum/MSIRDY: bit_size: 1 variants: - name: NotReady description: MSI oscillator not ready. value: 0 - name: Ready description: MSI oscillator ready. value: 1 enum/MSIRDYC: bit_size: 1 variants: - name: Clear description: Clear interrupt flag. value: 1 enum/MSIRDYF: bit_size: 1 variants: - name: NotInterrupted description: Not interrupted. value: 0 - name: Interrupted description: Interrupted. value: 1 enum/MSIRDYIE: bit_size: 1 variants: - name: Disabled description: Interrupt disabled. value: 0 - name: Enabled description: Interrupt enabled. value: 1 enum/OBLRSTF: bit_size: 1 variants: - name: NoReset description: No reset occurred. value: 0 - name: Reset description: Reset occurred. value: 1 enum/PINRSTF: bit_size: 1 variants: - name: NoReset description: No reset occurred. value: 0 - name: Reset description: Reset occurred. value: 1 enum/PKARST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/PKASMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/PLLCFGR_PLLP: bit_size: 5 variants: - name: Div2 description: PLL = VCO/(N+1). value: 1 - name: Div3 description: PLL = VCO/(N+1). value: 2 - name: Div4 description: PLL = VCO/(N+1). value: 3 - name: Div5 description: PLL = VCO/(N+1). value: 4 - name: Div6 description: PLL = VCO/(N+1). value: 5 - name: Div7 description: PLL = VCO/(N+1). value: 6 - name: Div8 description: PLL = VCO/(N+1). value: 7 - name: Div9 description: PLL = VCO/(N+1). value: 8 - name: Div10 description: PLL = VCO/(N+1). value: 9 - name: Div11 description: PLL = VCO/(N+1). value: 10 - name: Div12 description: PLL = VCO/(N+1). value: 11 - name: Div13 description: PLL = VCO/(N+1). value: 12 - name: Div14 description: PLL = VCO/(N+1). value: 13 - name: Div15 description: PLL = VCO/(N+1). value: 14 - name: Div16 description: PLL = VCO/(N+1). value: 15 - name: Div17 description: PLL = VCO/(N+1). value: 16 - name: Div18 description: PLL = VCO/(N+1). value: 17 - name: Div19 description: PLL = VCO/(N+1). value: 18 - name: Div20 description: PLL = VCO/(N+1). value: 19 - name: Div21 description: PLL = VCO/(N+1). value: 20 - name: Div22 description: PLL = VCO/(N+1). value: 21 - name: Div23 description: PLL = VCO/(N+1). value: 22 - name: Div24 description: PLL = VCO/(N+1). value: 23 - name: Div25 description: PLL = VCO/(N+1). value: 24 - name: Div26 description: PLL = VCO/(N+1). value: 25 - name: Div27 description: PLL = VCO/(N+1). value: 26 - name: Div28 description: PLL = VCO/(N+1). value: 27 - name: Div29 description: PLL = VCO/(N+1). value: 28 - name: Div30 description: PLL = VCO/(N+1). value: 29 - name: Div31 description: PLL = VCO/(N+1). value: 30 - name: Div32 description: PLL = VCO/(N+1). value: 31 enum/PLLCFGR_PLLPEN: bit_size: 1 variants: - name: Disabled description: PLLCLK output disabled. value: 0 - name: Enabled description: PLLCLK output enabled. value: 1 enum/PLLCFGR_PLLQ: bit_size: 3 variants: - name: Div2 description: PLL = VCO/(N+1). value: 1 - name: Div3 description: PLL = VCO/(N+1). value: 2 - name: Div4 description: PLL = VCO/(N+1). value: 3 - name: Div5 description: PLL = VCO/(N+1). value: 4 - name: Div6 description: PLL = VCO/(N+1). value: 5 - name: Div7 description: PLL = VCO/(N+1). value: 6 - name: Div8 description: PLL = VCO/(N+1). value: 7 enum/PLLCFGR_PLLQEN: bit_size: 1 variants: - name: Disabled description: PLLCLK output disabled. value: 0 - name: Enabled description: PLLCLK output enabled. value: 1 enum/PLLCFGR_PLLR: bit_size: 3 variants: - name: Div2 description: PLL = VCO/(N+1). value: 1 - name: Div3 description: PLL = VCO/(N+1). value: 2 - name: Div4 description: PLL = VCO/(N+1). value: 3 - name: Div5 description: PLL = VCO/(N+1). value: 4 - name: Div6 description: PLL = VCO/(N+1). value: 5 - name: Div7 description: PLL = VCO/(N+1). value: 6 - name: Div8 description: PLL = VCO/(N+1). value: 7 enum/PLLCFGR_PLLREN: bit_size: 1 variants: - name: Disabled description: PLLCLK output disabled. value: 0 - name: Enabled description: PLLCLK output enabled. value: 1 enum/PLLM: bit_size: 3 variants: - name: Div1 description: VCO input = PLL input / PLLM. value: 0 - name: Div2 description: VCO input = PLL input / PLLM. value: 1 - name: Div3 description: VCO input = PLL input / PLLM. value: 2 - name: Div4 description: VCO input = PLL input / PLLM. value: 3 - name: Div5 description: VCO input = PLL input / PLLM. value: 4 - name: Div6 description: VCO input = PLL input / PLLM. value: 5 - name: Div7 description: VCO input = PLL input / PLLM. value: 6 - name: Div8 description: VCO input = PLL input / PLLM. value: 7 enum/PLLON: bit_size: 1 variants: - name: Off description: Main PLL Off. value: 0 - name: On description: Main PLL On. value: 1 enum/PLLRDY: bit_size: 1 variants: - name: Unlocked description: PLL unlocked. value: 0 - name: Locked description: PLL Locked. value: 1 enum/PLLRDYC: bit_size: 1 variants: - name: Clear description: Clear interrupt flag. value: 1 enum/PLLRDYF: bit_size: 1 variants: - name: NotInterrupted description: Not interrupted. value: 0 - name: Interrupted description: Interrupted. value: 1 enum/PLLRDYIE: bit_size: 1 variants: - name: Disabled description: Interrupt disabled. value: 0 - name: Enabled description: Interrupt enabled. value: 1 enum/PLLSAI1CFGR_PLLP: bit_size: 5 variants: - name: Div2 description: PLL = VCO/(N+1). value: 1 - name: Div3 description: PLL = VCO/(N+1). value: 2 - name: Div4 description: PLL = VCO/(N+1). value: 3 - name: Div5 description: PLL = VCO/(N+1). value: 4 - name: Div6 description: PLL = VCO/(N+1). value: 5 - name: Div7 description: PLL = VCO/(N+1). value: 6 - name: Div8 description: PLL = VCO/(N+1). value: 7 - name: Div9 description: PLL = VCO/(N+1). value: 8 - name: Div10 description: PLL = VCO/(N+1). value: 9 - name: Div11 description: PLL = VCO/(N+1). value: 10 - name: Div12 description: PLL = VCO/(N+1). value: 11 - name: Div13 description: PLL = VCO/(N+1). value: 12 - name: Div14 description: PLL = VCO/(N+1). value: 13 - name: Div15 description: PLL = VCO/(N+1). value: 14 - name: Div16 description: PLL = VCO/(N+1). value: 15 - name: Div17 description: PLL = VCO/(N+1). value: 16 - name: Div18 description: PLL = VCO/(N+1). value: 17 - name: Div19 description: PLL = VCO/(N+1). value: 18 - name: Div20 description: PLL = VCO/(N+1). value: 19 - name: Div21 description: PLL = VCO/(N+1). value: 20 - name: Div22 description: PLL = VCO/(N+1). value: 21 - name: Div23 description: PLL = VCO/(N+1). value: 22 - name: Div24 description: PLL = VCO/(N+1). value: 23 - name: Div25 description: PLL = VCO/(N+1). value: 24 - name: Div26 description: PLL = VCO/(N+1). value: 25 - name: Div27 description: PLL = VCO/(N+1). value: 26 - name: Div28 description: PLL = VCO/(N+1). value: 27 - name: Div29 description: PLL = VCO/(N+1). value: 28 - name: Div30 description: PLL = VCO/(N+1). value: 29 - name: Div31 description: PLL = VCO/(N+1). value: 30 - name: Div32 description: PLL = VCO/(N+1). value: 31 enum/PLLSAI1CFGR_PLLPEN: bit_size: 1 variants: - name: Disabled description: PLLCLK output disabled. value: 0 - name: Enabled description: PLLCLK output enabled. value: 1 enum/PLLSAI1CFGR_PLLQ: bit_size: 3 variants: - name: Div2 description: PLL = VCO/(N+1). value: 1 - name: Div3 description: PLL = VCO/(N+1). value: 2 - name: Div4 description: PLL = VCO/(N+1). value: 3 - name: Div5 description: PLL = VCO/(N+1). value: 4 - name: Div6 description: PLL = VCO/(N+1). value: 5 - name: Div7 description: PLL = VCO/(N+1). value: 6 - name: Div8 description: PLL = VCO/(N+1). value: 7 enum/PLLSAI1CFGR_PLLQEN: bit_size: 1 variants: - name: Disabled description: PLLCLK output disabled. value: 0 - name: Enabled description: PLLCLK output enabled. value: 1 enum/PLLSAI1CFGR_PLLR: bit_size: 3 variants: - name: Div2 description: PLL = VCO/(N+1). value: 1 - name: Div3 description: PLL = VCO/(N+1). value: 2 - name: Div4 description: PLL = VCO/(N+1). value: 3 - name: Div5 description: PLL = VCO/(N+1). value: 4 - name: Div6 description: PLL = VCO/(N+1). value: 5 - name: Div7 description: PLL = VCO/(N+1). value: 6 - name: Div8 description: PLL = VCO/(N+1). value: 7 enum/PLLSAI1CFGR_PLLREN: bit_size: 1 variants: - name: Disabled description: PLLCLK output disabled. value: 0 - name: Enabled description: PLLCLK output enabled. value: 1 enum/PLLSAI1ON: bit_size: 1 variants: - name: Off description: PLLSAI1 Off. value: 0 - name: On description: PLLSAI1 On. value: 1 enum/PLLSAI1RDY: bit_size: 1 variants: - name: Unlocked description: PLLSAI1 unlocked. value: 0 - name: Locked description: PLLSAI1 unlocked. value: 1 enum/PLLSAI1RDYC: bit_size: 1 variants: - name: Clear description: Clear interrupt flag. value: 1 enum/PLLSAI1RDYF: bit_size: 1 variants: - name: NotInterrupted description: Not interrupted. value: 0 - name: Interrupted description: Interrupted. value: 1 enum/PLLSAI1RDYIE: bit_size: 1 variants: - name: Disabled description: Interrupt disabled. value: 0 - name: Enabled description: Interrupt enabled. value: 1 enum/PLLSRC: bit_size: 2 variants: - name: NoClock description: No clock sent to PLL. value: 0 - name: MSI description: MSI clock selected as PLL and PLLSAI1 clock entry. value: 1 - name: HSI16 description: HSI16 clock selected as PLL and PLLSAI1 clock entry. value: 2 - name: HSE32 description: HSE32 clock selected as PLL and PLLSAI1 clock entry. value: 3 enum/PPRE1: bit_size: 3 variants: - name: Div2 description: HCLK divided by 2. value: 4 - name: Div4 description: HCLK divided by 4. value: 5 - name: Div8 description: HCLK divided by 8. value: 6 - name: Div16 description: HCLK divided by 16. value: 7 enum/PPRE1F: bit_size: 1 variants: - name: NotApplied description: PCLK1 prescaler value not yet applied. value: 0 - name: Applied description: PCLK1 prescaler value applied. value: 1 enum/PPRE2: bit_size: 3 variants: - name: Div2 description: HCLK divided by 2. value: 4 - name: Div4 description: HCLK divided by 4. value: 5 - name: Div8 description: HCLK divided by 8. value: 6 - name: Div16 description: HCLK divided by 16. value: 7 enum/PPRE2F: bit_size: 1 variants: - name: NotApplied description: PCLK2 prescaler value not yet applied. value: 0 - name: Applied description: PCLK2 prescaler value applied. value: 1 enum/QSPIEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/QSPIRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/RFCSS: bit_size: 1 variants: - name: HSI16 description: HSI16 used for radio system HCLK5 and APB3 clock. value: 0 - name: HSE_Div2 description: HSE divided by 2 used for radio system HCLK5 and APB3 clock. value: 1 enum/RFRSTS: bit_size: 1 variants: - name: NoReset description: Radio system BLE and 802.15.4 not in reset. value: 0 - name: Reset description: Radio system BLE and 802.15.4 under reset. value: 1 enum/RFWKPSEL: bit_size: 2 variants: - name: NoClock description: No clock. value: 0 - name: LSE description: LSE oscillator clock selected. value: 1 - name: HSE description: HSE oscillator clock selected. value: 3 enum/RMVF: bit_size: 1 variants: - name: NoEffect description: No effect. value: 0 - name: Clear description: Reset flags reset. value: 1 enum/RNGRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/RNGSEL: bit_size: 2 variants: - name: CLK48 description: Use clock as selected by CLK48SEL. value: 0 - name: LSI description: LSI clock selected. value: 1 - name: LSE description: LSE clock selected. value: 2 enum/RNGSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/RTCEN: bit_size: 1 variants: - name: Disabled description: RTC clock disabled. value: 0 - name: Enabled description: RTC clock enabled. value: 1 enum/RTCSEL: bit_size: 2 variants: - name: NoClock description: No clock. value: 0 - name: LSE description: LSE oscillator clock selected. value: 1 - name: LSI description: LSI oscillator clock selected. value: 2 - name: HSE32 description: HSE32 oscillator clock divided by 32 selected. value: 3 enum/SAI1SEL: bit_size: 2 variants: - name: PLLSAI1 description: PLLSAI1P clock selected. value: 0 - name: PLL description: PLLP clock selected. value: 1 - name: HSI16 description: HSI16 clock selected. value: 2 - name: Ext description: External clock input selected. value: 3 enum/SAI1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/SFTRSTF: bit_size: 1 variants: - name: NoReset description: No reset occurred. value: 0 - name: Reset description: Reset occurred. value: 1 enum/SHDHPRE: bit_size: 4 variants: - name: Div1 description: SYSCLK not divided. value: 0 - name: Div3 description: SYSCLK divided by 3. value: 1 - name: Div5 description: SYSCLK divided by 5. value: 2 - name: Div6 description: SYSCLK divided by 6. value: 5 - name: Div10 description: SYSCLK divided by 10. value: 6 - name: Div32 description: SYSCLK divided by 32. value: 7 - name: Div2 description: SYSCLK divided by 2. value: 8 - name: Div4 description: SYSCLK divided by 4. value: 9 - name: Div8 description: SYSCLK divided by 8. value: 10 - name: Div16 description: SYSCLK divided by 16. value: 11 - name: Div64 description: SYSCLK divided by 64. value: 12 - name: Div128 description: SYSCLK divided by 128. value: 13 - name: Div256 description: SYSCLK divided by 256. value: 14 - name: Div512 description: SYSCLK divided by 512. value: 15 enum/SHDHPREF: bit_size: 1 variants: - name: NotApplied description: HCLK4 prescaler value not yet applied. value: 0 - name: Applied description: HCLK4 prescaler value applied. value: 1 enum/SMEN802: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/SMPSSEL: bit_size: 2 variants: - name: HSI16 description: HSI16 selected as SMPS step-down converter clock. value: 0 - name: MSI description: MSI selected as SMPS step-down converter clock. value: 1 - name: HSE description: HSE selected as SMPS step-down converter clock. value: 2 enum/SMPSSWS: bit_size: 2 variants: - name: HSI16 description: HSI16 oscillator used as SMPS step-down converter clock. value: 0 - name: MSI description: MSI oscillator used as SMPS step-down converter clock. value: 1 - name: HSE description: HSE oscillator used as SMPS step-down converter clock. value: 2 - name: NoClock description: No clock is used. value: 3 enum/SPI1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/SPI2RST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/SRAM1EN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/SRAM1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/SRAM2SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/STOPWUCK: bit_size: 1 variants: - name: MSI description: MSI oscillator selected as wakeup from stop clock and CSS backup clock. value: 0 - name: HSI16 description: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock. value: 1 enum/SW: bit_size: 2 variants: - name: MSI description: MSI oscillator used as system clock. value: 0 - name: HSI16 description: HSI16 oscillator used as system clock. value: 1 - name: HSE32 description: HSE32 oscillator used as system clock. value: 2 - name: PLLR description: PLLRCLK used as system clock. value: 3 enum/SWS: bit_size: 2 variants: - name: MSI description: MSI oscillator used as system clock. value: 0 - name: HSI16 description: HSI16 oscillator used as system clock. value: 1 - name: HSE32 description: HSE32 oscillator used as system clock. value: 2 - name: PLLR description: PLLRCLK used as system clock. value: 3 enum/TIM16SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/TIM17SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/TIM1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/TIM2RST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/TSCRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/TSCSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/USART1SEL: bit_size: 2 variants: - name: PCLK description: PCLK clock selected. value: 0 - name: SYSCLK description: SYSCLK clock selected. value: 1 - name: HSI16 description: HSI16 clock selected. value: 2 - name: LSE description: LSE clock selected. value: 3 enum/USART1SMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/USBFSRST: bit_size: 1 variants: - name: NoReset description: No effect. value: 0 - name: Reset description: Reset peripheral. value: 1 enum/WWDGEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1 enum/WWDGRSTF: bit_size: 1 variants: - name: NoReset description: No reset occurred. value: 0 - name: Reset description: Reset occurred. value: 1 enum/WWDGSMEN: bit_size: 1 variants: - name: Disabled description: Clock disabled. value: 0 - name: Enabled description: Clock enabled. value: 1