block/TIM16:
  description: TIM16.
  items:
  - name: CR1
    description: TIM16/TIM17 control register 1.
    byte_offset: 0
    bit_size: 16
    fieldset: CR1
  - name: CR2
    description: TIM16/TIM17 control register 2.
    byte_offset: 4
    bit_size: 16
    fieldset: CR2
  - name: DIER
    description: TIM16/TIM17 DMA/interrupt enable register.
    byte_offset: 12
    bit_size: 16
    fieldset: DIER
  - name: SR
    description: TIM16/TIM17 status register.
    byte_offset: 16
    bit_size: 16
    fieldset: SR
  - name: EGR
    description: event generation register.
    byte_offset: 20
    access: Write
    fieldset: EGR
  - name: CCER
    description: TIM16/TIM17 capture/compare enable register.
    byte_offset: 32
    bit_size: 16
    fieldset: CCER
  - name: CNT
    description: TIM16/TIM17 counter.
    byte_offset: 36
    fieldset: CNT
  - name: PSC
    description: TIM16/TIM17 prescaler.
    byte_offset: 40
    bit_size: 16
    fieldset: PSC
  - name: ARR
    description: TIM16/TIM17 auto-reload register.
    byte_offset: 44
    bit_size: 16
    fieldset: ARR
  - name: RCR
    description: TIM16/TIM17 repetition counter register.
    byte_offset: 48
    bit_size: 16
    fieldset: RCR
  - name: CCR1
    description: TIM16/TIM17 capture/compare register 1.
    byte_offset: 52
    bit_size: 16
    fieldset: CCR1
  - name: BDTR
    description: As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.
    byte_offset: 68
    fieldset: BDTR
  - name: DCR
    description: TIM16/TIM17 DMA control register.
    byte_offset: 72
    bit_size: 16
    fieldset: DCR
  - name: DMAR
    description: TIM16/TIM17 DMA address for full transfer.
    byte_offset: 76
    bit_size: 16
    fieldset: DMAR
  - name: AF1
    description: TIM17 alternate function register 1.
    byte_offset: 96
    fieldset: AF1
  - name: TISEL
    description: TIM17 input selection register.
    byte_offset: 104
    fieldset: TISEL
fieldset/AF1:
  description: TIM17 alternate function register 1.
  fields:
  - name: BKINE
    description: BKINE.
    bit_offset: 0
    bit_size: 1
  - name: BKDF1BK2E
    description: BKDF1BK2E.
    bit_offset: 8
    bit_size: 1
  - name: BKINP
    description: BKINP.
    bit_offset: 9
    bit_size: 1
fieldset/ARR:
  description: TIM16/TIM17 auto-reload register.
  bit_size: 16
  fields:
  - name: ARR
    description: ARR.
    bit_offset: 0
    bit_size: 16
fieldset/BDTR:
  description: As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.
  fields:
  - name: DTG
    description: DTG.
    bit_offset: 0
    bit_size: 8
  - name: LOCK
    description: LOCK.
    bit_offset: 8
    bit_size: 2
  - name: OSSI
    description: OSSI.
    bit_offset: 10
    bit_size: 1
  - name: OSSR
    description: OSSR.
    bit_offset: 11
    bit_size: 1
  - name: BKE
    description: BKE.
    bit_offset: 12
    bit_size: 1
  - name: BKP
    description: BKP.
    bit_offset: 13
    bit_size: 1
  - name: AOE
    description: AOE.
    bit_offset: 14
    bit_size: 1
  - name: MOE
    description: MOE.
    bit_offset: 15
    bit_size: 1
  - name: BKF
    description: BKF.
    bit_offset: 16
    bit_size: 4
  - name: BKDSRM
    description: BKDSRM.
    bit_offset: 26
    bit_size: 1
  - name: BKBID
    description: BKBID.
    bit_offset: 28
    bit_size: 1
fieldset/CCER:
  description: TIM16/TIM17 capture/compare enable register.
  bit_size: 16
  fields:
  - name: CC1E
    description: CC1E.
    bit_offset: 0
    bit_size: 1
  - name: CC1P
    description: CC1P.
    bit_offset: 1
    bit_size: 1
  - name: CC1NE
    description: CC1NE.
    bit_offset: 2
    bit_size: 1
  - name: CC1NP
    description: CC1NP.
    bit_offset: 3
    bit_size: 1
fieldset/CCR1:
  description: TIM16/TIM17 capture/compare register 1.
  bit_size: 16
  fields:
  - name: CCR1
    description: CCR1.
    bit_offset: 0
    bit_size: 16
fieldset/CNT:
  description: TIM16/TIM17 counter.
  fields:
  - name: CNT
    description: CNT.
    bit_offset: 0
    bit_size: 16
  - name: UIFCPY
    description: UIFCPY.
    bit_offset: 31
    bit_size: 1
fieldset/CR1:
  description: TIM16/TIM17 control register 1.
  bit_size: 16
  fields:
  - name: CEN
    description: CEN.
    bit_offset: 0
    bit_size: 1
  - name: UDIS
    description: UDIS.
    bit_offset: 1
    bit_size: 1
  - name: URS
    description: URS.
    bit_offset: 2
    bit_size: 1
  - name: OPM
    description: OPM.
    bit_offset: 3
    bit_size: 1
  - name: ARPE
    description: ARPE.
    bit_offset: 7
    bit_size: 1
  - name: CKD
    description: CKD.
    bit_offset: 8
    bit_size: 2
  - name: UIFREMAP
    description: UIFREMAP.
    bit_offset: 11
    bit_size: 1
fieldset/CR2:
  description: TIM16/TIM17 control register 2.
  bit_size: 16
  fields:
  - name: CCPC
    description: CCPC.
    bit_offset: 0
    bit_size: 1
  - name: CCUS
    description: CCUS.
    bit_offset: 2
    bit_size: 1
  - name: CCDS
    description: CCDS.
    bit_offset: 3
    bit_size: 1
  - name: OIS1
    description: OIS1.
    bit_offset: 8
    bit_size: 1
  - name: OIS1N
    description: OIS1N.
    bit_offset: 9
    bit_size: 1
fieldset/DCR:
  description: TIM16/TIM17 DMA control register.
  bit_size: 16
  fields:
  - name: DBA
    description: DBA.
    bit_offset: 0
    bit_size: 5
  - name: DBL
    description: DBL.
    bit_offset: 8
    bit_size: 5
fieldset/DIER:
  description: TIM16/TIM17 DMA/interrupt enable register.
  bit_size: 16
  fields:
  - name: UIE
    description: UIE.
    bit_offset: 0
    bit_size: 1
  - name: CC1IE
    description: CC1IE.
    bit_offset: 1
    bit_size: 1
  - name: COMIE
    description: COMIE.
    bit_offset: 5
    bit_size: 1
  - name: BIE
    description: BIE.
    bit_offset: 7
    bit_size: 1
  - name: UDE
    description: UDE.
    bit_offset: 8
    bit_size: 1
  - name: CC1DE
    description: CC1DE.
    bit_offset: 9
    bit_size: 1
  - name: COMDE
    description: COMDE.
    bit_offset: 13
    bit_size: 1
fieldset/DMAR:
  description: TIM16/TIM17 DMA address for full transfer.
  bit_size: 16
  fields:
  - name: DMAB
    description: DMAB.
    bit_offset: 0
    bit_size: 16
fieldset/EGR:
  description: event generation register.
  fields:
  - name: UG
    description: Update generation.
    bit_offset: 0
    bit_size: 1
fieldset/PSC:
  description: TIM16/TIM17 prescaler.
  bit_size: 16
  fields:
  - name: PSC
    description: PSC.
    bit_offset: 0
    bit_size: 16
fieldset/RCR:
  description: TIM16/TIM17 repetition counter register.
  bit_size: 16
  fields:
  - name: REP
    description: REP.
    bit_offset: 0
    bit_size: 8
fieldset/SR:
  description: TIM16/TIM17 status register.
  bit_size: 16
  fields:
  - name: UIF
    description: UIF.
    bit_offset: 0
    bit_size: 1
  - name: CC1IF
    description: CC1IF.
    bit_offset: 1
    bit_size: 1
  - name: COMIF
    description: COMIF.
    bit_offset: 5
    bit_size: 1
  - name: BIF
    description: BIF.
    bit_offset: 7
    bit_size: 1
  - name: CC1OF
    description: CC1OF.
    bit_offset: 9
    bit_size: 1
fieldset/TISEL:
  description: TIM17 input selection register.
  fields:
  - name: TI1SEL
    description: TI1SEL.
    bit_offset: 0
    bit_size: 4