block/OTG:
  description: OTG.
  items:
  - name: GOTGCTL
    description: The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.
    byte_offset: 0
    fieldset: GOTGCTL
  - name: GOTGINT
    description: The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
    byte_offset: 4
    fieldset: GOTGINT
  - name: GAHBCFG
    description: This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
    byte_offset: 8
    fieldset: GAHBCFG
  - name: GUSBCFG
    description: This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
    byte_offset: 12
    fieldset: GUSBCFG
  - name: GRSTCTL
    description: The application uses this register to reset various hardware features inside the core.
    byte_offset: 16
    fieldset: GRSTCTL
  - name: GINTSTS
    description: This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
    byte_offset: 20
    fieldset: GINTSTS
  - name: GINTMSK
    description: This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set.
    byte_offset: 24
    fieldset: GINTMSK
  - name: GRXSTSR
    description: This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000.
    byte_offset: 28
    access: Read
    fieldset: GRXSTSR
  - name: GRXSTSP
    description: This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted.
    byte_offset: 32
    access: Read
    fieldset: GRXSTSP
  - name: GRXFSIZ
    description: The application can program the RAM size that must be allocated to the Rx FIFO.
    byte_offset: 36
    fieldset: GRXFSIZ
  - name: HNPTXFSIZ
    description: Host mode.
    byte_offset: 40
    fieldset: HNPTXFSIZ
  - name: HNPTXSTS
    description: In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue.
    byte_offset: 44
    access: Read
    fieldset: HNPTXSTS
  - name: GCCFG
    description: OTG general core configuration register.
    byte_offset: 56
    fieldset: GCCFG
  - name: CID
    description: This is a register containing the Product ID as reset value.
    byte_offset: 60
    fieldset: CID
  - name: GLPMCFG
    description: OTG core LPM configuration register.
    byte_offset: 84
    fieldset: GLPMCFG
  - name: HPTXFSIZ
    description: OTG host periodic transmit FIFO size register.
    byte_offset: 256
    fieldset: HPTXFSIZ
  - name: DIEPTXF1
    description: OTG device IN endpoint transmit FIFO 1 size register.
    byte_offset: 260
    fieldset: DIEPTXF1
  - name: DIEPTXF2
    description: OTG device IN endpoint transmit FIFO 2 size register.
    byte_offset: 264
    fieldset: DIEPTXF2
  - name: DIEPTXF3
    description: OTG device IN endpoint transmit FIFO 3 size register.
    byte_offset: 268
    fieldset: DIEPTXF3
  - name: DIEPTXF4
    description: OTG device IN endpoint transmit FIFO 4 size register.
    byte_offset: 272
    fieldset: DIEPTXF4
  - name: DIEPTXF5
    description: OTG device IN endpoint transmit FIFO 5 size register.
    byte_offset: 276
    fieldset: DIEPTXF5
  - name: DIEPTXF6
    description: OTG device IN endpoint transmit FIFO 6 size register.
    byte_offset: 280
    fieldset: DIEPTXF6
  - name: DIEPTXF7
    description: OTG device IN endpoint transmit FIFO 7 size register.
    byte_offset: 284
    fieldset: DIEPTXF7
  - name: DIEPTXF8
    description: OTG device IN endpoint transmit FIFO 8 size register.
    byte_offset: 288
    fieldset: DIEPTXF8
  - name: HCFG
    description: This register configures the core after power-on. Do not make changes to this register after initializing the host.
    byte_offset: 1024
    fieldset: HCFG
  - name: HFIR
    description: This register stores the frame interval information for the current speed to which the OTG controller has enumerated.
    byte_offset: 1028
    fieldset: HFIR
  - name: HFNUM
    description: This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.
    byte_offset: 1032
    access: Read
    fieldset: HFNUM
  - name: HPTXSTS
    description: This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue.
    byte_offset: 1040
    access: Read
    fieldset: HPTXSTS
  - name: HAINT
    description: When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.
    byte_offset: 1044
    access: Read
    fieldset: HAINT
  - name: HAINTMSK
    description: The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
    byte_offset: 1048
    fieldset: HAINTMSK
  - name: HFLBADDR
    description: This register holds the starting address of the frame list information (scatter/gather mode).
    byte_offset: 1052
    fieldset: HFLBADDR
  - name: HPRT
    description: This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
    byte_offset: 1088
    fieldset: HPRT
  - name: HCCHAR0
    description: OTG host channel 0 characteristics register.
    byte_offset: 1280
    fieldset: HCCHAR0
  - name: HCSPLT0
    description: OTG host channel 0 split control register.
    byte_offset: 1284
    fieldset: HCSPLT0
  - name: HCINT0
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1288
    fieldset: HCINT0
  - name: HCINTMSK0
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1292
    fieldset: HCINTMSK0
  - name: HCTSIZ0
    description: OTG host channel 0 transfer size register.
    byte_offset: 1296
    fieldset: HCTSIZ0
  - name: HCDMA0
    description: OTG host channel 0 DMA address register in buffer DMA [alternate].
    byte_offset: 1300
    fieldset: HCDMA0
  - name: HCDMAB0
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1308
    access: Read
    fieldset: HCDMAB0
  - name: HCCHAR1
    description: OTG host channel 1 characteristics register.
    byte_offset: 1312
    fieldset: HCCHAR1
  - name: HCSPLT1
    description: OTG host channel 1 split control register.
    byte_offset: 1316
    fieldset: HCSPLT1
  - name: HCINT1
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1320
    fieldset: HCINT1
  - name: HCINTMSK1
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1324
    fieldset: HCINTMSK1
  - name: HCTSIZ1
    description: OTG host channel 1 transfer size register.
    byte_offset: 1328
    fieldset: HCTSIZ1
  - name: HCDMA1
    description: OTG host channel 1 DMA address register in buffer DMA [alternate].
    byte_offset: 1332
    fieldset: HCDMA1
  - name: HCDMAB1
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1340
    access: Read
    fieldset: HCDMAB1
  - name: HCCHAR2
    description: OTG host channel 2 characteristics register.
    byte_offset: 1344
    fieldset: HCCHAR2
  - name: HCSPLT2
    description: OTG host channel 2 split control register.
    byte_offset: 1348
    fieldset: HCSPLT2
  - name: HCINT2
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1352
    fieldset: HCINT2
  - name: HCINTMSK2
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1356
    fieldset: HCINTMSK2
  - name: HCTSIZ2
    description: OTG host channel 2 transfer size register.
    byte_offset: 1360
    fieldset: HCTSIZ2
  - name: HCDMA2
    description: OTG host channel 2 DMA address register in buffer DMA [alternate].
    byte_offset: 1364
    fieldset: HCDMA2
  - name: HCDMAB2
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1372
    access: Read
    fieldset: HCDMAB2
  - name: HCCHAR3
    description: OTG host channel 3 characteristics register.
    byte_offset: 1376
    fieldset: HCCHAR3
  - name: HCSPLT3
    description: OTG host channel 3 split control register.
    byte_offset: 1380
    fieldset: HCSPLT3
  - name: HCINT3
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1384
    fieldset: HCINT3
  - name: HCINTMSK3
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1388
    fieldset: HCINTMSK3
  - name: HCTSIZ3
    description: OTG host channel 3 transfer size register.
    byte_offset: 1392
    fieldset: HCTSIZ3
  - name: HCDMA3
    description: OTG host channel 3 DMA address register in buffer DMA [alternate].
    byte_offset: 1396
    fieldset: HCDMA3
  - name: HCDMAB3
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1404
    access: Read
    fieldset: HCDMAB3
  - name: HCCHAR4
    description: OTG host channel 4 characteristics register.
    byte_offset: 1408
    fieldset: HCCHAR4
  - name: HCSPLT4
    description: OTG host channel 4 split control register.
    byte_offset: 1412
    fieldset: HCSPLT4
  - name: HCINT4
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1416
    fieldset: HCINT4
  - name: HCINTMSK4
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1420
    fieldset: HCINTMSK4
  - name: HCTSIZ4
    description: OTG host channel 4 transfer size register.
    byte_offset: 1424
    fieldset: HCTSIZ4
  - name: HCDMA4
    description: OTG host channel 4 DMA address register in buffer DMA [alternate].
    byte_offset: 1428
    fieldset: HCDMA4
  - name: HCDMAB4
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1436
    access: Read
    fieldset: HCDMAB4
  - name: HCCHAR5
    description: OTG host channel 5 characteristics register.
    byte_offset: 1440
    fieldset: HCCHAR5
  - name: HCSPLT5
    description: OTG host channel 5 split control register.
    byte_offset: 1444
    fieldset: HCSPLT5
  - name: HCINT5
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1448
    fieldset: HCINT5
  - name: HCINTMSK5
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1452
    fieldset: HCINTMSK5
  - name: HCTSIZ5
    description: OTG host channel 5 transfer size register.
    byte_offset: 1456
    fieldset: HCTSIZ5
  - name: HCDMA5
    description: OTG host channel 5 DMA address register in buffer DMA [alternate].
    byte_offset: 1460
    fieldset: HCDMA5
  - name: HCDMAB5
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1468
    access: Read
    fieldset: HCDMAB5
  - name: HCCHAR6
    description: OTG host channel 6 characteristics register.
    byte_offset: 1472
    fieldset: HCCHAR6
  - name: HCSPLT6
    description: OTG host channel 6 split control register.
    byte_offset: 1476
    fieldset: HCSPLT6
  - name: HCINT6
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1480
    fieldset: HCINT6
  - name: HCINTMSK6
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1484
    fieldset: HCINTMSK6
  - name: HCTSIZ6
    description: OTG host channel 6 transfer size register.
    byte_offset: 1488
    fieldset: HCTSIZ6
  - name: HCDMA6
    description: OTG host channel 6 DMA address register in buffer DMA [alternate].
    byte_offset: 1492
    fieldset: HCDMA6
  - name: HCDMAB6
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1500
    access: Read
    fieldset: HCDMAB6
  - name: HCCHAR7
    description: OTG host channel 7 characteristics register.
    byte_offset: 1504
    fieldset: HCCHAR7
  - name: HCSPLT7
    description: OTG host channel 7 split control register.
    byte_offset: 1508
    fieldset: HCSPLT7
  - name: HCINT7
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1512
    fieldset: HCINT7
  - name: HCINTMSK7
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1516
    fieldset: HCINTMSK7
  - name: HCTSIZ7
    description: OTG host channel 7 transfer size register.
    byte_offset: 1520
    fieldset: HCTSIZ7
  - name: HCDMA7
    description: OTG host channel 7 DMA address register in buffer DMA [alternate].
    byte_offset: 1524
    fieldset: HCDMA7
  - name: HCDMAB7
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1532
    access: Read
    fieldset: HCDMAB7
  - name: HCCHAR8
    description: OTG host channel 8 characteristics register.
    byte_offset: 1536
    fieldset: HCCHAR8
  - name: HCSPLT8
    description: OTG host channel 8 split control register.
    byte_offset: 1540
    fieldset: HCSPLT8
  - name: HCINT8
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1544
    fieldset: HCINT8
  - name: HCINTMSK8
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1548
    fieldset: HCINTMSK8
  - name: HCTSIZ8
    description: OTG host channel 8 transfer size register.
    byte_offset: 1552
    fieldset: HCTSIZ8
  - name: HCDMA8
    description: OTG host channel 8 DMA address register in buffer DMA [alternate].
    byte_offset: 1556
    fieldset: HCDMA8
  - name: HCDMAB8
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1564
    access: Read
    fieldset: HCDMAB8
  - name: HCCHAR9
    description: OTG host channel 9 characteristics register.
    byte_offset: 1568
    fieldset: HCCHAR9
  - name: HCSPLT9
    description: OTG host channel 9 split control register.
    byte_offset: 1572
    fieldset: HCSPLT9
  - name: HCINT9
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1576
    fieldset: HCINT9
  - name: HCINTMSK9
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1580
    fieldset: HCINTMSK9
  - name: HCTSIZ9
    description: OTG host channel 9 transfer size register.
    byte_offset: 1584
    fieldset: HCTSIZ9
  - name: HCDMA9
    description: OTG host channel 9 DMA address register in buffer DMA [alternate].
    byte_offset: 1588
    fieldset: HCDMA9
  - name: HCDMAB9
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1596
    access: Read
    fieldset: HCDMAB9
  - name: HCCHAR10
    description: OTG host channel 10 characteristics register.
    byte_offset: 1600
    fieldset: HCCHAR10
  - name: HCSPLT10
    description: OTG host channel 10 split control register.
    byte_offset: 1604
    fieldset: HCSPLT10
  - name: HCINT10
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1608
    fieldset: HCINT10
  - name: HCINTMSK10
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1612
    fieldset: HCINTMSK10
  - name: HCTSIZ10
    description: OTG host channel 10 transfer size register.
    byte_offset: 1616
    fieldset: HCTSIZ10
  - name: HCDMA10
    description: OTG host channel 10 DMA address register in buffer DMA [alternate].
    byte_offset: 1620
    fieldset: HCDMA10
  - name: HCDMAB10
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1628
    access: Read
    fieldset: HCDMAB10
  - name: HCCHAR11
    description: OTG host channel 11 characteristics register.
    byte_offset: 1632
    fieldset: HCCHAR11
  - name: HCSPLT11
    description: OTG host channel 11 split control register.
    byte_offset: 1636
    fieldset: HCSPLT11
  - name: HCINT11
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1640
    fieldset: HCINT11
  - name: HCINTMSK11
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1644
    fieldset: HCINTMSK11
  - name: HCTSIZ11
    description: OTG host channel 11 transfer size register.
    byte_offset: 1648
    fieldset: HCTSIZ11
  - name: HCDMA11
    description: OTG host channel 11 DMA address register in buffer DMA [alternate].
    byte_offset: 1652
    fieldset: HCDMA11
  - name: HCDMAB11
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1660
    access: Read
    fieldset: HCDMAB11
  - name: HCCHAR12
    description: OTG host channel 12 characteristics register.
    byte_offset: 1664
    fieldset: HCCHAR12
  - name: HCSPLT12
    description: OTG host channel 12 split control register.
    byte_offset: 1668
    fieldset: HCSPLT12
  - name: HCINT12
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1672
    fieldset: HCINT12
  - name: HCINTMSK12
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1676
    fieldset: HCINTMSK12
  - name: HCTSIZ12
    description: OTG host channel 12 transfer size register.
    byte_offset: 1680
    fieldset: HCTSIZ12
  - name: HCDMA12
    description: OTG host channel 12 DMA address register in buffer DMA [alternate].
    byte_offset: 1684
    fieldset: HCDMA12
  - name: HCDMAB12
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1692
    access: Read
    fieldset: HCDMAB12
  - name: HCCHAR13
    description: OTG host channel 13 characteristics register.
    byte_offset: 1696
    fieldset: HCCHAR13
  - name: HCSPLT13
    description: OTG host channel 13 split control register.
    byte_offset: 1700
    fieldset: HCSPLT13
  - name: HCINT13
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1704
    fieldset: HCINT13
  - name: HCINTMSK13
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1708
    fieldset: HCINTMSK13
  - name: HCTSIZ13
    description: OTG host channel 13 transfer size register.
    byte_offset: 1712
    fieldset: HCTSIZ13
  - name: HCDMA13
    description: OTG host channel 13 DMA address register in buffer DMA [alternate].
    byte_offset: 1716
    fieldset: HCDMA13
  - name: HCDMAB13
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1724
    access: Read
    fieldset: HCDMAB13
  - name: HCCHAR14
    description: OTG host channel 14 characteristics register.
    byte_offset: 1728
    fieldset: HCCHAR14
  - name: HCSPLT14
    description: OTG host channel 14 split control register.
    byte_offset: 1732
    fieldset: HCSPLT14
  - name: HCINT14
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1736
    fieldset: HCINT14
  - name: HCINTMSK14
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1740
    fieldset: HCINTMSK14
  - name: HCTSIZ14
    description: OTG host channel 14 transfer size register.
    byte_offset: 1744
    fieldset: HCTSIZ14
  - name: HCDMA14
    description: OTG host channel 14 DMA address register in buffer DMA [alternate].
    byte_offset: 1748
    fieldset: HCDMA14
  - name: HCDMAB14
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1756
    access: Read
    fieldset: HCDMAB14
  - name: HCCHAR15
    description: OTG host channel 15 characteristics register.
    byte_offset: 1760
    fieldset: HCCHAR15
  - name: HCSPLT15
    description: OTG host channel 15 split control register.
    byte_offset: 1764
    fieldset: HCSPLT15
  - name: HCINT15
    description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
    byte_offset: 1768
    fieldset: HCINT15
  - name: HCINTMSK15
    description: This register reflects the mask for each channel status described in the previous section.
    byte_offset: 1772
    fieldset: HCINTMSK15
  - name: HCTSIZ15
    description: OTG host channel 15 transfer size register.
    byte_offset: 1776
    fieldset: HCTSIZ15
  - name: HCDMA15
    description: OTG host channel 15 DMA address register in buffer DMA [alternate].
    byte_offset: 1780
    fieldset: HCDMA15
  - name: HCDMAB15
    description: OTG host channel-n DMA address buffer register.
    byte_offset: 1788
    access: Read
    fieldset: HCDMAB15
  - name: DCFG
    description: This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
    byte_offset: 2048
    fieldset: DCFG
  - name: DCTL
    description: OTG device control register.
    byte_offset: 2052
    fieldset: DCTL
  - name: DSTS
    description: This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register.
    byte_offset: 2056
    access: Read
    fieldset: DSTS
  - name: DIEPMSK
    description: This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
    byte_offset: 2064
    fieldset: DIEPMSK
  - name: DOEPMSK
    description: This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
    byte_offset: 2068
    fieldset: DOEPMSK
  - name: DAINT
    description: When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx).
    byte_offset: 2072
    access: Read
    fieldset: DAINT
  - name: DAINTMSK
    description: The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set.
    byte_offset: 2076
    fieldset: DAINTMSK
  - name: DVBUSDIS
    description: This register specifies the VBUS discharge time after VBUS pulsing during SRP.
    byte_offset: 2088
    fieldset: DVBUSDIS
  - name: DVBUSPULSE
    description: This register specifies the VBUS pulsing time during SRP.
    byte_offset: 2092
    fieldset: DVBUSPULSE
  - name: DTHRCTL
    description: OTG device threshold control register.
    byte_offset: 2096
    fieldset: DTHRCTL
  - name: DIEPEMPMSK
    description: This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx).
    byte_offset: 2100
    fieldset: DIEPEMPMSK
  - name: DEACHINT
    description: OTG device each endpoint interrupt register.
    byte_offset: 2104
    access: Read
    fieldset: DEACHINT
  - name: DEACHINTMSK
    description: There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.
    byte_offset: 2108
    fieldset: DEACHINTMSK
  - name: HS_DIEPEACHMSK1
    description: 'This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.'
    byte_offset: 2116
    fieldset: HS_DIEPEACHMSK1
  - name: HS_DOEPEACHMSK1
    description: 'This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.'
    byte_offset: 2180
    fieldset: HS_DOEPEACHMSK1
  - name: DIEPCTL0
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2304
    fieldset: DIEPCTL0
  - name: DIEPINT0
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2312
    fieldset: DIEPINT0
  - name: DIEPTSIZ0
    description: The application must modify this register before enabling endpoint 0.
    byte_offset: 2320
    fieldset: DIEPTSIZ0
  - name: DIEPDMA0
    description: OTG device IN endpoint 0 DMA address register.
    byte_offset: 2324
    fieldset: DIEPDMA0
  - name: DTXFSTS0
    description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
    byte_offset: 2328
    access: Read
    fieldset: DTXFSTS0
  - name: DIEPCTL1
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2336
    fieldset: DIEPCTL1
  - name: DIEPINT1
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2344
    fieldset: DIEPINT1
  - name: DIEPTSIZ1
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2352
    fieldset: DIEPTSIZ1
  - name: DIEPDMA1
    description: OTG device IN endpoint 1 DMA address register.
    byte_offset: 2356
    fieldset: DIEPDMA1
  - name: DTXFSTS1
    description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
    byte_offset: 2360
    access: Read
    fieldset: DTXFSTS1
  - name: DIEPCTL2
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2368
    fieldset: DIEPCTL2
  - name: DIEPINT2
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2376
    fieldset: DIEPINT2
  - name: DIEPTSIZ2
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2384
    fieldset: DIEPTSIZ2
  - name: DIEPDMA2
    description: OTG device IN endpoint 2 DMA address register.
    byte_offset: 2388
    fieldset: DIEPDMA2
  - name: DTXFSTS2
    description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
    byte_offset: 2392
    access: Read
    fieldset: DTXFSTS2
  - name: DIEPCTL3
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2400
    fieldset: DIEPCTL3
  - name: DIEPINT3
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2408
    fieldset: DIEPINT3
  - name: DIEPTSIZ3
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2416
    fieldset: DIEPTSIZ3
  - name: DIEPDMA3
    description: OTG device IN endpoint 3 DMA address register.
    byte_offset: 2420
    fieldset: DIEPDMA3
  - name: DTXFSTS3
    description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
    byte_offset: 2424
    access: Read
    fieldset: DTXFSTS3
  - name: DIEPCTL4
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2432
    fieldset: DIEPCTL4
  - name: DIEPINT4
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2440
    fieldset: DIEPINT4
  - name: DIEPTSIZ4
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2448
    fieldset: DIEPTSIZ4
  - name: DIEPDMA4
    description: OTG device IN endpoint 4 DMA address register.
    byte_offset: 2452
    fieldset: DIEPDMA4
  - name: DTXFSTS4
    description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
    byte_offset: 2456
    access: Read
    fieldset: DTXFSTS4
  - name: DIEPCTL5
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2464
    fieldset: DIEPCTL5
  - name: DIEPINT5
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2472
    fieldset: DIEPINT5
  - name: DIEPTSIZ5
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2480
    fieldset: DIEPTSIZ5
  - name: DIEPDMA5
    description: OTG device IN endpoint 5 DMA address register.
    byte_offset: 2484
    fieldset: DIEPDMA5
  - name: DTXFSTS5
    description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
    byte_offset: 2488
    access: Read
    fieldset: DTXFSTS5
  - name: DIEPCTL6
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2496
    fieldset: DIEPCTL6
  - name: DIEPINT6
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2504
    fieldset: DIEPINT6
  - name: DIEPTSIZ6
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2512
    fieldset: DIEPTSIZ6
  - name: DIEPDMA6
    description: OTG device IN endpoint 6 DMA address register.
    byte_offset: 2516
    fieldset: DIEPDMA6
  - name: DTXFSTS6
    description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
    byte_offset: 2520
    access: Read
    fieldset: DTXFSTS6
  - name: DIEPCTL7
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2528
    fieldset: DIEPCTL7
  - name: DIEPINT7
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2536
    fieldset: DIEPINT7
  - name: DIEPTSIZ7
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2544
    fieldset: DIEPTSIZ7
  - name: DIEPDMA7
    description: OTG device IN endpoint 7 DMA address register.
    byte_offset: 2548
    fieldset: DIEPDMA7
  - name: DTXFSTS7
    description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
    byte_offset: 2552
    access: Read
    fieldset: DTXFSTS7
  - name: DIEPCTL8
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2560
    fieldset: DIEPCTL8
  - name: DIEPINT8
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2568
    fieldset: DIEPINT8
  - name: DIEPTSIZ8
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2576
    fieldset: DIEPTSIZ8
  - name: DIEPDMA8
    description: OTG device IN endpoint 8 DMA address register.
    byte_offset: 2580
    fieldset: DIEPDMA8
  - name: DTXFSTS8
    description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
    byte_offset: 2584
    access: Read
    fieldset: DTXFSTS8
  - name: DOEPCTL0
    description: This section describes the OTG_DOEPCTL0 register.
    byte_offset: 2816
    fieldset: DOEPCTL0
  - name: DOEPINT0
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2824
    fieldset: DOEPINT0
  - name: DOEPTSIZ0
    description: The application must modify this register before enabling endpoint 0.
    byte_offset: 2832
    fieldset: DOEPTSIZ0
  - name: DOEPDMA0
    description: OTG device OUT endpoint 0 DMA address register.
    byte_offset: 2836
    fieldset: DOEPDMA0
  - name: DOEPCTL1
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2848
    fieldset: DOEPCTL1
  - name: DOEPINT1
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2856
    fieldset: DOEPINT1
  - name: DOEPTSIZ1
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2864
    fieldset: DOEPTSIZ1
  - name: DOEPDMA1
    description: OTG device OUT endpoint 1 DMA address register.
    byte_offset: 2868
    fieldset: DOEPDMA1
  - name: DOEPCTL2
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2880
    fieldset: DOEPCTL2
  - name: DOEPINT2
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2888
    fieldset: DOEPINT2
  - name: DOEPTSIZ2
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2896
    fieldset: DOEPTSIZ2
  - name: DOEPDMA2
    description: OTG device OUT endpoint 2 DMA address register.
    byte_offset: 2900
    fieldset: DOEPDMA2
  - name: DOEPCTL3
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2912
    fieldset: DOEPCTL3
  - name: DOEPINT3
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2920
    fieldset: DOEPINT3
  - name: DOEPTSIZ3
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2928
    fieldset: DOEPTSIZ3
  - name: DOEPDMA3
    description: OTG device OUT endpoint 3 DMA address register.
    byte_offset: 2932
    fieldset: DOEPDMA3
  - name: DOEPCTL4
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2944
    fieldset: DOEPCTL4
  - name: DOEPINT4
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2952
    fieldset: DOEPINT4
  - name: DOEPTSIZ4
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2960
    fieldset: DOEPTSIZ4
  - name: DOEPDMA4
    description: OTG device OUT endpoint 4 DMA address register.
    byte_offset: 2964
    fieldset: DOEPDMA4
  - name: DOEPCTL5
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 2976
    fieldset: DOEPCTL5
  - name: DOEPINT5
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 2984
    fieldset: DOEPINT5
  - name: DOEPTSIZ5
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 2992
    fieldset: DOEPTSIZ5
  - name: DOEPDMA5
    description: OTG device OUT endpoint 5 DMA address register.
    byte_offset: 2996
    fieldset: DOEPDMA5
  - name: DOEPCTL6
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 3008
    fieldset: DOEPCTL6
  - name: DOEPINT6
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 3016
    fieldset: DOEPINT6
  - name: DOEPTSIZ6
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 3024
    fieldset: DOEPTSIZ6
  - name: DOEPDMA6
    description: OTG device OUT endpoint 6 DMA address register.
    byte_offset: 3028
    fieldset: DOEPDMA6
  - name: DOEPCTL7
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 3040
    fieldset: DOEPCTL7
  - name: DOEPINT7
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 3048
    fieldset: DOEPINT7
  - name: DOEPTSIZ7
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 3056
    fieldset: DOEPTSIZ7
  - name: DOEPDMA7
    description: OTG device OUT endpoint 7 DMA address register.
    byte_offset: 3060
    fieldset: DOEPDMA7
  - name: DOEPCTL8
    description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
    byte_offset: 3072
    fieldset: DOEPCTL8
  - name: DOEPINT8
    description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
    byte_offset: 3080
    fieldset: DOEPINT8
  - name: DOEPTSIZ8
    description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
    byte_offset: 3088
    fieldset: DOEPTSIZ8
  - name: DOEPDMA8
    description: OTG device OUT endpoint 8 DMA address register.
    byte_offset: 3092
    fieldset: DOEPDMA8
  - name: PCGCCTL
    description: This register is available in host and device modes.
    byte_offset: 3584
    fieldset: PCGCCTL
fieldset/CID:
  description: This is a register containing the Product ID as reset value.
  fields:
  - name: PRODUCT_ID
    description: PRODUCT_ID.
    bit_offset: 0
    bit_size: 32
fieldset/DAINT:
  description: When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx).
  fields:
  - name: IEPINT
    description: IEPINT.
    bit_offset: 0
    bit_size: 16
  - name: OEPINT
    description: OEPINT.
    bit_offset: 16
    bit_size: 16
fieldset/DAINTMSK:
  description: The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set.
  fields:
  - name: IEPM
    description: IEPM.
    bit_offset: 0
    bit_size: 16
  - name: OEPM
    description: OEPM.
    bit_offset: 16
    bit_size: 16
fieldset/DCFG:
  description: This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
  fields:
  - name: DSPD
    description: DSPD.
    bit_offset: 0
    bit_size: 2
  - name: NZLSOHSK
    description: NZLSOHSK.
    bit_offset: 2
    bit_size: 1
  - name: DAD
    description: DAD.
    bit_offset: 4
    bit_size: 7
  - name: PFIVL
    description: PFIVL.
    bit_offset: 11
    bit_size: 2
  - name: XCVRDLY
    description: XCVRDLY.
    bit_offset: 14
    bit_size: 1
  - name: ERRATIM
    description: ERRATIM.
    bit_offset: 15
    bit_size: 1
  - name: PERSCHIVL
    description: PERSCHIVL.
    bit_offset: 24
    bit_size: 2
fieldset/DCTL:
  description: OTG device control register.
  fields:
  - name: RWUSIG
    description: RWUSIG.
    bit_offset: 0
    bit_size: 1
  - name: SDIS
    description: SDIS.
    bit_offset: 1
    bit_size: 1
  - name: GINSTS
    description: GINSTS.
    bit_offset: 2
    bit_size: 1
  - name: GONSTS
    description: GONSTS.
    bit_offset: 3
    bit_size: 1
  - name: TCTL
    description: TCTL.
    bit_offset: 4
    bit_size: 3
  - name: SGINAK
    description: SGINAK.
    bit_offset: 7
    bit_size: 1
  - name: CGINAK
    description: CGINAK.
    bit_offset: 8
    bit_size: 1
  - name: SGONAK
    description: SGONAK.
    bit_offset: 9
    bit_size: 1
  - name: CGONAK
    description: CGONAK.
    bit_offset: 10
    bit_size: 1
  - name: POPRGDNE
    description: POPRGDNE.
    bit_offset: 11
    bit_size: 1
  - name: DSBESLRJCT
    description: DSBESLRJCT.
    bit_offset: 18
    bit_size: 1
fieldset/DEACHINT:
  description: OTG device each endpoint interrupt register.
  fields:
  - name: IEP1INT
    description: IEP1INT.
    bit_offset: 1
    bit_size: 1
  - name: OEP1INT
    description: OEP1INT.
    bit_offset: 17
    bit_size: 1
fieldset/DEACHINTMSK:
  description: There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.
  fields:
  - name: IEP1INTM
    description: IEP1INTM.
    bit_offset: 1
    bit_size: 1
  - name: OEP1INTM
    description: OEP1INTM.
    bit_offset: 17
    bit_size: 1
fieldset/DIEPCTL0:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: TXFNUM
    description: TXFNUM.
    bit_offset: 22
    bit_size: 4
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SODDFRM
    description: SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DIEPCTL1:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: TXFNUM
    description: TXFNUM.
    bit_offset: 22
    bit_size: 4
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SODDFRM
    description: SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DIEPCTL2:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: TXFNUM
    description: TXFNUM.
    bit_offset: 22
    bit_size: 4
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SODDFRM
    description: SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DIEPCTL3:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: TXFNUM
    description: TXFNUM.
    bit_offset: 22
    bit_size: 4
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SODDFRM
    description: SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DIEPCTL4:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: TXFNUM
    description: TXFNUM.
    bit_offset: 22
    bit_size: 4
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SODDFRM
    description: SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DIEPCTL5:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: TXFNUM
    description: TXFNUM.
    bit_offset: 22
    bit_size: 4
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SODDFRM
    description: SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DIEPCTL6:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: TXFNUM
    description: TXFNUM.
    bit_offset: 22
    bit_size: 4
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SODDFRM
    description: SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DIEPCTL7:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: TXFNUM
    description: TXFNUM.
    bit_offset: 22
    bit_size: 4
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SODDFRM
    description: SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DIEPCTL8:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: TXFNUM
    description: TXFNUM.
    bit_offset: 22
    bit_size: 4
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SODDFRM
    description: SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DIEPDMA0:
  description: OTG device IN endpoint 0 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DIEPDMA1:
  description: OTG device IN endpoint 1 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DIEPDMA2:
  description: OTG device IN endpoint 2 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DIEPDMA3:
  description: OTG device IN endpoint 3 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DIEPDMA4:
  description: OTG device IN endpoint 4 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DIEPDMA5:
  description: OTG device IN endpoint 5 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DIEPDMA6:
  description: OTG device IN endpoint 6 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DIEPDMA7:
  description: OTG device IN endpoint 7 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DIEPDMA8:
  description: OTG device IN endpoint 8 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DIEPEMPMSK:
  description: This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx).
  fields:
  - name: INEPTXFEM
    description: INEPTXFEM.
    bit_offset: 0
    bit_size: 16
fieldset/DIEPINT0:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: TOC
    description: TOC.
    bit_offset: 3
    bit_size: 1
  - name: ITTXFE
    description: ITTXFE.
    bit_offset: 4
    bit_size: 1
  - name: INEPNM
    description: INEPNM.
    bit_offset: 5
    bit_size: 1
  - name: INEPNE
    description: INEPNE.
    bit_offset: 6
    bit_size: 1
  - name: TXFE
    description: TXFE.
    bit_offset: 7
    bit_size: 1
  - name: TXFIFOUDRN
    description: TXFIFOUDRN.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: PKTDRPSTS
    description: PKTDRPSTS.
    bit_offset: 11
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
fieldset/DIEPINT1:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: TOC
    description: TOC.
    bit_offset: 3
    bit_size: 1
  - name: ITTXFE
    description: ITTXFE.
    bit_offset: 4
    bit_size: 1
  - name: INEPNM
    description: INEPNM.
    bit_offset: 5
    bit_size: 1
  - name: INEPNE
    description: INEPNE.
    bit_offset: 6
    bit_size: 1
  - name: TXFE
    description: TXFE.
    bit_offset: 7
    bit_size: 1
  - name: TXFIFOUDRN
    description: TXFIFOUDRN.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: PKTDRPSTS
    description: PKTDRPSTS.
    bit_offset: 11
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
fieldset/DIEPINT2:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: TOC
    description: TOC.
    bit_offset: 3
    bit_size: 1
  - name: ITTXFE
    description: ITTXFE.
    bit_offset: 4
    bit_size: 1
  - name: INEPNM
    description: INEPNM.
    bit_offset: 5
    bit_size: 1
  - name: INEPNE
    description: INEPNE.
    bit_offset: 6
    bit_size: 1
  - name: TXFE
    description: TXFE.
    bit_offset: 7
    bit_size: 1
  - name: TXFIFOUDRN
    description: TXFIFOUDRN.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: PKTDRPSTS
    description: PKTDRPSTS.
    bit_offset: 11
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
fieldset/DIEPINT3:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: TOC
    description: TOC.
    bit_offset: 3
    bit_size: 1
  - name: ITTXFE
    description: ITTXFE.
    bit_offset: 4
    bit_size: 1
  - name: INEPNM
    description: INEPNM.
    bit_offset: 5
    bit_size: 1
  - name: INEPNE
    description: INEPNE.
    bit_offset: 6
    bit_size: 1
  - name: TXFE
    description: TXFE.
    bit_offset: 7
    bit_size: 1
  - name: TXFIFOUDRN
    description: TXFIFOUDRN.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: PKTDRPSTS
    description: PKTDRPSTS.
    bit_offset: 11
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
fieldset/DIEPINT4:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: TOC
    description: TOC.
    bit_offset: 3
    bit_size: 1
  - name: ITTXFE
    description: ITTXFE.
    bit_offset: 4
    bit_size: 1
  - name: INEPNM
    description: INEPNM.
    bit_offset: 5
    bit_size: 1
  - name: INEPNE
    description: INEPNE.
    bit_offset: 6
    bit_size: 1
  - name: TXFE
    description: TXFE.
    bit_offset: 7
    bit_size: 1
  - name: TXFIFOUDRN
    description: TXFIFOUDRN.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: PKTDRPSTS
    description: PKTDRPSTS.
    bit_offset: 11
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
fieldset/DIEPINT5:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: TOC
    description: TOC.
    bit_offset: 3
    bit_size: 1
  - name: ITTXFE
    description: ITTXFE.
    bit_offset: 4
    bit_size: 1
  - name: INEPNM
    description: INEPNM.
    bit_offset: 5
    bit_size: 1
  - name: INEPNE
    description: INEPNE.
    bit_offset: 6
    bit_size: 1
  - name: TXFE
    description: TXFE.
    bit_offset: 7
    bit_size: 1
  - name: TXFIFOUDRN
    description: TXFIFOUDRN.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: PKTDRPSTS
    description: PKTDRPSTS.
    bit_offset: 11
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
fieldset/DIEPINT6:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: TOC
    description: TOC.
    bit_offset: 3
    bit_size: 1
  - name: ITTXFE
    description: ITTXFE.
    bit_offset: 4
    bit_size: 1
  - name: INEPNM
    description: INEPNM.
    bit_offset: 5
    bit_size: 1
  - name: INEPNE
    description: INEPNE.
    bit_offset: 6
    bit_size: 1
  - name: TXFE
    description: TXFE.
    bit_offset: 7
    bit_size: 1
  - name: TXFIFOUDRN
    description: TXFIFOUDRN.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: PKTDRPSTS
    description: PKTDRPSTS.
    bit_offset: 11
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
fieldset/DIEPINT7:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: TOC
    description: TOC.
    bit_offset: 3
    bit_size: 1
  - name: ITTXFE
    description: ITTXFE.
    bit_offset: 4
    bit_size: 1
  - name: INEPNM
    description: INEPNM.
    bit_offset: 5
    bit_size: 1
  - name: INEPNE
    description: INEPNE.
    bit_offset: 6
    bit_size: 1
  - name: TXFE
    description: TXFE.
    bit_offset: 7
    bit_size: 1
  - name: TXFIFOUDRN
    description: TXFIFOUDRN.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: PKTDRPSTS
    description: PKTDRPSTS.
    bit_offset: 11
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
fieldset/DIEPINT8:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: TOC
    description: TOC.
    bit_offset: 3
    bit_size: 1
  - name: ITTXFE
    description: ITTXFE.
    bit_offset: 4
    bit_size: 1
  - name: INEPNM
    description: INEPNM.
    bit_offset: 5
    bit_size: 1
  - name: INEPNE
    description: INEPNE.
    bit_offset: 6
    bit_size: 1
  - name: TXFE
    description: TXFE.
    bit_offset: 7
    bit_size: 1
  - name: TXFIFOUDRN
    description: TXFIFOUDRN.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: PKTDRPSTS
    description: PKTDRPSTS.
    bit_offset: 11
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
fieldset/DIEPMSK:
  description: This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: EPDM
    description: EPDM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: TOM
    description: TOM.
    bit_offset: 3
    bit_size: 1
  - name: ITTXFEMSK
    description: ITTXFEMSK.
    bit_offset: 4
    bit_size: 1
  - name: INEPNMM
    description: INEPNMM.
    bit_offset: 5
    bit_size: 1
  - name: INEPNEM
    description: INEPNEM.
    bit_offset: 6
    bit_size: 1
  - name: TXFURM
    description: TXFURM.
    bit_offset: 8
    bit_size: 1
  - name: BNAM
    description: BNAM.
    bit_offset: 9
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 13
    bit_size: 1
fieldset/DIEPTSIZ0:
  description: The application must modify this register before enabling endpoint 0.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 7
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 2
fieldset/DIEPTSIZ1:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: MCNT
    description: MCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DIEPTSIZ2:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: MCNT
    description: MCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DIEPTSIZ3:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: MCNT
    description: MCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DIEPTSIZ4:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: MCNT
    description: MCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DIEPTSIZ5:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: MCNT
    description: MCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DIEPTSIZ6:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: MCNT
    description: MCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DIEPTSIZ7:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: MCNT
    description: MCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DIEPTSIZ8:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: MCNT
    description: MCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DIEPTXF1:
  description: OTG device IN endpoint transmit FIFO 1 size register.
  fields:
  - name: INEPTXSA
    description: INEPTXSA.
    bit_offset: 0
    bit_size: 16
  - name: INEPTXFD
    description: INEPTXFD.
    bit_offset: 16
    bit_size: 16
fieldset/DIEPTXF2:
  description: OTG device IN endpoint transmit FIFO 2 size register.
  fields:
  - name: INEPTXSA
    description: INEPTXSA.
    bit_offset: 0
    bit_size: 16
  - name: INEPTXFD
    description: INEPTXFD.
    bit_offset: 16
    bit_size: 16
fieldset/DIEPTXF3:
  description: OTG device IN endpoint transmit FIFO 3 size register.
  fields:
  - name: INEPTXSA
    description: INEPTXSA.
    bit_offset: 0
    bit_size: 16
  - name: INEPTXFD
    description: INEPTXFD.
    bit_offset: 16
    bit_size: 16
fieldset/DIEPTXF4:
  description: OTG device IN endpoint transmit FIFO 4 size register.
  fields:
  - name: INEPTXSA
    description: INEPTXSA.
    bit_offset: 0
    bit_size: 16
  - name: INEPTXFD
    description: INEPTXFD.
    bit_offset: 16
    bit_size: 16
fieldset/DIEPTXF5:
  description: OTG device IN endpoint transmit FIFO 5 size register.
  fields:
  - name: INEPTXSA
    description: INEPTXSA.
    bit_offset: 0
    bit_size: 16
  - name: INEPTXFD
    description: INEPTXFD.
    bit_offset: 16
    bit_size: 16
fieldset/DIEPTXF6:
  description: OTG device IN endpoint transmit FIFO 6 size register.
  fields:
  - name: INEPTXSA
    description: INEPTXSA.
    bit_offset: 0
    bit_size: 16
  - name: INEPTXFD
    description: INEPTXFD.
    bit_offset: 16
    bit_size: 16
fieldset/DIEPTXF7:
  description: OTG device IN endpoint transmit FIFO 7 size register.
  fields:
  - name: INEPTXSA
    description: INEPTXSA.
    bit_offset: 0
    bit_size: 16
  - name: INEPTXFD
    description: INEPTXFD.
    bit_offset: 16
    bit_size: 16
fieldset/DIEPTXF8:
  description: OTG device IN endpoint transmit FIFO 8 size register.
  fields:
  - name: INEPTXSA
    description: INEPTXSA.
    bit_offset: 0
    bit_size: 16
  - name: INEPTXFD
    description: INEPTXFD.
    bit_offset: 16
    bit_size: 16
fieldset/DOEPCTL0:
  description: This section describes the OTG_DOEPCTL0 register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 2
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: SNPM
    description: SNPM.
    bit_offset: 20
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DOEPCTL1:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: SNPM
    description: SNPM.
    bit_offset: 20
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SD1PID_SODDFRM
    description: SD1PID_SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DOEPCTL2:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: SNPM
    description: SNPM.
    bit_offset: 20
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SD1PID_SODDFRM
    description: SD1PID_SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DOEPCTL3:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: SNPM
    description: SNPM.
    bit_offset: 20
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SD1PID_SODDFRM
    description: SD1PID_SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DOEPCTL4:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: SNPM
    description: SNPM.
    bit_offset: 20
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SD1PID_SODDFRM
    description: SD1PID_SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DOEPCTL5:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: SNPM
    description: SNPM.
    bit_offset: 20
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SD1PID_SODDFRM
    description: SD1PID_SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DOEPCTL6:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: SNPM
    description: SNPM.
    bit_offset: 20
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SD1PID_SODDFRM
    description: SD1PID_SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DOEPCTL7:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: SNPM
    description: SNPM.
    bit_offset: 20
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SD1PID_SODDFRM
    description: SD1PID_SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DOEPCTL8:
  description: The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: USBAEP
    description: USBAEP.
    bit_offset: 15
    bit_size: 1
  - name: EONUM_DPIP
    description: EONUM_DPIP.
    bit_offset: 16
    bit_size: 1
  - name: NAKSTS
    description: NAKSTS.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: SNPM
    description: SNPM.
    bit_offset: 20
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 21
    bit_size: 1
  - name: CNAK
    description: CNAK.
    bit_offset: 26
    bit_size: 1
  - name: SNAK
    description: SNAK.
    bit_offset: 27
    bit_size: 1
  - name: SD0PID_SEVNFRM
    description: SD0PID_SEVNFRM.
    bit_offset: 28
    bit_size: 1
  - name: SD1PID_SODDFRM
    description: SD1PID_SODDFRM.
    bit_offset: 29
    bit_size: 1
  - name: EPDIS
    description: EPDIS.
    bit_offset: 30
    bit_size: 1
  - name: EPENA
    description: EPENA.
    bit_offset: 31
    bit_size: 1
fieldset/DOEPDMA0:
  description: OTG device OUT endpoint 0 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DOEPDMA1:
  description: OTG device OUT endpoint 1 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DOEPDMA2:
  description: OTG device OUT endpoint 2 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DOEPDMA3:
  description: OTG device OUT endpoint 3 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DOEPDMA4:
  description: OTG device OUT endpoint 4 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DOEPDMA5:
  description: OTG device OUT endpoint 5 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DOEPDMA6:
  description: OTG device OUT endpoint 6 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DOEPDMA7:
  description: OTG device OUT endpoint 7 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DOEPDMA8:
  description: OTG device OUT endpoint 8 DMA address register.
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/DOEPINT0:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STUP
    description: STUP.
    bit_offset: 3
    bit_size: 1
  - name: OTEPDIS
    description: OTEPDIS.
    bit_offset: 4
    bit_size: 1
  - name: STSPHSRX
    description: STSPHSRX.
    bit_offset: 5
    bit_size: 1
  - name: B2BSTUP
    description: B2BSTUP.
    bit_offset: 6
    bit_size: 1
  - name: OUTPKTERR
    description: OUTPKTERR.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: BERR
    description: BERR.
    bit_offset: 12
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 14
    bit_size: 1
  - name: STPKTRX
    description: STPKTRX.
    bit_offset: 15
    bit_size: 1
fieldset/DOEPINT1:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STUP
    description: STUP.
    bit_offset: 3
    bit_size: 1
  - name: OTEPDIS
    description: OTEPDIS.
    bit_offset: 4
    bit_size: 1
  - name: STSPHSRX
    description: STSPHSRX.
    bit_offset: 5
    bit_size: 1
  - name: B2BSTUP
    description: B2BSTUP.
    bit_offset: 6
    bit_size: 1
  - name: OUTPKTERR
    description: OUTPKTERR.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: BERR
    description: BERR.
    bit_offset: 12
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 14
    bit_size: 1
  - name: STPKTRX
    description: STPKTRX.
    bit_offset: 15
    bit_size: 1
fieldset/DOEPINT2:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STUP
    description: STUP.
    bit_offset: 3
    bit_size: 1
  - name: OTEPDIS
    description: OTEPDIS.
    bit_offset: 4
    bit_size: 1
  - name: STSPHSRX
    description: STSPHSRX.
    bit_offset: 5
    bit_size: 1
  - name: B2BSTUP
    description: B2BSTUP.
    bit_offset: 6
    bit_size: 1
  - name: OUTPKTERR
    description: OUTPKTERR.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: BERR
    description: BERR.
    bit_offset: 12
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 14
    bit_size: 1
  - name: STPKTRX
    description: STPKTRX.
    bit_offset: 15
    bit_size: 1
fieldset/DOEPINT3:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STUP
    description: STUP.
    bit_offset: 3
    bit_size: 1
  - name: OTEPDIS
    description: OTEPDIS.
    bit_offset: 4
    bit_size: 1
  - name: STSPHSRX
    description: STSPHSRX.
    bit_offset: 5
    bit_size: 1
  - name: B2BSTUP
    description: B2BSTUP.
    bit_offset: 6
    bit_size: 1
  - name: OUTPKTERR
    description: OUTPKTERR.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: BERR
    description: BERR.
    bit_offset: 12
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 14
    bit_size: 1
  - name: STPKTRX
    description: STPKTRX.
    bit_offset: 15
    bit_size: 1
fieldset/DOEPINT4:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STUP
    description: STUP.
    bit_offset: 3
    bit_size: 1
  - name: OTEPDIS
    description: OTEPDIS.
    bit_offset: 4
    bit_size: 1
  - name: STSPHSRX
    description: STSPHSRX.
    bit_offset: 5
    bit_size: 1
  - name: B2BSTUP
    description: B2BSTUP.
    bit_offset: 6
    bit_size: 1
  - name: OUTPKTERR
    description: OUTPKTERR.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: BERR
    description: BERR.
    bit_offset: 12
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 14
    bit_size: 1
  - name: STPKTRX
    description: STPKTRX.
    bit_offset: 15
    bit_size: 1
fieldset/DOEPINT5:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STUP
    description: STUP.
    bit_offset: 3
    bit_size: 1
  - name: OTEPDIS
    description: OTEPDIS.
    bit_offset: 4
    bit_size: 1
  - name: STSPHSRX
    description: STSPHSRX.
    bit_offset: 5
    bit_size: 1
  - name: B2BSTUP
    description: B2BSTUP.
    bit_offset: 6
    bit_size: 1
  - name: OUTPKTERR
    description: OUTPKTERR.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: BERR
    description: BERR.
    bit_offset: 12
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 14
    bit_size: 1
  - name: STPKTRX
    description: STPKTRX.
    bit_offset: 15
    bit_size: 1
fieldset/DOEPINT6:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STUP
    description: STUP.
    bit_offset: 3
    bit_size: 1
  - name: OTEPDIS
    description: OTEPDIS.
    bit_offset: 4
    bit_size: 1
  - name: STSPHSRX
    description: STSPHSRX.
    bit_offset: 5
    bit_size: 1
  - name: B2BSTUP
    description: B2BSTUP.
    bit_offset: 6
    bit_size: 1
  - name: OUTPKTERR
    description: OUTPKTERR.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: BERR
    description: BERR.
    bit_offset: 12
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 14
    bit_size: 1
  - name: STPKTRX
    description: STPKTRX.
    bit_offset: 15
    bit_size: 1
fieldset/DOEPINT7:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STUP
    description: STUP.
    bit_offset: 3
    bit_size: 1
  - name: OTEPDIS
    description: OTEPDIS.
    bit_offset: 4
    bit_size: 1
  - name: STSPHSRX
    description: STSPHSRX.
    bit_offset: 5
    bit_size: 1
  - name: B2BSTUP
    description: B2BSTUP.
    bit_offset: 6
    bit_size: 1
  - name: OUTPKTERR
    description: OUTPKTERR.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: BERR
    description: BERR.
    bit_offset: 12
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 14
    bit_size: 1
  - name: STPKTRX
    description: STPKTRX.
    bit_offset: 15
    bit_size: 1
fieldset/DOEPINT8:
  description: This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: EPDISD
    description: EPDISD.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STUP
    description: STUP.
    bit_offset: 3
    bit_size: 1
  - name: OTEPDIS
    description: OTEPDIS.
    bit_offset: 4
    bit_size: 1
  - name: STSPHSRX
    description: STSPHSRX.
    bit_offset: 5
    bit_size: 1
  - name: B2BSTUP
    description: B2BSTUP.
    bit_offset: 6
    bit_size: 1
  - name: OUTPKTERR
    description: OUTPKTERR.
    bit_offset: 8
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 9
    bit_size: 1
  - name: BERR
    description: BERR.
    bit_offset: 12
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 13
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 14
    bit_size: 1
  - name: STPKTRX
    description: STPKTRX.
    bit_offset: 15
    bit_size: 1
fieldset/DOEPMSK:
  description: This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: EPDM
    description: EPDM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STUPM
    description: STUPM.
    bit_offset: 3
    bit_size: 1
  - name: OTEPDM
    description: OTEPDM.
    bit_offset: 4
    bit_size: 1
  - name: STSPHSRXM
    description: STSPHSRXM.
    bit_offset: 5
    bit_size: 1
  - name: B2BSTUPM
    description: B2BSTUPM.
    bit_offset: 6
    bit_size: 1
  - name: OUTPKTERRM
    description: OUTPKTERRM.
    bit_offset: 8
    bit_size: 1
  - name: BNAM
    description: BNAM.
    bit_offset: 9
    bit_size: 1
  - name: BERRM
    description: BERRM.
    bit_offset: 12
    bit_size: 1
  - name: NAKMSK
    description: NAKMSK.
    bit_offset: 13
    bit_size: 1
  - name: NYETMSK
    description: NYETMSK.
    bit_offset: 14
    bit_size: 1
fieldset/DOEPTSIZ0:
  description: The application must modify this register before enabling endpoint 0.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 7
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 1
  - name: STUPCNT
    description: STUPCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DOEPTSIZ1:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: RXDPID_STUPCNT
    description: RXDPID_STUPCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DOEPTSIZ2:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: RXDPID_STUPCNT
    description: RXDPID_STUPCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DOEPTSIZ3:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: RXDPID_STUPCNT
    description: RXDPID_STUPCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DOEPTSIZ4:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: RXDPID_STUPCNT
    description: RXDPID_STUPCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DOEPTSIZ5:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: RXDPID_STUPCNT
    description: RXDPID_STUPCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DOEPTSIZ6:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: RXDPID_STUPCNT
    description: RXDPID_STUPCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DOEPTSIZ7:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: RXDPID_STUPCNT
    description: RXDPID_STUPCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DOEPTSIZ8:
  description: The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: RXDPID_STUPCNT
    description: RXDPID_STUPCNT.
    bit_offset: 29
    bit_size: 2
fieldset/DSTS:
  description: This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register.
  fields:
  - name: SUSPSTS
    description: SUSPSTS.
    bit_offset: 0
    bit_size: 1
  - name: ENUMSPD
    description: ENUMSPD.
    bit_offset: 1
    bit_size: 2
  - name: EERR
    description: EERR.
    bit_offset: 3
    bit_size: 1
  - name: FNSOF
    description: FNSOF.
    bit_offset: 8
    bit_size: 14
  - name: DEVLNSTS
    description: DEVLNSTS.
    bit_offset: 22
    bit_size: 2
fieldset/DTHRCTL:
  description: OTG device threshold control register.
  fields:
  - name: NONISOTHREN
    description: NONISOTHREN.
    bit_offset: 0
    bit_size: 1
  - name: ISOTHREN
    description: ISOTHREN.
    bit_offset: 1
    bit_size: 1
  - name: TXTHRLEN
    description: TXTHRLEN.
    bit_offset: 2
    bit_size: 9
  - name: RXTHREN
    description: RXTHREN.
    bit_offset: 16
    bit_size: 1
  - name: RXTHRLEN
    description: RXTHRLEN.
    bit_offset: 17
    bit_size: 9
  - name: ARPEN
    description: ARPEN.
    bit_offset: 27
    bit_size: 1
fieldset/DTXFSTS0:
  description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
  fields:
  - name: INEPTFSAV
    description: INEPTFSAV.
    bit_offset: 0
    bit_size: 16
fieldset/DTXFSTS1:
  description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
  fields:
  - name: INEPTFSAV
    description: INEPTFSAV.
    bit_offset: 0
    bit_size: 16
fieldset/DTXFSTS2:
  description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
  fields:
  - name: INEPTFSAV
    description: INEPTFSAV.
    bit_offset: 0
    bit_size: 16
fieldset/DTXFSTS3:
  description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
  fields:
  - name: INEPTFSAV
    description: INEPTFSAV.
    bit_offset: 0
    bit_size: 16
fieldset/DTXFSTS4:
  description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
  fields:
  - name: INEPTFSAV
    description: INEPTFSAV.
    bit_offset: 0
    bit_size: 16
fieldset/DTXFSTS5:
  description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
  fields:
  - name: INEPTFSAV
    description: INEPTFSAV.
    bit_offset: 0
    bit_size: 16
fieldset/DTXFSTS6:
  description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
  fields:
  - name: INEPTFSAV
    description: INEPTFSAV.
    bit_offset: 0
    bit_size: 16
fieldset/DTXFSTS7:
  description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
  fields:
  - name: INEPTFSAV
    description: INEPTFSAV.
    bit_offset: 0
    bit_size: 16
fieldset/DTXFSTS8:
  description: This read-only register contains the free space information for the device IN endpoint Tx FIFO.
  fields:
  - name: INEPTFSAV
    description: INEPTFSAV.
    bit_offset: 0
    bit_size: 16
fieldset/DVBUSDIS:
  description: This register specifies the VBUS discharge time after VBUS pulsing during SRP.
  fields:
  - name: VBUSDT
    description: VBUSDT.
    bit_offset: 0
    bit_size: 16
fieldset/DVBUSPULSE:
  description: This register specifies the VBUS pulsing time during SRP.
  fields:
  - name: DVBUSP
    description: DVBUSP.
    bit_offset: 0
    bit_size: 16
fieldset/GAHBCFG:
  description: This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
  fields:
  - name: GINTMSK
    description: GINTMSK.
    bit_offset: 0
    bit_size: 1
  - name: HBSTLEN
    description: HBSTLEN.
    bit_offset: 1
    bit_size: 4
  - name: DMAEN
    description: DMAEN.
    bit_offset: 5
    bit_size: 1
  - name: TXFELVL
    description: TXFELVL.
    bit_offset: 7
    bit_size: 1
  - name: PTXFELVL
    description: PTXFELVL.
    bit_offset: 8
    bit_size: 1
fieldset/GCCFG:
  description: OTG general core configuration register.
  fields:
  - name: PDET
    description: PDET.
    bit_offset: 1
    bit_size: 1
  - name: SDET
    description: SDET.
    bit_offset: 2
    bit_size: 1
  - name: PS2DET
    description: PS2DET.
    bit_offset: 3
    bit_size: 1
  - name: PWRDWN
    description: PWRDWN.
    bit_offset: 16
    bit_size: 1
  - name: BCDEN
    description: BCDEN.
    bit_offset: 17
    bit_size: 1
  - name: PDEN
    description: PDEN.
    bit_offset: 19
    bit_size: 1
  - name: SDEN
    description: SDEN.
    bit_offset: 20
    bit_size: 1
  - name: VBDEN
    description: VBDEN.
    bit_offset: 21
    bit_size: 1
  - name: IDEN
    description: IDEN.
    bit_offset: 22
    bit_size: 1
fieldset/GINTMSK:
  description: This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set.
  fields:
  - name: MMISM
    description: MMISM.
    bit_offset: 1
    bit_size: 1
  - name: OTGINT
    description: OTGINT.
    bit_offset: 2
    bit_size: 1
  - name: SOFM
    description: SOFM.
    bit_offset: 3
    bit_size: 1
  - name: RXFLVLM
    description: RXFLVLM.
    bit_offset: 4
    bit_size: 1
  - name: NPTXFEM
    description: NPTXFEM.
    bit_offset: 5
    bit_size: 1
  - name: GINAKEFFM
    description: GINAKEFFM.
    bit_offset: 6
    bit_size: 1
  - name: GONAKEFFM
    description: GONAKEFFM.
    bit_offset: 7
    bit_size: 1
  - name: ESUSPM
    description: ESUSPM.
    bit_offset: 10
    bit_size: 1
  - name: USBSUSPM
    description: USBSUSPM.
    bit_offset: 11
    bit_size: 1
  - name: USBRST
    description: USBRST.
    bit_offset: 12
    bit_size: 1
  - name: ENUMDNEM
    description: ENUMDNEM.
    bit_offset: 13
    bit_size: 1
  - name: ISOODRPM
    description: ISOODRPM.
    bit_offset: 14
    bit_size: 1
  - name: EOPFM
    description: EOPFM.
    bit_offset: 15
    bit_size: 1
  - name: IEPINT
    description: IEPINT.
    bit_offset: 18
    bit_size: 1
  - name: OEPINT
    description: OEPINT.
    bit_offset: 19
    bit_size: 1
  - name: IISOIXFRM
    description: IISOIXFRM.
    bit_offset: 20
    bit_size: 1
  - name: IPXFRM
    description: IPXFRM.
    bit_offset: 21
    bit_size: 1
  - name: FSUSPM
    description: FSUSPM.
    bit_offset: 22
    bit_size: 1
  - name: RSTDETM
    description: RSTDETM.
    bit_offset: 23
    bit_size: 1
  - name: PRTIM
    description: PRTIM.
    bit_offset: 24
    bit_size: 1
  - name: HCIM
    description: HCIM.
    bit_offset: 25
    bit_size: 1
  - name: PTXFEM
    description: PTXFEM.
    bit_offset: 26
    bit_size: 1
  - name: LPMINTM
    description: LPMINTM.
    bit_offset: 27
    bit_size: 1
  - name: CIDSCHGM
    description: CIDSCHGM.
    bit_offset: 28
    bit_size: 1
  - name: DISCINT
    description: DISCINT.
    bit_offset: 29
    bit_size: 1
  - name: SRQIM
    description: SRQIM.
    bit_offset: 30
    bit_size: 1
  - name: WUIM
    description: WUIM.
    bit_offset: 31
    bit_size: 1
fieldset/GINTSTS:
  description: This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.
  fields:
  - name: CMOD
    description: CMOD.
    bit_offset: 0
    bit_size: 1
  - name: MMIS
    description: MMIS.
    bit_offset: 1
    bit_size: 1
  - name: OTGINT
    description: OTGINT.
    bit_offset: 2
    bit_size: 1
  - name: SOF
    description: SOF.
    bit_offset: 3
    bit_size: 1
  - name: RXFLVL
    description: RXFLVL.
    bit_offset: 4
    bit_size: 1
  - name: NPTXFE
    description: NPTXFE.
    bit_offset: 5
    bit_size: 1
  - name: GINAKEFF
    description: GINAKEFF.
    bit_offset: 6
    bit_size: 1
  - name: GONAKEFF
    description: GONAKEFF.
    bit_offset: 7
    bit_size: 1
  - name: ESUSP
    description: ESUSP.
    bit_offset: 10
    bit_size: 1
  - name: USBSUSP
    description: USBSUSP.
    bit_offset: 11
    bit_size: 1
  - name: USBRST
    description: USBRST.
    bit_offset: 12
    bit_size: 1
  - name: ENUMDNE
    description: ENUMDNE.
    bit_offset: 13
    bit_size: 1
  - name: ISOODRP
    description: ISOODRP.
    bit_offset: 14
    bit_size: 1
  - name: EOPF
    description: EOPF.
    bit_offset: 15
    bit_size: 1
  - name: IEPINT
    description: IEPINT.
    bit_offset: 18
    bit_size: 1
  - name: OEPINT
    description: OEPINT.
    bit_offset: 19
    bit_size: 1
  - name: IISOIXFR
    description: IISOIXFR.
    bit_offset: 20
    bit_size: 1
  - name: IPXFR
    description: IPXFR.
    bit_offset: 21
    bit_size: 1
  - name: DATAFSUSP
    description: DATAFSUSP.
    bit_offset: 22
    bit_size: 1
  - name: HPRTINT
    description: HPRTINT.
    bit_offset: 24
    bit_size: 1
  - name: HCINT
    description: HCINT.
    bit_offset: 25
    bit_size: 1
  - name: PTXFE
    description: PTXFE.
    bit_offset: 26
    bit_size: 1
  - name: CIDSCHG
    description: CIDSCHG.
    bit_offset: 28
    bit_size: 1
  - name: DISCINT
    description: DISCINT.
    bit_offset: 29
    bit_size: 1
  - name: SRQINT
    description: SRQINT.
    bit_offset: 30
    bit_size: 1
  - name: WKUPINT
    description: WKUPINT.
    bit_offset: 31
    bit_size: 1
fieldset/GLPMCFG:
  description: OTG core LPM configuration register.
  fields:
  - name: LPMEN
    description: LPMEN.
    bit_offset: 0
    bit_size: 1
  - name: LPMACK
    description: LPMACK.
    bit_offset: 1
    bit_size: 1
  - name: BESL
    description: BESL.
    bit_offset: 2
    bit_size: 4
  - name: REMWAKE
    description: REMWAKE.
    bit_offset: 6
    bit_size: 1
  - name: L1SSEN
    description: L1SSEN.
    bit_offset: 7
    bit_size: 1
  - name: BESLTHRS
    description: BESLTHRS.
    bit_offset: 8
    bit_size: 4
  - name: L1DSEN
    description: L1DSEN.
    bit_offset: 12
    bit_size: 1
  - name: LPMRSP
    description: LPMRSP.
    bit_offset: 13
    bit_size: 2
  - name: SLPSTS
    description: SLPSTS.
    bit_offset: 15
    bit_size: 1
  - name: L1RSMOK
    description: L1RSMOK.
    bit_offset: 16
    bit_size: 1
  - name: LPMCHIDX
    description: LPMCHIDX.
    bit_offset: 17
    bit_size: 4
  - name: LPMRCNT
    description: LPMRCNT.
    bit_offset: 21
    bit_size: 3
  - name: SNDLPM
    description: SNDLPM.
    bit_offset: 24
    bit_size: 1
  - name: LPMRCNTSTS
    description: LPMRCNTSTS.
    bit_offset: 25
    bit_size: 3
  - name: ENBESL
    description: ENBESL.
    bit_offset: 28
    bit_size: 1
fieldset/GOTGCTL:
  description: The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.
  fields:
  - name: SRQSCS
    description: SRQSCS.
    bit_offset: 0
    bit_size: 1
  - name: SRQ
    description: SRQ.
    bit_offset: 1
    bit_size: 1
  - name: VBVALOEN
    description: VBVALOEN.
    bit_offset: 2
    bit_size: 1
  - name: VBVALOVAL
    description: VBVALOVAL.
    bit_offset: 3
    bit_size: 1
  - name: AVALOEN
    description: AVALOEN.
    bit_offset: 4
    bit_size: 1
  - name: AVALOVAL
    description: AVALOVAL.
    bit_offset: 5
    bit_size: 1
  - name: BVALOEN
    description: BVALOEN.
    bit_offset: 6
    bit_size: 1
  - name: BVALOVAL
    description: BVALOVAL.
    bit_offset: 7
    bit_size: 1
  - name: HNGSCS
    description: HNGSCS.
    bit_offset: 8
    bit_size: 1
  - name: HNPRQ
    description: HNPRQ.
    bit_offset: 9
    bit_size: 1
  - name: HSHNPEN
    description: HSHNPEN.
    bit_offset: 10
    bit_size: 1
  - name: DHNPEN
    description: DHNPEN.
    bit_offset: 11
    bit_size: 1
  - name: EHEN
    description: EHEN.
    bit_offset: 12
    bit_size: 1
  - name: CIDSTS
    description: CIDSTS.
    bit_offset: 16
    bit_size: 1
  - name: DBCT
    description: DBCT.
    bit_offset: 17
    bit_size: 1
  - name: ASVLD
    description: ASVLD.
    bit_offset: 18
    bit_size: 1
  - name: BSVLD
    description: BSVLD.
    bit_offset: 19
    bit_size: 1
  - name: OTGVER
    description: OTGVER.
    bit_offset: 20
    bit_size: 1
  - name: CURMOD
    description: CURMOD.
    bit_offset: 21
    bit_size: 1
fieldset/GOTGINT:
  description: The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
  fields:
  - name: SEDET
    description: SEDET.
    bit_offset: 2
    bit_size: 1
  - name: SRSSCHG
    description: SRSSCHG.
    bit_offset: 8
    bit_size: 1
  - name: HNSSCHG
    description: HNSSCHG.
    bit_offset: 9
    bit_size: 1
  - name: HNGDET
    description: HNGDET.
    bit_offset: 17
    bit_size: 1
  - name: ADTOCHG
    description: ADTOCHG.
    bit_offset: 18
    bit_size: 1
  - name: DBCDNE
    description: DBCDNE.
    bit_offset: 19
    bit_size: 1
  - name: IDCHNG
    description: IDCHNG.
    bit_offset: 20
    bit_size: 1
fieldset/GRSTCTL:
  description: The application uses this register to reset various hardware features inside the core.
  fields:
  - name: CSRST
    description: CSRST.
    bit_offset: 0
    bit_size: 1
  - name: PSRST
    description: PSRST.
    bit_offset: 1
    bit_size: 1
  - name: RXFFLSH
    description: RXFFLSH.
    bit_offset: 4
    bit_size: 1
  - name: TXFFLSH
    description: TXFFLSH.
    bit_offset: 5
    bit_size: 1
  - name: TXFNUM
    description: TXFNUM.
    bit_offset: 6
    bit_size: 5
  - name: DMAREQ
    description: DMAREQ.
    bit_offset: 30
    bit_size: 1
  - name: AHBIDL
    description: AHBIDL.
    bit_offset: 31
    bit_size: 1
fieldset/GRXFSIZ:
  description: The application can program the RAM size that must be allocated to the Rx FIFO.
  fields:
  - name: RXFD
    description: RXFD.
    bit_offset: 0
    bit_size: 16
fieldset/GRXSTSP:
  description: This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted.
  fields:
  - name: EPNUM
    description: EPNUM.
    bit_offset: 0
    bit_size: 4
  - name: BCNT
    description: BCNT.
    bit_offset: 4
    bit_size: 11
  - name: DPID
    description: DPID.
    bit_offset: 15
    bit_size: 2
  - name: PKTSTS
    description: PKTSTS.
    bit_offset: 17
    bit_size: 4
  - name: FRMNUM
    description: FRMNUM.
    bit_offset: 21
    bit_size: 4
  - name: STSPHST
    description: STSPHST.
    bit_offset: 27
    bit_size: 1
fieldset/GRXSTSR:
  description: This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000.
  fields:
  - name: EPNUM
    description: EPNUM.
    bit_offset: 0
    bit_size: 4
  - name: BCNT
    description: BCNT.
    bit_offset: 4
    bit_size: 11
  - name: DPID
    description: DPID.
    bit_offset: 15
    bit_size: 2
  - name: PKTSTS
    description: PKTSTS.
    bit_offset: 17
    bit_size: 4
  - name: FRMNUM
    description: FRMNUM.
    bit_offset: 21
    bit_size: 4
  - name: STSPHST
    description: STSPHST.
    bit_offset: 27
    bit_size: 1
fieldset/GUSBCFG:
  description: This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
  fields:
  - name: TOCAL
    description: TOCAL.
    bit_offset: 0
    bit_size: 3
  - name: PHYSEL
    description: PHYSEL.
    bit_offset: 6
    bit_size: 1
  - name: SRPCAP
    description: SRPCAP.
    bit_offset: 8
    bit_size: 1
  - name: HNPCAP
    description: HNPCAP.
    bit_offset: 9
    bit_size: 1
  - name: TRDT
    description: TRDT.
    bit_offset: 10
    bit_size: 4
  - name: PHYLPC
    description: PHYLPC.
    bit_offset: 15
    bit_size: 1
  - name: TSDPS
    description: TSDPS.
    bit_offset: 22
    bit_size: 1
  - name: FHMOD
    description: FHMOD.
    bit_offset: 29
    bit_size: 1
  - name: FDMOD
    description: FDMOD.
    bit_offset: 30
    bit_size: 1
fieldset/HAINT:
  description: When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.
  fields:
  - name: HAINT
    description: HAINT.
    bit_offset: 0
    bit_size: 16
fieldset/HAINTMSK:
  description: The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
  fields:
  - name: HAINTM
    description: HAINTM.
    bit_offset: 0
    bit_size: 16
fieldset/HCCHAR0:
  description: OTG host channel 0 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR1:
  description: OTG host channel 1 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR10:
  description: OTG host channel 10 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR11:
  description: OTG host channel 11 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR12:
  description: OTG host channel 12 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR13:
  description: OTG host channel 13 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR14:
  description: OTG host channel 14 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR15:
  description: OTG host channel 15 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR2:
  description: OTG host channel 2 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR3:
  description: OTG host channel 3 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR4:
  description: OTG host channel 4 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR5:
  description: OTG host channel 5 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR6:
  description: OTG host channel 6 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR7:
  description: OTG host channel 7 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR8:
  description: OTG host channel 8 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCCHAR9:
  description: OTG host channel 9 characteristics register.
  fields:
  - name: MPSIZ
    description: MPSIZ.
    bit_offset: 0
    bit_size: 11
  - name: EPNUM
    description: EPNUM.
    bit_offset: 11
    bit_size: 4
  - name: EPDIR
    description: EPDIR.
    bit_offset: 15
    bit_size: 1
  - name: LSDEV
    description: LSDEV.
    bit_offset: 17
    bit_size: 1
  - name: EPTYP
    description: EPTYP.
    bit_offset: 18
    bit_size: 2
  - name: MCNT
    description: MCNT.
    bit_offset: 20
    bit_size: 2
  - name: DAD
    description: DAD.
    bit_offset: 22
    bit_size: 7
  - name: CHDIS
    description: CHDIS.
    bit_offset: 30
    bit_size: 1
  - name: CHENA
    description: CHENA.
    bit_offset: 31
    bit_size: 1
fieldset/HCDMA0:
  description: OTG host channel 0 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA1:
  description: OTG host channel 1 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA10:
  description: OTG host channel 10 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA11:
  description: OTG host channel 11 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA12:
  description: OTG host channel 12 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA13:
  description: OTG host channel 13 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA14:
  description: OTG host channel 14 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA15:
  description: OTG host channel 15 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA2:
  description: OTG host channel 2 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA3:
  description: OTG host channel 3 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA4:
  description: OTG host channel 4 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA5:
  description: OTG host channel 5 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA6:
  description: OTG host channel 6 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA7:
  description: OTG host channel 7 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA8:
  description: OTG host channel 8 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMA9:
  description: OTG host channel 9 DMA address register in buffer DMA [alternate].
  fields:
  - name: DMAADDR
    description: DMAADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB0:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB1:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB10:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB11:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB12:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB13:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB14:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB15:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB2:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB3:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB4:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB5:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB6:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB7:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB8:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCDMAB9:
  description: OTG host channel-n DMA address buffer register.
  fields:
  - name: HCDMAB
    description: HCDMAB.
    bit_offset: 0
    bit_size: 32
fieldset/HCFG:
  description: This register configures the core after power-on. Do not make changes to this register after initializing the host.
  fields:
  - name: FSLSPCS
    description: FSLSPCS.
    bit_offset: 0
    bit_size: 2
  - name: FSLSS
    description: FSLSS.
    bit_offset: 2
    bit_size: 1
  - name: DESCDMA
    description: DESCDMA.
    bit_offset: 23
    bit_size: 1
  - name: FRLSTEN
    description: FRLSTEN.
    bit_offset: 24
    bit_size: 2
  - name: PERSSCHEDENA
    description: PERSSCHEDENA.
    bit_offset: 26
    bit_size: 1
fieldset/HCINT0:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT1:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT10:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT11:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT12:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT13:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT14:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT15:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT2:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT3:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT4:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT5:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT6:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT7:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT8:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINT9:
  description: This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.
  fields:
  - name: XFRC
    description: XFRC.
    bit_offset: 0
    bit_size: 1
  - name: CHH
    description: CHH.
    bit_offset: 1
    bit_size: 1
  - name: AHBERR
    description: AHBERR.
    bit_offset: 2
    bit_size: 1
  - name: STALL
    description: STALL.
    bit_offset: 3
    bit_size: 1
  - name: NAK
    description: NAK.
    bit_offset: 4
    bit_size: 1
  - name: ACK
    description: ACK.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERR
    description: TXERR.
    bit_offset: 7
    bit_size: 1
  - name: BBERR
    description: BBERR.
    bit_offset: 8
    bit_size: 1
  - name: FRMOR
    description: FRMOR.
    bit_offset: 9
    bit_size: 1
  - name: DTERR
    description: DTERR.
    bit_offset: 10
    bit_size: 1
  - name: BNA
    description: BNA.
    bit_offset: 11
    bit_size: 1
  - name: XCSXACTERR
    description: XCSXACTERR.
    bit_offset: 12
    bit_size: 1
  - name: DESCLSTROLL
    description: DESCLSTROLL.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK0:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK1:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK10:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK11:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK12:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK13:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK14:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK15:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK2:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK3:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK4:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK5:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK6:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK7:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK8:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCINTMSK9:
  description: This register reflects the mask for each channel status described in the previous section.
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: CHHM
    description: CHHM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STALLM
    description: STALLM.
    bit_offset: 3
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 4
    bit_size: 1
  - name: ACKM
    description: ACKM.
    bit_offset: 5
    bit_size: 1
  - name: NYET
    description: NYET.
    bit_offset: 6
    bit_size: 1
  - name: TXERRM
    description: TXERRM.
    bit_offset: 7
    bit_size: 1
  - name: BBERRM
    description: BBERRM.
    bit_offset: 8
    bit_size: 1
  - name: FRMORM
    description: FRMORM.
    bit_offset: 9
    bit_size: 1
  - name: DTERRM
    description: DTERRM.
    bit_offset: 10
    bit_size: 1
  - name: BNAMSK
    description: BNAMSK.
    bit_offset: 11
    bit_size: 1
  - name: DESCLSTROLLMSK
    description: DESCLSTROLLMSK.
    bit_offset: 13
    bit_size: 1
fieldset/HCSPLT0:
  description: OTG host channel 0 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT1:
  description: OTG host channel 1 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT10:
  description: OTG host channel 10 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT11:
  description: OTG host channel 11 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT12:
  description: OTG host channel 12 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT13:
  description: OTG host channel 13 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT14:
  description: OTG host channel 14 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT15:
  description: OTG host channel 15 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT2:
  description: OTG host channel 2 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT3:
  description: OTG host channel 3 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT4:
  description: OTG host channel 4 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT5:
  description: OTG host channel 5 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT6:
  description: OTG host channel 6 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT7:
  description: OTG host channel 7 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT8:
  description: OTG host channel 8 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCSPLT9:
  description: OTG host channel 9 split control register.
  fields:
  - name: PRTADDR
    description: PRTADDR.
    bit_offset: 0
    bit_size: 7
  - name: HUBADDR
    description: HUBADDR.
    bit_offset: 7
    bit_size: 7
  - name: XACTPOS
    description: XACTPOS.
    bit_offset: 14
    bit_size: 2
  - name: COMPLSPLT
    description: COMPLSPLT.
    bit_offset: 16
    bit_size: 1
  - name: SPLITEN
    description: SPLITEN.
    bit_offset: 31
    bit_size: 1
fieldset/HCTSIZ0:
  description: OTG host channel 0 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ1:
  description: OTG host channel 1 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ10:
  description: OTG host channel 10 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ11:
  description: OTG host channel 11 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ12:
  description: OTG host channel 12 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ13:
  description: OTG host channel 13 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ14:
  description: OTG host channel 14 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ15:
  description: OTG host channel 15 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ2:
  description: OTG host channel 2 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ3:
  description: OTG host channel 3 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ4:
  description: OTG host channel 4 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ5:
  description: OTG host channel 5 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ6:
  description: OTG host channel 6 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ7:
  description: OTG host channel 7 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ8:
  description: OTG host channel 8 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HCTSIZ9:
  description: OTG host channel 9 transfer size register.
  fields:
  - name: XFRSIZ
    description: XFRSIZ.
    bit_offset: 0
    bit_size: 19
  - name: PKTCNT
    description: PKTCNT.
    bit_offset: 19
    bit_size: 10
  - name: DPID
    description: DPID.
    bit_offset: 29
    bit_size: 2
fieldset/HFIR:
  description: This register stores the frame interval information for the current speed to which the OTG controller has enumerated.
  fields:
  - name: FRIVL
    description: FRIVL.
    bit_offset: 0
    bit_size: 16
  - name: RLDCTRL
    description: RLDCTRL.
    bit_offset: 16
    bit_size: 1
fieldset/HFLBADDR:
  description: This register holds the starting address of the frame list information (scatter/gather mode).
  fields:
  - name: HFLBADDR
    description: HFLBADDR.
    bit_offset: 0
    bit_size: 32
fieldset/HFNUM:
  description: This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.
  fields:
  - name: FRNUM
    description: FRNUM.
    bit_offset: 0
    bit_size: 16
  - name: FTREM
    description: FTREM.
    bit_offset: 16
    bit_size: 16
fieldset/HNPTXFSIZ:
  description: Host mode.
  fields:
  - name: NPTXFSA
    description: NPTXFSA.
    bit_offset: 0
    bit_size: 16
  - name: NPTXFD
    description: NPTXFD.
    bit_offset: 16
    bit_size: 16
fieldset/HNPTXSTS:
  description: In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue.
  fields:
  - name: NPTXFSAV
    description: NPTXFSAV.
    bit_offset: 0
    bit_size: 16
  - name: NPTQXSAV
    description: NPTQXSAV.
    bit_offset: 16
    bit_size: 8
  - name: NPTXQTOP
    description: NPTXQTOP.
    bit_offset: 24
    bit_size: 7
fieldset/HPRT:
  description: This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
  fields:
  - name: PCSTS
    description: PCSTS.
    bit_offset: 0
    bit_size: 1
  - name: PCDET
    description: PCDET.
    bit_offset: 1
    bit_size: 1
  - name: PENA
    description: PENA.
    bit_offset: 2
    bit_size: 1
  - name: PENCHNG
    description: PENCHNG.
    bit_offset: 3
    bit_size: 1
  - name: POCA
    description: POCA.
    bit_offset: 4
    bit_size: 1
  - name: POCCHNG
    description: POCCHNG.
    bit_offset: 5
    bit_size: 1
  - name: PRES
    description: PRES.
    bit_offset: 6
    bit_size: 1
  - name: PSUSP
    description: PSUSP.
    bit_offset: 7
    bit_size: 1
  - name: PRST
    description: PRST.
    bit_offset: 8
    bit_size: 1
  - name: PLSTS
    description: PLSTS.
    bit_offset: 10
    bit_size: 2
  - name: PPWR
    description: PPWR.
    bit_offset: 12
    bit_size: 1
  - name: PTCTL
    description: PTCTL.
    bit_offset: 13
    bit_size: 4
  - name: PSPD
    description: PSPD.
    bit_offset: 17
    bit_size: 2
fieldset/HPTXFSIZ:
  description: OTG host periodic transmit FIFO size register.
  fields:
  - name: PTXSA
    description: PTXSA.
    bit_offset: 0
    bit_size: 16
  - name: PTXFSIZ
    description: PTXFSIZ.
    bit_offset: 16
    bit_size: 16
fieldset/HPTXSTS:
  description: This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue.
  fields:
  - name: PTXFSAVL
    description: PTXFSAVL.
    bit_offset: 0
    bit_size: 16
  - name: PTXQSAV
    description: PTXQSAV.
    bit_offset: 16
    bit_size: 8
  - name: PTXQTOP
    description: PTXQTOP.
    bit_offset: 24
    bit_size: 8
fieldset/HS_DIEPEACHMSK1:
  description: 'This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.'
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: EPDM
    description: EPDM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: TOM
    description: TOM.
    bit_offset: 3
    bit_size: 1
  - name: ITTXFEMSK
    description: ITTXFEMSK.
    bit_offset: 4
    bit_size: 1
  - name: INEPNEM
    description: INEPNEM.
    bit_offset: 6
    bit_size: 1
  - name: TXFURM
    description: TXFURM.
    bit_offset: 8
    bit_size: 1
  - name: BNAM
    description: BNAM.
    bit_offset: 9
    bit_size: 1
  - name: NAKM
    description: NAKM.
    bit_offset: 13
    bit_size: 1
fieldset/HS_DOEPEACHMSK1:
  description: 'This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.'
  fields:
  - name: XFRCM
    description: XFRCM.
    bit_offset: 0
    bit_size: 1
  - name: EPDM
    description: EPDM.
    bit_offset: 1
    bit_size: 1
  - name: AHBERRM
    description: AHBERRM.
    bit_offset: 2
    bit_size: 1
  - name: STUPM
    description: STUPM.
    bit_offset: 3
    bit_size: 1
  - name: OTEPDM
    description: OTEPDM.
    bit_offset: 4
    bit_size: 1
  - name: B2BSTUPM
    description: B2BSTUPM.
    bit_offset: 6
    bit_size: 1
  - name: OUTPKTERRM
    description: OUTPKTERRM.
    bit_offset: 8
    bit_size: 1
  - name: BNAM
    description: BNAM.
    bit_offset: 9
    bit_size: 1
  - name: BERRM
    description: BERRM.
    bit_offset: 12
    bit_size: 1
  - name: NAKMSK
    description: NAKMSK.
    bit_offset: 13
    bit_size: 1
  - name: NYETMSK
    description: NYETMSK.
    bit_offset: 14
    bit_size: 1
fieldset/PCGCCTL:
  description: This register is available in host and device modes.
  fields:
  - name: STPPCLK
    description: STPPCLK.
    bit_offset: 0
    bit_size: 1
  - name: GATEHCLK
    description: GATEHCLK.
    bit_offset: 1
    bit_size: 1
  - name: PHYSUSP
    description: PHYSUSP.
    bit_offset: 4
    bit_size: 1
  - name: ENL1GTG
    description: ENL1GTG.
    bit_offset: 5
    bit_size: 1
  - name: PHYSLEEP
    description: PHYSLEEP.
    bit_offset: 6
    bit_size: 1
  - name: SUSP
    description: SUSP.
    bit_offset: 7
    bit_size: 1