block/PWR:
  description: Power control.
  items:
  - name: CR
    description: Power control register (PWR_CR).
    byte_offset: 0
    fieldset: CR
  - name: CSR
    description: Power control register (PWR_CR).
    byte_offset: 4
    fieldset: CSR
fieldset/CR:
  description: Power control register (PWR_CR).
  fields:
  - name: LPDS
    description: Low Power Deep Sleep.
    bit_offset: 0
    bit_size: 1
  - name: PDDS
    description: Power Down Deep Sleep.
    bit_offset: 1
    bit_size: 1
    enum: PDDS
  - name: CWUF
    description: Clear Wake-up Flag.
    bit_offset: 2
    bit_size: 1
  - name: CSBF
    description: Clear STANDBY Flag.
    bit_offset: 3
    bit_size: 1
  - name: PVDE
    description: Power Voltage Detector Enable.
    bit_offset: 4
    bit_size: 1
  - name: PLS
    description: PVD Level Selection.
    bit_offset: 5
    bit_size: 3
  - name: DBP
    description: Disable Backup Domain write protection.
    bit_offset: 8
    bit_size: 1
fieldset/CSR:
  description: Power control register (PWR_CR).
  fields:
  - name: WUF
    description: Wake-Up Flag.
    bit_offset: 0
    bit_size: 1
  - name: SBF
    description: STANDBY Flag.
    bit_offset: 1
    bit_size: 1
  - name: PVDO
    description: PVD Output.
    bit_offset: 2
    bit_size: 1
  - name: EWUP
    description: Enable WKUP pin.
    bit_offset: 8
    bit_size: 1
enum/PDDS:
  bit_size: 1
  variants:
  - name: STOP_MODE
    description: Enter Stop mode when the CPU enters deepsleep.
    value: 0
  - name: STANDBY_MODE
    description: Enter Standby mode when the CPU enters deepsleep.
    value: 1