block/USART1: description: USART register block. items: - name: CR1 description: USART control register 1 [alternate]. byte_offset: 0 fieldset: CR1 - name: CR2 description: USART control register 2. byte_offset: 4 fieldset: CR2 - name: CR3 description: USART control register 3. byte_offset: 8 fieldset: CR3 - name: BRR description: USART baud rate register. byte_offset: 12 fieldset: BRR - name: GTPR description: USART guard time and prescaler register. byte_offset: 16 fieldset: GTPR - name: RTOR description: USART receiver timeout register. byte_offset: 20 fieldset: RTOR - name: RQR description: USART request register. byte_offset: 24 fieldset: RQR - name: ISR description: USART interrupt and status register [alternate]. byte_offset: 28 fieldset: ISR - name: ICR description: USART interrupt flag clear register. byte_offset: 32 fieldset: ICR - name: RDR description: USART receive data register. byte_offset: 36 fieldset: RDR - name: TDR description: USART transmit data register. byte_offset: 40 fieldset: TDR - name: PRESC description: USART prescaler register. byte_offset: 44 fieldset: PRESC fieldset/BRR: description: USART baud rate register. fields: - name: BRR description: 'USART baud rate BRR[15:4] BRR[15:4] = USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared.' bit_offset: 0 bit_size: 16 fieldset/CR1: description: USART control register 1 [alternate]. fields: - name: UE description: 'USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value.' bit_offset: 0 bit_size: 1 enum: UE - name: UESM description: 'USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985.' bit_offset: 1 bit_size: 1 enum: UESM - name: RE description: Receiver enable This bit enables the receiver. It is set and cleared by software. bit_offset: 2 bit_size: 1 enum: RE - name: TE description: 'Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.' bit_offset: 3 bit_size: 1 enum: TE - name: IDLEIE description: IDLE interrupt enable This bit is set and cleared by software. bit_offset: 4 bit_size: 1 enum: IDLEIE - name: RXNEIE description: RXFIFO not empty interrupt enable This bit is set and cleared by software. bit_offset: 5 bit_size: 1 enum: RXNEIE - name: TCIE description: Transmission complete interrupt enable This bit is set and cleared by software. bit_offset: 6 bit_size: 1 enum: TCIE - name: TXEIE description: TXFIFO not full interrupt enable This bit is set and cleared by software. bit_offset: 7 bit_size: 1 enum: TXEIE - name: PEIE description: PE interrupt enable This bit is set and cleared by software. bit_offset: 8 bit_size: 1 enum: PEIE - name: PS description: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0). bit_offset: 9 bit_size: 1 enum: PS - name: PCE description: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0). bit_offset: 10 bit_size: 1 enum: PCE - name: WAKE description: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). bit_offset: 11 bit_size: 1 enum: WAKE - name: M0 description: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0). bit_offset: 12 bit_size: 1 enum: M0 - name: MME description: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software. bit_offset: 13 bit_size: 1 enum: MME - name: CMIE description: Character match interrupt enable This bit is set and cleared by software. bit_offset: 14 bit_size: 1 enum: CMIE - name: OVER8 description: 'Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.' bit_offset: 15 bit_size: 1 enum: OVER8 - name: DEDT description: 'Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 16 bit_size: 5 - name: DEAT description: 'Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 21 bit_size: 5 - name: RTOIE description: 'Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value..' bit_offset: 26 bit_size: 1 enum: RTOIE - name: EOBIE description: 'End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 27 bit_size: 1 enum: EOBIE - name: M1 description: 'Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported.' bit_offset: 28 bit_size: 1 enum: M1 - name: FIFOEN description: 'FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.' bit_offset: 29 bit_size: 1 enum: FIFOEN - name: TXFEIE description: TXFIFO empty interrupt enable This bit is set and cleared by software. bit_offset: 30 bit_size: 1 enum: TXFEIE - name: RXFFIE description: RXFIFO Full interrupt enable This bit is set and cleared by software. bit_offset: 31 bit_size: 1 enum: RXFFIE fieldset/CR2: description: USART control register 2. fields: - name: SLVEN description: 'Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 0 bit_size: 1 enum: SLVEN - name: DIS_NSS description: 'When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 3 bit_size: 1 enum: DIS_NSS - name: ADDM7 description: '7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.' bit_offset: 4 bit_size: 1 enum: ADDM7 - name: LBDL description: 'LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 5 bit_size: 1 enum: LBDL - name: LBDIE description: 'LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 6 bit_size: 1 enum: LBDIE - name: LBCL description: 'Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 8 bit_size: 1 enum: LBCL - name: CPHA description: 'Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 9 bit_size: 1 enum: CPHA - name: CPOL description: 'Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 10 bit_size: 1 enum: CPOL - name: CLKEN description: 'Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.' bit_offset: 11 bit_size: 1 enum: CLKEN - name: STOP description: stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0). bit_offset: 12 bit_size: 2 enum: STOP - name: LINEN description: 'LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 14 bit_size: 1 enum: LINEN - name: SWAP description: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). bit_offset: 15 bit_size: 1 enum: SWAP - name: RXINV description: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0). bit_offset: 16 bit_size: 1 enum: RXINV - name: TXINV description: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0). bit_offset: 17 bit_size: 1 enum: TXINV - name: DATAINV description: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). bit_offset: 18 bit_size: 1 enum: DATAINV - name: MSBFIRST description: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). bit_offset: 19 bit_size: 1 enum: MSBFIRST - name: ABREN description: 'Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 20 bit_size: 1 enum: ABREN - name: ABRMOD description: 'Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 21 bit_size: 2 enum: ABRMOD - name: RTOEN description: 'Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 23 bit_size: 1 enum: RTOEN - name: ADD description: 'Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0).' bit_offset: 24 bit_size: 8 fieldset/CR3: description: USART control register 3. fields: - name: EIE description: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register). bit_offset: 0 bit_size: 1 enum: EIE - name: IREN description: 'IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 1 bit_size: 1 enum: IREN - name: IRLP description: 'IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 2 bit_size: 1 enum: IRLP - name: HDSEL description: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0). bit_offset: 3 bit_size: 1 enum: HDSEL - name: NACK description: 'Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 4 bit_size: 1 enum: NACK - name: SCEN description: 'Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 5 bit_size: 1 enum: SCEN - name: DMAR description: DMA enable receiver This bit is set/reset by software. bit_offset: 6 bit_size: 1 enum: DMAR - name: DMAT description: DMA enable transmitter This bit is set/reset by software. bit_offset: 7 bit_size: 1 enum: DMAT - name: RTSE description: 'RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 8 bit_size: 1 enum: RTSE - name: CTSE description: 'CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 9 bit_size: 1 enum: CTSE - name: CTSIE description: 'CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 10 bit_size: 1 enum: CTSIE - name: ONEBIT description: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0). bit_offset: 11 bit_size: 1 enum: ONEBIT - name: OVRDIS description: 'Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.' bit_offset: 12 bit_size: 1 enum: OVRDIS - name: DDRE description: 'DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.' bit_offset: 13 bit_size: 1 enum: DDRE - name: DEM description: 'Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value..' bit_offset: 14 bit_size: 1 enum: DEM - name: DEP description: 'Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 15 bit_size: 1 enum: DEP - name: SCARCNT description: 'Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 17 bit_size: 3 - name: WUS description: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985. bit_offset: 20 bit_size: 2 enum: WUS - name: WUFIE description: 'Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985.' bit_offset: 22 bit_size: 1 enum: WUFIE - name: TXFTIE description: TXFIFO threshold interrupt enable This bit is set and cleared by software. bit_offset: 23 bit_size: 1 enum: TXFTIE - name: TCBGTIE description: 'Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 24 bit_size: 1 enum: TCBGTIE - name: RXFTCFG description: 'Receive FIFO threshold configuration Remaining combinations: Reserved.' bit_offset: 25 bit_size: 3 enum: RXFTCFG - name: RXFTIE description: RXFIFO threshold interrupt enable This bit is set and cleared by software. bit_offset: 28 bit_size: 1 enum: RXFTIE - name: TXFTCFG description: 'TXFIFO threshold configuration Remaining combinations: Reserved.' bit_offset: 29 bit_size: 3 enum: TXFTCFG fieldset/GTPR: description: USART guard time and prescaler register. fields: - name: PSC description: 'Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0] = Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... ... This bitfield can only be written when the USART is disabled (UE = 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to 0 when the Smartcard and IrDA modes are not supported. Refer to.' bit_offset: 0 bit_size: 8 - name: GT description: 'Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 8 bit_size: 8 fieldset/ICR: description: USART interrupt flag clear register. fields: - name: PECF description: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register. bit_offset: 0 bit_size: 1 enum: PECF - name: FECF description: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register. bit_offset: 1 bit_size: 1 enum: FECF - name: NECF description: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register. bit_offset: 2 bit_size: 1 enum: NECF - name: ORECF description: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register. bit_offset: 3 bit_size: 1 enum: ORECF - name: IDLECF description: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register. bit_offset: 4 bit_size: 1 enum: IDLECF - name: TXFECF description: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register. bit_offset: 5 bit_size: 1 enum: TXFECF - name: TCCF description: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register. bit_offset: 6 bit_size: 1 enum: TCCF - name: TCBGTCF description: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. bit_offset: 7 bit_size: 1 enum: TCBGTCF - name: LBDCF description: 'LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 8 bit_size: 1 enum: LBDCF - name: CTSCF description: 'CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 9 bit_size: 1 enum: CTSCF - name: RTOCF description: 'Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to page 1985.' bit_offset: 11 bit_size: 1 enum: RTOCF - name: EOBCF description: 'End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 12 bit_size: 1 enum: EOBCF - name: UDRCF description: 'SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 13 bit_size: 1 enum: UDRCF - name: CMCF description: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register. bit_offset: 17 bit_size: 1 enum: CMCF - name: WUCF description: 'Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 1985.' bit_offset: 20 bit_size: 1 enum: WUCF fieldset/ISR: description: USART interrupt and status register [alternate]. fields: - name: PE description: 'Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.' bit_offset: 0 bit_size: 1 enum: PE - name: FE description: 'Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.' bit_offset: 1 bit_size: 1 enum: FE - name: NE description: 'Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 2012). This error is associated with the character in the USART_RDR.' bit_offset: 2 bit_size: 1 enum: NE - name: ORE description: 'Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.' bit_offset: 3 bit_size: 1 enum: ORE - name: IDLE description: 'Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set.' bit_offset: 4 bit_size: 1 enum: IDLE - name: RXFNE description: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register. bit_offset: 5 bit_size: 1 enum: RXFNE - name: TC description: 'Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.' bit_offset: 6 bit_size: 1 enum: TC - name: TXFNF description: 'TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission.' bit_offset: 7 bit_size: 1 enum: TXFNF - name: LBDF description: 'LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to.' bit_offset: 8 bit_size: 1 enum: LBDF - name: CTSIF description: 'CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.' bit_offset: 9 bit_size: 1 enum: CTSIF - name: CTS description: 'CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.' bit_offset: 10 bit_size: 1 enum: CTS - name: RTOF description: 'Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.' bit_offset: 11 bit_size: 1 enum: RTOF - name: EOBF description: 'End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to.' bit_offset: 12 bit_size: 1 enum: EOBF - name: UDR description: 'SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to.' bit_offset: 13 bit_size: 1 enum: UDR - name: ABRE description: 'Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.' bit_offset: 14 bit_size: 1 - name: ABRF description: 'Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.' bit_offset: 15 bit_size: 1 - name: BUSY description: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not). bit_offset: 16 bit_size: 1 enum: BUSY - name: CMF description: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register. bit_offset: 17 bit_size: 1 enum: CMF - name: SBKF description: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission. bit_offset: 18 bit_size: 1 enum: SBKF - name: RWU description: 'Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to.' bit_offset: 19 bit_size: 1 enum: RWU - name: WUF description: 'Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to.' bit_offset: 20 bit_size: 1 - name: TEACK description: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period. bit_offset: 21 bit_size: 1 - name: REACK description: 'Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to.' bit_offset: 22 bit_size: 1 - name: TXFE description: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register. bit_offset: 23 bit_size: 1 enum: TXFE - name: RXFF description: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register. bit_offset: 24 bit_size: 1 enum: RXFF - name: TCBGT description: 'Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is 1. Refer to on page 1985.' bit_offset: 25 bit_size: 1 enum: TCBGT - name: RXFT description: 'RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.' bit_offset: 26 bit_size: 1 enum: RXFT - name: TXFT description: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register. bit_offset: 27 bit_size: 1 enum: TXFT fieldset/PRESC: description: USART prescaler register. fields: - name: PRESCALER description: 'Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.' bit_offset: 0 bit_size: 4 enum: PRESCALER fieldset/RDR: description: USART receive data register. fields: - name: RDR description: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see ). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit. bit_offset: 0 bit_size: 9 fieldset/RQR: description: USART request register. fields: - name: ABRRQ description: 'Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to.' bit_offset: 0 bit_size: 1 enum: ABRRQ - name: SBKRQ description: 'Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.' bit_offset: 1 bit_size: 1 enum: SBKRQ - name: MMRQ description: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag. bit_offset: 2 bit_size: 1 enum: MMRQ - name: RXFRQ description: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition. bit_offset: 3 bit_size: 1 enum: RXFRQ - name: TXFRQ description: 'Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.' bit_offset: 4 bit_size: 1 enum: TXFRQ fieldset/RTOR: description: USART receiver timeout register. fields: - name: RTO description: 'Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character.' bit_offset: 0 bit_size: 24 - name: BLEN description: 'Block Length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block.' bit_offset: 24 bit_size: 8 fieldset/TDR: description: USART transmit data register. fields: - name: TDR description: 'Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1.' bit_offset: 0 bit_size: 9 enum/ABREN: bit_size: 1 variants: - name: Disabled description: Auto baud rate detection is disabled. value: 0 - name: Enabled description: Auto baud rate detection is enabled. value: 1 enum/ABRMOD: bit_size: 2 variants: - name: Start description: Measurement of the start bit is used to detect the baud rate. value: 0 - name: Edge description: Falling edge to falling edge measurement. value: 1 - name: Frame7F description: 0x7F frame detection. value: 2 - name: Frame55 description: 0x55 frame detection. value: 3 enum/ABRRQ: bit_size: 1 variants: - name: Request description: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame. value: 1 enum/ADDM7: bit_size: 1 variants: - name: Bit4 description: 4-bit address detection. value: 0 - name: Bit7 description: 7-bit address detection. value: 1 enum/BUSY: bit_size: 1 variants: - name: Idle description: USART is idle (no reception). value: 0 - name: Busy description: Reception on going. value: 1 enum/CLKEN: bit_size: 1 variants: - name: Disabled description: CK pin disabled. value: 0 - name: Enabled description: CK pin enabled. value: 1 enum/CMCF: bit_size: 1 variants: - name: Clear description: Clears the CMF flag in the ISR register. value: 1 enum/CMF: bit_size: 1 variants: - name: NoMatch description: No Character match detected. value: 0 - name: Match description: Character match detected. value: 1 enum/CMIE: bit_size: 1 variants: - name: Disabled description: Interrupt is disabled. value: 0 - name: Enabled description: Interrupt is generated when the CMF bit is set in the ISR register. value: 1 enum/CPHA: bit_size: 1 variants: - name: First description: The first clock transition is the first data capture edge. value: 0 - name: Second description: The second clock transition is the first data capture edge. value: 1 enum/CPOL: bit_size: 1 variants: - name: Low description: Steady low value on CK pin outside transmission window. value: 0 - name: High description: Steady high value on CK pin outside transmission window. value: 1 enum/CTS: bit_size: 1 variants: - name: Set description: CTS line set. value: 0 - name: Reset description: CTS line reset. value: 1 enum/CTSCF: bit_size: 1 variants: - name: Clear description: Clears the CTSIF flag in the ISR register. value: 1 enum/CTSE: bit_size: 1 variants: - name: Disabled description: CTS hardware flow control disabled. value: 0 - name: Enabled description: CTS mode enabled, data is only transmitted when the CTS input is asserted. value: 1 enum/CTSIE: bit_size: 1 variants: - name: Disabled description: Interrupt is inhibited. value: 0 - name: Enabled description: An interrupt is generated whenever CTSIF=1 in the ISR register. value: 1 enum/CTSIF: bit_size: 1 variants: - name: NotChanged description: No change occurred on the CTS status line. value: 0 - name: Changed description: A change occurred on the CTS status line. value: 1 enum/DATAINV: bit_size: 1 variants: - name: Positive description: Logical data from the data register are send/received in positive/direct logic. value: 0 - name: Negative description: Logical data from the data register are send/received in negative/inverse logic. value: 1 enum/DDRE: bit_size: 1 variants: - name: NotDisabled description: DMA is not disabled in case of reception error. value: 0 - name: Disabled description: DMA is disabled following a reception error. value: 1 enum/DEM: bit_size: 1 variants: - name: Disabled description: DE function is disabled. value: 0 - name: Enabled description: The DE signal is output on the RTS pin. value: 1 enum/DEP: bit_size: 1 variants: - name: High description: DE signal is active high. value: 0 - name: Low description: DE signal is active low. value: 1 enum/DIS_NSS: bit_size: 1 variants: - name: Disabled description: SPI slave selection depends on NSS input pin. value: 0 - name: Enabled description: SPI slave is always selected and NSS input pin is ignored. value: 1 enum/DMAR: bit_size: 1 variants: - name: Disabled description: DMA mode is disabled for reception. value: 0 - name: Enabled description: DMA mode is enabled for reception. value: 1 enum/DMAT: bit_size: 1 variants: - name: Disabled description: DMA mode is disabled for transmission. value: 0 - name: Enabled description: DMA mode is enabled for transmission. value: 1 enum/EIE: bit_size: 1 variants: - name: Disabled description: Interrupt is inhibited. value: 0 - name: Enabled description: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register. value: 1 enum/EOBCF: bit_size: 1 variants: - name: Clear description: Clears the EOBF flag in the ISR register. value: 1 enum/EOBF: bit_size: 1 variants: - name: NotReached description: End of Block not reached. value: 0 - name: Reached description: End of Block (number of characters) reached. value: 1 enum/EOBIE: bit_size: 1 variants: - name: Disabled description: Interrupt is inhibited. value: 0 - name: Enabled description: A USART interrupt is generated when the EOBF flag is set in the ISR register. value: 1 enum/FE: bit_size: 1 variants: - name: NoError description: No Framing error is detected. value: 0 - name: Error description: Framing error or break character is detected. value: 1 enum/FECF: bit_size: 1 variants: - name: Clear description: Clears the FE flag in the ISR register. value: 1 enum/FIFOEN: bit_size: 1 variants: - name: Disabled description: FIFO mode is disabled. value: 0 - name: Enabled description: FIFO mode is enabled. value: 1 enum/HDSEL: bit_size: 1 variants: - name: NotSelected description: Half duplex mode is not selected. value: 0 - name: Selected description: Half duplex mode is selected. value: 1 enum/IDLE: bit_size: 1 variants: - name: NoIdle description: No Idle Line is detected. value: 0 - name: Idle description: Idle Line is detected. value: 1 enum/IDLECF: bit_size: 1 variants: - name: Clear description: Clears the IDLE flag in the ISR register. value: 1 enum/IDLEIE: bit_size: 1 variants: - name: Disabled description: Interrupt is disabled. value: 0 - name: Enabled description: Interrupt is generated whenever IDLE=1 in the ISR register. value: 1 enum/IREN: bit_size: 1 variants: - name: Disabled description: IrDA disabled. value: 0 - name: Enabled description: IrDA enabled. value: 1 enum/IRLP: bit_size: 1 variants: - name: Normal description: Normal mode. value: 0 - name: LowPower description: Low-power mode. value: 1 enum/LBCL: bit_size: 1 variants: - name: NotOutput description: The clock pulse of the last data bit is not output to the CK pin. value: 0 - name: Output description: The clock pulse of the last data bit is output to the CK pin. value: 1 enum/LBDCF: bit_size: 1 variants: - name: Clear description: Clears the LBDF flag in the ISR register. value: 1 enum/LBDF: bit_size: 1 variants: - name: NotDetected description: LIN break not detected. value: 0 - name: Detected description: LIN break detected. value: 1 enum/LBDIE: bit_size: 1 variants: - name: Disabled description: Interrupt is inhibited. value: 0 - name: Enabled description: An interrupt is generated whenever LBDF=1 in the ISR register. value: 1 enum/LBDL: bit_size: 1 variants: - name: Bit10 description: 10-bit break detection. value: 0 - name: Bit11 description: 11-bit break detection. value: 1 enum/LINEN: bit_size: 1 variants: - name: Disabled description: LIN mode disabled. value: 0 - name: Enabled description: LIN mode enabled. value: 1 enum/M0: bit_size: 1 variants: - name: Bit8 description: 1 start bit, 8 data bits, n stop bits. value: 0 - name: Bit9 description: 1 start bit, 9 data bits, n stop bits. value: 1 enum/M1: bit_size: 1 variants: - name: M0 description: Use M0 to set the data bits. value: 0 - name: Bit7 description: 1 start bit, 7 data bits, n stop bits. value: 1 enum/MME: bit_size: 1 variants: - name: Disabled description: Receiver in active mode permanently. value: 0 - name: Enabled description: Receiver can switch between mute mode and active mode. value: 1 enum/MMRQ: bit_size: 1 variants: - name: Mute description: Puts the USART in mute mode and sets the RWU flag. value: 1 enum/MSBFIRST: bit_size: 1 variants: - name: LSB description: data is transmitted/received with data bit 0 first, following the start bit. value: 0 - name: MSB description: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit. value: 1 enum/NACK: bit_size: 1 variants: - name: Disabled description: NACK transmission in case of parity error is disabled. value: 0 - name: Enabled description: NACK transmission during parity error is enabled. value: 1 enum/NE: bit_size: 1 variants: - name: NoNoise description: No noise is detected. value: 0 - name: Noise description: Noise is detected. value: 1 enum/NECF: bit_size: 1 variants: - name: Clear description: Clears the NF flag in the ISR register. value: 1 enum/ONEBIT: bit_size: 1 variants: - name: Sample3 description: Three sample bit method. value: 0 - name: Sample1 description: One sample bit method. value: 1 enum/ORE: bit_size: 1 variants: - name: NoOverrun description: No Overrun error. value: 0 - name: Overrun description: Overrun error is detected. value: 1 enum/ORECF: bit_size: 1 variants: - name: Clear description: Clears the ORE flag in the ISR register. value: 1 enum/OVER8: bit_size: 1 variants: - name: Oversampling16 description: Oversampling by 16. value: 0 - name: Oversampling8 description: Oversampling by 8. value: 1 enum/OVRDIS: bit_size: 1 variants: - name: Enabled description: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. value: 0 - name: Disabled description: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register. value: 1 enum/PCE: bit_size: 1 variants: - name: Disabled description: Parity control disabled. value: 0 - name: Enabled description: Parity control enabled. value: 1 enum/PE: bit_size: 1 variants: - name: NoError description: No parity error. value: 0 - name: Error description: Parity error. value: 1 enum/PECF: bit_size: 1 variants: - name: Clear description: Clears the PE flag in the ISR register. value: 1 enum/PEIE: bit_size: 1 variants: - name: Disabled description: Interrupt is disabled. value: 0 - name: Enabled description: Interrupt is generated whenever PE=1 in the ISR register. value: 1 enum/PRESCALER: bit_size: 4 variants: - name: Div1 description: Input clock divided by 1. value: 0 - name: Div2 description: Input clock divided by 2. value: 1 - name: Div4 description: Input clock divided by 4. value: 2 - name: Div6 description: Input clock divided by 6. value: 3 - name: Div8 description: Input clock divided by 8. value: 4 - name: Div10 description: Input clock divided by 10. value: 5 - name: Div12 description: Input clock divided by 12. value: 6 - name: Div16 description: Input clock divided by 16. value: 7 - name: Div32 description: Input clock divided by 32. value: 8 - name: Div64 description: Input clock divided by 64. value: 9 - name: Div128 description: Input clock divided by 128. value: 10 - name: Div256 description: Input clock divided by 256. value: 11 enum/PS: bit_size: 1 variants: - name: Even description: Even parity. value: 0 - name: Odd description: Odd parity. value: 1 enum/RE: bit_size: 1 variants: - name: Disabled description: Receiver is disabled. value: 0 - name: Enabled description: Receiver is enabled. value: 1 enum/RTOCF: bit_size: 1 variants: - name: Clear description: Clears the RTOF flag in the ISR register. value: 1 enum/RTOEN: bit_size: 1 variants: - name: Disabled description: Receiver timeout feature disabled. value: 0 - name: Enabled description: Receiver timeout feature enabled. value: 1 enum/RTOF: bit_size: 1 variants: - name: NotReached description: Timeout value not reached. value: 0 - name: Reached description: Timeout value reached without any data reception. value: 1 enum/RTOIE: bit_size: 1 variants: - name: Disabled description: Interrupt is inhibited. value: 0 - name: Enabled description: An USART interrupt is generated when the RTOF bit is set in the ISR register. value: 1 enum/RTSE: bit_size: 1 variants: - name: Disabled description: RTS hardware flow control disabled. value: 0 - name: Enabled description: RTS output enabled, data is only requested when there is space in the receive buffer. value: 1 enum/RWU: bit_size: 1 variants: - name: Active description: Receiver in Active mode. value: 0 - name: Mute description: Receiver in Mute mode. value: 1 enum/RXFF: bit_size: 1 variants: - name: NotFull description: RXFIFO not full. value: 0 - name: Full description: RXFIFO Full. value: 1 enum/RXFFIE: bit_size: 1 variants: - name: Disabled description: Interrupt inhibited. value: 0 - name: Enabled description: USART interrupt generated when RXFF = 1 in the USART_ISR register. value: 1 enum/RXFNE: bit_size: 1 variants: - name: NoData description: Data is not received. value: 0 - name: DataReady description: Received data is ready to be read. value: 1 enum/RXFRQ: bit_size: 1 variants: - name: Discard description: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition. value: 1 enum/RXFT: bit_size: 1 variants: - name: NotReached description: Receive FIFO does not reach the programmed threshold. value: 0 - name: Reached description: Receive FIFO reached the programmed threshold. value: 1 enum/RXFTCFG: bit_size: 3 variants: - name: Depth_1_8 description: RXFIFO reaches 1/8 of its depth. value: 0 - name: Depth_1_4 description: RXFIFO reaches 1/4 of its depth. value: 1 - name: Depth_1_2 description: RXFIFO reaches 1/2 of its depth. value: 2 - name: Depth_3_4 description: RXFIFO reaches 3/4 of its depth. value: 3 - name: Depth_7_8 description: RXFIFO reaches 7/8 of its depth. value: 4 - name: Full description: RXFIFO becomes full. value: 5 enum/RXFTIE: bit_size: 1 variants: - name: Disabled description: Interrupt inhibited. value: 0 - name: Enabled description: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. value: 1 enum/RXINV: bit_size: 1 variants: - name: Standard description: RX pin signal works using the standard logic levels. value: 0 - name: Inverted description: RX pin signal values are inverted. value: 1 enum/RXNEIE: bit_size: 1 variants: - name: Disabled description: Interrupt is disabled. value: 0 - name: Enabled description: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register. value: 1 enum/SBKF: bit_size: 1 variants: - name: NoBreak description: No break character transmitted. value: 0 - name: Break description: Break character transmitted. value: 1 enum/SBKRQ: bit_size: 1 variants: - name: Break description: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. value: 1 enum/SCEN: bit_size: 1 variants: - name: Disabled description: Smartcard Mode disabled. value: 0 - name: Enabled description: Smartcard Mode enabled. value: 1 enum/SLVEN: bit_size: 1 variants: - name: Disabled description: Slave mode disabled. value: 0 - name: Enabled description: Slave mode enabled. value: 1 enum/STOP: bit_size: 2 variants: - name: Stop1 description: 1 stop bit. value: 0 - name: Stop0p5 description: 0.5 stop bit. value: 1 - name: Stop2 description: 2 stop bit. value: 2 - name: Stop1p5 description: 1.5 stop bit. value: 3 enum/SWAP: bit_size: 1 variants: - name: Standard description: TX/RX pins are used as defined in standard pinout. value: 0 - name: Swapped description: The TX and RX pins functions are swapped. value: 1 enum/TC: bit_size: 1 variants: - name: TxNotComplete description: Transmission is not complete. value: 0 - name: TxComplete description: Transmission is complete. value: 1 enum/TCBGT: bit_size: 1 variants: - name: NotCompleted description: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card). value: 0 - name: Completed description: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card). value: 1 enum/TCBGTCF: bit_size: 1 variants: - name: Clear description: Clear the TCBGT flag in the ISR register. value: 1 enum/TCBGTIE: bit_size: 1 variants: - name: Disabled description: Interrupt inhibited. value: 0 - name: Enabled description: USART interrupt generated whenever TCBGT=1 in the USART_ISR register. value: 1 enum/TCCF: bit_size: 1 variants: - name: Clear description: Clears the TC flag in the ISR register. value: 1 enum/TCIE: bit_size: 1 variants: - name: Disabled description: Interrupt is disabled. value: 0 - name: Enabled description: Interrupt is generated whenever TC=1 in the ISR register. value: 1 enum/TE: bit_size: 1 variants: - name: Disabled description: Transmitter is disabled. value: 0 - name: Enabled description: Transmitter is enabled. value: 1 enum/TXEIE: bit_size: 1 variants: - name: Disabled description: Interrupt is disabled. value: 0 - name: Enabled description: Interrupt is generated whenever TXE=1 in the ISR register. value: 1 enum/TXFE: bit_size: 1 variants: - name: NotEmpty description: TXFIFO not empty. value: 0 - name: Empty description: TXFIFO empty. value: 1 enum/TXFECF: bit_size: 1 variants: - name: Clear description: Clear the TXFE flag in the ISR register. value: 1 enum/TXFEIE: bit_size: 1 variants: - name: Disabled description: Interrupt inhibited. value: 0 - name: Enabled description: USART interrupt generated when TXFE = 1 in the USART_ISR register. value: 1 enum/TXFNF: bit_size: 1 variants: - name: Full description: Transmit FIFO is full. value: 0 - name: NotFull description: Transmit FIFO is not full. value: 1 enum/TXFRQ: bit_size: 1 variants: - name: Discard description: Set the TXE flags. This allows to discard the transmit data. value: 1 enum/TXFT: bit_size: 1 variants: - name: NotReached description: TXFIFO does not reach the programmed threshold. value: 0 - name: Reached description: TXFIFO reached the programmed threshold. value: 1 enum/TXFTCFG: bit_size: 3 variants: - name: Depth_1_8 description: TXFIFO reaches 1/8 of its depth. value: 0 - name: Depth_1_4 description: TXFIFO reaches 1/4 of its depth. value: 1 - name: Depth_1_2 description: TXFIFO reaches 1/2 of its depth. value: 2 - name: Depth_3_4 description: TXFIFO reaches 3/4 of its depth. value: 3 - name: Depth_7_8 description: TXFIFO reaches 7/8 of its depth. value: 4 - name: Empty description: TXFIFO becomes empty. value: 5 enum/TXFTIE: bit_size: 1 variants: - name: Disabled description: Interrupt inhibited. value: 0 - name: Enabled description: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG. value: 1 enum/TXINV: bit_size: 1 variants: - name: Standard description: TX pin signal works using the standard logic levels. value: 0 - name: Inverted description: TX pin signal values are inverted. value: 1 enum/UDR: bit_size: 1 variants: - name: NoUnderrun description: No underrun error. value: 0 - name: Underrun description: underrun error. value: 1 enum/UDRCF: bit_size: 1 variants: - name: Clear description: Clear the UDR flag in the ISR register. value: 1 enum/UE: bit_size: 1 variants: - name: Disabled description: UART is disabled. value: 0 - name: Enabled description: UART is enabled. value: 1 enum/UESM: bit_size: 1 variants: - name: Disabled description: USART not able to wake up the MCU from Stop mode. value: 0 - name: Enabled description: USART able to wake up the MCU from Stop mode. value: 1 enum/WAKE: bit_size: 1 variants: - name: Idle description: Idle line. value: 0 - name: Address description: Address mask. value: 1 enum/WUCF: bit_size: 1 variants: - name: Clear description: Clears the WUF flag in the ISR register. value: 1 enum/WUFIE: bit_size: 1 variants: - name: Disabled description: Interrupt is inhibited. value: 0 - name: Enabled description: An USART interrupt is generated whenever WUF=1 in the ISR register. value: 1 enum/WUS: bit_size: 2 variants: - name: Address description: WUF active on address match. value: 0 - name: Start description: WuF active on Start bit detection. value: 2 - name: RXNE description: WUF active on RXNE. value: 3