diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 0bf4b80..66994cb 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -376,6 +376,11 @@ { "name": "AES", "address": 1108082688, + "registers": { + "kind": "aes", + "version": "v3b", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index 8906394..6d8a842 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -384,6 +384,11 @@ { "name": "AES", "address": 1108082688, + "registers": { + "kind": "aes", + "version": "v3b", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index 5b70db4..957b5ff 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -348,6 +348,11 @@ { "name": "AES", "address": 1108082688, + "registers": { + "kind": "aes", + "version": "v3b", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index daaafa0..fbade8c 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -352,6 +352,11 @@ { "name": "AES", "address": 1108082688, + "registers": { + "kind": "aes", + "version": "v3b", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index f33c5eb..aeb5c19 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -352,6 +352,11 @@ { "name": "AES", "address": 1108082688, + "registers": { + "kind": "aes", + "version": "v3b", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index 1a9d6fc..25e60d6 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -376,6 +376,11 @@ { "name": "AES", "address": 1108082688, + "registers": { + "kind": "aes", + "version": "v3b", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index 9c2fb25..abda50c 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -251,7 +251,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index 759f151..1a5c26b 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -247,7 +247,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 3dee2cc..9eb5fa4 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -239,7 +239,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index 40b54db..36003d1 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -309,7 +309,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index af45e04..f5c3da6 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -331,7 +331,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index a2323ef..21d28b9 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -712,7 +712,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index c023cae..537f104 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -624,7 +624,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index 49b999d..e66b77f 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -672,7 +672,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index b6d389d..ab7acd9 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -712,7 +712,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index 453389a..ebf73fb 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -674,7 +674,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index e4b7ca7..d552167 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -696,7 +696,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index 75b0995..63e218b 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -712,7 +712,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index db2f4bf..d5b5bab 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -441,7 +441,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index c9b35b0..8790532 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -441,7 +441,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index 9997ab1..d7a0019 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -393,7 +393,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index ed5cb14..e755e27 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -415,7 +415,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 6db0dbd..9edc97e 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -445,7 +445,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 8b47aa0..d82581c 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -437,7 +437,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index 41b5f6a..296d196 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -437,7 +437,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 9e6503d..501d0d9 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -387,7 +387,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index 2967d3b..6e2cb04 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -441,7 +441,7 @@ "address": 1108082688, "registers": { "kind": "aes", - "version": "u5", + "version": "v3a", "block": "AES" }, "rcc": { diff --git a/data/chips/STM32WBA52CE.json b/data/chips/STM32WBA52CE.json index 6ba48f0..1153655 100644 --- a/data/chips/STM32WBA52CE.json +++ b/data/chips/STM32WBA52CE.json @@ -124,6 +124,11 @@ { "name": "AES", "address": 1108082688, + "registers": { + "kind": "aes", + "version": "v3b", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32WBA52CG.json b/data/chips/STM32WBA52CG.json index bef060b..0d750e7 100644 --- a/data/chips/STM32WBA52CG.json +++ b/data/chips/STM32WBA52CG.json @@ -124,6 +124,11 @@ { "name": "AES", "address": 1108082688, + "registers": { + "kind": "aes", + "version": "v3b", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32WBA52KE.json b/data/chips/STM32WBA52KE.json index f200e97..4b4f20f 100644 --- a/data/chips/STM32WBA52KE.json +++ b/data/chips/STM32WBA52KE.json @@ -120,6 +120,11 @@ { "name": "AES", "address": 1108082688, + "registers": { + "kind": "aes", + "version": "v3b", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32WBA52KG.json b/data/chips/STM32WBA52KG.json index ed46b7b..95d3d79 100644 --- a/data/chips/STM32WBA52KG.json +++ b/data/chips/STM32WBA52KG.json @@ -120,6 +120,11 @@ { "name": "AES", "address": 1108082688, + "registers": { + "kind": "aes", + "version": "v3b", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/registers/aes_u5.json b/data/registers/aes_v3a.json similarity index 81% rename from data/registers/aes_u5.json rename to data/registers/aes_v3a.json index fcfb0e0..75c59ed 100644 --- a/data/registers/aes_u5.json +++ b/data/registers/aes_v3a.json @@ -17,14 +17,12 @@ { "name": "DINR", "description": "Data input register", - "byte_offset": 8, - "fieldset": "DINR" + "byte_offset": 8 }, { "name": "DOUTR", "description": "Data output register", - "byte_offset": 12, - "fieldset": "DOUTR" + "byte_offset": 12 }, { "name": "KEYR", @@ -41,8 +39,7 @@ 44 ] }, - "byte_offset": 16, - "fieldset": "KEYR" + "byte_offset": 16 }, { "name": "IVR", @@ -51,8 +48,7 @@ "len": 4, "stride": 4 }, - "byte_offset": 32, - "fieldset": "IVR" + "byte_offset": 32 }, { "name": "SUSPR", @@ -61,8 +57,7 @@ "len": 8, "stride": 4 }, - "byte_offset": 64, - "fieldset": "SUSPR" + "byte_offset": 64 }, { "name": "IER", @@ -108,10 +103,20 @@ "enum": "MODE" }, { - "name": "CHMOD10", - "description": "Chaining mode bit1 bit0", - "bit_offset": 5, - "bit_size": 2 + "name": "CHMOD", + "description": "Chaining mode selection", + "bit_offset": [ + { + "start": 5, + "end": 6 + }, + { + "start": 16, + "end": 16 + } + ], + "bit_size": 3, + "enum": "CHMOD" }, { "name": "DMAINEN", @@ -132,12 +137,6 @@ "bit_size": 2, "enum": "GCMPH" }, - { - "name": "CHMOD2", - "description": "Chaining mode bit2", - "bit_offset": 16, - "bit_size": 1 - }, { "name": "KEYSIZE", "description": "Key size selection", @@ -164,28 +163,6 @@ } ] }, - "fieldset/DINR": { - "description": "Data input register", - "fields": [ - { - "name": "DIN", - "description": "Input data word", - "bit_offset": 0, - "bit_size": 32 - } - ] - }, - "fieldset/DOUTR": { - "description": "Data output register", - "fields": [ - { - "name": "DOUT", - "description": "Output data word", - "bit_offset": 0, - "bit_size": 32 - } - ] - }, "fieldset/ICR": { "description": "Interrupt clear register", "fields": [ @@ -255,28 +232,6 @@ } ] }, - "fieldset/IVR": { - "description": "Initialization vector register", - "fields": [ - { - "name": "IVI", - "description": "Initialization vector input", - "bit_offset": 0, - "bit_size": 32 - } - ] - }, - "fieldset/KEYR": { - "description": "Key register", - "fields": [ - { - "name": "KEY", - "description": "Cryptographic key", - "bit_offset": 0, - "bit_size": 32 - } - ] - }, "fieldset/SR": { "description": "Status register", "fields": [ @@ -312,14 +267,33 @@ } ] }, - "fieldset/SUSPR": { - "description": "Suspend register", - "fields": [ + "enum/CHMOD": { + "bit_size": 3, + "variants": [ { - "name": "SUSP", - "description": "AES suspend", - "bit_offset": 0, - "bit_size": 32 + "name": "ECB", + "description": "Electronic codebook", + "value": 0 + }, + { + "name": "CBC", + "description": "Cipher-block chaining", + "value": 1 + }, + { + "name": "CTR", + "description": "Counter mode", + "value": 2 + }, + { + "name": "GCM_GMAC", + "description": "Galois counter mode and Galois message authentication code", + "value": 3 + }, + { + "name": "CCM", + "description": "Counter with CBC-MAC", + "value": 4 } ] }, diff --git a/data/registers/aes_v3b.json b/data/registers/aes_v3b.json new file mode 100644 index 0000000..761c0bb --- /dev/null +++ b/data/registers/aes_v3b.json @@ -0,0 +1,364 @@ +{ + "block/AES": { + "description": "Advanced encryption standard hardware accelerator", + "items": [ + { + "name": "CR", + "description": "Control register", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "SR", + "description": "Status register", + "byte_offset": 4, + "fieldset": "SR" + }, + { + "name": "DINR", + "description": "Data input register", + "byte_offset": 8 + }, + { + "name": "DOUTR", + "description": "Data output register", + "byte_offset": 12 + }, + { + "name": "KEYR", + "description": "Key register", + "array": { + "offsets": [ + 0, + 4, + 8, + 12, + 32, + 36, + 40, + 44 + ] + }, + "byte_offset": 16 + }, + { + "name": "IVR", + "description": "Initialization vector register", + "array": { + "len": 4, + "stride": 4 + }, + "byte_offset": 32 + }, + { + "name": "SUSPR", + "description": "Suspend register", + "array": { + "len": 8, + "stride": 4 + }, + "byte_offset": 64 + }, + { + "name": "IER", + "description": "interrupt enable register", + "byte_offset": 768, + "fieldset": "IER" + }, + { + "name": "ISR", + "description": "interrupt status register", + "byte_offset": 772, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "interrupt clear register", + "byte_offset": 776, + "fieldset": "ICR" + } + ] + }, + "fieldset/CR": { + "description": "Control register", + "fields": [ + { + "name": "EN", + "description": "AES enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DATATYPE", + "description": "Data type selection", + "bit_offset": 1, + "bit_size": 2, + "enum": "DATATYPE" + }, + { + "name": "MODE", + "description": "Operating mode", + "bit_offset": 3, + "bit_size": 2, + "enum": "MODE" + }, + { + "name": "CHMOD", + "description": "Chaining mode selection", + "bit_offset": [ + { + "start": 5, + "end": 6 + }, + { + "start": 16, + "end": 16 + } + ], + "bit_size": 3, + "enum": "CHMOD" + }, + { + "name": "DMAINEN", + "description": "Enable DMA management of data input phase", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "DMAOUTEN", + "description": "Enable DMA management of data output phase", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "GCMPH", + "description": "GCM or CCM phase selection", + "bit_offset": 13, + "bit_size": 2, + "enum": "GCMPH" + }, + { + "name": "KEYSIZE", + "description": "Key size selection", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "NPBLB", + "description": "Number of padding bytes in last block of payload", + "bit_offset": 20, + "bit_size": 4 + }, + { + "name": "KMOD", + "description": "Key mode selection", + "bit_offset": 24, + "bit_size": 2 + }, + { + "name": "IPRST", + "description": "AES peripheral software reset", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "Interrupt clear register", + "fields": [ + { + "name": "RWEIF", + "description": "Read or write error interrupt flag clear", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "KEIF", + "description": "Key error interrupt flag clear", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "Interrupt enable register", + "fields": [ + { + "name": "CCFIE", + "description": "Computation complete flag interrupt enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "RWEIE", + "description": "Read or write error interrupt enable", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "KEIE", + "description": "Key error interrupt enable", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "Interrupt status register", + "fields": [ + { + "name": "CCF", + "description": "Computation complete flag", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "RWEIF", + "description": "Read or write error interrupt flag", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "KEIF", + "description": "Key error interrupt flag", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/SR": { + "description": "Status register", + "fields": [ + { + "name": "CCF", + "description": "Computation complete flag", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "RDERR", + "description": "Read error flag", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "WRERR", + "description": "Write error flag", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSY", + "description": "Busy flag", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "KEYVALID", + "description": "Key valid flag", + "bit_offset": 7, + "bit_size": 1 + } + ] + }, + "enum/CHMOD": { + "bit_size": 3, + "variants": [ + { + "name": "ECB", + "description": "Electronic codebook", + "value": 0 + }, + { + "name": "CBC", + "description": "Cipher-block chaining", + "value": 1 + }, + { + "name": "CTR", + "description": "Counter mode", + "value": 2 + }, + { + "name": "GCM_GMAC", + "description": "Galois counter mode and Galois message authentication code", + "value": 3 + }, + { + "name": "CCM", + "description": "Counter with CBC-MAC", + "value": 4 + } + ] + }, + "enum/DATATYPE": { + "bit_size": 2, + "variants": [ + { + "name": "None", + "description": "Word", + "value": 0 + }, + { + "name": "HalfWord", + "description": "Half-word (16-bit)", + "value": 1 + }, + { + "name": "Byte", + "description": "Byte (8-bit)", + "value": 2 + }, + { + "name": "Bit", + "description": "Bit", + "value": 3 + } + ] + }, + "enum/GCMPH": { + "bit_size": 2, + "variants": [ + { + "name": "Init phase", + "description": "Init phase", + "value": 0 + }, + { + "name": "Header phase", + "description": "Header phase", + "value": 1 + }, + { + "name": "Payload phase", + "description": "Payload phase", + "value": 2 + }, + { + "name": "Final phase", + "description": "Final phase", + "value": 3 + } + ] + }, + "enum/MODE": { + "bit_size": 2, + "variants": [ + { + "name": "Mode1", + "description": "Encryption", + "value": 0 + }, + { + "name": "Mode2", + "description": "Key derivation (or key preparation for ECB/CBC decryption)", + "value": 1 + }, + { + "name": "Mode3", + "description": "Decryption", + "value": 2 + } + ] + } +} \ No newline at end of file