diff --git a/data/chips/STM32L4P5AE.json b/data/chips/STM32L4P5AE.json index 099ce1f..3417ec0 100644 --- a/data/chips/STM32L4P5AE.json +++ b/data/chips/STM32L4P5AE.json @@ -3248,6 +3248,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3270,6 +3285,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3292,6 +3322,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4P5AG.json b/data/chips/STM32L4P5AG.json index b783489..f5a92e7 100644 --- a/data/chips/STM32L4P5AG.json +++ b/data/chips/STM32L4P5AG.json @@ -3252,6 +3252,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3274,6 +3289,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3296,6 +3326,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4P5CE.json b/data/chips/STM32L4P5CE.json index d169250..5f28e7b 100644 --- a/data/chips/STM32L4P5CE.json +++ b/data/chips/STM32L4P5CE.json @@ -1998,6 +1998,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2020,6 +2035,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2042,6 +2072,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4P5CG.json b/data/chips/STM32L4P5CG.json index 194c330..e5cd0db 100644 --- a/data/chips/STM32L4P5CG.json +++ b/data/chips/STM32L4P5CG.json @@ -2006,6 +2006,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2028,6 +2043,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2050,6 +2080,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4P5QE.json b/data/chips/STM32L4P5QE.json index 0c10e0c..a7b6d60 100644 --- a/data/chips/STM32L4P5QE.json +++ b/data/chips/STM32L4P5QE.json @@ -3103,6 +3103,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3125,6 +3140,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3147,6 +3177,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4P5QG.json b/data/chips/STM32L4P5QG.json index 9b24b82..de3eeb8 100644 --- a/data/chips/STM32L4P5QG.json +++ b/data/chips/STM32L4P5QG.json @@ -3111,6 +3111,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3133,6 +3148,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3155,6 +3185,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4P5RE.json b/data/chips/STM32L4P5RE.json index 93fb8d7..5eeee32 100644 --- a/data/chips/STM32L4P5RE.json +++ b/data/chips/STM32L4P5RE.json @@ -2286,6 +2286,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2308,6 +2323,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2330,6 +2360,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4P5RG.json b/data/chips/STM32L4P5RG.json index cbfbd9d..e574dcf 100644 --- a/data/chips/STM32L4P5RG.json +++ b/data/chips/STM32L4P5RG.json @@ -2290,6 +2290,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2312,6 +2327,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2334,6 +2364,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4P5VE.json b/data/chips/STM32L4P5VE.json index 3e160e4..213f12f 100644 --- a/data/chips/STM32L4P5VE.json +++ b/data/chips/STM32L4P5VE.json @@ -2867,6 +2867,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2889,6 +2904,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2911,6 +2941,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4P5VG.json b/data/chips/STM32L4P5VG.json index b7c71ca..42b78de 100644 --- a/data/chips/STM32L4P5VG.json +++ b/data/chips/STM32L4P5VG.json @@ -2875,6 +2875,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2897,6 +2912,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2919,6 +2949,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4P5ZE.json b/data/chips/STM32L4P5ZE.json index 5936387..cb9a0c7 100644 --- a/data/chips/STM32L4P5ZE.json +++ b/data/chips/STM32L4P5ZE.json @@ -3113,6 +3113,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3135,6 +3150,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3157,6 +3187,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4P5ZG.json b/data/chips/STM32L4P5ZG.json index f82bdb0..e391bbc 100644 --- a/data/chips/STM32L4P5ZG.json +++ b/data/chips/STM32L4P5ZG.json @@ -3117,6 +3117,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3139,6 +3154,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3161,6 +3191,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4Q5AG.json b/data/chips/STM32L4Q5AG.json index 1de6ed7..916b536 100644 --- a/data/chips/STM32L4Q5AG.json +++ b/data/chips/STM32L4Q5AG.json @@ -3291,6 +3291,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3313,6 +3328,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3335,6 +3365,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4Q5CG.json b/data/chips/STM32L4Q5CG.json index edee987..0d0f540 100644 --- a/data/chips/STM32L4Q5CG.json +++ b/data/chips/STM32L4Q5CG.json @@ -2045,6 +2045,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2067,6 +2082,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2089,6 +2119,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4Q5QG.json b/data/chips/STM32L4Q5QG.json index 4752cda..6ad7ab1 100644 --- a/data/chips/STM32L4Q5QG.json +++ b/data/chips/STM32L4Q5QG.json @@ -3146,6 +3146,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3168,6 +3183,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3190,6 +3220,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4Q5RG.json b/data/chips/STM32L4Q5RG.json index 507212b..b67fa3f 100644 --- a/data/chips/STM32L4Q5RG.json +++ b/data/chips/STM32L4Q5RG.json @@ -2329,6 +2329,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2351,6 +2366,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2373,6 +2403,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4Q5VG.json b/data/chips/STM32L4Q5VG.json index 766b218..94544d6 100644 --- a/data/chips/STM32L4Q5VG.json +++ b/data/chips/STM32L4Q5VG.json @@ -2914,6 +2914,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2936,6 +2951,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2958,6 +2988,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4Q5ZG.json b/data/chips/STM32L4Q5ZG.json index 08fd13d..53c60f9 100644 --- a/data/chips/STM32L4Q5ZG.json +++ b/data/chips/STM32L4Q5ZG.json @@ -3156,6 +3156,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3178,6 +3193,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3200,6 +3230,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R5AG.json b/data/chips/STM32L4R5AG.json index ea748d4..7729dc3 100644 --- a/data/chips/STM32L4R5AG.json +++ b/data/chips/STM32L4R5AG.json @@ -2907,6 +2907,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2929,6 +2944,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2951,6 +2981,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R5AI.json b/data/chips/STM32L4R5AI.json index 817dfb3..4bf3a07 100644 --- a/data/chips/STM32L4R5AI.json +++ b/data/chips/STM32L4R5AI.json @@ -2911,6 +2911,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2933,6 +2948,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2955,6 +2985,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R5QG.json b/data/chips/STM32L4R5QG.json index 74d9322..f64598c 100644 --- a/data/chips/STM32L4R5QG.json +++ b/data/chips/STM32L4R5QG.json @@ -2766,6 +2766,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2788,6 +2803,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2810,6 +2840,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R5QI.json b/data/chips/STM32L4R5QI.json index 53ac029..03b23eb 100644 --- a/data/chips/STM32L4R5QI.json +++ b/data/chips/STM32L4R5QI.json @@ -2766,6 +2766,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2788,6 +2803,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2810,6 +2840,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R5VG.json b/data/chips/STM32L4R5VG.json index cdced4c..8b8c57a 100644 --- a/data/chips/STM32L4R5VG.json +++ b/data/chips/STM32L4R5VG.json @@ -2517,6 +2517,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2539,6 +2554,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2561,6 +2591,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R5VI.json b/data/chips/STM32L4R5VI.json index 250d4ae..c56f18a 100644 --- a/data/chips/STM32L4R5VI.json +++ b/data/chips/STM32L4R5VI.json @@ -2517,6 +2517,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2539,6 +2554,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2561,6 +2591,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R5ZG.json b/data/chips/STM32L4R5ZG.json index 6506766..66f7af2 100644 --- a/data/chips/STM32L4R5ZG.json +++ b/data/chips/STM32L4R5ZG.json @@ -2776,6 +2776,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2798,6 +2813,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2820,6 +2850,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R5ZI.json b/data/chips/STM32L4R5ZI.json index e0f2e89..91ab29d 100644 --- a/data/chips/STM32L4R5ZI.json +++ b/data/chips/STM32L4R5ZI.json @@ -2786,6 +2786,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2808,6 +2823,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2830,6 +2860,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R7AI.json b/data/chips/STM32L4R7AI.json index b0c822b..4b58715 100644 --- a/data/chips/STM32L4R7AI.json +++ b/data/chips/STM32L4R7AI.json @@ -3162,6 +3162,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3184,6 +3199,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3206,6 +3236,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R7VI.json b/data/chips/STM32L4R7VI.json index 401aadb..de35817 100644 --- a/data/chips/STM32L4R7VI.json +++ b/data/chips/STM32L4R7VI.json @@ -2732,6 +2732,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2754,6 +2769,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2776,6 +2806,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R7ZI.json b/data/chips/STM32L4R7ZI.json index 0ccef8a..fc20b19 100644 --- a/data/chips/STM32L4R7ZI.json +++ b/data/chips/STM32L4R7ZI.json @@ -3027,6 +3027,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3049,6 +3064,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3071,6 +3101,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R9AG.json b/data/chips/STM32L4R9AG.json index 29421f2..e3384c2 100644 --- a/data/chips/STM32L4R9AG.json +++ b/data/chips/STM32L4R9AG.json @@ -3120,6 +3120,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3142,6 +3157,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3164,6 +3194,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R9AI.json b/data/chips/STM32L4R9AI.json index b662830..b9a6bb3 100644 --- a/data/chips/STM32L4R9AI.json +++ b/data/chips/STM32L4R9AI.json @@ -3120,6 +3120,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3142,6 +3157,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3164,6 +3194,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R9VG.json b/data/chips/STM32L4R9VG.json index 983d603..406b346 100644 --- a/data/chips/STM32L4R9VG.json +++ b/data/chips/STM32L4R9VG.json @@ -2632,6 +2632,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2654,6 +2669,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2676,6 +2706,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R9VI.json b/data/chips/STM32L4R9VI.json index 4d97aaf..98fdfeb 100644 --- a/data/chips/STM32L4R9VI.json +++ b/data/chips/STM32L4R9VI.json @@ -2632,6 +2632,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2654,6 +2669,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2676,6 +2706,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R9ZG.json b/data/chips/STM32L4R9ZG.json index 3d8bca0..a3440e5 100644 --- a/data/chips/STM32L4R9ZG.json +++ b/data/chips/STM32L4R9ZG.json @@ -3026,6 +3026,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3048,6 +3063,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3070,6 +3100,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4R9ZI.json b/data/chips/STM32L4R9ZI.json index 4db09b0..24a016c 100644 --- a/data/chips/STM32L4R9ZI.json +++ b/data/chips/STM32L4R9ZI.json @@ -3036,6 +3036,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3058,6 +3073,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3080,6 +3110,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4S5AI.json b/data/chips/STM32L4S5AI.json index c129563..3e04b0d 100644 --- a/data/chips/STM32L4S5AI.json +++ b/data/chips/STM32L4S5AI.json @@ -2980,6 +2980,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3002,6 +3017,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3024,6 +3054,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4S5QI.json b/data/chips/STM32L4S5QI.json index 16fa03d..788d61d 100644 --- a/data/chips/STM32L4S5QI.json +++ b/data/chips/STM32L4S5QI.json @@ -2835,6 +2835,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2857,6 +2872,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2879,6 +2909,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4S5VI.json b/data/chips/STM32L4S5VI.json index e9f0ecf..f3196b7 100644 --- a/data/chips/STM32L4S5VI.json +++ b/data/chips/STM32L4S5VI.json @@ -2590,6 +2590,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2612,6 +2627,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2634,6 +2664,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4S5ZI.json b/data/chips/STM32L4S5ZI.json index eb4f535..e7af8dc 100644 --- a/data/chips/STM32L4S5ZI.json +++ b/data/chips/STM32L4S5ZI.json @@ -2849,6 +2849,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2871,6 +2886,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2893,6 +2923,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4S7AI.json b/data/chips/STM32L4S7AI.json index ab5c1c7..1213590 100644 --- a/data/chips/STM32L4S7AI.json +++ b/data/chips/STM32L4S7AI.json @@ -3235,6 +3235,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3257,6 +3272,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3279,6 +3309,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4S7VI.json b/data/chips/STM32L4S7VI.json index a56cb4a..38fe885 100644 --- a/data/chips/STM32L4S7VI.json +++ b/data/chips/STM32L4S7VI.json @@ -2805,6 +2805,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2827,6 +2842,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2849,6 +2879,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4S7ZI.json b/data/chips/STM32L4S7ZI.json index 0541bdc..32cb403 100644 --- a/data/chips/STM32L4S7ZI.json +++ b/data/chips/STM32L4S7ZI.json @@ -3100,6 +3100,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3122,6 +3137,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3144,6 +3174,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4S9AI.json b/data/chips/STM32L4S9AI.json index 3f0cbd5..6cfb17e 100644 --- a/data/chips/STM32L4S9AI.json +++ b/data/chips/STM32L4S9AI.json @@ -3193,6 +3193,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3215,6 +3230,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3237,6 +3267,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4S9VI.json b/data/chips/STM32L4S9VI.json index 7d24e5c..dcbf0e7 100644 --- a/data/chips/STM32L4S9VI.json +++ b/data/chips/STM32L4S9VI.json @@ -2705,6 +2705,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2727,6 +2742,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -2749,6 +2779,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L4S9ZI.json b/data/chips/STM32L4S9ZI.json index 1d98c31..8edf531 100644 --- a/data/chips/STM32L4S9ZI.json +++ b/data/chips/STM32L4S9ZI.json @@ -3099,6 +3099,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3121,6 +3136,21 @@ "version": "v1", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": { + "register": "CCIPR2", + "field": "OCTOSPISEL" + }, + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI2EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI2RST" + } + }, "interrupts": [ { "signal": "GLOBAL", @@ -3143,6 +3173,18 @@ "version": "v1", "block": "OCTOSPIM" }, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "OCTOSPIMEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "OCTOSPIMRST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L552CC.json b/data/chips/STM32L552CC.json index e88c234..1c0db36 100644 --- a/data/chips/STM32L552CC.json +++ b/data/chips/STM32L552CC.json @@ -1690,6 +1690,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L552CE.json b/data/chips/STM32L552CE.json index 4d5cc7f..3ad4252 100644 --- a/data/chips/STM32L552CE.json +++ b/data/chips/STM32L552CE.json @@ -1698,6 +1698,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L552ME.json b/data/chips/STM32L552ME.json index bf2330a..dc29b69 100644 --- a/data/chips/STM32L552ME.json +++ b/data/chips/STM32L552ME.json @@ -1834,6 +1834,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L552QC.json b/data/chips/STM32L552QC.json index d5e877d..3e5c751 100644 --- a/data/chips/STM32L552QC.json +++ b/data/chips/STM32L552QC.json @@ -2359,6 +2359,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L552QE.json b/data/chips/STM32L552QE.json index a92ac6b..d5a15ed 100644 --- a/data/chips/STM32L552QE.json +++ b/data/chips/STM32L552QE.json @@ -2367,6 +2367,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L552RC.json b/data/chips/STM32L552RC.json index 62b8667..ae6c28e 100644 --- a/data/chips/STM32L552RC.json +++ b/data/chips/STM32L552RC.json @@ -1807,6 +1807,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L552RE.json b/data/chips/STM32L552RE.json index af26239..df662b4 100644 --- a/data/chips/STM32L552RE.json +++ b/data/chips/STM32L552RE.json @@ -1815,6 +1815,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L552VC.json b/data/chips/STM32L552VC.json index a4dd8d3..d4d3ef7 100644 --- a/data/chips/STM32L552VC.json +++ b/data/chips/STM32L552VC.json @@ -2124,6 +2124,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L552VE.json b/data/chips/STM32L552VE.json index a9279b8..382ca36 100644 --- a/data/chips/STM32L552VE.json +++ b/data/chips/STM32L552VE.json @@ -2128,6 +2128,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L552ZC.json b/data/chips/STM32L552ZC.json index 73d2ef3..3a50c10 100644 --- a/data/chips/STM32L552ZC.json +++ b/data/chips/STM32L552ZC.json @@ -2359,6 +2359,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L552ZE.json b/data/chips/STM32L552ZE.json index 7db0ccb..56174f4 100644 --- a/data/chips/STM32L552ZE.json +++ b/data/chips/STM32L552ZE.json @@ -2363,6 +2363,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index e6a0c9e..f1e3b7a 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -1737,6 +1737,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index e3c6eb4..a16421d 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -1873,6 +1873,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index b858433..b9bfd37 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -2406,6 +2406,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index 252b833..951b4ef 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -1854,6 +1854,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index b499466..80a5c25 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -2167,6 +2167,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index 97b3f39..ffe82f3 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -2402,6 +2402,18 @@ "version": "v2", "block": "OCTOSPI" }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "OCTOSPI1EN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "OCTOSPI1RST" + } + }, "pins": [ { "pin": "PA1", diff --git a/data/registers/rcc_l4plus.json b/data/registers/rcc_l4plus.json index 7715203..8993fb7 100644 --- a/data/registers/rcc_l4plus.json +++ b/data/registers/rcc_l4plus.json @@ -469,7 +469,7 @@ "bit_size": 1 }, { - "name": "OSPIMEN", + "name": "OCTOSPIMEN", "description": "OctoSPI IO manager clock enable", "bit_offset": 20, "bit_size": 1 @@ -588,7 +588,7 @@ "bit_size": 1 }, { - "name": "OSPIMRST", + "name": "OCTOSPIMRST", "description": "OCTOSPI IO manager reset", "bit_offset": 20, "bit_size": 1 @@ -731,7 +731,7 @@ "bit_size": 1 }, { - "name": "OSPIMSMEN", + "name": "OCTOSPIMSMEN", "description": "OctoSPI IO manager clocks enable during Sleep and Stop modes", "bit_offset": 20, "bit_size": 1 @@ -760,13 +760,13 @@ "bit_size": 1 }, { - "name": "OSPI1EN", + "name": "OCTOSPI1EN", "description": "OctoSPI1 memory interface clock enable", "bit_offset": 8, "bit_size": 1 }, { - "name": "OSPI2EN", + "name": "OCTOSPI2EN", "description": "OSPI2EN memory interface clock enable", "bit_offset": 9, "bit_size": 1 @@ -783,13 +783,13 @@ "bit_size": 1 }, { - "name": "OSPI1RST", + "name": "OCTOSPI1RST", "description": "OctoSPI1 memory interface reset", "bit_offset": 8, "bit_size": 1 }, { - "name": "OSPI2RST", + "name": "OCTOSPI2RST", "description": "OctOSPI2 memory interface reset", "bit_offset": 9, "bit_size": 1 @@ -806,13 +806,13 @@ "bit_size": 1 }, { - "name": "OSPI1SMEN", + "name": "OCTOSPI1SMEN", "description": "OctoSPI1 memory interface clocks enable during Sleep and Stop modes", "bit_offset": 8, "bit_size": 1 }, { - "name": "OCTOSPI2", + "name": "OCTOSPI2SMEN", "description": "OctoSPI2 memory interface clocks enable during Sleep and Stop modes", "bit_offset": 9, "bit_size": 1 @@ -1795,11 +1795,11 @@ "bit_size": 2 }, { - "name": "OSPISEL", + "name": "OCTOSPISEL", "description": "Octospi clock source selection", "bit_offset": 20, "bit_size": 2, - "enum": "OSPISEL" + "enum": "OCTOSPISEL" } ] }, @@ -2987,7 +2987,7 @@ } ] }, - "enum/OSPISEL": { + "enum/OCTOSPISEL": { "bit_size": 2, "variants": [ { diff --git a/data/registers/rcc_l5.json b/data/registers/rcc_l5.json index d6ded4d..24b5387 100644 --- a/data/registers/rcc_l5.json +++ b/data/registers/rcc_l5.json @@ -836,8 +836,8 @@ "bit_size": 1 }, { - "name": "OSPI1EN", - "description": "OSPI1EN", + "name": "OCTOSPI1EN", + "description": "OCTOSPI1EN", "bit_offset": 8, "bit_size": 1 } @@ -853,8 +853,8 @@ "bit_size": 1 }, { - "name": "OSPI1RST", - "description": "OSPI1RST", + "name": "OCTOSPI1RST", + "description": "OCTOSPI1RST", "bit_offset": 8, "bit_size": 1 } @@ -870,8 +870,8 @@ "bit_size": 1 }, { - "name": "OSPI1SECF", - "description": "OSPI1SECF", + "name": "OCTOSPI1SECF", + "description": "OCTOSPI1SECF", "bit_offset": 8, "bit_size": 1 } @@ -887,8 +887,8 @@ "bit_size": 1 }, { - "name": "OSPI1SMEN", - "description": "OSPI1SMEN", + "name": "OCTOSPI1SMEN", + "description": "OCTOSPI1SMEN", "bit_offset": 8, "bit_size": 1 } @@ -2126,7 +2126,7 @@ "bit_size": 1 }, { - "name": "OSPISEL", + "name": "OCTOSPISEL", "description": "Octospi clock source selection", "bit_offset": 20, "bit_size": 2