diff --git a/data/chips/STM32U031C6.json b/data/chips/STM32U031C6.json index 590d02d..c8b5361 100644 --- a/data/chips/STM32U031C6.json +++ b/data/chips/STM32U031C6.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,7 +119,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -200,6 +210,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1279,6 +1294,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031C8.json b/data/chips/STM32U031C8.json index e3e122f..6e7421d 100644 --- a/data/chips/STM32U031C8.json +++ b/data/chips/STM32U031C8.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,7 +119,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -200,6 +210,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1279,6 +1294,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031F4.json b/data/chips/STM32U031F4.json index 117db70..618b773 100644 --- a/data/chips/STM32U031F4.json +++ b/data/chips/STM32U031F4.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -187,6 +197,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1165,6 +1180,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031F6.json b/data/chips/STM32U031F6.json index 27768d4..ba1e19d 100644 --- a/data/chips/STM32U031F6.json +++ b/data/chips/STM32U031F6.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -187,6 +197,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1165,6 +1180,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031F8.json b/data/chips/STM32U031F8.json index 95cc607..eeb9ff5 100644 --- a/data/chips/STM32U031F8.json +++ b/data/chips/STM32U031F8.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -187,6 +197,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1165,6 +1180,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031G6.json b/data/chips/STM32U031G6.json index 1843d8a..fb2777e 100644 --- a/data/chips/STM32U031G6.json +++ b/data/chips/STM32U031G6.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -187,6 +197,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1120,6 +1135,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031G8.json b/data/chips/STM32U031G8.json index 01dd54d..ca946d7 100644 --- a/data/chips/STM32U031G8.json +++ b/data/chips/STM32U031G8.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -187,6 +197,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1120,6 +1135,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031K4.json b/data/chips/STM32U031K4.json index 594b714..9f6afed 100644 --- a/data/chips/STM32U031K4.json +++ b/data/chips/STM32U031K4.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -187,6 +197,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1150,6 +1165,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031K6.json b/data/chips/STM32U031K6.json index 3e9f997..30b4270 100644 --- a/data/chips/STM32U031K6.json +++ b/data/chips/STM32U031K6.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -187,6 +197,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1150,6 +1165,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031K8.json b/data/chips/STM32U031K8.json index 1173b29..1d80454 100644 --- a/data/chips/STM32U031K8.json +++ b/data/chips/STM32U031K8.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -187,6 +197,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1150,6 +1165,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031R6.json b/data/chips/STM32U031R6.json index a206148..cadabfc 100644 --- a/data/chips/STM32U031R6.json +++ b/data/chips/STM32U031R6.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,7 +143,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -236,6 +246,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1399,6 +1414,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031R8.json b/data/chips/STM32U031R8.json index 4f7f5f5..7caf769 100644 --- a/data/chips/STM32U031R8.json +++ b/data/chips/STM32U031R8.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,7 +143,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -236,6 +246,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1399,6 +1414,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U073C8.json b/data/chips/STM32U073C8.json index 0beee34..692f832 100644 --- a/data/chips/STM32U073C8.json +++ b/data/chips/STM32U073C8.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,7 +119,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -264,6 +274,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -287,6 +302,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1869,6 +1889,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3415,6 +3440,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3462,7 +3492,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073CB.json b/data/chips/STM32U073CB.json index 1609657..fb7e982 100644 --- a/data/chips/STM32U073CB.json +++ b/data/chips/STM32U073CB.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,7 +119,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -264,6 +274,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -287,6 +302,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1869,6 +1889,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3415,6 +3440,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3462,7 +3492,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073CC.json b/data/chips/STM32U073CC.json index 1e3d8a1..a838d7e 100644 --- a/data/chips/STM32U073CC.json +++ b/data/chips/STM32U073CC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,7 +119,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -264,6 +274,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -287,6 +302,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1869,6 +1889,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3415,6 +3440,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3462,7 +3492,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073H8.json b/data/chips/STM32U073H8.json index 2b8e23c..c5cfa68 100644 --- a/data/chips/STM32U073H8.json +++ b/data/chips/STM32U073H8.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -255,6 +265,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -278,6 +293,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1751,6 +1771,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3163,6 +3188,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3210,7 +3240,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073HB.json b/data/chips/STM32U073HB.json index e0f5ae2..8c9a313 100644 --- a/data/chips/STM32U073HB.json +++ b/data/chips/STM32U073HB.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -255,6 +265,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -278,6 +293,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1751,6 +1771,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3163,6 +3188,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3210,7 +3240,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073HC.json b/data/chips/STM32U073HC.json index e996fd2..7538c59 100644 --- a/data/chips/STM32U073HC.json +++ b/data/chips/STM32U073HC.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -255,6 +265,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -278,6 +293,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1751,6 +1771,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3163,6 +3188,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3210,7 +3240,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073K8.json b/data/chips/STM32U073K8.json index cf03d77..79bebed 100644 --- a/data/chips/STM32U073K8.json +++ b/data/chips/STM32U073K8.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -246,6 +256,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -269,6 +284,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1655,6 +1675,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3018,6 +3043,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3065,7 +3095,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073KB.json b/data/chips/STM32U073KB.json index f83bf2d..61198e8 100644 --- a/data/chips/STM32U073KB.json +++ b/data/chips/STM32U073KB.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -246,6 +256,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -269,6 +284,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1655,6 +1675,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3018,6 +3043,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3065,7 +3095,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073KC.json b/data/chips/STM32U073KC.json index 94c96ce..b468ba4 100644 --- a/data/chips/STM32U073KC.json +++ b/data/chips/STM32U073KC.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -246,6 +256,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -269,6 +284,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1655,6 +1675,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3018,6 +3043,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3065,7 +3095,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073M8.json b/data/chips/STM32U073M8.json index 6ce7c9c..b27060a 100644 --- a/data/chips/STM32U073M8.json +++ b/data/chips/STM32U073M8.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,7 +143,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -304,6 +314,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -327,6 +342,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2328,6 +2348,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -4133,6 +4158,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -4185,7 +4215,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073MB.json b/data/chips/STM32U073MB.json index 6a14049..686a696 100644 --- a/data/chips/STM32U073MB.json +++ b/data/chips/STM32U073MB.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,7 +143,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -304,6 +314,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -327,6 +342,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2328,6 +2348,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -4133,6 +4158,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -4185,7 +4215,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073MC.json b/data/chips/STM32U073MC.json index f4560e5..3c639a7 100644 --- a/data/chips/STM32U073MC.json +++ b/data/chips/STM32U073MC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,7 +143,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -304,6 +314,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -327,6 +342,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2328,6 +2348,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -4133,6 +4158,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -4185,7 +4215,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073R8.json b/data/chips/STM32U073R8.json index 958d797..120c954 100644 --- a/data/chips/STM32U073R8.json +++ b/data/chips/STM32U073R8.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,7 +143,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -300,6 +310,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -323,6 +338,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2169,6 +2189,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3859,6 +3884,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3911,7 +3941,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073RB.json b/data/chips/STM32U073RB.json index 51d51ba..4653527 100644 --- a/data/chips/STM32U073RB.json +++ b/data/chips/STM32U073RB.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,7 +143,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -300,6 +310,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -323,6 +338,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2169,6 +2189,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3859,6 +3884,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3911,7 +3941,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073RC.json b/data/chips/STM32U073RC.json index 5b6a8de..6001c11 100644 --- a/data/chips/STM32U073RC.json +++ b/data/chips/STM32U073RC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,7 +143,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", @@ -300,6 +310,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -323,6 +338,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2169,6 +2189,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3859,6 +3884,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3911,7 +3941,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U083CC.json b/data/chips/STM32U083CC.json index e711825..0123263 100644 --- a/data/chips/STM32U083CC.json +++ b/data/chips/STM32U083CC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,7 +119,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "AES", @@ -292,6 +302,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -315,6 +330,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1897,6 +1917,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3443,6 +3468,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3490,7 +3520,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U083HC.json b/data/chips/STM32U083HC.json index 74bdd0a..779c151 100644 --- a/data/chips/STM32U083HC.json +++ b/data/chips/STM32U083HC.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "AES", @@ -283,6 +293,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -306,6 +321,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1779,6 +1799,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3191,6 +3216,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3238,7 +3268,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U083KC.json b/data/chips/STM32U083KC.json index 6233ca4..8880b27 100644 --- a/data/chips/STM32U083KC.json +++ b/data/chips/STM32U083KC.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,7 +115,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "AES", @@ -274,6 +284,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -297,6 +312,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1683,6 +1703,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3046,6 +3071,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3093,7 +3123,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U083MC.json b/data/chips/STM32U083MC.json index 39c078a..ae68003 100644 --- a/data/chips/STM32U083MC.json +++ b/data/chips/STM32U083MC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,7 +143,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "AES", @@ -332,6 +342,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -355,6 +370,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2356,6 +2376,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -4161,6 +4186,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -4213,7 +4243,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U083RC.json b/data/chips/STM32U083RC.json index d6f2e54..fd37403 100644 --- a/data/chips/STM32U083RC.json +++ b/data/chips/STM32U083RC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,7 +143,12 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "AES", @@ -328,6 +338,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -351,6 +366,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2197,6 +2217,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3887,6 +3912,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3939,7 +3969,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/registers/adc_u0.json b/data/registers/adc_u0.json new file mode 100644 index 0000000..e22db70 --- /dev/null +++ b/data/registers/adc_u0.json @@ -0,0 +1,705 @@ +{ + "block/ADC": { + "description": "Analog to Digital Converter", + "items": [ + { + "name": "ISR", + "description": "ADC interrupt and status register", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "IER", + "description": "ADC interrupt enable register", + "byte_offset": 4, + "fieldset": "IER" + }, + { + "name": "CR", + "description": "ADC control register", + "byte_offset": 8, + "fieldset": "CR" + }, + { + "name": "CFGR1", + "description": "ADC configuration register 1", + "byte_offset": 12, + "fieldset": "CFGR1" + }, + { + "name": "CFGR2", + "description": "ADC configuration register 2", + "byte_offset": 16, + "fieldset": "CFGR2" + }, + { + "name": "SMPR", + "description": "ADC sampling time register", + "byte_offset": 20, + "fieldset": "SMPR" + }, + { + "name": "AWD1TR", + "description": "watchdog threshold register", + "byte_offset": 32, + "fieldset": "AWD1TR" + }, + { + "name": "AWD2TR", + "description": "watchdog threshold register", + "byte_offset": 36, + "fieldset": "AWD2TR" + }, + { + "name": "CHSELR", + "description": "channel selection register", + "byte_offset": 40, + "fieldset": "CHSELR" + }, + { + "name": "CHSELR_1", + "description": "channel selection register CHSELRMOD = 1 in ADC_CFGR1", + "byte_offset": 40, + "fieldset": "CHSELR_1" + }, + { + "name": "AWD3TR", + "description": "watchdog threshold register", + "byte_offset": 44, + "fieldset": "AWD3TR" + }, + { + "name": "DR", + "description": "ADC group regular conversion data register", + "byte_offset": 64, + "access": "Read", + "fieldset": "DR" + }, + { + "name": "AWD2CR", + "description": "ADC analog watchdog 2 configuration register", + "byte_offset": 160, + "fieldset": "AWD2CR" + }, + { + "name": "AWD3CR", + "description": "ADC analog watchdog 3 configuration register", + "byte_offset": 164, + "fieldset": "AWD3CR" + }, + { + "name": "CALFACT", + "description": "ADC calibration factors register", + "byte_offset": 180, + "fieldset": "CALFACT" + }, + { + "name": "CCR", + "description": "ADC common control register", + "byte_offset": 776, + "fieldset": "CCR" + } + ] + }, + "fieldset/AWD1TR": { + "description": "watchdog threshold register", + "fields": [ + { + "name": "LT1", + "description": "ADC analog watchdog 1 threshold low", + "bit_offset": 0, + "bit_size": 12 + }, + { + "name": "HT1", + "description": "ADC analog watchdog 1 threshold high", + "bit_offset": 16, + "bit_size": 12 + } + ] + }, + "fieldset/AWD2CR": { + "description": "ADC analog watchdog 2 configuration register", + "fields": [ + { + "name": "AWD2CH", + "description": "ADC analog watchdog 2 monitored channel selection", + "bit_offset": 0, + "bit_size": 19 + } + ] + }, + "fieldset/AWD2TR": { + "description": "watchdog threshold register", + "fields": [ + { + "name": "LT2", + "description": "ADC analog watchdog 2 threshold low", + "bit_offset": 0, + "bit_size": 12 + }, + { + "name": "HT2", + "description": "ADC analog watchdog 2 threshold high", + "bit_offset": 16, + "bit_size": 12 + } + ] + }, + "fieldset/AWD3CR": { + "description": "ADC analog watchdog 3 configuration register", + "fields": [ + { + "name": "AWD3CH", + "description": "ADC analog watchdog 3 monitored channel selection", + "bit_offset": 0, + "bit_size": 19 + } + ] + }, + "fieldset/AWD3TR": { + "description": "watchdog threshold register", + "fields": [ + { + "name": "LT3", + "description": "ADC analog watchdog 3 threshold high", + "bit_offset": 0, + "bit_size": 12 + }, + { + "name": "HT3", + "description": "ADC analog watchdog 3 threshold high", + "bit_offset": 16, + "bit_size": 12 + } + ] + }, + "fieldset/CALFACT": { + "description": "ADC calibration factors register", + "fields": [ + { + "name": "CALFACT", + "description": "ADC calibration factor in single-ended mode", + "bit_offset": 0, + "bit_size": 7 + } + ] + }, + "fieldset/CCR": { + "description": "ADC common control register", + "fields": [ + { + "name": "PRESC", + "description": "ADC prescaler", + "bit_offset": 18, + "bit_size": 4 + }, + { + "name": "VREFEN", + "description": "VREFINT enable", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "TSEN", + "description": "Temperature sensor enable", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "VBATEN", + "description": "VBAT enable", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR1": { + "description": "ADC configuration register 1", + "fields": [ + { + "name": "DMAEN", + "description": "ADC DMA transfer enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMACFG", + "description": "ADC DMA transfer configuration", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "SCANDIR", + "description": "Scan sequence direction", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "RES", + "description": "ADC data resolution", + "bit_offset": 3, + "bit_size": 2, + "enum": "RES" + }, + { + "name": "ALIGN", + "description": "ADC data alignement", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "EXTSEL", + "description": "ADC group regular external trigger source", + "bit_offset": 6, + "bit_size": 3 + }, + { + "name": "EXTEN", + "description": "ADC group regular external trigger polarity", + "bit_offset": 10, + "bit_size": 2 + }, + { + "name": "OVRMOD", + "description": "ADC group regular overrun configuration", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "CONT", + "description": "ADC group regular continuous conversion mode", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "WAIT", + "description": "Wait conversion mode", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "AUTOFF", + "description": "Auto-off mode", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "DISCEN", + "description": "ADC group regular sequencer discontinuous mode", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "CHSELRMOD", + "description": "Mode selection of the ADC_CHSELR register", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "AWD1SGL", + "description": "ADC analog watchdog 1 monitoring a single channel or all channels", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "AWD1EN", + "description": "ADC analog watchdog 1 enable on scope ADC group regular", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "AWDCH1CH", + "description": "ADC analog watchdog 1 monitored channel selection", + "bit_offset": 26, + "bit_size": 5 + } + ] + }, + "fieldset/CFGR2": { + "description": "ADC configuration register 2", + "fields": [ + { + "name": "OVSE", + "description": "ADC oversampler enable on scope ADC group regular", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "OVSR", + "description": "ADC oversampling ratio", + "bit_offset": 2, + "bit_size": 3 + }, + { + "name": "OVSS", + "description": "ADC oversampling shift", + "bit_offset": 5, + "bit_size": 4 + }, + { + "name": "TOVS", + "description": "ADC oversampling discontinuous mode (triggered mode) for ADC group regular", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LFTRIG", + "description": "Low frequency trigger mode enable", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "CKMODE", + "description": "ADC clock mode", + "bit_offset": 30, + "bit_size": 2 + } + ] + }, + "fieldset/CHSELR": { + "description": "channel selection register", + "fields": [ + { + "name": "CHSEL", + "description": "Channel-x selection", + "bit_offset": 0, + "bit_size": 19 + } + ] + }, + "fieldset/CHSELR_1": { + "description": "channel selection register CHSELRMOD = 1 in ADC_CFGR1", + "fields": [ + { + "name": "SQ1", + "description": "conversion of the sequence", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "SQ2", + "description": "conversion of the sequence", + "bit_offset": 4, + "bit_size": 4 + }, + { + "name": "SQ3", + "description": "conversion of the sequence", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SQ4", + "description": "conversion of the sequence", + "bit_offset": 12, + "bit_size": 4 + }, + { + "name": "SQ5", + "description": "conversion of the sequence", + "bit_offset": 16, + "bit_size": 4 + }, + { + "name": "SQ6", + "description": "conversion of the sequence", + "bit_offset": 20, + "bit_size": 4 + }, + { + "name": "SQ7", + "description": "conversion of the sequence", + "bit_offset": 24, + "bit_size": 4 + }, + { + "name": "SQ8", + "description": "conversion of the sequence", + "bit_offset": 28, + "bit_size": 4 + } + ] + }, + "fieldset/CR": { + "description": "ADC control register", + "fields": [ + { + "name": "ADEN", + "description": "ADC enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ADDIS", + "description": "ADC disable", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ADSTART", + "description": "ADC group regular conversion start", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ADSTP", + "description": "ADC group regular conversion stop", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADVREGEN", + "description": "ADC voltage regulator enable", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ADCAL", + "description": "ADC calibration", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/DR": { + "description": "ADC group regular conversion data register", + "fields": [ + { + "name": "regularDATA", + "description": "ADC group regular conversion data", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/IER": { + "description": "ADC interrupt enable register", + "fields": [ + { + "name": "ADRDYIE", + "description": "ADC ready interrupt", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "EOSMPIE", + "description": "ADC group regular end of sampling interrupt", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EOCIE", + "description": "ADC group regular end of unitary conversion interrupt", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "EOSIE", + "description": "ADC group regular end of sequence conversions interrupt", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "OVRIE", + "description": "ADC group regular overrun interrupt", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AWD1IE", + "description": "ADC analog watchdog 1 interrupt", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AWD2IE", + "description": "ADC analog watchdog 2 interrupt", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AWD3IE", + "description": "ADC analog watchdog 3 interrupt", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "EOCALIE", + "description": "End of calibration interrupt enable", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "CCRDYIE", + "description": "Channel Configuration Ready Interrupt enable", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "ADC interrupt and status register", + "fields": [ + { + "name": "ADRDY", + "description": "ADC ready flag", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "EOSMP", + "description": "ADC group regular end of sampling flag", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EOC", + "description": "ADC group regular end of unitary conversion flag", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "EOS", + "description": "ADC group regular end of sequence conversions flag", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "OVR", + "description": "ADC group regular overrun flag", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AWD1", + "description": "ADC analog watchdog 1 flag", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AWD2", + "description": "ADC analog watchdog 2 flag", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AWD3", + "description": "ADC analog watchdog 3 flag", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "EOCAL", + "description": "End Of Calibration flag", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "CCRDY", + "description": "Channel Configuration Ready flag", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/SMPR": { + "description": "ADC sampling time register", + "fields": [ + { + "name": "SMP1", + "description": "Sampling time selection", + "bit_offset": 0, + "bit_size": 3, + "enum": "SAMPLE_TIME" + }, + { + "name": "SMP2", + "description": "Sampling time selection", + "bit_offset": 4, + "bit_size": 3, + "enum": "SAMPLE_TIME" + }, + { + "name": "SMPSEL", + "description": "Channel sampling time selection", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 19, + "stride": 0 + } + } + ] + }, + "enum/RES": { + "bit_size": 2, + "variants": [ + { + "name": "Bits12", + "description": "12-bit resolution", + "value": 0 + }, + { + "name": "Bits10", + "description": "10-bit resolution", + "value": 1 + }, + { + "name": "Bits8", + "description": "8-bit resolution", + "value": 2 + }, + { + "name": "Bits6", + "description": "6-bit resolution", + "value": 3 + } + ] + }, + "enum/SAMPLE_TIME": { + "bit_size": 3, + "variants": [ + { + "name": "Cycles1_5", + "description": "1.5 ADC cycles", + "value": 0 + }, + { + "name": "Cycles3_5", + "description": "3.5 ADC cycles", + "value": 1 + }, + { + "name": "Cycles7_5", + "description": "7.5 ADC cycles", + "value": 2 + }, + { + "name": "Cycles12_5", + "description": "12.5 ADC cycles", + "value": 3 + }, + { + "name": "Cycles19_5", + "description": "19.5 ADC cycles", + "value": 4 + }, + { + "name": "Cycles39_5", + "description": "39.5 ADC cycles", + "value": 5 + }, + { + "name": "Cycles79_5", + "description": "79.5 ADC cycles", + "value": 6 + }, + { + "name": "Cycles160_5", + "description": "160.5 ADC cycles", + "value": 7 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/usbram_32_1024.json b/data/registers/usbram_32_1024.json new file mode 100644 index 0000000..4550d45 --- /dev/null +++ b/data/registers/usbram_32_1024.json @@ -0,0 +1,16 @@ +{ + "block/USBRAM": { + "description": "USB Endpoint memory", + "items": [ + { + "name": "MEM", + "description": "USB Endpoint memory", + "array": { + "len": 256, + "stride": 4 + }, + "byte_offset": 0 + } + ] + } +} \ No newline at end of file