diff --git a/data/chips/STM32H723VE.json b/data/chips/STM32H723VE.json index ac7975f..24e8771 100644 --- a/data/chips/STM32H723VE.json +++ b/data/chips/STM32H723VE.json @@ -6645,7 +6645,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H723VG.json b/data/chips/STM32H723VG.json index dde05c7..6e66735 100644 --- a/data/chips/STM32H723VG.json +++ b/data/chips/STM32H723VG.json @@ -6645,7 +6645,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H723ZE.json b/data/chips/STM32H723ZE.json index 14dd056..0ee62b9 100644 --- a/data/chips/STM32H723ZE.json +++ b/data/chips/STM32H723ZE.json @@ -7939,7 +7939,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8020,7 +8023,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H723ZG.json b/data/chips/STM32H723ZG.json index 6877cba..f05aa9f 100644 --- a/data/chips/STM32H723ZG.json +++ b/data/chips/STM32H723ZG.json @@ -7939,7 +7939,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8020,7 +8023,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H725AE.json b/data/chips/STM32H725AE.json index d512c3a..3da6fff 100644 --- a/data/chips/STM32H725AE.json +++ b/data/chips/STM32H725AE.json @@ -7419,7 +7419,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7500,7 +7503,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H725AG.json b/data/chips/STM32H725AG.json index d25e8a3..885735f 100644 --- a/data/chips/STM32H725AG.json +++ b/data/chips/STM32H725AG.json @@ -7425,7 +7425,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7506,7 +7509,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H725IE.json b/data/chips/STM32H725IE.json index 5f97287..cfb9958 100644 --- a/data/chips/STM32H725IE.json +++ b/data/chips/STM32H725IE.json @@ -8870,7 +8870,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8951,7 +8954,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H725IG.json b/data/chips/STM32H725IG.json index 61e5e3b..deec69e 100644 --- a/data/chips/STM32H725IG.json +++ b/data/chips/STM32H725IG.json @@ -8876,7 +8876,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8957,7 +8960,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H725VE.json b/data/chips/STM32H725VE.json index 20d7a91..ad2cca2 100644 --- a/data/chips/STM32H725VE.json +++ b/data/chips/STM32H725VE.json @@ -6510,7 +6510,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H725VG.json b/data/chips/STM32H725VG.json index 5532579..bfbbde3 100644 --- a/data/chips/STM32H725VG.json +++ b/data/chips/STM32H725VG.json @@ -7212,7 +7212,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H725ZE.json b/data/chips/STM32H725ZE.json index 8df2d72..10e976d 100644 --- a/data/chips/STM32H725ZE.json +++ b/data/chips/STM32H725ZE.json @@ -6806,7 +6806,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6887,7 +6890,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H725ZG.json b/data/chips/STM32H725ZG.json index 6798178..97863f3 100644 --- a/data/chips/STM32H725ZG.json +++ b/data/chips/STM32H725ZG.json @@ -6812,7 +6812,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6893,7 +6896,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index da86577..bb3ce0e 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -7540,7 +7540,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7621,7 +7624,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index 23683e5..a3debc4 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -8991,7 +8991,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -9072,7 +9075,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index 24ebabd..ae1bbe1 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -6760,7 +6760,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index cfc106e..816982e 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -8054,7 +8054,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8135,7 +8138,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index eb974c5..ed5cdce 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -6760,7 +6760,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index 5f66baf..66d402b 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -8054,7 +8054,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8135,7 +8138,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index a828c56..3a1dd23 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -7545,7 +7545,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7626,7 +7629,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index e1e1ab7..3b89987 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -8996,7 +8996,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -9077,7 +9080,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index b15e113..c248932 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -7332,7 +7332,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index 0849330..9a81487 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -6932,7 +6932,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7013,7 +7016,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H742AG.json b/data/chips/STM32H742AG.json index a34be4d..a37e200 100644 --- a/data/chips/STM32H742AG.json +++ b/data/chips/STM32H742AG.json @@ -6646,7 +6646,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6727,7 +6730,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H742AI.json b/data/chips/STM32H742AI.json index dedd7ba..9a7e892 100644 --- a/data/chips/STM32H742AI.json +++ b/data/chips/STM32H742AI.json @@ -6657,7 +6657,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6738,7 +6741,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H742BG.json b/data/chips/STM32H742BG.json index c37394f..0752f21 100644 --- a/data/chips/STM32H742BG.json +++ b/data/chips/STM32H742BG.json @@ -7043,7 +7043,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7124,7 +7127,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H742BI.json b/data/chips/STM32H742BI.json index 30d9684..b5e875a 100644 --- a/data/chips/STM32H742BI.json +++ b/data/chips/STM32H742BI.json @@ -7054,7 +7054,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7135,7 +7138,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H742IG.json b/data/chips/STM32H742IG.json index 566425b..95e61a6 100644 --- a/data/chips/STM32H742IG.json +++ b/data/chips/STM32H742IG.json @@ -8058,7 +8058,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8139,7 +8142,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H742II.json b/data/chips/STM32H742II.json index 4462c51..f59e744 100644 --- a/data/chips/STM32H742II.json +++ b/data/chips/STM32H742II.json @@ -8069,7 +8069,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8150,7 +8153,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H742VG.json b/data/chips/STM32H742VG.json index 5eca6f7..c1289a9 100644 --- a/data/chips/STM32H742VG.json +++ b/data/chips/STM32H742VG.json @@ -6061,7 +6061,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H742VI.json b/data/chips/STM32H742VI.json index 2cd3e9e..327b6af 100644 --- a/data/chips/STM32H742VI.json +++ b/data/chips/STM32H742VI.json @@ -6072,7 +6072,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H742XG.json b/data/chips/STM32H742XG.json index edd9611..7f1ed57 100644 --- a/data/chips/STM32H742XG.json +++ b/data/chips/STM32H742XG.json @@ -7449,7 +7449,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7530,7 +7533,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H742XI.json b/data/chips/STM32H742XI.json index 2d1f16e..a22b6c2 100644 --- a/data/chips/STM32H742XI.json +++ b/data/chips/STM32H742XI.json @@ -7460,7 +7460,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7541,7 +7544,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H742ZG.json b/data/chips/STM32H742ZG.json index 8934b20..95cd41c 100644 --- a/data/chips/STM32H742ZG.json +++ b/data/chips/STM32H742ZG.json @@ -6244,7 +6244,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6325,7 +6328,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H742ZI.json b/data/chips/STM32H742ZI.json index fd12584..140900f 100644 --- a/data/chips/STM32H742ZI.json +++ b/data/chips/STM32H742ZI.json @@ -6255,7 +6255,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6336,7 +6339,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H743AG.json b/data/chips/STM32H743AG.json index be5dfdc..1673de0 100644 --- a/data/chips/STM32H743AG.json +++ b/data/chips/STM32H743AG.json @@ -7076,7 +7076,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7157,7 +7160,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H743AI.json b/data/chips/STM32H743AI.json index 65df044..9646837 100644 --- a/data/chips/STM32H743AI.json +++ b/data/chips/STM32H743AI.json @@ -7087,7 +7087,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7168,7 +7171,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H743BG.json b/data/chips/STM32H743BG.json index 06f161e..14a99c4 100644 --- a/data/chips/STM32H743BG.json +++ b/data/chips/STM32H743BG.json @@ -7653,7 +7653,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7734,7 +7737,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H743BI.json b/data/chips/STM32H743BI.json index b14435b..9e8135b 100644 --- a/data/chips/STM32H743BI.json +++ b/data/chips/STM32H743BI.json @@ -7664,7 +7664,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7745,7 +7748,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H743IG.json b/data/chips/STM32H743IG.json index d175793..824f615 100644 --- a/data/chips/STM32H743IG.json +++ b/data/chips/STM32H743IG.json @@ -8508,7 +8508,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8589,7 +8592,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H743II.json b/data/chips/STM32H743II.json index af44a4f..71e3153 100644 --- a/data/chips/STM32H743II.json +++ b/data/chips/STM32H743II.json @@ -8519,7 +8519,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8600,7 +8603,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H743VG.json b/data/chips/STM32H743VG.json index 5e6ec05..ec24a97 100644 --- a/data/chips/STM32H743VG.json +++ b/data/chips/STM32H743VG.json @@ -6346,7 +6346,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H743VI.json b/data/chips/STM32H743VI.json index 4ce952e..8a9e1b3 100644 --- a/data/chips/STM32H743VI.json +++ b/data/chips/STM32H743VI.json @@ -6357,7 +6357,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H743XG.json b/data/chips/STM32H743XG.json index c908c9b..fce68d5 100644 --- a/data/chips/STM32H743XG.json +++ b/data/chips/STM32H743XG.json @@ -8059,7 +8059,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8140,7 +8143,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H743XI.json b/data/chips/STM32H743XI.json index aebeec9..7885905 100644 --- a/data/chips/STM32H743XI.json +++ b/data/chips/STM32H743XI.json @@ -8070,7 +8070,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8151,7 +8154,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H743ZG.json b/data/chips/STM32H743ZG.json index 263b441..f950552 100644 --- a/data/chips/STM32H743ZG.json +++ b/data/chips/STM32H743ZG.json @@ -6584,7 +6584,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6665,7 +6668,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H743ZI.json b/data/chips/STM32H743ZI.json index b601da7..24fe915 100644 --- a/data/chips/STM32H743ZI.json +++ b/data/chips/STM32H743ZI.json @@ -6595,7 +6595,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6676,7 +6679,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H745BG.json b/data/chips/STM32H745BG.json index 0c0b093..9fc1411 100644 --- a/data/chips/STM32H745BG.json +++ b/data/chips/STM32H745BG.json @@ -7534,7 +7534,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7615,7 +7618,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -17427,7 +17433,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -17508,7 +17517,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H745BI.json b/data/chips/STM32H745BI.json index 07488c4..dbaf9ee 100644 --- a/data/chips/STM32H745BI.json +++ b/data/chips/STM32H745BI.json @@ -7545,7 +7545,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7626,7 +7629,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -17438,7 +17444,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -17519,7 +17528,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H745IG.json b/data/chips/STM32H745IG.json index da25182..3f9747b 100644 --- a/data/chips/STM32H745IG.json +++ b/data/chips/STM32H745IG.json @@ -8376,7 +8376,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8457,7 +8460,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -18011,7 +18017,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -18092,7 +18101,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H745II.json b/data/chips/STM32H745II.json index fae6229..aa8a801 100644 --- a/data/chips/STM32H745II.json +++ b/data/chips/STM32H745II.json @@ -8387,7 +8387,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8468,7 +8471,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -18022,7 +18028,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -18103,7 +18112,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H745XG.json b/data/chips/STM32H745XG.json index c3c5f4c..d5367e3 100644 --- a/data/chips/STM32H745XG.json +++ b/data/chips/STM32H745XG.json @@ -8050,7 +8050,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8131,7 +8134,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -18117,7 +18123,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -18198,7 +18207,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H745XI.json b/data/chips/STM32H745XI.json index d359b8c..045b57b 100644 --- a/data/chips/STM32H745XI.json +++ b/data/chips/STM32H745XI.json @@ -8061,7 +8061,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8142,7 +8145,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -18128,7 +18134,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -18209,7 +18218,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H745ZG.json b/data/chips/STM32H745ZG.json index bd81b38..c82adb4 100644 --- a/data/chips/STM32H745ZG.json +++ b/data/chips/STM32H745ZG.json @@ -6420,7 +6420,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6501,7 +6504,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -15248,7 +15254,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -15329,7 +15338,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H745ZI.json b/data/chips/STM32H745ZI.json index c1ec499..b0617ed 100644 --- a/data/chips/STM32H745ZI.json +++ b/data/chips/STM32H745ZI.json @@ -6431,7 +6431,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6512,7 +6515,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -15259,7 +15265,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -15340,7 +15349,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index a2ec17b..710abb8 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -6773,7 +6773,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6854,7 +6857,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -15862,7 +15868,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -15943,7 +15952,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index d9aa80c..081a513 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -6784,7 +6784,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6865,7 +6868,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -15873,7 +15879,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -15954,7 +15963,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index 1c0b04b..687fbdf 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -7537,7 +7537,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7618,7 +7621,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -17301,7 +17307,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -17382,7 +17391,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index cdc7a73..6c16e20 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -7548,7 +7548,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7629,7 +7632,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -17312,7 +17318,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -17393,7 +17402,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index ef0c0dd..c1b4c13 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -6815,7 +6815,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6896,7 +6899,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -15904,7 +15910,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -15985,7 +15994,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index d42d624..a3e833e 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -6826,7 +6826,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6907,7 +6910,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -15915,7 +15921,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -15996,7 +16005,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index 4f6b99d..699a295 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -8103,7 +8103,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8184,7 +8187,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -18221,7 +18227,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -18302,7 +18311,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index 3c664e0..5169973 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -8114,7 +8114,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8195,7 +8198,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -18232,7 +18238,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -18313,7 +18322,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index c1cd5a5..36731dc 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -6344,7 +6344,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -14890,7 +14893,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H750IB.json b/data/chips/STM32H750IB.json index 3a675d1..74dc270 100644 --- a/data/chips/STM32H750IB.json +++ b/data/chips/STM32H750IB.json @@ -8564,7 +8564,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8645,7 +8648,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H750VB.json b/data/chips/STM32H750VB.json index 0042e11..29afeab 100644 --- a/data/chips/STM32H750VB.json +++ b/data/chips/STM32H750VB.json @@ -5796,7 +5796,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H750XB.json b/data/chips/STM32H750XB.json index 41d8545..401ba33 100644 --- a/data/chips/STM32H750XB.json +++ b/data/chips/STM32H750XB.json @@ -8115,7 +8115,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8196,7 +8199,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H750ZB.json b/data/chips/STM32H750ZB.json index 70b5d49..a7053bf 100644 --- a/data/chips/STM32H750ZB.json +++ b/data/chips/STM32H750ZB.json @@ -6628,7 +6628,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6709,7 +6712,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H753AI.json b/data/chips/STM32H753AI.json index 1b22be8..9dce09d 100644 --- a/data/chips/STM32H753AI.json +++ b/data/chips/STM32H753AI.json @@ -7166,7 +7166,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7247,7 +7250,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H753BI.json b/data/chips/STM32H753BI.json index f3c71fd..7c8ded6 100644 --- a/data/chips/STM32H753BI.json +++ b/data/chips/STM32H753BI.json @@ -7743,7 +7743,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7824,7 +7827,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H753II.json b/data/chips/STM32H753II.json index c47d429..25e13fc 100644 --- a/data/chips/STM32H753II.json +++ b/data/chips/STM32H753II.json @@ -8598,7 +8598,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8679,7 +8682,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H753VI.json b/data/chips/STM32H753VI.json index 99055ef..02384a8 100644 --- a/data/chips/STM32H753VI.json +++ b/data/chips/STM32H753VI.json @@ -6436,7 +6436,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H753XI.json b/data/chips/STM32H753XI.json index 5c11c2d..97b3d1f 100644 --- a/data/chips/STM32H753XI.json +++ b/data/chips/STM32H753XI.json @@ -8149,7 +8149,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8230,7 +8233,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H753ZI.json b/data/chips/STM32H753ZI.json index 6a03329..e8021a2 100644 --- a/data/chips/STM32H753ZI.json +++ b/data/chips/STM32H753ZI.json @@ -6674,7 +6674,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6755,7 +6758,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index a62e280..e906c8f 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -7624,7 +7624,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7705,7 +7708,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -17594,7 +17600,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -17675,7 +17684,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index 846503d..b894ae3 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -8466,7 +8466,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8547,7 +8550,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -18178,7 +18184,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -18259,7 +18268,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index 43a2e74..d18fd72 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -8140,7 +8140,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8221,7 +8224,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -18284,7 +18290,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -18365,7 +18374,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index 9fb8822..c0367f9 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -6510,7 +6510,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6591,7 +6594,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -15415,7 +15421,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -15496,7 +15505,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index e59993a..0669319 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -6863,7 +6863,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6944,7 +6947,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -16029,7 +16035,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -16110,7 +16119,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index 7837f39..5b611b1 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -7627,7 +7627,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7708,7 +7711,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -17468,7 +17474,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -17549,7 +17558,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 7c67479..14084d1 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -6905,7 +6905,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6986,7 +6989,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -16071,7 +16077,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -16152,7 +16161,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 63b3b7b..86b8894 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -8193,7 +8193,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8274,7 +8277,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" @@ -18388,7 +18394,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -18469,7 +18478,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index a17e12d..c8de16f 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -6423,7 +6423,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -15046,7 +15049,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index a78fb93..ceef8f3 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -6936,7 +6936,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7017,7 +7020,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index bd6539f..5b999ab 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -6947,7 +6947,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7028,7 +7031,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index 5cd2c9c..e960bfd 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -10925,7 +10925,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -11006,7 +11009,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index 9900d86..7e4186a 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -10936,7 +10936,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -11017,7 +11020,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index 4de3693..9c3a155 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -7897,7 +7897,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7978,7 +7981,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index 9045191..f0d6eda 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -7914,7 +7914,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7995,7 +7998,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index 6f244c3..d6d5ee5 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -7805,7 +7805,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7886,7 +7889,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index 4e1a348..abd9fe0 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -7816,7 +7816,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7897,7 +7900,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index bf39d40..6df76ca 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -6127,7 +6127,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index 2a60a17..461f40a 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -7527,7 +7527,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index 13157e9..1355545 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -7538,7 +7538,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index 4cf22de..8ccd303 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -7452,7 +7452,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7533,7 +7536,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index 420038c..26e0c4d 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -7463,7 +7463,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7544,7 +7547,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index b335165..1f14b88 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -7045,7 +7045,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7126,7 +7129,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index fb0f9dc..fa4b6b2 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -8725,7 +8725,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8806,7 +8809,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index 1ddbe54..5834975 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -5803,7 +5803,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index dbcc7bc..0ed326e 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -6691,7 +6691,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6772,7 +6775,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index 7c87e61..7dc415b 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -7067,7 +7067,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7148,7 +7151,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index 54c32a4..3403058 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -11056,7 +11056,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -11137,7 +11140,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index 56b8bd6..254f519 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -8034,7 +8034,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8115,7 +8118,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index fc6a043..521dac2 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -7936,7 +7936,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8017,7 +8020,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index c60eab1..3c813bf 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -6232,7 +6232,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index 495d5ad..c19d090 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -7643,7 +7643,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index 20e2b82..80afb4c 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -7583,7 +7583,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7664,7 +7667,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "D2CCIP1R", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7R3A8.json b/data/chips/STM32H7R3A8.json index 4a263d1..4ade7fe 100644 --- a/data/chips/STM32H7R3A8.json +++ b/data/chips/STM32H7R3A8.json @@ -5680,7 +5680,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -5776,7 +5779,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7R3I8.json b/data/chips/STM32H7R3I8.json index 5bb1c2b..728e34a 100644 --- a/data/chips/STM32H7R3I8.json +++ b/data/chips/STM32H7R3I8.json @@ -7071,7 +7071,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7172,7 +7175,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7R3L8.json b/data/chips/STM32H7R3L8.json index 33394a4..2ae691e 100644 --- a/data/chips/STM32H7R3L8.json +++ b/data/chips/STM32H7R3L8.json @@ -7956,7 +7956,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8057,7 +8060,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7R3R8.json b/data/chips/STM32H7R3R8.json index 2d3c0ba..4c75aef 100644 --- a/data/chips/STM32H7R3R8.json +++ b/data/chips/STM32H7R3R8.json @@ -3028,7 +3028,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7R3V8.json b/data/chips/STM32H7R3V8.json index af31796..0bf9671 100644 --- a/data/chips/STM32H7R3V8.json +++ b/data/chips/STM32H7R3V8.json @@ -4807,7 +4807,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7R3Z8.json b/data/chips/STM32H7R3Z8.json index e04cddc..8afa5b7 100644 --- a/data/chips/STM32H7R3Z8.json +++ b/data/chips/STM32H7R3Z8.json @@ -6186,7 +6186,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6267,7 +6270,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7R7A8.json b/data/chips/STM32H7R7A8.json index 4b1f79e..1c5e941 100644 --- a/data/chips/STM32H7R7A8.json +++ b/data/chips/STM32H7R7A8.json @@ -5833,7 +5833,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -5934,7 +5937,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7R7I8.json b/data/chips/STM32H7R7I8.json index 930773b..f38c337 100644 --- a/data/chips/STM32H7R7I8.json +++ b/data/chips/STM32H7R7I8.json @@ -7219,7 +7219,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7315,7 +7318,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7R7L8.json b/data/chips/STM32H7R7L8.json index faafc73..60319b8 100644 --- a/data/chips/STM32H7R7L8.json +++ b/data/chips/STM32H7R7L8.json @@ -8239,7 +8239,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8340,7 +8343,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7R7Z8.json b/data/chips/STM32H7R7Z8.json index 86803fb..10c8287 100644 --- a/data/chips/STM32H7R7Z8.json +++ b/data/chips/STM32H7R7Z8.json @@ -5208,7 +5208,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -5284,7 +5287,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7S3A8.json b/data/chips/STM32H7S3A8.json index c109517..c9747fd 100644 --- a/data/chips/STM32H7S3A8.json +++ b/data/chips/STM32H7S3A8.json @@ -5805,7 +5805,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -5901,7 +5904,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7S3I8.json b/data/chips/STM32H7S3I8.json index db386fd..d70e015 100644 --- a/data/chips/STM32H7S3I8.json +++ b/data/chips/STM32H7S3I8.json @@ -7196,7 +7196,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7297,7 +7300,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7S3L8.json b/data/chips/STM32H7S3L8.json index c21fce9..de3d4fe 100644 --- a/data/chips/STM32H7S3L8.json +++ b/data/chips/STM32H7S3L8.json @@ -8081,7 +8081,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8182,7 +8185,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7S3R8.json b/data/chips/STM32H7S3R8.json index 4d04c45..66e551c 100644 --- a/data/chips/STM32H7S3R8.json +++ b/data/chips/STM32H7S3R8.json @@ -3153,7 +3153,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7S3V8.json b/data/chips/STM32H7S3V8.json index 0ed0130..df4013f 100644 --- a/data/chips/STM32H7S3V8.json +++ b/data/chips/STM32H7S3V8.json @@ -4932,7 +4932,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7S3Z8.json b/data/chips/STM32H7S3Z8.json index 0f5c024..56cf61d 100644 --- a/data/chips/STM32H7S3Z8.json +++ b/data/chips/STM32H7S3Z8.json @@ -6311,7 +6311,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6392,7 +6395,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7S7A8.json b/data/chips/STM32H7S7A8.json index 5584a38..a5c8443 100644 --- a/data/chips/STM32H7S7A8.json +++ b/data/chips/STM32H7S7A8.json @@ -5958,7 +5958,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -6059,7 +6062,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7S7I8.json b/data/chips/STM32H7S7I8.json index 8d1ebe1..9ff9754 100644 --- a/data/chips/STM32H7S7I8.json +++ b/data/chips/STM32H7S7I8.json @@ -7344,7 +7344,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -7440,7 +7443,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7S7L8.json b/data/chips/STM32H7S7L8.json index bac01ec..9f725e4 100644 --- a/data/chips/STM32H7S7L8.json +++ b/data/chips/STM32H7S7L8.json @@ -8364,7 +8364,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -8465,7 +8468,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/chips/STM32H7S7Z8.json b/data/chips/STM32H7S7Z8.json index c7f2ef6..9683137 100644 --- a/data/chips/STM32H7S7Z8.json +++ b/data/chips/STM32H7S7Z8.json @@ -5333,7 +5333,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI4EN" @@ -5409,7 +5412,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "APB2PERCKSELR", + "field": "SPI45SEL" + }, "enable": { "register": "APB2ENR", "field": "SPI5EN" diff --git a/data/registers/rcc_h7ab.json b/data/registers/rcc_h7ab.json index 365dac1..c7a86b1 100644 --- a/data/registers/rcc_h7ab.json +++ b/data/registers/rcc_h7ab.json @@ -7229,7 +7229,7 @@ "bit_size": 3, "variants": [ { - "name": "HCLK2", + "name": "PCLK2", "description": "APB2 clock selected as peripheral clock", "value": 0 }, diff --git a/data/registers/rcc_h7rs.json b/data/registers/rcc_h7rs.json index cb0a8b8..6b4a9f2 100644 --- a/data/registers/rcc_h7rs.json +++ b/data/registers/rcc_h7rs.json @@ -6840,7 +6840,7 @@ "bit_size": 3, "variants": [ { - "name": "HCLK2", + "name": "PCLK2", "description": "APB2 clock selected as peripheral clock", "value": 0 },