diff --git a/data/chips/STM32F469AE.json b/data/chips/STM32F469AE.json index 5858889..6a78741 100644 --- a/data/chips/STM32F469AE.json +++ b/data/chips/STM32F469AE.json @@ -1245,6 +1245,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F469AG.json b/data/chips/STM32F469AG.json index 4d30150..42e6368 100644 --- a/data/chips/STM32F469AG.json +++ b/data/chips/STM32F469AG.json @@ -1245,6 +1245,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F469AI.json b/data/chips/STM32F469AI.json index 0896f85..da292b9 100644 --- a/data/chips/STM32F469AI.json +++ b/data/chips/STM32F469AI.json @@ -1278,6 +1278,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F469BE.json b/data/chips/STM32F469BE.json index 48e41d6..dab6faf 100644 --- a/data/chips/STM32F469BE.json +++ b/data/chips/STM32F469BE.json @@ -1307,6 +1307,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F469BG.json b/data/chips/STM32F469BG.json index bbdb027..939757e 100644 --- a/data/chips/STM32F469BG.json +++ b/data/chips/STM32F469BG.json @@ -1307,6 +1307,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F469BI.json b/data/chips/STM32F469BI.json index 26682bd..cb9ca33 100644 --- a/data/chips/STM32F469BI.json +++ b/data/chips/STM32F469BI.json @@ -1340,6 +1340,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F469IE.json b/data/chips/STM32F469IE.json index ac57c04..795a189 100644 --- a/data/chips/STM32F469IE.json +++ b/data/chips/STM32F469IE.json @@ -1266,6 +1266,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F469IG.json b/data/chips/STM32F469IG.json index a7f0782..9761a00 100644 --- a/data/chips/STM32F469IG.json +++ b/data/chips/STM32F469IG.json @@ -1266,6 +1266,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F469II.json b/data/chips/STM32F469II.json index dab54bb..8721da9 100644 --- a/data/chips/STM32F469II.json +++ b/data/chips/STM32F469II.json @@ -1299,6 +1299,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F469NE.json b/data/chips/STM32F469NE.json index 6af4e9f..75e87e2 100644 --- a/data/chips/STM32F469NE.json +++ b/data/chips/STM32F469NE.json @@ -1307,6 +1307,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F469NG.json b/data/chips/STM32F469NG.json index 3036aa1..9af9898 100644 --- a/data/chips/STM32F469NG.json +++ b/data/chips/STM32F469NG.json @@ -1307,6 +1307,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F469NI.json b/data/chips/STM32F469NI.json index b67d2a4..ebc6252 100644 --- a/data/chips/STM32F469NI.json +++ b/data/chips/STM32F469NI.json @@ -1340,6 +1340,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F469VE.json b/data/chips/STM32F469VE.json index 1fbbb0a..c919c82 100644 --- a/data/chips/STM32F469VE.json +++ b/data/chips/STM32F469VE.json @@ -1093,6 +1093,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F469VG.json b/data/chips/STM32F469VG.json index 47504ca..87a0b6c 100644 --- a/data/chips/STM32F469VG.json +++ b/data/chips/STM32F469VG.json @@ -1093,6 +1093,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F469VI.json b/data/chips/STM32F469VI.json index 60ea822..3d38492 100644 --- a/data/chips/STM32F469VI.json +++ b/data/chips/STM32F469VI.json @@ -1126,6 +1126,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F469ZE.json b/data/chips/STM32F469ZE.json index b914ac2..7808b64 100644 --- a/data/chips/STM32F469ZE.json +++ b/data/chips/STM32F469ZE.json @@ -1190,6 +1190,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F469ZG.json b/data/chips/STM32F469ZG.json index d5385f8..89078ee 100644 --- a/data/chips/STM32F469ZG.json +++ b/data/chips/STM32F469ZG.json @@ -1190,6 +1190,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F469ZI.json b/data/chips/STM32F469ZI.json index a2588f5..f6b3d18 100644 --- a/data/chips/STM32F469ZI.json +++ b/data/chips/STM32F469ZI.json @@ -1223,6 +1223,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F479AG.json b/data/chips/STM32F479AG.json index 1a21dd2..977bd75 100644 --- a/data/chips/STM32F479AG.json +++ b/data/chips/STM32F479AG.json @@ -1284,6 +1284,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F479AI.json b/data/chips/STM32F479AI.json index aed580d..1012093 100644 --- a/data/chips/STM32F479AI.json +++ b/data/chips/STM32F479AI.json @@ -1317,6 +1317,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F479BG.json b/data/chips/STM32F479BG.json index 75907e6..434224a 100644 --- a/data/chips/STM32F479BG.json +++ b/data/chips/STM32F479BG.json @@ -1346,6 +1346,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F479BI.json b/data/chips/STM32F479BI.json index a706c9f..1f4daec 100644 --- a/data/chips/STM32F479BI.json +++ b/data/chips/STM32F479BI.json @@ -1379,6 +1379,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F479IG.json b/data/chips/STM32F479IG.json index 128b9e6..98d2e9c 100644 --- a/data/chips/STM32F479IG.json +++ b/data/chips/STM32F479IG.json @@ -1305,6 +1305,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F479II.json b/data/chips/STM32F479II.json index 4ebff93..964b8b1 100644 --- a/data/chips/STM32F479II.json +++ b/data/chips/STM32F479II.json @@ -1338,6 +1338,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F479NG.json b/data/chips/STM32F479NG.json index f15a38f..9f17c5c 100644 --- a/data/chips/STM32F479NG.json +++ b/data/chips/STM32F479NG.json @@ -1346,6 +1346,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F479NI.json b/data/chips/STM32F479NI.json index 52f5ec1..82b05b2 100644 --- a/data/chips/STM32F479NI.json +++ b/data/chips/STM32F479NI.json @@ -1379,6 +1379,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F479VG.json b/data/chips/STM32F479VG.json index 9e58945..e615d5b 100644 --- a/data/chips/STM32F479VG.json +++ b/data/chips/STM32F479VG.json @@ -1132,6 +1132,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F479VI.json b/data/chips/STM32F479VI.json index 6f14571..e7efd75 100644 --- a/data/chips/STM32F479VI.json +++ b/data/chips/STM32F479VI.json @@ -1165,6 +1165,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F479ZG.json b/data/chips/STM32F479ZG.json index 2bcea7d..0e79285 100644 --- a/data/chips/STM32F479ZG.json +++ b/data/chips/STM32F479ZG.json @@ -1229,6 +1229,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F479ZI.json b/data/chips/STM32F479ZI.json index 921dca5..aa487e7 100644 --- a/data/chips/STM32F479ZI.json +++ b/data/chips/STM32F479ZI.json @@ -1262,6 +1262,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F768AI.json b/data/chips/STM32F768AI.json index 6b26052..f8135f6 100644 --- a/data/chips/STM32F768AI.json +++ b/data/chips/STM32F768AI.json @@ -1335,6 +1335,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F769AG.json b/data/chips/STM32F769AG.json index c673501..2c5dc20 100644 --- a/data/chips/STM32F769AG.json +++ b/data/chips/STM32F769AG.json @@ -1335,6 +1335,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F769AI.json b/data/chips/STM32F769AI.json index 23c96fc..5c1ed98 100644 --- a/data/chips/STM32F769AI.json +++ b/data/chips/STM32F769AI.json @@ -1624,6 +1624,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F769BG.json b/data/chips/STM32F769BG.json index 140b429..13c8d9c 100644 --- a/data/chips/STM32F769BG.json +++ b/data/chips/STM32F769BG.json @@ -1715,6 +1715,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F769BI.json b/data/chips/STM32F769BI.json index 6ac6073..27e0dc6 100644 --- a/data/chips/STM32F769BI.json +++ b/data/chips/STM32F769BI.json @@ -1715,6 +1715,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F769IG.json b/data/chips/STM32F769IG.json index b6ecc59..9102fdb 100644 --- a/data/chips/STM32F769IG.json +++ b/data/chips/STM32F769IG.json @@ -1665,6 +1665,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F769II.json b/data/chips/STM32F769II.json index d8b5503..638debf 100644 --- a/data/chips/STM32F769II.json +++ b/data/chips/STM32F769II.json @@ -1665,6 +1665,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F769NG.json b/data/chips/STM32F769NG.json index 31bcbf0..061b2d6 100644 --- a/data/chips/STM32F769NG.json +++ b/data/chips/STM32F769NG.json @@ -1715,6 +1715,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F769NI.json b/data/chips/STM32F769NI.json index 665f947..cc17ad9 100644 --- a/data/chips/STM32F769NI.json +++ b/data/chips/STM32F769NI.json @@ -1715,6 +1715,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F778AI.json b/data/chips/STM32F778AI.json index db86e54..ec2a8cb 100644 --- a/data/chips/STM32F778AI.json +++ b/data/chips/STM32F778AI.json @@ -1657,6 +1657,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F779AI.json b/data/chips/STM32F779AI.json index 3551454..8eea465 100644 --- a/data/chips/STM32F779AI.json +++ b/data/chips/STM32F779AI.json @@ -1663,6 +1663,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073822720, diff --git a/data/chips/STM32F779BI.json b/data/chips/STM32F779BI.json index 9056031..b6d1978 100644 --- a/data/chips/STM32F779BI.json +++ b/data/chips/STM32F779BI.json @@ -1754,6 +1754,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F779II.json b/data/chips/STM32F779II.json index ae9177f..00ea3f3 100644 --- a/data/chips/STM32F779II.json +++ b/data/chips/STM32F779II.json @@ -1704,6 +1704,43 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32F779NI.json b/data/chips/STM32F779NI.json index 1d949a9..41ccc1b 100644 --- a/data/chips/STM32F779NI.json +++ b/data/chips/STM32F779NI.json @@ -1754,6 +1754,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index ef4bb81..f662f3d 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -1632,6 +1632,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -10657,6 +10699,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index 56ceb5a..4df04a8 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -1643,6 +1643,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -10668,6 +10710,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index 24b6f59..3f97e1e 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -1745,6 +1745,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -11445,6 +11487,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index 582c1a1..3e621d0 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -1756,6 +1756,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -11456,6 +11498,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index 8f95239..aec8c91 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -1632,6 +1632,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -10657,6 +10699,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index 7a5956b..0342ee9 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -1643,6 +1643,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -10668,6 +10710,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index c86ef55..f2b0bd4 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -1809,6 +1809,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -11858,6 +11905,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index 3254037..76dc8cd 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -1820,6 +1820,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -11869,6 +11916,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index 098e59a..d016f1b 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -1581,6 +1581,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -10063,6 +10105,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index a88ef25..3aaadcf 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -1688,6 +1688,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -10790,6 +10832,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index 9274149..78f5a54 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -1801,6 +1801,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -11578,6 +11620,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 4b12380..fda6eca 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -1688,6 +1688,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -10790,6 +10832,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 8ae953a..306ba2a 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -1865,6 +1865,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -11991,6 +12038,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + }, + { + "pin": "PJ2", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index 6208d82..26696a5 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -1626,6 +1626,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, @@ -10185,6 +10227,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1342177280, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK3", + "kernel_clock": { + "register": "D1CCIPR", + "field": "DSISEL" + }, + "enable": { + "register": "APB3ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB3RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TE", + "af": 13 + }, + { + "pin": "PB11", + "signal": "TE", + "af": 13 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "ETH", "address": 1073905664, diff --git a/data/chips/STM32L4R9AG.json b/data/chips/STM32L4R9AG.json index bee84f1..583fdf0 100644 --- a/data/chips/STM32L4R9AG.json +++ b/data/chips/STM32L4R9AG.json @@ -1466,6 +1466,58 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PB7", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG6", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073808384, diff --git a/data/chips/STM32L4R9AI.json b/data/chips/STM32L4R9AI.json index 7e17353..91ad407 100644 --- a/data/chips/STM32L4R9AI.json +++ b/data/chips/STM32L4R9AI.json @@ -1466,6 +1466,58 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PB7", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG6", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073808384, diff --git a/data/chips/STM32L4R9VG.json b/data/chips/STM32L4R9VG.json index c699a68..fe474f6 100644 --- a/data/chips/STM32L4R9VG.json +++ b/data/chips/STM32L4R9VG.json @@ -1331,6 +1331,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PB7", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073808384, diff --git a/data/chips/STM32L4R9VI.json b/data/chips/STM32L4R9VI.json index 8af6085..f8302b0 100644 --- a/data/chips/STM32L4R9VI.json +++ b/data/chips/STM32L4R9VI.json @@ -1331,6 +1331,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PB7", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073808384, diff --git a/data/chips/STM32L4R9ZG.json b/data/chips/STM32L4R9ZG.json index ff03e55..0cfe30d 100644 --- a/data/chips/STM32L4R9ZG.json +++ b/data/chips/STM32L4R9ZG.json @@ -1392,6 +1392,58 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PB7", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG6", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073808384, diff --git a/data/chips/STM32L4R9ZI.json b/data/chips/STM32L4R9ZI.json index 27e19c7..520f808 100644 --- a/data/chips/STM32L4R9ZI.json +++ b/data/chips/STM32L4R9ZI.json @@ -1402,6 +1402,58 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PB7", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG6", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073808384, diff --git a/data/chips/STM32L4S9AI.json b/data/chips/STM32L4S9AI.json index 5166957..1f19056 100644 --- a/data/chips/STM32L4S9AI.json +++ b/data/chips/STM32L4S9AI.json @@ -1505,6 +1505,58 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PB7", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG6", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073808384, diff --git a/data/chips/STM32L4S9VI.json b/data/chips/STM32L4S9VI.json index 6790a3f..43b76c5 100644 --- a/data/chips/STM32L4S9VI.json +++ b/data/chips/STM32L4S9VI.json @@ -1370,6 +1370,48 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PB7", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073808384, diff --git a/data/chips/STM32L4S9ZI.json b/data/chips/STM32L4S9ZI.json index 5b321dd..a4550bb 100644 --- a/data/chips/STM32L4S9ZI.json +++ b/data/chips/STM32L4S9ZI.json @@ -1431,6 +1431,58 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "v1", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PB11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PB7", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG6", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1073808384, diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index 51b1dd1..bd29659 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -1070,6 +1070,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "u5", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PF10", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG5", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1174544384, diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index 8b587fb..3cae8bc 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -1070,6 +1070,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "u5", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PF10", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG5", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1174544384, diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index 0f2e3ec..2294bac 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -1070,6 +1070,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "u5", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PF10", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG5", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1174544384, diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index 3663853..8db5835 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -984,6 +984,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "u5", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PF10", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG5", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1174544384, diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index 071d677..b72428b 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -984,6 +984,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "u5", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PF10", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG5", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1174544384, diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 5aa67dd..502a609 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -1109,6 +1109,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "u5", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PF10", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG5", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1174544384, diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index 63644c3..e27a66d 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -1109,6 +1109,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "u5", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PF10", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG5", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1174544384, diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index f60161d..1038757 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -1023,6 +1023,53 @@ } ] }, + { + "name": "DSIHOST", + "address": 1073835008, + "registers": { + "kind": "dsihost", + "version": "u5", + "block": "DSIHOST" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR2", + "field": "DSISEL" + }, + "enable": { + "register": "APB2ENR", + "field": "DSIEN" + }, + "reset": { + "register": "APB2RSTR", + "field": "DSIRST" + } + }, + "pins": [ + { + "pin": "PF10", + "signal": "TE", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TE", + "af": 11 + }, + { + "pin": "PG5", + "signal": "TE", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DSI" + } + ] + }, { "name": "EXTI", "address": 1174544384, diff --git a/data/registers/dsihost_u5.json b/data/registers/dsihost_u5.json new file mode 100644 index 0000000..8b9a866 --- /dev/null +++ b/data/registers/dsihost_u5.json @@ -0,0 +1,2618 @@ +{ + "block/DSIHOST": { + "description": "DSI Host.", + "items": [ + { + "name": "VR", + "description": "DSI Host version register.", + "byte_offset": 0, + "fieldset": "VR" + }, + { + "name": "CR", + "description": "DSI Host control register.", + "byte_offset": 4, + "fieldset": "CR" + }, + { + "name": "CCR", + "description": "DSI Host clock control register.", + "byte_offset": 8, + "fieldset": "CCR" + }, + { + "name": "LVCIDR", + "description": "DSI Host LTDC VCID register.", + "byte_offset": 12, + "fieldset": "LVCIDR" + }, + { + "name": "LCOLCR", + "description": "DSI Host LTDC color coding register.", + "byte_offset": 16, + "fieldset": "LCOLCR" + }, + { + "name": "LPCR", + "description": "DSI Host LTDC polarity configuration register.", + "byte_offset": 20, + "fieldset": "LPCR" + }, + { + "name": "LPMCR", + "description": "DSI Host low-power mode configuration register.", + "byte_offset": 24, + "fieldset": "LPMCR" + }, + { + "name": "PCR", + "description": "DSI Host protocol configuration register.", + "byte_offset": 44, + "fieldset": "PCR" + }, + { + "name": "GVCIDR", + "description": "DSI Host generic VCID register.", + "byte_offset": 48, + "fieldset": "GVCIDR" + }, + { + "name": "MCR", + "description": "DSI Host mode configuration register.", + "byte_offset": 52, + "fieldset": "MCR" + }, + { + "name": "VMCR", + "description": "DSI Host video mode configuration register.", + "byte_offset": 56, + "fieldset": "VMCR" + }, + { + "name": "VPCR", + "description": "DSI Host video packet configuration register.", + "byte_offset": 60, + "fieldset": "VPCR" + }, + { + "name": "VCCR", + "description": "DSI Host video chunks configuration register.", + "byte_offset": 64, + "fieldset": "VCCR" + }, + { + "name": "VNPCR", + "description": "DSI Host video null packet configuration register.", + "byte_offset": 68, + "fieldset": "VNPCR" + }, + { + "name": "VHSACR", + "description": "DSI Host video HSA configuration register.", + "byte_offset": 72, + "fieldset": "VHSACR" + }, + { + "name": "VHBPCR", + "description": "DSI Host video HBP configuration register.", + "byte_offset": 76, + "fieldset": "VHBPCR" + }, + { + "name": "VLCR", + "description": "DSI Host video line configuration register.", + "byte_offset": 80, + "fieldset": "VLCR" + }, + { + "name": "VVSACR", + "description": "DSI Host video VSA configuration register.", + "byte_offset": 84, + "fieldset": "VVSACR" + }, + { + "name": "VVBPCR", + "description": "DSI Host video VBP configuration register.", + "byte_offset": 88, + "fieldset": "VVBPCR" + }, + { + "name": "VVFPCR", + "description": "DSI Host video VFP configuration register.", + "byte_offset": 92, + "fieldset": "VVFPCR" + }, + { + "name": "VVACR", + "description": "DSI Host video VA configuration register.", + "byte_offset": 96, + "fieldset": "VVACR" + }, + { + "name": "LCCR", + "description": "DSI Host LTDC command configuration register.", + "byte_offset": 100, + "fieldset": "LCCR" + }, + { + "name": "CMCR", + "description": "DSI Host command mode configuration register.", + "byte_offset": 104, + "fieldset": "CMCR" + }, + { + "name": "GHCR", + "description": "DSI Host generic header configuration register.", + "byte_offset": 108, + "fieldset": "GHCR" + }, + { + "name": "GPDR", + "description": "DSI Host generic payload data register.", + "byte_offset": 112, + "fieldset": "GPDR" + }, + { + "name": "GPSR", + "description": "DSI Host generic packet status register.", + "byte_offset": 116, + "fieldset": "GPSR" + }, + { + "name": "TCCR0", + "description": "DSI Host timeout counter configuration register 0.", + "byte_offset": 120, + "fieldset": "TCCR0" + }, + { + "name": "TCCR1", + "description": "DSI Host timeout counter configuration register 1.", + "byte_offset": 124, + "fieldset": "TCCR1" + }, + { + "name": "TCCR2", + "description": "DSI Host timeout counter configuration register 2.", + "byte_offset": 128, + "fieldset": "TCCR2" + }, + { + "name": "TCCR3", + "description": "DSI Host timeout counter configuration register 3.", + "byte_offset": 132, + "fieldset": "TCCR3" + }, + { + "name": "TCCR4", + "description": "DSI Host timeout counter configuration register 4.", + "byte_offset": 136, + "fieldset": "TCCR4" + }, + { + "name": "TCCR5", + "description": "DSI Host timeout counter configuration register 5.", + "byte_offset": 140, + "fieldset": "TCCR5" + }, + { + "name": "CLCR", + "description": "DSI Host clock lane configuration register.", + "byte_offset": 148, + "fieldset": "CLCR" + }, + { + "name": "CLTCR", + "description": "DSI Host clock lane timer configuration register.", + "byte_offset": 152, + "fieldset": "CLTCR" + }, + { + "name": "DLTCR", + "description": "DSI Host data lane timer configuration register.", + "byte_offset": 156, + "fieldset": "DLTCR" + }, + { + "name": "PCTLR", + "description": "DSI Host PHY control register.", + "byte_offset": 160, + "fieldset": "PCTLR" + }, + { + "name": "PCONFR", + "description": "DSI Host PHY configuration register.", + "byte_offset": 164, + "fieldset": "PCONFR" + }, + { + "name": "PUCR", + "description": "DSI Host PHY ULPS control register.", + "byte_offset": 168, + "fieldset": "PUCR" + }, + { + "name": "PTTCR", + "description": "DSI Host PHY TX triggers configuration register.", + "byte_offset": 172, + "fieldset": "PTTCR" + }, + { + "name": "PSR", + "description": "DSI Host PHY status register.", + "byte_offset": 176, + "fieldset": "PSR" + }, + { + "name": "ISR0", + "description": "DSI Host interrupt and status register 0.", + "byte_offset": 188, + "fieldset": "ISR0" + }, + { + "name": "ISR1", + "description": "DSI Host interrupt and status register 1.", + "byte_offset": 192, + "fieldset": "ISR1" + }, + { + "name": "IER0", + "description": "DSI Host interrupt enable register 0.", + "byte_offset": 196, + "fieldset": "IER0" + }, + { + "name": "IER1", + "description": "DSI Host interrupt enable register 1.", + "byte_offset": 200, + "fieldset": "IER1" + }, + { + "name": "FIR0", + "description": "DSI Host force interrupt register 0.", + "byte_offset": 216, + "fieldset": "FIR0" + }, + { + "name": "FIR1", + "description": "DSI Host force interrupt register 1.", + "byte_offset": 220, + "fieldset": "FIR1" + }, + { + "name": "DLTRCR", + "description": "DSI Host data lane timer read configuration register.", + "byte_offset": 244, + "fieldset": "DLTRCR" + }, + { + "name": "VSCR", + "description": "DSI Host video shadow control register.", + "byte_offset": 256, + "fieldset": "VSCR" + }, + { + "name": "LCVCIDR", + "description": "DSI Host LTDC current VCID register.", + "byte_offset": 268, + "fieldset": "LCVCIDR" + }, + { + "name": "LCCCR", + "description": "DSI Host LTDC current color coding register.", + "byte_offset": 272, + "fieldset": "LCCCR" + }, + { + "name": "LPMCCR", + "description": "DSI Host low-power mode current configuration register.", + "byte_offset": 280, + "fieldset": "LPMCCR" + }, + { + "name": "VMCCR", + "description": "DSI Host video mode current configuration register.", + "byte_offset": 312, + "fieldset": "VMCCR" + }, + { + "name": "VPCCR", + "description": "DSI Host video packet current configuration register.", + "byte_offset": 316, + "fieldset": "VPCCR" + }, + { + "name": "VCCCR", + "description": "DSI Host video chunks current configuration register.", + "byte_offset": 320, + "fieldset": "VCCCR" + }, + { + "name": "VNPCCR", + "description": "DSI Host video null packet current configuration register.", + "byte_offset": 324, + "fieldset": "VNPCCR" + }, + { + "name": "VHSACCR", + "description": "DSI Host video HSA current configuration register.", + "byte_offset": 328, + "fieldset": "VHSACCR" + }, + { + "name": "VHBPCCR", + "description": "DSI Host video HBP current configuration register.", + "byte_offset": 332, + "fieldset": "VHBPCCR" + }, + { + "name": "VLCCR", + "description": "DSI Host video line current configuration register.", + "byte_offset": 336, + "fieldset": "VLCCR" + }, + { + "name": "VVSACCR", + "description": "DSI Host video VSA current configuration register.", + "byte_offset": 340, + "fieldset": "VVSACCR" + }, + { + "name": "VVBPCCR", + "description": "DSI Host video VBP current configuration register.", + "byte_offset": 344, + "fieldset": "VVBPCCR" + }, + { + "name": "VVFPCCR", + "description": "DSI Host video VFP current configuration register.", + "byte_offset": 348, + "fieldset": "VVFPCCR" + }, + { + "name": "VVACCR", + "description": "DSI Host video VA current configuration register.", + "byte_offset": 352, + "fieldset": "VVACCR" + }, + { + "name": "FBSR", + "description": "DSI Host FIFO and buffer status register.", + "byte_offset": 360, + "fieldset": "FBSR" + }, + { + "name": "WCFGR", + "description": "DSI Wrapper configuration register.", + "byte_offset": 1024, + "fieldset": "WCFGR" + }, + { + "name": "WCR", + "description": "DSI Wrapper control register.", + "byte_offset": 1028, + "fieldset": "WCR" + }, + { + "name": "WIER", + "description": "DSI Wrapper interrupt enable register.", + "byte_offset": 1032, + "fieldset": "WIER" + }, + { + "name": "WISR", + "description": "DSI Wrapper interrupt and status register.", + "byte_offset": 1036, + "fieldset": "WISR" + }, + { + "name": "WIFCR", + "description": "DSI Wrapper interrupt flag clear register.", + "byte_offset": 1040, + "fieldset": "WIFCR" + }, + { + "name": "WPCR0", + "description": "DSI Wrapper PHY configuration register 0.", + "byte_offset": 1048, + "fieldset": "WPCR0" + }, + { + "name": "WRPCR", + "description": "DSI Wrapper regulator and PLL control register.", + "byte_offset": 1072, + "fieldset": "WRPCR" + }, + { + "name": "BCFGR", + "description": "DSI bias configuration register.", + "byte_offset": 2056, + "fieldset": "BCFGR" + }, + { + "name": "DPCBCR", + "description": "DSI D-PHY clock band control register.", + "byte_offset": 3076, + "fieldset": "DPCBCR" + }, + { + "name": "DPCSRCR", + "description": "DSI D-PHY clock skew rate control register.", + "byte_offset": 3124, + "fieldset": "DPCSRCR" + }, + { + "name": "DPDL0BCR", + "description": "DSI D-PHY data lane 0 band control register.", + "byte_offset": 3184, + "fieldset": "DPDL0BCR" + }, + { + "name": "DPDL0SRCR", + "description": "DSI D-PHY data lane 0 skew rate control register.", + "byte_offset": 3232, + "fieldset": "DPDL0SRCR" + }, + { + "name": "DPDL1BCR", + "description": "DSI D-PHY data lane 1 band control register.", + "byte_offset": 3336, + "fieldset": "DPDL1BCR" + }, + { + "name": "DPDL1SRCR", + "description": "DSI D-PHY data lane 1 skew rate control register.", + "byte_offset": 3384, + "fieldset": "DPDL1SRCR" + } + ] + }, + "fieldset/BCFGR": { + "description": "DSI bias configuration register.", + "fields": [ + { + "name": "PWRUP", + "description": "Power-up This bit powers-up the reference bias for the MIPI D-PHY.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/CCR": { + "description": "DSI Host clock control register.", + "fields": [ + { + "name": "TXECKDIV", + "description": "TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "TOCKDIV", + "description": "Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error.", + "bit_offset": 8, + "bit_size": 8 + } + ] + }, + "fieldset/CLCR": { + "description": "DSI Host clock lane configuration register.", + "fields": [ + { + "name": "DPCC", + "description": "D-PHY clock control This bit controls the D-PHY clock state:.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACR", + "description": "Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows.", + "bit_offset": 1, + "bit_size": 1 + } + ] + }, + "fieldset/CLTCR": { + "description": "DSI Host clock lane timer configuration register.", + "fields": [ + { + "name": "LP2HS_TIME", + "description": "Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from low‑power to high-speed transmission measured in lane byte clock cycles.", + "bit_offset": 0, + "bit_size": 10 + }, + { + "name": "HS2LP_TIME", + "description": "High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from high‑speed to low-power transmission measured in lane byte clock cycles.", + "bit_offset": 16, + "bit_size": 10 + } + ] + }, + "fieldset/CMCR": { + "description": "DSI Host command mode configuration register.", + "fields": [ + { + "name": "TEARE", + "description": "Tearing effect acknowledge request enable This bit enables the tearing effect acknowledge request:.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ARE", + "description": "Acknowledge request enable This bit enables the acknowledge request after each packet transmission:.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GSW0TX", + "description": "Generic short write zero parameters transmission This bit configures the generic short write packet with zero parameters command transmission type:.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "GSW1TX", + "description": "Generic short write one parameters transmission This bit configures the generic short write packet with one parameters command transmission type:.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "GSW2TX", + "description": "Generic short write two parameters transmission This bit configures the generic short write packet with two parameters command transmission type:.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "GSR0TX", + "description": "Generic short read zero parameters transmission This bit configures the generic short read packet with zero parameters command transmission type:.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "GSR1TX", + "description": "Generic short read one parameters transmission This bit configures the generic short read packet with one parameters command transmission type:.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "GSR2TX", + "description": "Generic short read two parameters transmission This bit configures the generic short read packet with two parameters command transmission type:.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GLWTX", + "description": "Generic long write transmission This bit configures the generic long write packet command transmission type :.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "DSW0TX", + "description": "DCS short write zero parameter transmission This bit configures the DCS short write packet with zero parameter command transmission type:.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "DSW1TX", + "description": "DCS short read one parameter transmission This bit configures the DCS short read packet with one parameter command transmission type:.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "DSR0TX", + "description": "DCS short read zero parameter transmission This bit configures the DCS short read packet with zero parameter command transmission type:.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "DLWTX", + "description": "DCS long write transmission This bit configures the DCS long write packet command transmission type:.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "MRDPS", + "description": "Maximum read packet size This bit configures the maximum read packet size command transmission type:.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CR": { + "description": "DSI Host control register.", + "fields": [ + { + "name": "EN", + "description": "Enable This bit configures the DSI Host in either power-up mode or to reset.", + "bit_offset": 0, + "bit_size": 1 + } + ] + }, + "fieldset/DLTCR": { + "description": "DSI Host data lane timer configuration register.", + "fields": [ + { + "name": "LP2HS_TIME", + "description": "Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles.", + "bit_offset": 0, + "bit_size": 10 + }, + { + "name": "HS2LP_TIME", + "description": "High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles.", + "bit_offset": 16, + "bit_size": 10 + } + ] + }, + "fieldset/DLTRCR": { + "description": "DSI Host data lane timer read configuration register.", + "fields": [ + { + "name": "MRD_TIME", + "description": "Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress.", + "bit_offset": 0, + "bit_size": 15 + } + ] + }, + "fieldset/DPCBCR": { + "description": "DSI D-PHY clock band control register.", + "fields": [ + { + "name": "BC", + "description": "Band control This field selects the frequency band used by the D-PHY. Others: Reserved.", + "bit_offset": 3, + "bit_size": 5 + } + ] + }, + "fieldset/DPCSRCR": { + "description": "DSI D-PHY clock skew rate control register.", + "fields": [ + { + "name": "SRC", + "description": "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "fieldset/DPDL0BCR": { + "description": "DSI D-PHY data lane 0 band control register.", + "fields": [ + { + "name": "BC", + "description": "Band control This field selects the frequency band used by the D-PHY. Others: Reserved.", + "bit_offset": 0, + "bit_size": 5 + } + ] + }, + "fieldset/DPDL0SRCR": { + "description": "DSI D-PHY data lane 0 skew rate control register.", + "fields": [ + { + "name": "SRC", + "description": "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "fieldset/DPDL1BCR": { + "description": "DSI D-PHY data lane 1 band control register.", + "fields": [ + { + "name": "BC", + "description": "Band control This field selects the frequency band used by the D-PHY. Others: Reserved.", + "bit_offset": 0, + "bit_size": 5 + } + ] + }, + "fieldset/DPDL1SRCR": { + "description": "DSI D-PHY data lane 1 skew rate control register.", + "fields": [ + { + "name": "SRC", + "description": "Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "fieldset/FBSR": { + "description": "DSI Host FIFO and buffer status register.", + "fields": [ + { + "name": "VCWFE", + "description": "Video mode command write FIFO empty This bit indicates the empty status of the video mode write command FIFO:.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "VCWFF", + "description": "Video mode command write FIFO full This bit indicates the full status of the video mode write command FIFO:.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "VPWFE", + "description": "Video mode payload write FIFO empty This bit indicates the empty status of the video mode write payload FIFO:.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "VPWFF", + "description": "Video mode payload write FIFO full This bit indicates the full status of the video mode write payload FIFO:.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ACWFE", + "description": "Adapted command mode command write FIFO empty This bit indicates the empty status of the adapted command mode write command FIFO:.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ACWFF", + "description": "Adapted command mode command write FIFO full This bit indicates the full status of the adapted command mode write command FIFO:.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "APWFE", + "description": "Adapted command mode payload write FIFO empty This bit indicates the empty status of the adapted command mode write payload FIFO:.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "APWFF", + "description": "Adapted command mode payload write FIFO full This bit indicates the full status of the adapted command mode write payload FIFO:.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "VPBE", + "description": "Video mode payload buffer empty This bit indicates the empty status of the video mode payload internal buffer:.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "VPBF", + "description": "Video mode payload buffer full This bit indicates the full status of the video mode payload internal buffer:.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ACBE", + "description": "Adapted command mode command buffer empty This bit indicates the empty status of the adapted command mode command internal buffer:.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ACBF", + "description": "Adapted command mode command buffer full This bit indicates the full status of the adapted command mode command internal buffer:.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "APBE", + "description": "Adapted command mode payload buffer empty This bit indicates the empty status of the adapted command mode payload internal buffer:.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "APBF", + "description": "Adapted command mode payload buffer full This bit indicates the full status of the adapted command mode payload internal buffer:.", + "bit_offset": 23, + "bit_size": 1 + } + ] + }, + "fieldset/FIR0": { + "description": "DSI Host force interrupt register 0.", + "fields": [ + { + "name": "FAE0", + "description": "Force acknowledge error 0 Writing one to this bit forces an acknowledge error 0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "FAE1", + "description": "Force acknowledge error 1 Writing one to this bit forces an acknowledge error 1.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "FAE2", + "description": "Force acknowledge error 2 Writing one to this bit forces an acknowledge error 2.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "FAE3", + "description": "Force acknowledge error 3 Writing one to this bit forces an acknowledge error 3.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FAE4", + "description": "Force acknowledge error 4 Writing one to this bit forces an acknowledge error 4.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "FAE5", + "description": "Force acknowledge error 5 Writing one to this bit forces an acknowledge error 5.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FAE6", + "description": "Force acknowledge error 6 Writing one to this bit forces an acknowledge error 6.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "FAE7", + "description": "Force acknowledge error 7 Writing one to this bit forces an acknowledge error 7.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "FAE8", + "description": "Force acknowledge error 8 Writing one to this bit forces an acknowledge error 8.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FAE9", + "description": "Force acknowledge error 9 Writing one to this bit forces an acknowledge error 9.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "FAE10", + "description": "Force acknowledge error 10 Writing one to this bit forces an acknowledge error 10.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "FAE11", + "description": "Force acknowledge error 11 Writing one to this bit forces an acknowledge error 11.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "FAE12", + "description": "Force acknowledge error 12 Writing one to this bit forces an acknowledge error 12.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "FAE13", + "description": "Force acknowledge error 13 Writing one to this bit forces an acknowledge error 13.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "FAE14", + "description": "Force acknowledge error 14 Writing one to this bit forces an acknowledge error 14.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "FAE15", + "description": "Force acknowledge error 15 Writing one to this bit forces an acknowledge error 15.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "FPE0", + "description": "Force PHY error 0 Writing one to this bit forces a PHY error 0.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "FPE1", + "description": "Force PHY error 1 Writing one to this bit forces a PHY error 1.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "FPE2", + "description": "Force PHY error 2 Writing one to this bit forces a PHY error 2.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "FPE3", + "description": "Force PHY error 3 Writing one to this bit forces a PHY error 3.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "FPE4", + "description": "Force PHY error 4 Writing one to this bit forces a PHY error 4.", + "bit_offset": 20, + "bit_size": 1 + } + ] + }, + "fieldset/FIR1": { + "description": "DSI Host force interrupt register 1.", + "fields": [ + { + "name": "FTOHSTX", + "description": "Force timeout high-speed transmission Writing one to this bit forces a timeout high-speed transmission.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "FTOLPRX", + "description": "Force timeout low-power reception Writing one to this bit forces a timeout low-power reception.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "FECCSE", + "description": "Force ECC single-bit error Writing one to this bit forces a ECC single-bit error.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "FECCME", + "description": "Force ECC multi-bit error Writing one to this bit forces a ECC multi-bit error.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FCRCE", + "description": "Force CRC error Writing one to this bit forces a CRC error.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "FPSE", + "description": "Force packet size error Writing one to this bit forces a packet size error.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FEOTPE", + "description": "Force EoTp error Writing one to this bit forces a EoTp error.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "FLPWRE", + "description": "Force LTDC payload write error Writing one to this bit forces a LTDC payload write error.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "FGCWRE", + "description": "Force generic command write error Writing one to this bit forces a generic command write error.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FGPWRE", + "description": "Force generic payload write error Writing one to this bit forces a generic payload write error.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "FGPTXE", + "description": "Force generic payload transmit error Writing one to this bit forces a generic payload transmit error.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "FGPRDE", + "description": "Force generic payload read error Writing one to this bit forces a generic payload read error.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "FGPRXE", + "description": "Force generic payload receive error Writing one to this bit forces a generic payload receive error.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "FPBUE", + "description": "Force payload buffer underflow error Writing one to this bit forces a payload undrflow error.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/GHCR": { + "description": "DSI Host generic header configuration register.", + "fields": [ + { + "name": "DT", + "description": "Type This field configures the packet data type of the header packet.", + "bit_offset": 0, + "bit_size": 6 + }, + { + "name": "VCID", + "description": "Channel This field configures the virtual channel ID of the header packet.", + "bit_offset": 6, + "bit_size": 2 + }, + { + "name": "WCLSB", + "description": "WordCount LSB This field configures the less significant byte of the header packet word count for long packets, or data 0 for short packets.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "WCMSB", + "description": "WordCount MSB This field configures the most significant byte of the header packet's word count for long packets, or data 1 for short packets.", + "bit_offset": 16, + "bit_size": 8 + } + ] + }, + "fieldset/GPDR": { + "description": "DSI Host generic payload data register.", + "fields": [ + { + "name": "DATA1", + "description": "Payload byte 1 This field indicates the byte 1 of the packet payload.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "DATA2", + "description": "Payload byte 2 This field indicates the byte 2 of the packet payload.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "DATA3", + "description": "Payload byte 3 This field indicates the byte 3 of the packet payload.", + "bit_offset": 16, + "bit_size": 8 + }, + { + "name": "DATA4", + "description": "Payload byte 4 This field indicates the byte 4 of the packet payload.", + "bit_offset": 24, + "bit_size": 8 + } + ] + }, + "fieldset/GPSR": { + "description": "DSI Host generic packet status register.", + "fields": [ + { + "name": "CMDFE", + "description": "Command FIFO empty This bit indicates the empty status of the generic command FIFO:.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CMDFF", + "description": "Command FIFO full This bit indicates the full status of the generic command FIFO:.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "PWRFE", + "description": "Payload write FIFO empty This bit indicates the empty status of the generic write payload FIFO:.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PWRFF", + "description": "Payload write FIFO full This bit indicates the full status of the generic write payload FIFO:.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PRDFE", + "description": "Payload read FIFO empty This bit indicates the empty status of the generic read payload FIFO:.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PRDFF", + "description": "Payload read FIFO full This bit indicates the full status of the generic read payload FIFO:.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "RCB", + "description": "Read command busy This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO:.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "CMDBE", + "description": "Command buffer empty This bit indicates the empty status of the generic payload internal buffer:.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "CMDBF", + "description": "Command buffer full This bit indicates the full status of the generic command internal buffer:.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "PBE", + "description": "Payload buffer empty This bit indicates the empty status of the generic payload internal buffer:.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "PBF", + "description": "Payload buffer full This bit indicates the full status of the generic payload internal buffer:.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/GVCIDR": { + "description": "DSI Host generic VCID register.", + "fields": [ + { + "name": "VCIDRX", + "description": "Virtual channel ID for reception This field indicates the generic interface read-back virtual channel identification.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "VCIDTX", + "description": "Virtual channel ID for transmission This field indicates the generic interface virtual channel identification where the generic packet is automatically generated and transmitted.", + "bit_offset": 16, + "bit_size": 2 + } + ] + }, + "fieldset/IER0": { + "description": "DSI Host interrupt enable register 0.", + "fields": [ + { + "name": "AE0IE", + "description": "Acknowledge error 0 interrupt enable This bit enables the interrupt generation on acknowledge error 0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AE1IE", + "description": "Acknowledge error 1 interrupt enable This bit enables the interrupt generation on acknowledge error 1.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AE2IE", + "description": "Acknowledge error 2 interrupt enable This bit enables the interrupt generation on acknowledge error 2.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AE3IE", + "description": "Acknowledge error 3 interrupt enable This bit enables the interrupt generation on acknowledge error 3.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AE4IE", + "description": "Acknowledge error 4 interrupt enable This bit enables the interrupt generation on acknowledge error 4.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AE5IE", + "description": "Acknowledge error 5 interrupt enable This bit enables the interrupt generation on acknowledge error 5.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AE6IE", + "description": "Acknowledge error 6 interrupt enable This bit enables the interrupt generation on acknowledge error 6.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AE7IE", + "description": "Acknowledge error 7 interrupt enable This bit enables the interrupt generation on acknowledge error 7.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AE8IE", + "description": "Acknowledge error 8 interrupt enable This bit enables the interrupt generation on acknowledge error 8.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AE9IE", + "description": "Acknowledge error 9 interrupt enable This bit enables the interrupt generation on acknowledge error 9.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "AE10IE", + "description": "Acknowledge error 10 interrupt enable This bit enables the interrupt generation on acknowledge error 10.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "AE11IE", + "description": "Acknowledge error 11 interrupt enable This bit enables the interrupt generation on acknowledge error 11.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "AE12IE", + "description": "Acknowledge error 12 interrupt enable This bit enables the interrupt generation on acknowledge error 12.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "AE13IE", + "description": "Acknowledge error 13 interrupt enable This bit enables the interrupt generation on acknowledge error 13.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "AE14IE", + "description": "Acknowledge error 14 interrupt enable This bit enables the interrupt generation on acknowledge error 14.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "AE15IE", + "description": "Acknowledge error 15 interrupt enable This bit enables the interrupt generation on acknowledge error 15.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "PE0IE", + "description": "PHY error 0 interrupt enable This bit enables the interrupt generation on PHY error 0.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PE1IE", + "description": "PHY error 1 interrupt enable This bit enables the interrupt generation on PHY error 1.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "PE2IE", + "description": "PHY error 2 interrupt enable This bit enables the interrupt generation on PHY error 2.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "PE3IE", + "description": "PHY error 3 interrupt enable This bit enables the interrupt generation on PHY error 4.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "PE4IE", + "description": "PHY error 4 interrupt enable This bit enables the interrupt generation on PHY error 4.", + "bit_offset": 20, + "bit_size": 1 + } + ] + }, + "fieldset/IER1": { + "description": "DSI Host interrupt enable register 1.", + "fields": [ + { + "name": "TOHSTXIE", + "description": "Timeout high-speed transmission interrupt enable This bit enables the interrupt generation on timeout high-speed transmission.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TOLPRXIE", + "description": "Timeout low-power reception interrupt enable This bit enables the interrupt generation on timeout low-power reception.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ECCSEIE", + "description": "ECC single-bit error interrupt enable This bit enables the interrupt generation on ECC single-bit error.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ECCMEIE", + "description": "ECC multi-bit error interrupt enable This bit enables the interrupt generation on ECC multi-bit error.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CRCEIE", + "description": "CRC error interrupt enable This bit enables the interrupt generation on CRC error.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PSEIE", + "description": "Packet size error interrupt enable This bit enables the interrupt generation on packet size error.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "EOTPEIE", + "description": "EoTp error interrupt enable This bit enables the interrupt generation on EoTp error.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "LPWREIE", + "description": "LTDC payload write error interrupt enable This bit enables the interrupt generation on LTDC payload write error.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GCWREIE", + "description": "Generic command write error interrupt enable This bit enables the interrupt generation on generic command write error.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "GPWREIE", + "description": "Generic payload write error interrupt enable This bit enables the interrupt generation on generic payload write error.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "GPTXEIE", + "description": "Generic payload transmit error interrupt enable This bit enables the interrupt generation on generic payload transmit error.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "GPRDEIE", + "description": "Generic payload read error interrupt enable This bit enables the interrupt generation on generic payload read error.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "GPRXEIE", + "description": "Generic payload receive error interrupt enable This bit enables the interrupt generation on generic payload receive error.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "PBUEIE", + "description": "Payload buffer underflow error interrupt enable This bit enables the interrupt generation on payload buffer underflow error.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/ISR0": { + "description": "DSI Host interrupt and status register 0.", + "fields": [ + { + "name": "AE0", + "description": "Acknowledge error 0 This bit retrieves the SoT error from the acknowledge error report.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AE1", + "description": "Acknowledge error 1 This bit retrieves the SoT sync error from the acknowledge error report.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AE2", + "description": "Acknowledge error 2 This bit retrieves the EoT sync error from the acknowledge error report.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AE3", + "description": "Acknowledge error 3 This bit retrieves the escape mode entry command error from the acknowledge error report.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AE4", + "description": "Acknowledge error 4 This bit retrieves the LP transmit sync error from the acknowledge error report.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AE5", + "description": "Acknowledge error 5 This bit retrieves the peripheral timeout error from the acknowledge error report.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AE6", + "description": "Acknowledge error 6 This bit retrieves the false control error from the acknowledge error report.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AE7", + "description": "Acknowledge error 7 This bit retrieves the reserved (specific to the device) from the acknowledge error report.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AE8", + "description": "Acknowledge error 8 This bit retrieves the ECC error, single-bit (detected and corrected) from the acknowledge error report.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AE9", + "description": "Acknowledge error 9 This bit retrieves the ECC error, multi-bit (detected, not corrected) from the acknowledge error report.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "AE10", + "description": "Acknowledge error 10 This bit retrieves the checksum error (long packet only) from the acknowledge error report.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "AE11", + "description": "Acknowledge error 11 This bit retrieves the not recognized DSI data type from the acknowledge error report.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "AE12", + "description": "Acknowledge error 12 This bit retrieves the DSI VC ID Invalid from the acknowledge error report.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "AE13", + "description": "Acknowledge error 13 This bit retrieves the invalid transmission length from the acknowledge error report.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "AE14", + "description": "Acknowledge error 14 This bit retrieves the reserved (specific to the device) from the acknowledge error report.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "AE15", + "description": "Acknowledge error 15 This bit retrieves the DSI protocol violation from the acknowledge error report.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "PE0", + "description": "PHY error 0 This bit indicates the ErrEsc escape entry error from lane 0.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PE1", + "description": "PHY error 1 This bit indicates the ErrSyncEsc low-power transmission synchronization error from lane 0.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "PE2", + "description": "PHY error 2 This bit indicates the ErrControl error from lane 0.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "PE3", + "description": "PHY error 3 This bit indicates the LP0 contention error ErrContentionLP0 from lane 0.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "PE4", + "description": "PHY error 4 This bit indicates the LP1 contention error ErrContentionLP1 from lane 0.", + "bit_offset": 20, + "bit_size": 1 + } + ] + }, + "fieldset/ISR1": { + "description": "DSI Host interrupt and status register 1.", + "fields": [ + { + "name": "TOHSTX", + "description": "Timeout high-speed transmission This bit indicates that the high-speed transmission timeout counter reached the end and contention is detected.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TOLPRX", + "description": "Timeout low-power reception This bit indicates that the low-power reception timeout counter reached the end and contention is detected.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ECCSE", + "description": "ECC single-bit error This bit indicates that the ECC single error is detected and corrected in a received packet.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ECCME", + "description": "ECC multi-bit error This bit indicates that the ECC multiple error is detected in a received packet.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CRCE", + "description": "CRC error This bit indicates that the CRC error is detected in the received packet payload.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PSE", + "description": "Packet size error This bit indicates that the packet size error is detected during the packet reception.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "EOTPE", + "description": "EoTp error This bit indicates that the EoTp packet is not received at the end of the incoming peripheral transmission.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "LPWRE", + "description": "LTDC payload write error This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GCWRE", + "description": "Generic command write error This bit indicates that the system tried to write a command through the generic interface and the FIFO is full. Therefore, the command is not written.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "GPWRE", + "description": "Generic payload write error This bit indicates that the system tried to write a payload data through the generic interface and the FIFO is full. Therefore, the payload is not written.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "GPTXE", + "description": "Generic payload transmit error This bit indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "GPRDE", + "description": "Generic payload read error This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "GPRXE", + "description": "Generic payload receive error This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "PBUE", + "description": "Payload buffer underflow error This bit indicates that underflow has occurred when reading payload to build DSI packet for video mode.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/LCCCR": { + "description": "DSI Host LTDC current color coding register.", + "fields": [ + { + "name": "COLC", + "description": "Color coding This field returns the current LTDC interface color coding. 0110-1111: reserved If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "LPE", + "description": "Loosely packed enable This bit returns the current state of the loosely packed variant to 18-bit configurations.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/LCCR": { + "description": "DSI Host LTDC command configuration register.", + "fields": [ + { + "name": "CMDSIZE", + "description": "Command size This field configures the maximum allowed size for an LTDC write memory command, measured in pixels. Automatic partitioning of data obtained from LTDC is permanently enabled.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/LCOLCR": { + "description": "DSI Host LTDC color coding register.", + "fields": [ + { + "name": "COLC", + "description": "Color coding This field configures the DPI color coding. Others: Reserved.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "LPE", + "description": "Loosely packet enable This bit enables the loosely packed variant to 18-bit configuration.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/LCVCIDR": { + "description": "DSI Host LTDC current VCID register.", + "fields": [ + { + "name": "VCID", + "description": "Virtual channel ID This field returns the virtual channel ID for the LTDC interface.", + "bit_offset": 0, + "bit_size": 2 + } + ] + }, + "fieldset/LPCR": { + "description": "DSI Host LTDC polarity configuration register.", + "fields": [ + { + "name": "DEP", + "description": "Data enable polarity This bit configures the polarity of data enable pin.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "VSP", + "description": "VSYNC polarity This bit configures the polarity of VSYNC pin.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "HSP", + "description": "HSYNC polarity This bit configures the polarity of HSYNC pin.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/LPMCCR": { + "description": "DSI Host low-power mode current configuration register.", + "fields": [ + { + "name": "VLPSIZE", + "description": "VACT largest packet size This field returns the current size, in bytes, of the largest packet that can fit in a line during VACT regions, for the transmission of commands in low-power mode.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LPSIZE", + "description": "Largest packet size This field is returns the current size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions, for the transmission of commands in low-power mode.", + "bit_offset": 16, + "bit_size": 8 + } + ] + }, + "fieldset/LPMCR": { + "description": "DSI Host low-power mode configuration register.", + "fields": [ + { + "name": "VLPSIZE", + "description": "VACT largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VACT regions.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LPSIZE", + "description": "Largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions.", + "bit_offset": 16, + "bit_size": 8 + } + ] + }, + "fieldset/LVCIDR": { + "description": "DSI Host LTDC VCID register.", + "fields": [ + { + "name": "VCID", + "description": "Virtual channel ID These bits configure the virtual channel ID for the LTDC interface traffic.", + "bit_offset": 0, + "bit_size": 2 + } + ] + }, + "fieldset/MCR": { + "description": "DSI Host mode configuration register.", + "fields": [ + { + "name": "CMDM", + "description": "Command mode This bit configures the DSI Host in either video or command mode.", + "bit_offset": 0, + "bit_size": 1 + } + ] + }, + "fieldset/PCONFR": { + "description": "DSI Host PHY configuration register.", + "fields": [ + { + "name": "NL", + "description": "Number of lanes This field configures the number of active data lanes: Others: Reserved.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "SW_TIME", + "description": "Stop wait time This field configures the minimum wait period to request a high-speed transmission after the Stop state.", + "bit_offset": 8, + "bit_size": 8 + } + ] + }, + "fieldset/PCR": { + "description": "DSI Host protocol configuration register.", + "fields": [ + { + "name": "ETTXE", + "description": "EoTp transmission enable This bit enables the EoTP transmission.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ETRXE", + "description": "EoTp reception enable This bit enables the EoTp reception.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BTAE", + "description": "Bus-turn-around enable This bit enables the bus-turn-around (BTA) request.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ECCRXE", + "description": "ECC reception enable This bit enables the ECC reception, error correction and reporting.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CRCRXE", + "description": "CRC reception enable This bit enables the CRC reception and error reporting.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ETTXLPE", + "description": "EoTp transmission in low-power enable This bit enables the EoTP transmission in low-power.", + "bit_offset": 5, + "bit_size": 1 + } + ] + }, + "fieldset/PCTLR": { + "description": "DSI Host PHY control register.", + "fields": [ + { + "name": "DEN", + "description": "Digital enable When set to 0, this bit places the digital section of the D-PHY in the reset state.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CKE", + "description": "Clock enable This bit enables the D-PHY clock lane module:.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/PSR": { + "description": "DSI Host PHY status register.", + "fields": [ + { + "name": "PD", + "description": "PHY direction This bit indicates the status of phydirection D-PHY signal.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "PSSC", + "description": "PHY stop state clock lane This bit indicates the status of phystopstateclklane D-PHY signal.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "UANC", + "description": "ULPS active not clock lane This bit indicates the status of ulpsactivenotclklane D-PHY signal.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PSS0", + "description": "PHY stop state lane 0 This bit indicates the status of phystopstate0lane D-PHY signal.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UAN0", + "description": "ULPS active not lane 1 This bit indicates the status of ulpsactivenot0lane D-PHY signal.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "RUE0", + "description": "RX ULPS escape lane 0 This bit indicates the status of rxulpsesc0lane D-PHY signal.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "PSS1", + "description": "PHY stop state lane 1 This bit indicates the status of phystopstate1lane D-PHY signal.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "UAN1", + "description": "ULPS active not lane 1 This bit indicates the status of ulpsactivenot1lane D-PHY signal.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/PTTCR": { + "description": "DSI Host PHY TX triggers configuration register.", + "fields": [ + { + "name": "TX_TRIG", + "description": "Transmission trigger Escape mode transmit trigger 0-3. Only one bit of TX_TRIG is asserted at any given time.", + "bit_offset": 0, + "bit_size": 4 + } + ] + }, + "fieldset/PUCR": { + "description": "DSI Host PHY ULPS control register.", + "fields": [ + { + "name": "URCL", + "description": "ULPS request on clock lane ULPS mode request on clock lane.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "UECL", + "description": "ULPS exit on clock lane ULPS mode exit on clock lane.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "URDL", + "description": "ULPS request on data lane ULPS mode request on all active data lanes.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "UEDL", + "description": "ULPS exit on data lane ULPS mode exit on all active data lanes.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/TCCR0": { + "description": "DSI Host timeout counter configuration register 0.", + "fields": [ + { + "name": "LPRX_TOCNT", + "description": "Low-power reception timeout counter This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in TOCKDIV cycles).", + "bit_offset": 0, + "bit_size": 16 + }, + { + "name": "HSTX_TOCNT", + "description": "High-speed transmission timeout counter This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in TOCKDIV cycles). If using the non-burst mode and there is no enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link returns the low-power state once per frame, then configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV ≥ the time of one FRAME data transmission * (1 + 10%) In burst mode, RGB pixel packets are time-compressed, leaving more time during a scan line. Therefore, if in burst mode and there is enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link can return low-power mode and back in this time interval to save power. For this, configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV ≥ the time of one LINE data transmission * (1 + 10%).", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR1": { + "description": "DSI Host timeout counter configuration register 1.", + "fields": [ + { + "name": "HSRD_TOCNT", + "description": "High-speed read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a high-speed read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR2": { + "description": "DSI Host timeout counter configuration register 2.", + "fields": [ + { + "name": "LPRD_TOCNT", + "description": "Low-power read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR3": { + "description": "DSI Host timeout counter configuration register 3.", + "fields": [ + { + "name": "HSWR_TOCNT", + "description": "High-speed write timeout counter This field sets a period for which the DSI Host keeps the link inactive after sending a high-speed write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.", + "bit_offset": 0, + "bit_size": 16 + }, + { + "name": "PM", + "description": "Presp mode When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: dpivsync_edpiwms has risen and fallen. Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/TCCR4": { + "description": "DSI Host timeout counter configuration register 4.", + "fields": [ + { + "name": "LPWR_TOCNT", + "description": "Low-power write timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR5": { + "description": "DSI Host timeout counter configuration register 5.", + "fields": [ + { + "name": "BTA_TOCNT", + "description": "Bus-turn-around timeout counter This field sets a period for which the DSI Host keeps the link still, after completing a bus-turn-around. This period is measured in cycles of lanebyteclk. The counting starts when the D‑PHY enters the Stop state and causes no interrupts.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/VCCCR": { + "description": "DSI Host video chunks current configuration register.", + "fields": [ + { + "name": "NUMC", + "description": "Number of chunks This field returns the number of chunks being transmitted during a line period.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VCCR": { + "description": "DSI Host video chunks configuration register.", + "fields": [ + { + "name": "NUMC", + "description": "Number of chunks This register configures the number of chunks to be transmitted during a line period (a chunk consists of a video packet and a null packet). If set to 0 or 1, the video line is transmitted in a single packet. If set to 1, the packet is part of a chunk, so a null packet follows it if NPSIZE > 0. Otherwise, multiple chunks are used to transmit each video line.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VHBPCCR": { + "description": "DSI Host video HBP current configuration register.", + "fields": [ + { + "name": "HBP", + "description": "Horizontal back-porch duration This field returns the horizontal back-porch period in lane byte clock cycles.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VHBPCR": { + "description": "DSI Host video HBP configuration register.", + "fields": [ + { + "name": "HBP", + "description": "Horizontal back-porch duration This fields configures the horizontal back-porch period in lane byte clock cycles.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VHSACCR": { + "description": "DSI Host video HSA current configuration register.", + "fields": [ + { + "name": "HSA", + "description": "Horizontal synchronism active duration This fields returns the horizontal synchronism active period in lane byte clock cycles.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VHSACR": { + "description": "DSI Host video HSA configuration register.", + "fields": [ + { + "name": "HSA", + "description": "Horizontal synchronism active duration This fields configures the horizontal synchronism active period in lane byte clock cycles.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VLCCR": { + "description": "DSI Host video line current configuration register.", + "fields": [ + { + "name": "HLINE", + "description": "Horizontal line duration This field returns the current total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles.", + "bit_offset": 0, + "bit_size": 15 + } + ] + }, + "fieldset/VLCR": { + "description": "DSI Host video line configuration register.", + "fields": [ + { + "name": "HLINE", + "description": "Horizontal line duration This fields configures the total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles.", + "bit_offset": 0, + "bit_size": 15 + } + ] + }, + "fieldset/VMCCR": { + "description": "DSI Host video mode current configuration register.", + "fields": [ + { + "name": "VMT", + "description": "Video mode type This field returns the current video mode transmission type: 1x: Burst mode.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "LPVSAE", + "description": "Low-power vertical sync time enable This bit returns the current state of return to low-power inside the vertical sync time (VSA) period when timing allows.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPVBPE", + "description": "Low-power vertical back-porch enable This bit returns the current state of return to low-power inside the vertical back-porch (VBP) period when timing allows.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "LPVFPE", + "description": "Low-power vertical front-porch enable This bit returns the current state of return to low-power inside the vertical front-porch (VFP) period when timing allows.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "LPVAE", + "description": "Low-power vertical active enable This bit returns the current state of return to low-power inside the vertical active (VACT) period when timing allows.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LPHBPE", + "description": "Low-power horizontal back-porch enable This bit returns the current state of return to low-power inside the horizontal back-porch (HBP) period when timing allows.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "LPHFE", + "description": "Low-power horizontal front-porch enable This bit returns the current state of return to low-power inside the horizontal front-porch (HFP) period when timing allows.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "FBTAAE", + "description": "Frame BTA acknowledge enable This bit returns the current state of request for an acknowledge response at the end of a frame.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPCE", + "description": "Low-power command enable This bit returns the current command transmission state in low-power mode.", + "bit_offset": 9, + "bit_size": 1 + } + ] + }, + "fieldset/VMCR": { + "description": "DSI Host video mode configuration register.", + "fields": [ + { + "name": "VMT", + "description": "Video mode type This field configures the video mode transmission type : 1x: Burst mode.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "LPVSAE", + "description": "Low-power vertical sync active enable This bit enables to return to low-power inside the vertical sync time (VSA) period when timing allows.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPVBPE", + "description": "Low-power vertical back-porch enable This bit enables to return to low-power inside the vertical back-porch (VBP) period when timing allows.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPVFPE", + "description": "Low-power vertical front-porch enable This bit enables to return to low-power inside the vertical front-porch (VFP) period when timing allows.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPVAE", + "description": "Low-power vertical active enable This bit enables to return to low-power inside the vertical active (VACT) period when timing allows.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPHBPE", + "description": "Low-power horizontal back-porch enable This bit enables the return to low-power inside the horizontal back-porch (HBP) period when timing allows.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "LPHFPE", + "description": "Low-power horizontal front-porch enable This bit enables the return to low-power inside the horizontal front-porch (HFP) period when timing allows.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "FBTAAE", + "description": "Frame bus-turn-around acknowledge enable This bit enables the request for an acknowledge response at the end of a frame.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "LPCE", + "description": "Low-power command enable This bit enables the command transmission only in low-power mode.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "PGE", + "description": "Pattern generator enable This bit enables the video mode pattern generator.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PGM", + "description": "Pattern generator mode This bit configures the pattern generator mode.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "PGO", + "description": "Pattern generator orientation This bit configures the color bar orientation.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/VNPCCR": { + "description": "DSI Host video null packet current configuration register.", + "fields": [ + { + "name": "NPSIZE", + "description": "Null packet size This field returns the number of bytes inside a null packet.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VNPCR": { + "description": "DSI Host video null packet configuration register.", + "fields": [ + { + "name": "NPSIZE", + "description": "Null packet size This field configures the number of bytes inside a null packet. Setting to 0 disables the null packets.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VPCCR": { + "description": "DSI Host video packet current configuration register.", + "fields": [ + { + "name": "VPSIZE", + "description": "Video packet size This field returns the number of pixels in a single video packet.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VPCR": { + "description": "DSI Host video packet configuration register.", + "fields": [ + { + "name": "VPSIZE", + "description": "Video packet size This field configures the number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4. For YCbCr data types, it must be a multiple of 2 as described in the DSI specification.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VR": { + "description": "DSI Host version register.", + "fields": [ + { + "name": "VERSION", + "description": "Version of the DSI Host This read-only register contains the version of the DSI Host.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/VSCR": { + "description": "DSI Host video shadow control register.", + "fields": [ + { + "name": "EN", + "description": "Enable When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. When this bit is set along with the UR bit, the auxiliary registers are automatically updated.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "UR", + "description": "Update register When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/VVACCR": { + "description": "DSI Host video VA current configuration register.", + "fields": [ + { + "name": "VA", + "description": "Vertical active duration This field returns the current vertical active period measured in number of horizontal lines.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VVACR": { + "description": "DSI Host video VA configuration register.", + "fields": [ + { + "name": "VA", + "description": "Vertical active duration This fields configures the vertical active period measured in number of horizontal lines.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VVBPCCR": { + "description": "DSI Host video VBP current configuration register.", + "fields": [ + { + "name": "VBP", + "description": "Vertical back-porch duration This field returns the current vertical back-porch period measured in number of horizontal lines.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVBPCR": { + "description": "DSI Host video VBP configuration register.", + "fields": [ + { + "name": "VBP", + "description": "Vertical back-porch duration This fields configures the vertical back-porch period measured in number of horizontal lines.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVFPCCR": { + "description": "DSI Host video VFP current configuration register.", + "fields": [ + { + "name": "VFP", + "description": "Vertical front-porch duration This field returns the current vertical front-porch period measured in number of horizontal lines.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVFPCR": { + "description": "DSI Host video VFP configuration register.", + "fields": [ + { + "name": "VFP", + "description": "Vertical front-porch duration This fields configures the vertical front-porch period measured in number of horizontal lines.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVSACCR": { + "description": "DSI Host video VSA current configuration register.", + "fields": [ + { + "name": "VSA", + "description": "Vertical synchronism active duration This field returns the current vertical synchronism active period measured in number of horizontal lines.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVSACR": { + "description": "DSI Host video VSA configuration register.", + "fields": [ + { + "name": "VSA", + "description": "Vertical synchronism active duration This fields configures the vertical synchronism active period measured in number of horizontal lines.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/WCFGR": { + "description": "DSI Wrapper configuration register.", + "fields": [ + { + "name": "DSIM", + "description": "DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (CR.EN = 0).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "COLMUX", + "description": "Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0).", + "bit_offset": 1, + "bit_size": 3 + }, + { + "name": "TESRC", + "description": "TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TEPOL", + "description": "TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AR", + "description": "Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (CR.EN = 0).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "VSPOL", + "description": "VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0).", + "bit_offset": 7, + "bit_size": 1 + } + ] + }, + "fieldset/WCR": { + "description": "DSI Wrapper control register.", + "fields": [ + { + "name": "COLM", + "description": "Color mode This bit controls the display color mode in video mode.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SHTDN", + "description": "Shutdown This bit controls the display shutdown in video mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "LTDCEN", + "description": "LTDC enable This bit enables the LTDC for a frame transfer in adapted command mode.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "DSIEN", + "description": "DSI enable This bit enables the DSI Wrapper.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/WIER": { + "description": "DSI Wrapper interrupt enable register.", + "fields": [ + { + "name": "TEIE", + "description": "Tearing effect interrupt enable This bit enables the tearing effect interrupt.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ERIE", + "description": "End of refresh interrupt enable This bit enables the end of refresh interrupt.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "PLLLIE", + "description": "PLL lock interrupt enable This bit enables the PLL lock interrupt.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "PLLUIE", + "description": "PLL unlock interrupt enable This bit enables the PLL unlock interrupt.", + "bit_offset": 10, + "bit_size": 1 + } + ] + }, + "fieldset/WIFCR": { + "description": "DSI Wrapper interrupt flag clear register.", + "fields": [ + { + "name": "CTEIF", + "description": "Clear tearing effect interrupt flag Write 1 clears the TEIF flag in the WSR register.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CERIF", + "description": "Clear end of refresh interrupt flag Write 1 clears the ERIF flag in the WSR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CPLLLIF", + "description": "Clear PLL lock interrupt flag Write 1 clears the PLLLIF flag in the WSR register.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "CPLLUIF", + "description": "Clear PLL unlock interrupt flag Write 1 clears the PLLUIF flag in the WSR register.", + "bit_offset": 10, + "bit_size": 1 + } + ] + }, + "fieldset/WISR": { + "description": "DSI Wrapper interrupt and status register.", + "fields": [ + { + "name": "TEIF", + "description": "Tearing effect interrupt flag This bit is set when a tearing effect event occurs.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ERIF", + "description": "End of refresh interrupt flag This bit is set when the transfer of a frame in adapted command mode is finished.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BUSY", + "description": "Busy flag This bit is set when the transfer of a frame in adapted command mode is ongoing.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PLLLS", + "description": "PLL lock status This bit is set when the PLL is locked and cleared when it is unlocked.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "PLLLIF", + "description": "PLL lock interrupt flag This bit is set when the PLL becomes locked.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "PLLUIF", + "description": "PLL unlock interrupt flag This bit is set when the PLL becomes unlocked.", + "bit_offset": 10, + "bit_size": 1 + } + ] + }, + "fieldset/WPCR0": { + "description": "DSI Wrapper PHY configuration register 0.", + "fields": [ + { + "name": "SWCL", + "description": "Swap clock lane pins This bit swaps the pins on clock lane.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SWDL0", + "description": "Swap data lane 0 pins This bit swaps the pins on data lane 0.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SWDL1", + "description": "Swap data lane 1 pins This bit swaps the pins on clock lane.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FTXSMCL", + "description": "Force in TX Stop mode the clock lane This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "FTXSMDL", + "description": "Force in TX Stop mode the data lanes This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence.", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/WRPCR": { + "description": "DSI Wrapper regulator and PLL control register.", + "fields": [ + { + "name": "PLLEN", + "description": "PLL enable This bit enables the D-PHY PLL.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "NDIV", + "description": "PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 ... 511: PLL loop divided by 511x2.", + "bit_offset": 2, + "bit_size": 9 + }, + { + "name": "IDF", + "description": "PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 ... 511: PLL input divided by 511.", + "bit_offset": 11, + "bit_size": 9 + }, + { + "name": "ODF", + "description": "PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 ... 511: PLL output divided by 511.", + "bit_offset": 20, + "bit_size": 9 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/dsihost_v1.json b/data/registers/dsihost_v1.json new file mode 100644 index 0000000..f1a746c --- /dev/null +++ b/data/registers/dsihost_v1.json @@ -0,0 +1,2639 @@ +{ + "block/DSIHOST": { + "description": "DSI Host.", + "items": [ + { + "name": "VR", + "description": "DSI Host Version Register.", + "byte_offset": 0, + "access": "Read", + "fieldset": "VR" + }, + { + "name": "CR", + "description": "DSI Host Control Register.", + "byte_offset": 4, + "fieldset": "CR" + }, + { + "name": "CCR", + "description": "DSI HOST Clock Control Register.", + "byte_offset": 8, + "fieldset": "CCR" + }, + { + "name": "LVCIDR", + "description": "DSI Host LTDC VCID Register.", + "byte_offset": 12, + "fieldset": "LVCIDR" + }, + { + "name": "LCOLCR", + "description": "DSI Host LTDC Color Coding Register.", + "byte_offset": 16, + "fieldset": "LCOLCR" + }, + { + "name": "LPCR", + "description": "DSI Host LTDC Polarity Configuration Register.", + "byte_offset": 20, + "fieldset": "LPCR" + }, + { + "name": "LPMCR", + "description": "DSI Host Low-Power mode Configuration Register.", + "byte_offset": 24, + "fieldset": "LPMCR" + }, + { + "name": "PCR", + "description": "DSI Host Protocol Configuration Register.", + "byte_offset": 44, + "fieldset": "PCR" + }, + { + "name": "GVCIDR", + "description": "DSI Host Generic VCID Register.", + "byte_offset": 48, + "fieldset": "GVCIDR" + }, + { + "name": "MCR", + "description": "DSI Host mode Configuration Register.", + "byte_offset": 52, + "fieldset": "MCR" + }, + { + "name": "VMCR", + "description": "DSI Host Video mode Configuration Register.", + "byte_offset": 56, + "fieldset": "VMCR" + }, + { + "name": "VPCR", + "description": "DSI Host Video Packet Configuration Register.", + "byte_offset": 60, + "fieldset": "VPCR" + }, + { + "name": "VCCR", + "description": "DSI Host Video Chunks Configuration Register.", + "byte_offset": 64, + "fieldset": "VCCR" + }, + { + "name": "VNPCR", + "description": "DSI Host Video Null Packet Configuration Register.", + "byte_offset": 68, + "fieldset": "VNPCR" + }, + { + "name": "VHSACR", + "description": "DSI Host Video HSA Configuration Register.", + "byte_offset": 72, + "fieldset": "VHSACR" + }, + { + "name": "VHBPCR", + "description": "DSI Host Video HBP Configuration Register.", + "byte_offset": 76, + "fieldset": "VHBPCR" + }, + { + "name": "VLCR", + "description": "DSI Host Video Line Configuration Register.", + "byte_offset": 80, + "fieldset": "VLCR" + }, + { + "name": "VVSACR", + "description": "DSI Host Video VSA Configuration Register.", + "byte_offset": 84, + "fieldset": "VVSACR" + }, + { + "name": "VVBPCR", + "description": "DSI Host Video VBP Configuration Register.", + "byte_offset": 88, + "fieldset": "VVBPCR" + }, + { + "name": "VVFPCR", + "description": "DSI Host Video VFP Configuration Register.", + "byte_offset": 92, + "fieldset": "VVFPCR" + }, + { + "name": "VVACR", + "description": "DSI Host Video VA Configuration Register.", + "byte_offset": 96, + "fieldset": "VVACR" + }, + { + "name": "LCCR", + "description": "DSI Host LTDC Command Configuration Register.", + "byte_offset": 100, + "fieldset": "LCCR" + }, + { + "name": "CMCR", + "description": "DSI Host Command mode Configuration Register.", + "byte_offset": 104, + "fieldset": "CMCR" + }, + { + "name": "GHCR", + "description": "DSI Host Generic Header Configuration Register.", + "byte_offset": 108, + "fieldset": "GHCR" + }, + { + "name": "GPDR", + "description": "DSI Host Generic Payload Data Register.", + "byte_offset": 112, + "fieldset": "GPDR" + }, + { + "name": "GPSR", + "description": "DSI Host Generic Packet Status Register.", + "byte_offset": 116, + "access": "Read", + "fieldset": "GPSR" + }, + { + "name": "TCCR0", + "description": "DSI Host Timeout Counter Configuration Register 0.", + "byte_offset": 120, + "fieldset": "TCCR0" + }, + { + "name": "TCCR1", + "description": "DSI Host Timeout Counter Configuration Register 1.", + "byte_offset": 124, + "fieldset": "TCCR1" + }, + { + "name": "TCCR2", + "description": "DSI Host Timeout Counter Configuration Register 2.", + "byte_offset": 128, + "fieldset": "TCCR2" + }, + { + "name": "TCCR3", + "description": "DSI Host Timeout Counter Configuration Register 3.", + "byte_offset": 132, + "fieldset": "TCCR3" + }, + { + "name": "TCCR4", + "description": "DSI Host Timeout Counter Configuration Register 4.", + "byte_offset": 136, + "fieldset": "TCCR4" + }, + { + "name": "TCCR5", + "description": "DSI Host Timeout Counter Configuration Register 5.", + "byte_offset": 140, + "fieldset": "TCCR5" + }, + { + "name": "CLCR", + "description": "DSI Host Clock Lane Configuration Register.", + "byte_offset": 148, + "fieldset": "CLCR" + }, + { + "name": "CLTCR", + "description": "DSI Host Clock Lane Timer Configuration Register.", + "byte_offset": 152, + "fieldset": "CLTCR" + }, + { + "name": "DLTCR", + "description": "DSI Host Data Lane Timer Configuration Register.", + "byte_offset": 156, + "fieldset": "DLTCR" + }, + { + "name": "PCTLR", + "description": "DSI Host PHY Control Register.", + "byte_offset": 160, + "fieldset": "PCTLR" + }, + { + "name": "PCONFR", + "description": "DSI Host PHY Configuration Register.", + "byte_offset": 164, + "fieldset": "PCONFR" + }, + { + "name": "PUCR", + "description": "DSI Host PHY ULPS Control Register.", + "byte_offset": 168, + "fieldset": "PUCR" + }, + { + "name": "PTTCR", + "description": "DSI Host PHY TX Triggers Configuration Register.", + "byte_offset": 172, + "fieldset": "PTTCR" + }, + { + "name": "PSR", + "description": "DSI Host PHY Status Register.", + "byte_offset": 176, + "access": "Read", + "fieldset": "PSR" + }, + { + "name": "ISR0", + "description": "DSI Host Interrupt & Status Register 0.", + "byte_offset": 188, + "access": "Read", + "fieldset": "ISR0" + }, + { + "name": "ISR1", + "description": "DSI Host Interrupt & Status Register 1.", + "byte_offset": 192, + "access": "Read", + "fieldset": "ISR1" + }, + { + "name": "IER0", + "description": "DSI Host Interrupt Enable Register 0.", + "byte_offset": 196, + "fieldset": "IER0" + }, + { + "name": "IER1", + "description": "DSI Host Interrupt Enable Register 1.", + "byte_offset": 200, + "fieldset": "IER1" + }, + { + "name": "FIR0", + "description": "DSI Host Force Interrupt Register 0.", + "byte_offset": 216, + "access": "Write", + "fieldset": "FIR0" + }, + { + "name": "FIR1", + "description": "DSI Host Force Interrupt Register 1.", + "byte_offset": 220, + "access": "Write", + "fieldset": "FIR1" + }, + { + "name": "VSCR", + "description": "DSI Host Video Shadow Control Register.", + "byte_offset": 256, + "fieldset": "VSCR" + }, + { + "name": "LCVCIDR", + "description": "DSI Host LTDC Current VCID Register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "LCVCIDR" + }, + { + "name": "LCCCR", + "description": "DSI Host LTDC Current Color Coding Register.", + "byte_offset": 272, + "access": "Read", + "fieldset": "LCCCR" + }, + { + "name": "LPMCCR", + "description": "DSI Host Low-Power mode Current Configuration Register.", + "byte_offset": 280, + "access": "Read", + "fieldset": "LPMCCR" + }, + { + "name": "VMCCR", + "description": "DSI Host Video mode Current Configuration Register.", + "byte_offset": 312, + "access": "Read", + "fieldset": "VMCCR" + }, + { + "name": "VPCCR", + "description": "DSI Host Video Packet Current Configuration Register.", + "byte_offset": 316, + "access": "Read", + "fieldset": "VPCCR" + }, + { + "name": "VCCCR", + "description": "DSI Host Video Chunks Current Configuration Register.", + "byte_offset": 320, + "access": "Read", + "fieldset": "VCCCR" + }, + { + "name": "VNPCCR", + "description": "DSI Host Video Null Packet Current Configuration Register.", + "byte_offset": 324, + "access": "Read", + "fieldset": "VNPCCR" + }, + { + "name": "VHSACCR", + "description": "DSI Host Video HSA Current Configuration Register.", + "byte_offset": 328, + "access": "Read", + "fieldset": "VHSACCR" + }, + { + "name": "VHBPCCR", + "description": "DSI Host Video HBP Current Configuration Register.", + "byte_offset": 332, + "access": "Read", + "fieldset": "VHBPCCR" + }, + { + "name": "VLCCR", + "description": "DSI Host Video Line Current Configuration Register.", + "byte_offset": 336, + "access": "Read", + "fieldset": "VLCCR" + }, + { + "name": "VVSACCR", + "description": "DSI Host Video VSA Current Configuration Register.", + "byte_offset": 340, + "access": "Read", + "fieldset": "VVSACCR" + }, + { + "name": "VVBPCCR", + "description": "DSI Host Video VBP Current Configuration Register.", + "byte_offset": 344, + "access": "Read", + "fieldset": "VVBPCCR" + }, + { + "name": "VVFPCCR", + "description": "DSI Host Video VFP Current Configuration Register.", + "byte_offset": 348, + "access": "Read", + "fieldset": "VVFPCCR" + }, + { + "name": "VVACCR", + "description": "DSI Host Video VA Current Configuration Register.", + "byte_offset": 352, + "access": "Read", + "fieldset": "VVACCR" + }, + { + "name": "WCFGR", + "description": "DSI Wrapper Configuration Register.", + "byte_offset": 1024, + "fieldset": "WCFGR" + }, + { + "name": "WCR", + "description": "DSI Wrapper Control Register.", + "byte_offset": 1028, + "fieldset": "WCR" + }, + { + "name": "WIER", + "description": "DSI Wrapper Interrupt Enable Register.", + "byte_offset": 1032, + "fieldset": "WIER" + }, + { + "name": "WISR", + "description": "DSI Wrapper Interrupt & Status Register.", + "byte_offset": 1036, + "access": "Read", + "fieldset": "WISR" + }, + { + "name": "WIFCR", + "description": "DSI Wrapper Interrupt Flag Clear Register.", + "byte_offset": 1040, + "fieldset": "WIFCR" + }, + { + "name": "WPCR0", + "description": "DSI Wrapper PHY Configuration Register 0.", + "byte_offset": 1048, + "fieldset": "WPCR0" + }, + { + "name": "WPCR1", + "description": "DSI Wrapper PHY Configuration Register 1.", + "byte_offset": 1052, + "fieldset": "WPCR1" + }, + { + "name": "WPCR2", + "description": "DSI Wrapper PHY Configuration Register 2.", + "byte_offset": 1056, + "fieldset": "WPCR2" + }, + { + "name": "WPCR3", + "description": "DSI Wrapper PHY Configuration Register 3.", + "byte_offset": 1060, + "fieldset": "WPCR3" + }, + { + "name": "WPCR4", + "description": "DSI Wrapper PHY Configuration Register 4.", + "byte_offset": 1064, + "fieldset": "WPCR4" + }, + { + "name": "WRPCR", + "description": "DSI Wrapper Regulator and PLL Control Register.", + "byte_offset": 1072, + "fieldset": "WRPCR" + } + ] + }, + "fieldset/CCR": { + "description": "DSI HOST Clock Control Register.", + "fields": [ + { + "name": "TXECKDIV", + "description": "TX Escape Clock Division.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "TOCKDIV", + "description": "Timeout Clock Division.", + "bit_offset": 8, + "bit_size": 8 + } + ] + }, + "fieldset/CLCR": { + "description": "DSI Host Clock Lane Configuration Register.", + "fields": [ + { + "name": "DPCC", + "description": "D-PHY Clock Control.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACR", + "description": "Automatic Clock lane Control.", + "bit_offset": 1, + "bit_size": 1 + } + ] + }, + "fieldset/CLTCR": { + "description": "DSI Host Clock Lane Timer Configuration Register.", + "fields": [ + { + "name": "LP2HS_TIME", + "description": "Low-Power to High-Speed Time.", + "bit_offset": 0, + "bit_size": 10 + }, + { + "name": "HS2LP_TIME", + "description": "High-Speed to Low-Power Time.", + "bit_offset": 16, + "bit_size": 10 + } + ] + }, + "fieldset/CMCR": { + "description": "DSI Host Command mode Configuration Register.", + "fields": [ + { + "name": "TEARE", + "description": "Tearing Effect Acknowledge Request Enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ARE", + "description": "Acknowledge Request Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GSW0TX", + "description": "Generic Short Write Zero parameters Transmission.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "GSW1TX", + "description": "Generic Short Write One parameters Transmission.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "GSW2TX", + "description": "Generic Short Write Two parameters Transmission.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "GSR0TX", + "description": "Generic Short Read Zero parameters Transmission.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "GSR1TX", + "description": "Generic Short Read One parameters Transmission.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "GSR2TX", + "description": "Generic Short Read Two parameters Transmission.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GLWTX", + "description": "Generic Long Write Transmission.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "DSW0TX", + "description": "DCS Short Write Zero parameter Transmission.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "DSW1TX", + "description": "DCS Short Read One parameter Transmission.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "DSR0TX", + "description": "DCS Short Read Zero parameter Transmission.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "DLWTX", + "description": "DCS Long Write Transmission.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "MRDPS", + "description": "Maximum Read Packet Size.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CR": { + "description": "DSI Host Control Register.", + "fields": [ + { + "name": "EN", + "description": "Enable.", + "bit_offset": 0, + "bit_size": 1 + } + ] + }, + "fieldset/DLTCR": { + "description": "DSI Host Data Lane Timer Configuration Register.", + "fields": [ + { + "name": "MRD_TIME", + "description": "Maximum Read Time.", + "bit_offset": 0, + "bit_size": 15 + }, + { + "name": "LP2HS_TIME", + "description": "Low-Power To High-Speed Time.", + "bit_offset": 16, + "bit_size": 8 + }, + { + "name": "HS2LP_TIME", + "description": "High-Speed To Low-Power Time.", + "bit_offset": 24, + "bit_size": 8 + } + ] + }, + "fieldset/FIR0": { + "description": "DSI Host Force Interrupt Register 0.", + "fields": [ + { + "name": "FAE0", + "description": "Force Acknowledge Error 0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "FAE1", + "description": "Force Acknowledge Error 1.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "FAE2", + "description": "Force Acknowledge Error 2.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "FAE3", + "description": "Force Acknowledge Error 3.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FAE4", + "description": "Force Acknowledge Error 4.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "FAE5", + "description": "Force Acknowledge Error 5.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FAE6", + "description": "Force Acknowledge Error 6.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "FAE7", + "description": "Force Acknowledge Error 7.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "FAE8", + "description": "Force Acknowledge Error 8.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FAE9", + "description": "Force Acknowledge Error 9.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "FAE10", + "description": "Force Acknowledge Error 10.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "FAE11", + "description": "Force Acknowledge Error 11.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "FAE12", + "description": "Force Acknowledge Error 12.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "FAE13", + "description": "Force Acknowledge Error 13.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "FAE14", + "description": "Force Acknowledge Error 14.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "FAE15", + "description": "Force Acknowledge Error 15.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "FPE0", + "description": "Force PHY Error 0.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "FPE1", + "description": "Force PHY Error 1.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "FPE2", + "description": "Force PHY Error 2.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "FPE3", + "description": "Force PHY Error 3.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "FPE4", + "description": "Force PHY Error 4.", + "bit_offset": 20, + "bit_size": 1 + } + ] + }, + "fieldset/FIR1": { + "description": "DSI Host Force Interrupt Register 1.", + "fields": [ + { + "name": "FTOHSTX", + "description": "Force Timeout High-Speed Transmission.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "FTOLPRX", + "description": "Force Timeout Low-Power Reception.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "FECCSE", + "description": "Force ECC Single-bit Error.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "FECCME", + "description": "Force ECC Multi-bit Error.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FCRCE", + "description": "Force CRC Error.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "FPSE", + "description": "Force Packet Size Error.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FEOTPE", + "description": "Force EoTp Error.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "FLPWRE", + "description": "Force LTDC Payload Write Error.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "FGCWRE", + "description": "Force Generic Command Write Error.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FGPWRE", + "description": "Force Generic Payload Write Error.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "FGPTXE", + "description": "Force Generic Payload Transmit Error.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "FGPRDE", + "description": "Force Generic Payload Read Error.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "FGPRXE", + "description": "Force Generic Payload Receive Error.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/GHCR": { + "description": "DSI Host Generic Header Configuration Register.", + "fields": [ + { + "name": "DT", + "description": "Type.", + "bit_offset": 0, + "bit_size": 6 + }, + { + "name": "VCID", + "description": "Channel.", + "bit_offset": 6, + "bit_size": 2 + }, + { + "name": "WCLSB", + "description": "WordCount LSB.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "WCMSB", + "description": "WordCount MSB.", + "bit_offset": 16, + "bit_size": 8 + } + ] + }, + "fieldset/GPDR": { + "description": "DSI Host Generic Payload Data Register.", + "fields": [ + { + "name": "DATA1", + "description": "Payload Byte 1.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "DATA2", + "description": "Payload Byte 2.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "DATA3", + "description": "Payload Byte 3.", + "bit_offset": 16, + "bit_size": 8 + }, + { + "name": "DATA4", + "description": "Payload Byte 4.", + "bit_offset": 24, + "bit_size": 8 + } + ] + }, + "fieldset/GPSR": { + "description": "DSI Host Generic Packet Status Register.", + "fields": [ + { + "name": "CMDFE", + "description": "Command FIFO Empty.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CMDFF", + "description": "Command FIFO Full.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "PWRFE", + "description": "Payload Write FIFO Empty.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PWRFF", + "description": "Payload Write FIFO Full.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PRDFE", + "description": "Payload Read FIFO Empty.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PRDFF", + "description": "Payload Read FIFO Full.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "RCB", + "description": "Read Command Busy.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/GVCIDR": { + "description": "DSI Host Generic VCID Register.", + "fields": [ + { + "name": "VCID", + "description": "Virtual Channel ID.", + "bit_offset": 0, + "bit_size": 2 + } + ] + }, + "fieldset/IER0": { + "description": "DSI Host Interrupt Enable Register 0.", + "fields": [ + { + "name": "AE0IE", + "description": "Acknowledge Error 0 Interrupt Enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AE1IE", + "description": "Acknowledge Error 1 Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AE2IE", + "description": "Acknowledge Error 2 Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AE3IE", + "description": "Acknowledge Error 3 Interrupt Enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AE4IE", + "description": "Acknowledge Error 4 Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AE5IE", + "description": "Acknowledge Error 5 Interrupt Enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AE6IE", + "description": "Acknowledge Error 6 Interrupt Enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AE7IE", + "description": "Acknowledge Error 7 Interrupt Enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AE8IE", + "description": "Acknowledge Error 8 Interrupt Enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AE9IE", + "description": "Acknowledge Error 9 Interrupt Enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "AE10IE", + "description": "Acknowledge Error 10 Interrupt Enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "AE11IE", + "description": "Acknowledge Error 11 Interrupt Enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "AE12IE", + "description": "Acknowledge Error 12 Interrupt Enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "AE13IE", + "description": "Acknowledge Error 13 Interrupt Enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "AE14IE", + "description": "Acknowledge Error 14 Interrupt Enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "AE15IE", + "description": "Acknowledge Error 15 Interrupt Enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "PE0IE", + "description": "PHY Error 0 Interrupt Enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PE1IE", + "description": "PHY Error 1 Interrupt Enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "PE2IE", + "description": "PHY Error 2 Interrupt Enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "PE3IE", + "description": "PHY Error 3 Interrupt Enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "PE4IE", + "description": "PHY Error 4 Interrupt Enable.", + "bit_offset": 20, + "bit_size": 1 + } + ] + }, + "fieldset/IER1": { + "description": "DSI Host Interrupt Enable Register 1.", + "fields": [ + { + "name": "TOHSTXIE", + "description": "Timeout High-Speed Transmission Interrupt Enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TOLPRXIE", + "description": "Timeout Low-Power Reception Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ECCSEIE", + "description": "ECC Single-bit Error Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ECCMEIE", + "description": "ECC Multi-bit Error Interrupt Enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CRCEIE", + "description": "CRC Error Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PSEIE", + "description": "Packet Size Error Interrupt Enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "EOTPEIE", + "description": "EoTp Error Interrupt Enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "LPWREIE", + "description": "LTDC Payload Write Error Interrupt Enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GCWREIE", + "description": "Generic Command Write Error Interrupt Enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "GPWREIE", + "description": "Generic Payload Write Error Interrupt Enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "GPTXEIE", + "description": "Generic Payload Transmit Error Interrupt Enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "GPRDEIE", + "description": "Generic Payload Read Error Interrupt Enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "GPRXEIE", + "description": "Generic Payload Receive Error Interrupt Enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/ISR0": { + "description": "DSI Host Interrupt & Status Register 0.", + "fields": [ + { + "name": "AE0", + "description": "Acknowledge Error 0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AE1", + "description": "Acknowledge Error 1.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AE2", + "description": "Acknowledge Error 2.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AE3", + "description": "Acknowledge Error 3.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AE4", + "description": "Acknowledge Error 4.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AE5", + "description": "Acknowledge Error 5.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AE6", + "description": "Acknowledge Error 6.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AE7", + "description": "Acknowledge Error 7.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AE8", + "description": "Acknowledge Error 8.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AE9", + "description": "Acknowledge Error 9.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "AE10", + "description": "Acknowledge Error 10.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "AE11", + "description": "Acknowledge Error 11.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "AE12", + "description": "Acknowledge Error 12.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "AE13", + "description": "Acknowledge Error 13.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "AE14", + "description": "Acknowledge Error 14.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "AE15", + "description": "Acknowledge Error 15.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "PE0", + "description": "PHY Error 0.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PE1", + "description": "PHY Error 1.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "PE2", + "description": "PHY Error 2.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "PE3", + "description": "PHY Error 3.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "PE4", + "description": "PHY Error 4.", + "bit_offset": 20, + "bit_size": 1 + } + ] + }, + "fieldset/ISR1": { + "description": "DSI Host Interrupt & Status Register 1.", + "fields": [ + { + "name": "TOHSTX", + "description": "Timeout High-Speed Transmission.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TOLPRX", + "description": "Timeout Low-Power Reception.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ECCSE", + "description": "ECC Single-bit Error.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ECCME", + "description": "ECC Multi-bit Error.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CRCE", + "description": "CRC Error.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PSE", + "description": "Packet Size Error.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "EOTPE", + "description": "EoTp Error.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "LPWRE", + "description": "LTDC Payload Write Error.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GCWRE", + "description": "Generic Command Write Error.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "GPWRE", + "description": "Generic Payload Write Error.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "GPTXE", + "description": "Generic Payload Transmit Error.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "GPRDE", + "description": "Generic Payload Read Error.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "GPRXE", + "description": "Generic Payload Receive Error.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/LCCCR": { + "description": "DSI Host LTDC Current Color Coding Register.", + "fields": [ + { + "name": "COLC", + "description": "Color Coding.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "LPE", + "description": "Loosely Packed Enable.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/LCCR": { + "description": "DSI Host LTDC Command Configuration Register.", + "fields": [ + { + "name": "CMDSIZE", + "description": "Command Size.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/LCOLCR": { + "description": "DSI Host LTDC Color Coding Register.", + "fields": [ + { + "name": "COLC", + "description": "Color Coding.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "LPE", + "description": "Loosely Packet Enable.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/LCVCIDR": { + "description": "DSI Host LTDC Current VCID Register.", + "fields": [ + { + "name": "VCID", + "description": "Virtual Channel ID.", + "bit_offset": 0, + "bit_size": 2 + } + ] + }, + "fieldset/LPCR": { + "description": "DSI Host LTDC Polarity Configuration Register.", + "fields": [ + { + "name": "DEP", + "description": "Data Enable Polarity.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "VSP", + "description": "VSYNC Polarity.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "HSP", + "description": "HSYNC Polarity.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/LPMCCR": { + "description": "DSI Host Low-Power mode Current Configuration Register.", + "fields": [ + { + "name": "VLPSIZE", + "description": "VACT Largest Packet Size.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LPSIZE", + "description": "Largest Packet Size.", + "bit_offset": 16, + "bit_size": 8 + } + ] + }, + "fieldset/LPMCR": { + "description": "DSI Host Low-Power mode Configuration Register.", + "fields": [ + { + "name": "VLPSIZE", + "description": "VACT Largest Packet Size.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LPSIZE", + "description": "Largest Packet Size.", + "bit_offset": 16, + "bit_size": 8 + } + ] + }, + "fieldset/LVCIDR": { + "description": "DSI Host LTDC VCID Register.", + "fields": [ + { + "name": "VCID", + "description": "Virtual Channel ID.", + "bit_offset": 0, + "bit_size": 2 + } + ] + }, + "fieldset/MCR": { + "description": "DSI Host mode Configuration Register.", + "fields": [ + { + "name": "CMDM", + "description": "Command mode.", + "bit_offset": 0, + "bit_size": 1 + } + ] + }, + "fieldset/PCONFR": { + "description": "DSI Host PHY Configuration Register.", + "fields": [ + { + "name": "NL", + "description": "Number of Lanes.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "SW_TIME", + "description": "Stop Wait Time.", + "bit_offset": 8, + "bit_size": 8 + } + ] + }, + "fieldset/PCR": { + "description": "DSI Host Protocol Configuration Register.", + "fields": [ + { + "name": "ETTXE", + "description": "EoTp Transmission Enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ETRXE", + "description": "EoTp Reception Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BTAE", + "description": "Bus Turn Around Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ECCRXE", + "description": "ECC Reception Enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CRCRXE", + "description": "CRC Reception Enable.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/PCTLR": { + "description": "DSI Host PHY Control Register.", + "fields": [ + { + "name": "DEN", + "description": "Digital Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CKE", + "description": "Clock Enable.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/PSR": { + "description": "DSI Host PHY Status Register.", + "fields": [ + { + "name": "PD", + "description": "PHY Direction.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "PSSC", + "description": "PHY Stop State Clock lane.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "UANC", + "description": "ULPS Active Not Clock lane.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PSS0", + "description": "PHY Stop State lane 0.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UAN0", + "description": "ULPS Active Not lane 1.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "RUE0", + "description": "RX ULPS Escape lane 0.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "PSS1", + "description": "PHY Stop State lane 1.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "UAN1", + "description": "ULPS Active Not lane 1.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/PTTCR": { + "description": "DSI Host PHY TX Triggers Configuration Register.", + "fields": [ + { + "name": "TX_TRIG", + "description": "Transmission Trigger.", + "bit_offset": 0, + "bit_size": 4 + } + ] + }, + "fieldset/PUCR": { + "description": "DSI Host PHY ULPS Control Register.", + "fields": [ + { + "name": "URCL", + "description": "ULPS Request on Clock Lane.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "UECL", + "description": "ULPS Exit on Clock Lane.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "URDL", + "description": "ULPS Request on Data Lane.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "UEDL", + "description": "ULPS Exit on Data Lane.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/TCCR0": { + "description": "DSI Host Timeout Counter Configuration Register 0.", + "fields": [ + { + "name": "LPRX_TOCNT", + "description": "Low-power Reception Timeout Counter.", + "bit_offset": 0, + "bit_size": 16 + }, + { + "name": "HSTX_TOCNT", + "description": "High-Speed Transmission Timeout Counter.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR1": { + "description": "DSI Host Timeout Counter Configuration Register 1.", + "fields": [ + { + "name": "HSRD_TOCNT", + "description": "High-Speed Read Timeout Counter.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR2": { + "description": "DSI Host Timeout Counter Configuration Register 2.", + "fields": [ + { + "name": "LPRD_TOCNT", + "description": "Low-Power Read Timeout Counter.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR3": { + "description": "DSI Host Timeout Counter Configuration Register 3.", + "fields": [ + { + "name": "HSWR_TOCNT", + "description": "High-Speed Write Timeout Counter.", + "bit_offset": 0, + "bit_size": 16 + }, + { + "name": "PM", + "description": "Presp mode.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/TCCR4": { + "description": "DSI Host Timeout Counter Configuration Register 4.", + "fields": [ + { + "name": "LSWR_TOCNT", + "description": "Low-Power Write Timeout Counter.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR5": { + "description": "DSI Host Timeout Counter Configuration Register 5.", + "fields": [ + { + "name": "BTA_TOCNT", + "description": "Bus-Turn-Around Timeout Counter.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/VCCCR": { + "description": "DSI Host Video Chunks Current Configuration Register.", + "fields": [ + { + "name": "NUMC", + "description": "Number of Chunks.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VCCR": { + "description": "DSI Host Video Chunks Configuration Register.", + "fields": [ + { + "name": "NUMC", + "description": "Number of Chunks.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VHBPCCR": { + "description": "DSI Host Video HBP Current Configuration Register.", + "fields": [ + { + "name": "HBP", + "description": "Horizontal Back-Porch duration.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VHBPCR": { + "description": "DSI Host Video HBP Configuration Register.", + "fields": [ + { + "name": "HBP", + "description": "Horizontal Back-Porch duration.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VHSACCR": { + "description": "DSI Host Video HSA Current Configuration Register.", + "fields": [ + { + "name": "HSA", + "description": "Horizontal Synchronism Active duration.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VHSACR": { + "description": "DSI Host Video HSA Configuration Register.", + "fields": [ + { + "name": "HSA", + "description": "Horizontal Synchronism Active duration.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VLCCR": { + "description": "DSI Host Video Line Current Configuration Register.", + "fields": [ + { + "name": "HLINE", + "description": "Horizontal Line duration.", + "bit_offset": 0, + "bit_size": 15 + } + ] + }, + "fieldset/VLCR": { + "description": "DSI Host Video Line Configuration Register.", + "fields": [ + { + "name": "HLINE", + "description": "Horizontal Line duration.", + "bit_offset": 0, + "bit_size": 15 + } + ] + }, + "fieldset/VMCCR": { + "description": "DSI Host Video mode Current Configuration Register.", + "fields": [ + { + "name": "VMT", + "description": "Video mode Type.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "LPVSAE", + "description": "Low-Power Vertical Sync time Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPVBPE", + "description": "Low-power Vertical Back-Porch Enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "LPVFPE", + "description": "Low-power Vertical Front-Porch Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "LPVAE", + "description": "Low-Power Vertical Active Enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LPHBPE", + "description": "Low-power Horizontal Back-Porch Enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "LPHFE", + "description": "Low-Power Horizontal Front-Porch Enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "FBTAAE", + "description": "Frame BTA Acknowledge Enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPCE", + "description": "Low-Power Command Enable.", + "bit_offset": 9, + "bit_size": 1 + } + ] + }, + "fieldset/VMCR": { + "description": "DSI Host Video mode Configuration Register.", + "fields": [ + { + "name": "VMT", + "description": "Video mode Type.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "LPVSAE", + "description": "Low-Power Vertical Sync Active Enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPVBPE", + "description": "Low-power Vertical Back-Porch Enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPVFPE", + "description": "Low-power Vertical Front-porch Enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPVAE", + "description": "Low-Power Vertical Active Enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPHBPE", + "description": "Low-Power Horizontal Back-Porch Enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "LPHFPE", + "description": "Low-Power Horizontal Front-Porch Enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "FBTAAE", + "description": "Frame Bus-Turn-Around Acknowledge Enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "LPCE", + "description": "Low-Power Command Enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "PGE", + "description": "Pattern Generator Enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PGM", + "description": "Pattern Generator mode.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "PGO", + "description": "Pattern Generator Orientation.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/VNPCCR": { + "description": "DSI Host Video Null Packet Current Configuration Register.", + "fields": [ + { + "name": "NPSIZE", + "description": "Null Packet Size.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VNPCR": { + "description": "DSI Host Video Null Packet Configuration Register.", + "fields": [ + { + "name": "NPSIZE", + "description": "Null Packet Size.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VPCCR": { + "description": "DSI Host Video Packet Current Configuration Register.", + "fields": [ + { + "name": "VPSIZE", + "description": "Video Packet Size.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VPCR": { + "description": "DSI Host Video Packet Configuration Register.", + "fields": [ + { + "name": "VPSIZE", + "description": "Video Packet Size.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VR": { + "description": "DSI Host Version Register.", + "fields": [ + { + "name": "VERSION", + "description": "Version of the DSI Host.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/VSCR": { + "description": "DSI Host Video Shadow Control Register.", + "fields": [ + { + "name": "EN", + "description": "Enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "UR", + "description": "Update Register.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/VVACCR": { + "description": "DSI Host Video VA Current Configuration Register.", + "fields": [ + { + "name": "VA", + "description": "Vertical Active duration.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VVACR": { + "description": "DSI Host Video VA Configuration Register.", + "fields": [ + { + "name": "VA", + "description": "Vertical Active duration.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VVBPCCR": { + "description": "DSI Host Video VBP Current Configuration Register.", + "fields": [ + { + "name": "VBP", + "description": "Vertical Back-Porch duration.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVBPCR": { + "description": "DSI Host Video VBP Configuration Register.", + "fields": [ + { + "name": "VBP", + "description": "Vertical Back-Porch duration.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVFPCCR": { + "description": "DSI Host Video VFP Current Configuration Register.", + "fields": [ + { + "name": "VFP", + "description": "Vertical Front-Porch duration.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVFPCR": { + "description": "DSI Host Video VFP Configuration Register.", + "fields": [ + { + "name": "VFP", + "description": "Vertical Front-Porch duration.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVSACCR": { + "description": "DSI Host Video VSA Current Configuration Register.", + "fields": [ + { + "name": "VSA", + "description": "Vertical Synchronism Active duration.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVSACR": { + "description": "DSI Host Video VSA Configuration Register.", + "fields": [ + { + "name": "VSA", + "description": "Vertical Synchronism Active duration.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/WCFGR": { + "description": "DSI Wrapper Configuration Register.", + "fields": [ + { + "name": "DSIM", + "description": "DSI Mode.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "COLMUX", + "description": "Color Multiplexing.", + "bit_offset": 1, + "bit_size": 3 + }, + { + "name": "TESRC", + "description": "TE Source.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TEPOL", + "description": "TE Polarity.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AR", + "description": "Automatic Refresh.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "VSPOL", + "description": "VSync Polarity.", + "bit_offset": 7, + "bit_size": 1 + } + ] + }, + "fieldset/WCR": { + "description": "DSI Wrapper Control Register.", + "fields": [ + { + "name": "COLM", + "description": "Color Mode.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SHTDN", + "description": "Shutdown.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "LTDCEN", + "description": "LTDC Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "DSIEN", + "description": "DSI Enable.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/WIER": { + "description": "DSI Wrapper Interrupt Enable Register.", + "fields": [ + { + "name": "TEIE", + "description": "Tearing Effect Interrupt Enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ERIE", + "description": "End of Refresh Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "PLLLIE", + "description": "PLL Lock Interrupt Enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "PLLUIE", + "description": "PLL Unlock Interrupt Enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "RRIE", + "description": "Regulator Ready Interrupt Enable.", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/WIFCR": { + "description": "DSI Wrapper Interrupt Flag Clear Register.", + "fields": [ + { + "name": "CTEIF", + "description": "Clear Tearing Effect Interrupt Flag.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CERIF", + "description": "Clear End of Refresh Interrupt Flag.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CPLLLIF", + "description": "Clear PLL Lock Interrupt Flag.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "CPLLUIF", + "description": "Clear PLL Unlock Interrupt Flag.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "CRRIF", + "description": "Clear Regulator Ready Interrupt Flag.", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/WISR": { + "description": "DSI Wrapper Interrupt & Status Register.", + "fields": [ + { + "name": "TEIF", + "description": "Tearing Effect Interrupt Flag.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ERIF", + "description": "End of Refresh Interrupt Flag.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BUSY", + "description": "Busy Flag.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PLLLS", + "description": "PLL Lock Status.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "PLLLIF", + "description": "PLL Lock Interrupt Flag.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "PLLUIF", + "description": "PLL Unlock Interrupt Flag.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "RRS", + "description": "Regulator Ready Status.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "RRIF", + "description": "Regulator Ready Interrupt Flag.", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/WPCR0": { + "description": "DSI Wrapper PHY Configuration Register 0.", + "fields": [ + { + "name": "UIX4", + "description": "Unit Interval multiplied by 4.", + "bit_offset": 0, + "bit_size": 6 + }, + { + "name": "SWCL", + "description": "Swap Clock Lane pins.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SWDL0", + "description": "Swap Data Lane 0 pins.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SWDL1", + "description": "Swap Data Lane 1 pins.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "HSICL", + "description": "Invert Hight-Speed data signal on Clock Lane.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "HSIDL0", + "description": "Invert the Hight-Speed data signal on Data Lane 0.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "HSIDL1", + "description": "Invert the High-Speed data signal on Data Lane 1.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "FTXSMCL", + "description": "Force in TX Stop Mode the Clock Lane.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "FTXSMDL", + "description": "Force in TX Stop Mode the Data Lanes.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "CDOFFDL", + "description": "Contention Detection OFF on Data Lanes.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "TDDL", + "description": "Turn Disable Data Lanes.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PDEN", + "description": "Pull-Down Enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "TCLKPREPEN", + "description": "custom time for tCLK-PREPARE Enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "TCLKZEROEN", + "description": "custom time for tCLK-ZERO Enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "THSPREPEN", + "description": "custom time for tHS-PREPARE Enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "THSTRAILEN", + "description": "custom time for tHS-TRAIL Enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "THSZEROEN", + "description": "custom time for tHS-ZERO Enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "TLPXDEN", + "description": "custom time for tLPX for Data lanes Enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "THSEXITEN", + "description": "custom time for tHS-EXIT Enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "TLPXCEN", + "description": "custom time for tLPX for Clock lane Enable.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "TCLKPOSTEN", + "description": "custom time for tCLK-POST Enable.", + "bit_offset": 27, + "bit_size": 1 + } + ] + }, + "fieldset/WPCR1": { + "description": "DSI Wrapper PHY Configuration Register 1.", + "fields": [ + { + "name": "HSTXDCL", + "description": "High-Speed Transmission Delay on Clock Lane.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "HSTXDLL", + "description": "High-Speed Transmission Delay on Data Lanes.", + "bit_offset": 2, + "bit_size": 2 + }, + { + "name": "LPSRCL", + "description": "Low-Power transmission Slew Rate Compensation on Clock Lane.", + "bit_offset": 6, + "bit_size": 2 + }, + { + "name": "LPSRDL", + "description": "Low-Power transmission Slew Rate Compensation on Data Lanes.", + "bit_offset": 8, + "bit_size": 2 + }, + { + "name": "SDCC", + "description": "SDD Control.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "HSTXSRCCL", + "description": "High-Speed Transmission Slew Rate Control on Clock Lane.", + "bit_offset": 16, + "bit_size": 2 + }, + { + "name": "HSTXSRCDL", + "description": "High-Speed Transmission Slew Rate Control on Data Lanes.", + "bit_offset": 18, + "bit_size": 2 + }, + { + "name": "FLPRXLPM", + "description": "Forces LP Receiver in Low-Power Mode.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "LPRXFT", + "description": "Low-Power RX low-pass Filtering Tuning.", + "bit_offset": 25, + "bit_size": 2 + } + ] + }, + "fieldset/WPCR2": { + "description": "DSI Wrapper PHY Configuration Register 2.", + "fields": [ + { + "name": "TCLKPREP", + "description": "tCLK-PREPARE.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "TCLKZEO", + "description": "tCLK-ZERO.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "THSPREP", + "description": "tHS-PREPARE.", + "bit_offset": 16, + "bit_size": 8 + }, + { + "name": "THSTRAIL", + "description": "tHSTRAIL.", + "bit_offset": 24, + "bit_size": 8 + } + ] + }, + "fieldset/WPCR3": { + "description": "DSI Wrapper PHY Configuration Register 3.", + "fields": [ + { + "name": "THSZERO", + "description": "tHS-ZERO.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "TLPXD", + "description": "tLPX for Data lanes.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "THSEXIT", + "description": "tHSEXIT.", + "bit_offset": 16, + "bit_size": 8 + }, + { + "name": "TLPXC", + "description": "tLPXC for Clock lane.", + "bit_offset": 24, + "bit_size": 8 + } + ] + }, + "fieldset/WPCR4": { + "description": "DSI Wrapper PHY Configuration Register 4.", + "fields": [ + { + "name": "TCLKPOST", + "description": "tCLK-POST.", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "fieldset/WRPCR": { + "description": "DSI Wrapper Regulator and PLL Control Register.", + "fields": [ + { + "name": "PLLEN", + "description": "PLL Enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "NDIV", + "description": "PLL Loop Division Factor.", + "bit_offset": 2, + "bit_size": 7 + }, + { + "name": "IDF", + "description": "PLL Input Division Factor.", + "bit_offset": 11, + "bit_size": 4 + }, + { + "name": "ODF", + "description": "PLL Output Division Factor.", + "bit_offset": 16, + "bit_size": 2 + }, + { + "name": "REGEN", + "description": "Regulator Enable.", + "bit_offset": 24, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/dsihost_v2.json b/data/registers/dsihost_v2.json new file mode 100644 index 0000000..86fb91a --- /dev/null +++ b/data/registers/dsihost_v2.json @@ -0,0 +1,2600 @@ +{ + "block/DSIHOST": { + "description": "DSIHOST1.", + "items": [ + { + "name": "VR", + "description": "DSI Host version register.", + "byte_offset": 0, + "access": "Read", + "fieldset": "VR" + }, + { + "name": "CR", + "description": "DSI Host control register.", + "byte_offset": 4, + "fieldset": "CR" + }, + { + "name": "CCR", + "description": "DSI Host clock control register.", + "byte_offset": 8, + "fieldset": "CCR" + }, + { + "name": "LVCIDR", + "description": "DSI Host LTDC VCID register.", + "byte_offset": 12, + "fieldset": "LVCIDR" + }, + { + "name": "LCOLCR", + "description": "DSI Host LTDC color coding register.", + "byte_offset": 16, + "fieldset": "LCOLCR" + }, + { + "name": "LPCR", + "description": "DSI Host LTDC polarity configuration register.", + "byte_offset": 20, + "fieldset": "LPCR" + }, + { + "name": "LPMCR", + "description": "DSI Host low-power mode configuration register.", + "byte_offset": 24, + "fieldset": "LPMCR" + }, + { + "name": "PCR", + "description": "DSI Host protocol configuration register.", + "byte_offset": 44, + "fieldset": "PCR" + }, + { + "name": "GVCIDR", + "description": "DSI Host generic VCID register.", + "byte_offset": 48, + "access": "Read", + "fieldset": "GVCIDR" + }, + { + "name": "MCR", + "description": "DSI Host mode configuration register.", + "byte_offset": 52, + "fieldset": "MCR" + }, + { + "name": "VMCR", + "description": "DSI Host video mode configuration register.", + "byte_offset": 56, + "fieldset": "VMCR" + }, + { + "name": "VPCR", + "description": "DSI Host video packet configuration register.", + "byte_offset": 60, + "fieldset": "VPCR" + }, + { + "name": "VCCR", + "description": "DSI Host video chunks configuration register.", + "byte_offset": 64, + "fieldset": "VCCR" + }, + { + "name": "VNPCR", + "description": "DSI Host video null packet configuration register.", + "byte_offset": 68, + "fieldset": "VNPCR" + }, + { + "name": "VHSACR", + "description": "DSI Host video HSA configuration register.", + "byte_offset": 72, + "fieldset": "VHSACR" + }, + { + "name": "VHBPCR", + "description": "DSI Host video HBP configuration register.", + "byte_offset": 76, + "fieldset": "VHBPCR" + }, + { + "name": "VLCR", + "description": "DSI Host video line configuration register.", + "byte_offset": 80, + "fieldset": "VLCR" + }, + { + "name": "VVSACR", + "description": "DSI Host video VSA configuration register.", + "byte_offset": 84, + "fieldset": "VVSACR" + }, + { + "name": "VVBPCR", + "description": "DSI Host video VBP configuration register.", + "byte_offset": 88, + "fieldset": "VVBPCR" + }, + { + "name": "VVFPCR", + "description": "DSI Host video VFP configuration register.", + "byte_offset": 92, + "fieldset": "VVFPCR" + }, + { + "name": "VVACR", + "description": "DSI Host video VA configuration register.", + "byte_offset": 96, + "fieldset": "VVACR" + }, + { + "name": "LCCR", + "description": "DSI Host LTDC command configuration register.", + "byte_offset": 100, + "fieldset": "LCCR" + }, + { + "name": "CMCR", + "description": "DSI Host command mode configuration register.", + "byte_offset": 104, + "fieldset": "CMCR" + }, + { + "name": "GHCR", + "description": "DSI Host generic header configuration register.", + "byte_offset": 108, + "fieldset": "GHCR" + }, + { + "name": "GPDR", + "description": "DSI Host generic payload data register.", + "byte_offset": 112, + "fieldset": "GPDR" + }, + { + "name": "GPSR", + "description": "DSI Host generic packet status register.", + "byte_offset": 116, + "access": "Read", + "fieldset": "GPSR" + }, + { + "name": "TCCR0", + "description": "DSI Host timeout counter configuration register 0.", + "byte_offset": 120, + "fieldset": "TCCR0" + }, + { + "name": "TCCR1", + "description": "DSI Host timeout counter configuration register 1.", + "byte_offset": 124, + "fieldset": "TCCR1" + }, + { + "name": "TCCR2", + "description": "DSI Host timeout counter configuration register 2.", + "byte_offset": 128, + "fieldset": "TCCR2" + }, + { + "name": "TCCR3", + "description": "DSI Host timeout counter configuration register 3.", + "byte_offset": 132, + "fieldset": "TCCR3" + }, + { + "name": "TCCR4", + "description": "DSI Host timeout counter configuration register 4.", + "byte_offset": 136, + "fieldset": "TCCR4" + }, + { + "name": "TCCR5", + "description": "DSI Host timeout counter configuration register 5.", + "byte_offset": 140, + "fieldset": "TCCR5" + }, + { + "name": "CLCR", + "description": "DSI Host clock lane configuration register.", + "byte_offset": 148, + "fieldset": "CLCR" + }, + { + "name": "CLTCR", + "description": "DSI Host clock lane timer configuration register.", + "byte_offset": 152, + "fieldset": "CLTCR" + }, + { + "name": "DLTCR", + "description": "DSI Host data lane timer configuration register.", + "byte_offset": 156, + "fieldset": "DLTCR" + }, + { + "name": "PCTLR", + "description": "DSI Host PHY control register.", + "byte_offset": 160, + "fieldset": "PCTLR" + }, + { + "name": "PCONFR", + "description": "DSI Host PHY configuration register.", + "byte_offset": 164, + "fieldset": "PCONFR" + }, + { + "name": "PUCR", + "description": "DSI Host PHY ULPS control register.", + "byte_offset": 168, + "fieldset": "PUCR" + }, + { + "name": "PTTCR", + "description": "DSI Host PHY TX triggers configuration register.", + "byte_offset": 172, + "fieldset": "PTTCR" + }, + { + "name": "PSR", + "description": "DSI Host PHY status register.", + "byte_offset": 176, + "access": "Read", + "fieldset": "PSR" + }, + { + "name": "ISR0", + "description": "DSI Host interrupt and status register 0.", + "byte_offset": 188, + "access": "Read", + "fieldset": "ISR0" + }, + { + "name": "ISR1", + "description": "DSI Host interrupt and status register 1.", + "byte_offset": 192, + "access": "Read", + "fieldset": "ISR1" + }, + { + "name": "IER0", + "description": "DSI Host interrupt enable register 0.", + "byte_offset": 196, + "fieldset": "IER0" + }, + { + "name": "IER1", + "description": "DSI Host interrupt enable register 1.", + "byte_offset": 200, + "fieldset": "IER1" + }, + { + "name": "FIR0", + "description": "DSI Host force interrupt register 0.", + "byte_offset": 216, + "access": "Write", + "fieldset": "FIR0" + }, + { + "name": "FIR1", + "description": "DSI Host force interrupt register 1.", + "byte_offset": 220, + "access": "Write", + "fieldset": "FIR1" + }, + { + "name": "DLTRCR", + "description": "DSI Host data lane timer read configuration register.", + "byte_offset": 244, + "fieldset": "DLTRCR" + }, + { + "name": "VSCR", + "description": "DSI Host video shadow control register.", + "byte_offset": 256, + "fieldset": "VSCR" + }, + { + "name": "LCVCIDR", + "description": "DSI Host LTDC current VCID register.", + "byte_offset": 268, + "fieldset": "LCVCIDR" + }, + { + "name": "LCCCR", + "description": "DSI Host LTDC current color coding register.", + "byte_offset": 272, + "access": "Read", + "fieldset": "LCCCR" + }, + { + "name": "LPMCCR", + "description": "DSI Host low-power mode current configuration register.", + "byte_offset": 280, + "access": "Read", + "fieldset": "LPMCCR" + }, + { + "name": "VMCCR", + "description": "DSI Host video mode current configuration register.", + "byte_offset": 312, + "access": "Read", + "fieldset": "VMCCR" + }, + { + "name": "VPCCR", + "description": "DSI Host video packet current configuration register.", + "byte_offset": 316, + "access": "Read", + "fieldset": "VPCCR" + }, + { + "name": "VCCCR", + "description": "DSI Host video chunks current configuration register.", + "byte_offset": 320, + "access": "Read", + "fieldset": "VCCCR" + }, + { + "name": "VNPCCR", + "description": "DSI Host video null packet current configuration register.", + "byte_offset": 324, + "access": "Read", + "fieldset": "VNPCCR" + }, + { + "name": "VHSACCR", + "description": "DSI Host video HSA current configuration register.", + "byte_offset": 328, + "access": "Read", + "fieldset": "VHSACCR" + }, + { + "name": "VHBPCCR", + "description": "DSI Host video HBP current configuration register.", + "byte_offset": 332, + "access": "Read", + "fieldset": "VHBPCCR" + }, + { + "name": "VLCCR", + "description": "DSI Host video line current configuration register.", + "byte_offset": 336, + "access": "Read", + "fieldset": "VLCCR" + }, + { + "name": "VVSACCR", + "description": "DSI Host video VSA current configuration register.", + "byte_offset": 340, + "access": "Read", + "fieldset": "VVSACCR" + }, + { + "name": "VVBPCCR", + "description": "DSI Host video VBP current configuration register.", + "byte_offset": 344, + "access": "Read", + "fieldset": "VVBPCCR" + }, + { + "name": "VVFPCCR", + "description": "DSI Host video VFP current configuration register.", + "byte_offset": 348, + "access": "Read", + "fieldset": "VVFPCCR" + }, + { + "name": "VVACCR", + "description": "DSI Host video VA current configuration register.", + "byte_offset": 352, + "access": "Read", + "fieldset": "VVACCR" + }, + { + "name": "WCFGR", + "description": "DSI wrapper configuration register.", + "byte_offset": 1024, + "fieldset": "WCFGR" + }, + { + "name": "WCR", + "description": "DSI wrapper control register.", + "byte_offset": 1028, + "fieldset": "WCR" + }, + { + "name": "WIER", + "description": "DSI wrapper interrupt enable register.", + "byte_offset": 1032, + "fieldset": "WIER" + }, + { + "name": "WISR", + "description": "DSI wrapper interrupt and status register.", + "byte_offset": 1036, + "access": "Read", + "fieldset": "WISR" + }, + { + "name": "WIFCR", + "description": "DSI wrapper interrupt flag clear register.", + "byte_offset": 1040, + "access": "Write", + "fieldset": "WIFCR" + }, + { + "name": "WPCR0", + "description": "DSI wrapper PHY configuration register 0.", + "byte_offset": 1048, + "fieldset": "WPCR0" + }, + { + "name": "WPCR1", + "description": "This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0).", + "byte_offset": 1052, + "fieldset": "WPCR1" + }, + { + "name": "WRPCR", + "description": "DSI wrapper regulator and PLL control register.", + "byte_offset": 1072, + "fieldset": "WRPCR" + }, + { + "name": "HWCFGR", + "description": "DSI Host hardware configuration register.", + "byte_offset": 2032, + "access": "Read", + "fieldset": "HWCFGR" + }, + { + "name": "VERR", + "description": "DSI Host version register.", + "byte_offset": 2036, + "access": "Read", + "fieldset": "VERR" + }, + { + "name": "IPIDR", + "description": "DSI Host identification register.", + "byte_offset": 2040, + "access": "Read", + "fieldset": "IPIDR" + }, + { + "name": "SIDR", + "description": "DSI Host size identification register.", + "byte_offset": 2044, + "access": "Read", + "fieldset": "SIDR" + } + ] + }, + "fieldset/CCR": { + "description": "DSI Host clock control register.", + "fields": [ + { + "name": "TXECKDIV", + "description": "TXECKDIV.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "TOCKDIV", + "description": "TOCKDIV.", + "bit_offset": 8, + "bit_size": 8 + } + ] + }, + "fieldset/CLCR": { + "description": "DSI Host clock lane configuration register.", + "fields": [ + { + "name": "DPCC", + "description": "DPCC.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACR", + "description": "ACR.", + "bit_offset": 1, + "bit_size": 1 + } + ] + }, + "fieldset/CLTCR": { + "description": "DSI Host clock lane timer configuration register.", + "fields": [ + { + "name": "LP2HS_TIME", + "description": "LP2HS_TIME.", + "bit_offset": 0, + "bit_size": 10 + }, + { + "name": "HS2LP_TIME", + "description": "HS2LP_TIME.", + "bit_offset": 16, + "bit_size": 10 + } + ] + }, + "fieldset/CMCR": { + "description": "DSI Host command mode configuration register.", + "fields": [ + { + "name": "TEARE", + "description": "TEARE.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ARE", + "description": "ARE.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GSW0TX", + "description": "GSW0TX.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "GSW1TX", + "description": "GSW1TX.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "GSW2TX", + "description": "GSW2TX.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "GSR0TX", + "description": "GSR0TX.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "GSR1TX", + "description": "GSR1TX.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "GSR2TX", + "description": "GSR2TX.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GLWTX", + "description": "GLWTX.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "DSW0TX", + "description": "DSW0TX.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "DSW1TX", + "description": "DSW1TX.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "DSR0TX", + "description": "DSR0TX.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "DLWTX", + "description": "DLWTX.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "MRDPS", + "description": "MRDPS.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CR": { + "description": "DSI Host control register.", + "fields": [ + { + "name": "EN", + "description": "EN.", + "bit_offset": 0, + "bit_size": 1 + } + ] + }, + "fieldset/DLTCR": { + "description": "DSI Host data lane timer configuration register.", + "fields": [ + { + "name": "LP2HS_TIME", + "description": "LP2HS_TIME.", + "bit_offset": 0, + "bit_size": 10 + }, + { + "name": "HS2LP_TIME", + "description": "HS2LP_TIME.", + "bit_offset": 16, + "bit_size": 10 + } + ] + }, + "fieldset/DLTRCR": { + "description": "DSI Host data lane timer read configuration register.", + "fields": [ + { + "name": "MRD_TIME", + "description": "MRD_TIME.", + "bit_offset": 0, + "bit_size": 15 + } + ] + }, + "fieldset/FIR0": { + "description": "DSI Host force interrupt register 0.", + "fields": [ + { + "name": "FAE0", + "description": "FAE0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "FAE1", + "description": "FAE1.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "FAE2", + "description": "FAE2.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "FAE3", + "description": "FAE3.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FAE4", + "description": "FAE4.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "FAE5", + "description": "FAE5.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FAE6", + "description": "FAE6.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "FAE7", + "description": "FAE7.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "FAE8", + "description": "FAE8.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FAE9", + "description": "FAE9.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "FAE10", + "description": "FAE10.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "FAE11", + "description": "FAE11.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "FAE12", + "description": "FAE12.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "FAE13", + "description": "FAE13.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "FAE14", + "description": "FAE14.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "FAE15", + "description": "FAE15.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "FPE0", + "description": "FPE0.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "FPE1", + "description": "FPE1.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "FPE2", + "description": "FPE2.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "FPE3", + "description": "FPE3.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "FPE4", + "description": "FPE4.", + "bit_offset": 20, + "bit_size": 1 + } + ] + }, + "fieldset/FIR1": { + "description": "DSI Host force interrupt register 1.", + "fields": [ + { + "name": "FTOHSTX", + "description": "FTOHSTX.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "FTOLPRX", + "description": "FTOLPRX.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "FECCSE", + "description": "FECCSE.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "FECCME", + "description": "FECCME.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FCRCE", + "description": "FCRCE.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "FPSE", + "description": "FPSE.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FEOTPE", + "description": "FEOTPE.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "FLPWRE", + "description": "FLPWRE.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "FGCWRE", + "description": "FGCWRE.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FGPWRE", + "description": "FGPWRE.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "FGPTXE", + "description": "FGPTXE.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "FGPRDE", + "description": "FGPRDE.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "FGPRXE", + "description": "FGPRXE.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/GHCR": { + "description": "DSI Host generic header configuration register.", + "fields": [ + { + "name": "DT", + "description": "DT.", + "bit_offset": 0, + "bit_size": 6 + }, + { + "name": "VCID", + "description": "VCID.", + "bit_offset": 6, + "bit_size": 2 + }, + { + "name": "WCLSB", + "description": "WCLSB.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "WCMSB", + "description": "WCMSB.", + "bit_offset": 16, + "bit_size": 8 + } + ] + }, + "fieldset/GPDR": { + "description": "DSI Host generic payload data register.", + "fields": [ + { + "name": "DATA1", + "description": "DATA1.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "DATA2", + "description": "DATA2.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "DATA3", + "description": "DATA3.", + "bit_offset": 16, + "bit_size": 8 + }, + { + "name": "DATA4", + "description": "DATA4.", + "bit_offset": 24, + "bit_size": 8 + } + ] + }, + "fieldset/GPSR": { + "description": "DSI Host generic packet status register.", + "fields": [ + { + "name": "CMDFE", + "description": "CMDFE.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CMDFF", + "description": "CMDFF.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "PWRFE", + "description": "PWRFE.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PWRFF", + "description": "PWRFF.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PRDFE", + "description": "PRDFE.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PRDFF", + "description": "PRDFF.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "RCB", + "description": "RCB.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/GVCIDR": { + "description": "DSI Host generic VCID register.", + "fields": [ + { + "name": "VCID", + "description": "VCID.", + "bit_offset": 0, + "bit_size": 2 + } + ] + }, + "fieldset/HWCFGR": { + "description": "DSI Host hardware configuration register.", + "fields": [ + { + "name": "TECHNO", + "description": "TECHNO.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "FIFOSIZE", + "description": "FIFOSIZE.", + "bit_offset": 4, + "bit_size": 12 + } + ] + }, + "fieldset/IER0": { + "description": "DSI Host interrupt enable register 0.", + "fields": [ + { + "name": "AE0IE", + "description": "AE0IE.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AE1IE", + "description": "AE1IE.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AE2IE", + "description": "AE2IE.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AE3IE", + "description": "AE3IE.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AE4IE", + "description": "AE4IE.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AE5IE", + "description": "AE5IE.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AE6IE", + "description": "AE6IE.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AE7IE", + "description": "AE7IE.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AE8IE", + "description": "AE8IE.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AE9IE", + "description": "AE9IE.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "AE10IE", + "description": "AE10IE.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "AE11IE", + "description": "AE11IE.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "AE12IE", + "description": "AE12IE.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "AE13IE", + "description": "AE13IE.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "AE14IE", + "description": "AE14IE.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "AE15IE", + "description": "AE15IE.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "PE0IE", + "description": "PE0IE.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PE1IE", + "description": "PE1IE.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "PE2IE", + "description": "PE2IE.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "PE3IE", + "description": "PE3IE.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "PE4IE", + "description": "PE4IE.", + "bit_offset": 20, + "bit_size": 1 + } + ] + }, + "fieldset/IER1": { + "description": "DSI Host interrupt enable register 1.", + "fields": [ + { + "name": "TOHSTXIE", + "description": "TOHSTXIE.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TOLPRXIE", + "description": "TOLPRXIE.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ECCSEIE", + "description": "ECCSEIE.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ECCMEIE", + "description": "ECCMEIE.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CRCEIE", + "description": "CRCEIE.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PSEIE", + "description": "PSEIE.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "EOTPEIE", + "description": "EOTPEIE.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "LPWREIE", + "description": "LPWREIE.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GCWREIE", + "description": "GCWREIE.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "GPWREIE", + "description": "GPWREIE.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "GPTXEIE", + "description": "GPTXEIE.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "GPRDEIE", + "description": "GPRDEIE.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "GPRXEIE", + "description": "GPRXEIE.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/IPIDR": { + "description": "DSI Host identification register.", + "fields": [ + { + "name": "ID", + "description": "ID.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/ISR0": { + "description": "DSI Host interrupt and status register 0.", + "fields": [ + { + "name": "AE0", + "description": "AE0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AE1", + "description": "AE1.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AE2", + "description": "AE2.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AE3", + "description": "AE3.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AE4", + "description": "AE4.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AE5", + "description": "AE5.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AE6", + "description": "AE6.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AE7", + "description": "AE7.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AE8", + "description": "AE8.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AE9", + "description": "AE9.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "AE10", + "description": "AE10.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "AE11", + "description": "AE11.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "AE12", + "description": "AE12.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "AE13", + "description": "AE13.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "AE14", + "description": "AE14.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "AE15", + "description": "AE15.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "PE0", + "description": "PE0.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PE1", + "description": "PE1.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "PE2", + "description": "PE2.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "PE3", + "description": "PE3.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "PE4", + "description": "PE4.", + "bit_offset": 20, + "bit_size": 1 + } + ] + }, + "fieldset/ISR1": { + "description": "DSI Host interrupt and status register 1.", + "fields": [ + { + "name": "TOHSTX", + "description": "TOHSTX.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TOLPRX", + "description": "TOLPRX.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ECCSE", + "description": "ECCSE.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ECCME", + "description": "ECCME.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CRCE", + "description": "CRCE.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PSE", + "description": "PSE.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "EOTPE", + "description": "EOTPE.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "LPWRE", + "description": "LPWRE.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GCWRE", + "description": "GCWRE.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "GPWRE", + "description": "GPWRE.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "GPTXE", + "description": "GPTXE.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "GPRDE", + "description": "GPRDE.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "GPRXE", + "description": "GPRXE.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/LCCCR": { + "description": "DSI Host LTDC current color coding register.", + "fields": [ + { + "name": "COLC", + "description": "COLC.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "LPE", + "description": "LPE.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/LCCR": { + "description": "DSI Host LTDC command configuration register.", + "fields": [ + { + "name": "CMDSIZE", + "description": "CMDSIZE.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/LCOLCR": { + "description": "DSI Host LTDC color coding register.", + "fields": [ + { + "name": "COLC", + "description": "COLC.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "LPE", + "description": "LPE.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/LCVCIDR": { + "description": "DSI Host LTDC current VCID register.", + "fields": [ + { + "name": "VCID", + "description": "VCID.", + "bit_offset": 0, + "bit_size": 2 + } + ] + }, + "fieldset/LPCR": { + "description": "DSI Host LTDC polarity configuration register.", + "fields": [ + { + "name": "DEP", + "description": "DEP.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "VSP", + "description": "VSP.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "HSP", + "description": "HSP.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/LPMCCR": { + "description": "DSI Host low-power mode current configuration register.", + "fields": [ + { + "name": "VLPSIZE", + "description": "VLPSIZE.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LPSIZE", + "description": "LPSIZE.", + "bit_offset": 16, + "bit_size": 8 + } + ] + }, + "fieldset/LPMCR": { + "description": "DSI Host low-power mode configuration register.", + "fields": [ + { + "name": "VLPSIZE", + "description": "VLPSIZE.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LPSIZE", + "description": "LPSIZE.", + "bit_offset": 16, + "bit_size": 8 + } + ] + }, + "fieldset/LVCIDR": { + "description": "DSI Host LTDC VCID register.", + "fields": [ + { + "name": "VCID", + "description": "VCID.", + "bit_offset": 0, + "bit_size": 2 + } + ] + }, + "fieldset/MCR": { + "description": "DSI Host mode configuration register.", + "fields": [ + { + "name": "CMDM", + "description": "CMDM.", + "bit_offset": 0, + "bit_size": 1 + } + ] + }, + "fieldset/PCONFR": { + "description": "DSI Host PHY configuration register.", + "fields": [ + { + "name": "NL", + "description": "NL.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "SW_TIME", + "description": "SW_TIME.", + "bit_offset": 8, + "bit_size": 8 + } + ] + }, + "fieldset/PCR": { + "description": "DSI Host protocol configuration register.", + "fields": [ + { + "name": "ETTXE", + "description": "ETTXE.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ETRXE", + "description": "ETRXE.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BTAE", + "description": "BTAE.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ECCRXE", + "description": "ECCRXE.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CRCRXE", + "description": "CRCRXE.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/PCTLR": { + "description": "DSI Host PHY control register.", + "fields": [ + { + "name": "DEN", + "description": "DEN.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CKE", + "description": "CKE.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/PSR": { + "description": "DSI Host PHY status register.", + "fields": [ + { + "name": "PD", + "description": "PD.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "PSSC", + "description": "PSSC.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "UANC", + "description": "UANC.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PSS0", + "description": "PSS0.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UAN0", + "description": "UAN0.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "RUE0", + "description": "RUE0.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "PSS1", + "description": "PSS1.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "UAN1", + "description": "UAN1.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/PTTCR": { + "description": "DSI Host PHY TX triggers configuration register.", + "fields": [ + { + "name": "TX_TRIG", + "description": "TX_TRIG.", + "bit_offset": 0, + "bit_size": 4 + } + ] + }, + "fieldset/PUCR": { + "description": "DSI Host PHY ULPS control register.", + "fields": [ + { + "name": "URCL", + "description": "URCL.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "UECL", + "description": "UECL.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "URDL", + "description": "URDL.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "UEDL", + "description": "UEDL.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/SIDR": { + "description": "DSI Host size identification register.", + "fields": [ + { + "name": "SID", + "description": "SID.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/TCCR0": { + "description": "DSI Host timeout counter configuration register 0.", + "fields": [ + { + "name": "LPRX_TOCNT", + "description": "LPRX_TOCNT.", + "bit_offset": 0, + "bit_size": 16 + }, + { + "name": "HSTX_TOCNT", + "description": "HSTX_TOCNT.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR1": { + "description": "DSI Host timeout counter configuration register 1.", + "fields": [ + { + "name": "HSRD_TOCNT", + "description": "HSRD_TOCNT.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR2": { + "description": "DSI Host timeout counter configuration register 2.", + "fields": [ + { + "name": "LPRD_TOCNT", + "description": "LPRD_TOCNT.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR3": { + "description": "DSI Host timeout counter configuration register 3.", + "fields": [ + { + "name": "HSWR_TOCNT", + "description": "HSWR_TOCNT.", + "bit_offset": 0, + "bit_size": 16 + }, + { + "name": "PM", + "description": "PM.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/TCCR4": { + "description": "DSI Host timeout counter configuration register 4.", + "fields": [ + { + "name": "LPWR_TOCNT", + "description": "LPWR_TOCNT.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/TCCR5": { + "description": "DSI Host timeout counter configuration register 5.", + "fields": [ + { + "name": "BTA_TOCNT", + "description": "BTA_TOCNT.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/VCCCR": { + "description": "DSI Host video chunks current configuration register.", + "fields": [ + { + "name": "NUMC", + "description": "NUMC.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VCCR": { + "description": "DSI Host video chunks configuration register.", + "fields": [ + { + "name": "NUMC", + "description": "NUMC.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VERR": { + "description": "DSI Host version register.", + "fields": [ + { + "name": "MINREV", + "description": "MINREV.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "MAJREV", + "description": "MAJREV.", + "bit_offset": 4, + "bit_size": 4 + } + ] + }, + "fieldset/VHBPCCR": { + "description": "DSI Host video HBP current configuration register.", + "fields": [ + { + "name": "HBP", + "description": "HBP.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VHBPCR": { + "description": "DSI Host video HBP configuration register.", + "fields": [ + { + "name": "HBP", + "description": "HBP.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VHSACCR": { + "description": "DSI Host video HSA current configuration register.", + "fields": [ + { + "name": "HSA", + "description": "HSA.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VHSACR": { + "description": "DSI Host video HSA configuration register.", + "fields": [ + { + "name": "HSA", + "description": "HSA.", + "bit_offset": 0, + "bit_size": 12 + } + ] + }, + "fieldset/VLCCR": { + "description": "DSI Host video line current configuration register.", + "fields": [ + { + "name": "HLINE", + "description": "HLINE.", + "bit_offset": 0, + "bit_size": 15 + } + ] + }, + "fieldset/VLCR": { + "description": "DSI Host video line configuration register.", + "fields": [ + { + "name": "HLINE", + "description": "HLINE.", + "bit_offset": 0, + "bit_size": 15 + } + ] + }, + "fieldset/VMCCR": { + "description": "DSI Host video mode current configuration register.", + "fields": [ + { + "name": "VMT", + "description": "VMT.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "LPVSAE", + "description": "LPVSAE.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPVBPE", + "description": "LPVBPE.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "LPVFPE", + "description": "LPVFPE.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "LPVAE", + "description": "LPVAE.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LPHBPE", + "description": "LPHBPE.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "LPHFE", + "description": "LPHFE.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "FBTAAE", + "description": "FBTAAE.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPCE", + "description": "LPCE.", + "bit_offset": 9, + "bit_size": 1 + } + ] + }, + "fieldset/VMCR": { + "description": "DSI Host video mode configuration register.", + "fields": [ + { + "name": "VMT", + "description": "VMT.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "LPVSAE", + "description": "LPVSAE.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPVBPE", + "description": "LPVBPE.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPVFPE", + "description": "LPVFPE.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPVAE", + "description": "LPVAE.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPHBPE", + "description": "LPHBPE.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "LPHFPE", + "description": "LPHFPE.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "FBTAAE", + "description": "FBTAAE.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "LPCE", + "description": "LPCE.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "PGE", + "description": "PGE.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PGM", + "description": "PGM.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "PGO", + "description": "PGO.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/VNPCCR": { + "description": "DSI Host video null packet current configuration register.", + "fields": [ + { + "name": "NPSIZE", + "description": "NPSIZE.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VNPCR": { + "description": "DSI Host video null packet configuration register.", + "fields": [ + { + "name": "NPSIZE", + "description": "NPSIZE.", + "bit_offset": 0, + "bit_size": 13 + } + ] + }, + "fieldset/VPCCR": { + "description": "DSI Host video packet current configuration register.", + "fields": [ + { + "name": "VPSIZE", + "description": "VPSIZE.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VPCR": { + "description": "DSI Host video packet configuration register.", + "fields": [ + { + "name": "VPSIZE", + "description": "VPSIZE.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VR": { + "description": "DSI Host version register.", + "fields": [ + { + "name": "VERSION", + "description": "VERSION.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/VSCR": { + "description": "DSI Host video shadow control register.", + "fields": [ + { + "name": "EN", + "description": "EN.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "UR", + "description": "UR.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/VVACCR": { + "description": "DSI Host video VA current configuration register.", + "fields": [ + { + "name": "VA", + "description": "VA.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VVACR": { + "description": "DSI Host video VA configuration register.", + "fields": [ + { + "name": "VA", + "description": "VA.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/VVBPCCR": { + "description": "DSI Host video VBP current configuration register.", + "fields": [ + { + "name": "VBP", + "description": "VBP.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVBPCR": { + "description": "DSI Host video VBP configuration register.", + "fields": [ + { + "name": "VBP", + "description": "VBP.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVFPCCR": { + "description": "DSI Host video VFP current configuration register.", + "fields": [ + { + "name": "VFP", + "description": "VFP.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVFPCR": { + "description": "DSI Host video VFP configuration register.", + "fields": [ + { + "name": "VFP", + "description": "VFP.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVSACCR": { + "description": "DSI Host video VSA current configuration register.", + "fields": [ + { + "name": "VSA", + "description": "VSA.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/VVSACR": { + "description": "DSI Host video VSA configuration register.", + "fields": [ + { + "name": "VSA", + "description": "VSA.", + "bit_offset": 0, + "bit_size": 10 + } + ] + }, + "fieldset/WCFGR": { + "description": "DSI wrapper configuration register.", + "fields": [ + { + "name": "DSIM", + "description": "DSIM.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "COLMUX", + "description": "COLMUX.", + "bit_offset": 1, + "bit_size": 3 + }, + { + "name": "TESRC", + "description": "TESRC.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TEPOL", + "description": "TEPOL.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AR", + "description": "AR.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "VSPOL", + "description": "VSPOL.", + "bit_offset": 7, + "bit_size": 1 + } + ] + }, + "fieldset/WCR": { + "description": "DSI wrapper control register.", + "fields": [ + { + "name": "COLM", + "description": "COLM.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SHTDN", + "description": "SHTDN.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "LTDCEN", + "description": "LTDCEN.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "DSIEN", + "description": "DSIEN.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/WIER": { + "description": "DSI wrapper interrupt enable register.", + "fields": [ + { + "name": "TEIE", + "description": "TEIE.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ERIE", + "description": "ERIE.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "PLLLIE", + "description": "PLLLIE.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "PLLUIE", + "description": "PLLUIE.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "RRIE", + "description": "RRIE.", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/WIFCR": { + "description": "DSI wrapper interrupt flag clear register.", + "fields": [ + { + "name": "CTEIF", + "description": "CTEIF.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CERIF", + "description": "CERIF.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CPLLLIF", + "description": "CPLLLIF.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "CPLLUIF", + "description": "CPLLUIF.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "CRRIF", + "description": "CRRIF.", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/WISR": { + "description": "DSI wrapper interrupt and status register.", + "fields": [ + { + "name": "TEIF", + "description": "TEIF.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ERIF", + "description": "ERIF.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BUSY", + "description": "BUSY.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PLLLS", + "description": "PLLLS.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "PLLLIF", + "description": "PLLLIF.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "PLLUIF", + "description": "PLLUIF.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "RRS", + "description": "RRS.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "RRIF", + "description": "RRIF.", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/WPCR0": { + "description": "DSI wrapper PHY configuration register 0.", + "fields": [ + { + "name": "UIX4", + "description": "UIX4.", + "bit_offset": 0, + "bit_size": 6 + }, + { + "name": "SWCL", + "description": "SWCL.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SWDL0", + "description": "SWDL0.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SWDL1", + "description": "SWDL1.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "HSICL", + "description": "HSICL.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "HSIDL0", + "description": "HSIDL0.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "HSIDL1", + "description": "HSIDL1.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "FTXSMCL", + "description": "FTXSMCL.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "FTXSMDL", + "description": "FTXSMDL.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "CDOFFDL", + "description": "CDOFFDL.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "TDDL", + "description": "TDDL.", + "bit_offset": 16, + "bit_size": 1 + } + ] + }, + "fieldset/WPCR1": { + "description": "This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0).", + "fields": [ + { + "name": "SKEWCL", + "description": "SKEWCL.", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "SKEWDL", + "description": "SKEWDL.", + "bit_offset": 2, + "bit_size": 2 + }, + { + "name": "LPTXSRCL", + "description": "LPTXSRCL.", + "bit_offset": 6, + "bit_size": 2 + }, + { + "name": "LPTXSRDL", + "description": "LPTXSRDL.", + "bit_offset": 8, + "bit_size": 2 + }, + { + "name": "SDDCCL", + "description": "SDDCCL.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "SDDCDL", + "description": "SDDCDL.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "HSTXSRUCL", + "description": "HSTXSRUCL.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "HSTXSRDCL", + "description": "HSTXSRDCL.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "HSTXSRUDL", + "description": "HSTXSRUDL.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "HSTXSRDDL", + "description": "HSTXSRDDL.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/WRPCR": { + "description": "DSI wrapper regulator and PLL control register.", + "fields": [ + { + "name": "PLLEN", + "description": "PLLEN.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "NDIV", + "description": "NDIV.", + "bit_offset": 2, + "bit_size": 7 + }, + { + "name": "IDF", + "description": "IDF.", + "bit_offset": 11, + "bit_size": 4 + }, + { + "name": "ODF", + "description": "ODF.", + "bit_offset": 16, + "bit_size": 2 + }, + { + "name": "REGEN", + "description": "REGEN.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "BGREN", + "description": "BGREN.", + "bit_offset": 28, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/ltdc_v1.json b/data/registers/ltdc_v1.json index e310c9f..4dd6e6e 100644 --- a/data/registers/ltdc_v1.json +++ b/data/registers/ltdc_v1.json @@ -218,15 +218,18 @@ "description": "Layerx Blending Factors Configuration Register", "fields": [ { - "name": "BF", + "name": "BF2", "description": "Blending Factor 2", "bit_offset": 0, "bit_size": 3, - "array": { - "len": 2, - "stride": 8 - }, "enum": "BF2" + }, + { + "name": "BF1", + "description": "Blending Factor 1", + "bit_offset": 8, + "bit_size": 3, + "enum": "BF1" } ] }, @@ -711,6 +714,21 @@ } ] }, + "enum/BF1": { + "bit_size": 3, + "variants": [ + { + "name": "Constant", + "description": "BF1 = constant alpha", + "value": 4 + }, + { + "name": "Pixel", + "description": "BF1 = pixel alpha * constant alpha", + "value": 7 + } + ] + }, "enum/BF2": { "bit_size": 3, "variants": [ diff --git a/data/registers/rcc_h7.json b/data/registers/rcc_h7.json index f61e894..e508c0c 100644 --- a/data/registers/rcc_h7.json +++ b/data/registers/rcc_h7.json @@ -4626,9 +4626,10 @@ }, { "name": "DSISEL", - "description": "kernel clock source selection", + "description": "DSI clock source selection (not available on all chips)", "bit_offset": 8, - "bit_size": 1 + "bit_size": 1, + "enum": "DSISEL" }, { "name": "SDMMCSEL", @@ -5333,6 +5334,21 @@ } ] }, + "enum/DSISEL": { + "bit_size": 1, + "variants": [ + { + "name": "DSI_PHY", + "description": "DSI-PHY used as DSI byte lane clock source (usual case)", + "value": 0 + }, + { + "name": "PLL2_Q", + "description": "PLL2_Q used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)", + "value": 1 + } + ] + }, "enum/FDCANSEL": { "bit_size": 2, "variants": [ diff --git a/data/registers/rcc_h7ab.json b/data/registers/rcc_h7ab.json index 087334f..46f8d05 100644 --- a/data/registers/rcc_h7ab.json +++ b/data/registers/rcc_h7ab.json @@ -3034,12 +3034,6 @@ "bit_size": 2, "enum": "FMCSEL" }, - { - "name": "DSISEL", - "description": "kernel clock source selection", - "bit_offset": 8, - "bit_size": 1 - }, { "name": "SDMMCSEL", "description": "SDMMC kernel clock source selection", diff --git a/data/registers/rcc_h7rm0433.json b/data/registers/rcc_h7rm0433.json index f093f01..e3149b6 100644 --- a/data/registers/rcc_h7rm0433.json +++ b/data/registers/rcc_h7rm0433.json @@ -4599,12 +4599,6 @@ "bit_size": 2, "enum": "FMCSEL" }, - { - "name": "DSISEL", - "description": "kernel clock source selection", - "bit_offset": 8, - "bit_size": 1 - }, { "name": "SDMMCSEL", "description": "SDMMC kernel clock source selection", diff --git a/data/registers/rcc_l4plus.json b/data/registers/rcc_l4plus.json index 8993fb7..ef260c2 100644 --- a/data/registers/rcc_l4plus.json +++ b/data/registers/rcc_l4plus.json @@ -2571,7 +2571,7 @@ "bit_size": 1, "variants": [ { - "name": "DSIPHY", + "name": "DSI_PHY", "description": "DSI-PHY is selected as DSI byte lane clock source (usual case)", "value": 0 }, diff --git a/data/registers/rcc_u5.json b/data/registers/rcc_u5.json index 9fcaa19..dafaa98 100644 --- a/data/registers/rcc_u5.json +++ b/data/registers/rcc_u5.json @@ -3741,8 +3741,8 @@ "value": 0 }, { - "name": "DCLK", - "description": "DSI PHY PLL output selected", + "name": "DSI_PHY", + "description": "DSI PHY PLL output selected (formerly called DCLK, renamed to DSI_PHY to match other chip families)", "value": 1 } ]