diff --git a/data/chips/STM32H723VE.json b/data/chips/STM32H723VE.json index 9990e0b..2cc3731 100644 --- a/data/chips/STM32H723VE.json +++ b/data/chips/STM32H723VE.json @@ -2683,6 +2683,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H723VG.json b/data/chips/STM32H723VG.json index 3c8d011..88d3559 100644 --- a/data/chips/STM32H723VG.json +++ b/data/chips/STM32H723VG.json @@ -2683,6 +2683,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H723ZE.json b/data/chips/STM32H723ZE.json index c1b4496..10805b7 100644 --- a/data/chips/STM32H723ZE.json +++ b/data/chips/STM32H723ZE.json @@ -3035,6 +3035,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H723ZG.json b/data/chips/STM32H723ZG.json index 5b28d6a..9423d26 100644 --- a/data/chips/STM32H723ZG.json +++ b/data/chips/STM32H723ZG.json @@ -3035,6 +3035,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H725AE.json b/data/chips/STM32H725AE.json index 49ce264..5b9e47c 100644 --- a/data/chips/STM32H725AE.json +++ b/data/chips/STM32H725AE.json @@ -3136,6 +3136,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H725AG.json b/data/chips/STM32H725AG.json index f96d84c..5cae6a5 100644 --- a/data/chips/STM32H725AG.json +++ b/data/chips/STM32H725AG.json @@ -3142,6 +3142,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H725IE.json b/data/chips/STM32H725IE.json index 8150671..4e6709b 100644 --- a/data/chips/STM32H725IE.json +++ b/data/chips/STM32H725IE.json @@ -3221,6 +3221,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H725IG.json b/data/chips/STM32H725IG.json index e3d2c75..d9fc4f2 100644 --- a/data/chips/STM32H725IG.json +++ b/data/chips/STM32H725IG.json @@ -3227,6 +3227,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H725RE.json b/data/chips/STM32H725RE.json index 6681eda..05ed7a5 100644 --- a/data/chips/STM32H725RE.json +++ b/data/chips/STM32H725RE.json @@ -1827,6 +1827,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H725RG.json b/data/chips/STM32H725RG.json index e1825fb..4e27aca 100644 --- a/data/chips/STM32H725RG.json +++ b/data/chips/STM32H725RG.json @@ -1833,6 +1833,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H725VE.json b/data/chips/STM32H725VE.json index c036516..63daba9 100644 --- a/data/chips/STM32H725VE.json +++ b/data/chips/STM32H725VE.json @@ -2598,6 +2598,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H725VG.json b/data/chips/STM32H725VG.json index 65f5577..19b6534 100644 --- a/data/chips/STM32H725VG.json +++ b/data/chips/STM32H725VG.json @@ -2608,6 +2608,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H725ZE.json b/data/chips/STM32H725ZE.json index 83d5da0..dd0857e 100644 --- a/data/chips/STM32H725ZE.json +++ b/data/chips/STM32H725ZE.json @@ -2862,6 +2862,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H725ZG.json b/data/chips/STM32H725ZG.json index 2aea6dd..d7527da 100644 --- a/data/chips/STM32H725ZG.json +++ b/data/chips/STM32H725ZG.json @@ -2868,6 +2868,22 @@ } } }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index 6286fe4..7ea1569 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -3227,6 +3227,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index 0e1a30b..25b4252 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -3312,6 +3312,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index c81b1bf..3783f89 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -2768,6 +2768,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index 6d6a096..4a3e75c 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -3120,6 +3120,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index 5a8ae58..5617e17 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -2768,6 +2768,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index 61d5bcd..1632693 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -3120,6 +3120,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index 1395858..4cc7b68 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -3227,6 +3227,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index d70bdfe..5a5054d 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -3312,6 +3312,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H735RG.json b/data/chips/STM32H735RG.json index c453516..a773d79 100644 --- a/data/chips/STM32H735RG.json +++ b/data/chips/STM32H735RG.json @@ -1918,6 +1918,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index 509e292..2c16dea 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -2693,6 +2693,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index 5ba6dfc..23a211e 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -2953,6 +2953,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742AG.json b/data/chips/STM32H742AG.json index 0bb6a7f..1b26619 100644 --- a/data/chips/STM32H742AG.json +++ b/data/chips/STM32H742AG.json @@ -3125,6 +3125,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742AI.json b/data/chips/STM32H742AI.json index eb6fc86..26c7c16 100644 --- a/data/chips/STM32H742AI.json +++ b/data/chips/STM32H742AI.json @@ -3136,6 +3136,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742BG.json b/data/chips/STM32H742BG.json index 08e830c..20cca59 100644 --- a/data/chips/STM32H742BG.json +++ b/data/chips/STM32H742BG.json @@ -3250,6 +3250,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742BI.json b/data/chips/STM32H742BI.json index cf4d620..9f777ff 100644 --- a/data/chips/STM32H742BI.json +++ b/data/chips/STM32H742BI.json @@ -3261,6 +3261,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742IG.json b/data/chips/STM32H742IG.json index e5cfda1..da5e0c7 100644 --- a/data/chips/STM32H742IG.json +++ b/data/chips/STM32H742IG.json @@ -3254,6 +3254,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742II.json b/data/chips/STM32H742II.json index 28fbbee..8e04f4f 100644 --- a/data/chips/STM32H742II.json +++ b/data/chips/STM32H742II.json @@ -3265,6 +3265,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742VG.json b/data/chips/STM32H742VG.json index d5c4295..8388926 100644 --- a/data/chips/STM32H742VG.json +++ b/data/chips/STM32H742VG.json @@ -2664,6 +2664,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742VI.json b/data/chips/STM32H742VI.json index d7a02a3..583d0c2 100644 --- a/data/chips/STM32H742VI.json +++ b/data/chips/STM32H742VI.json @@ -2675,6 +2675,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742XG.json b/data/chips/STM32H742XG.json index 473da6a..fffbf8f 100644 --- a/data/chips/STM32H742XG.json +++ b/data/chips/STM32H742XG.json @@ -3314,6 +3314,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742XI.json b/data/chips/STM32H742XI.json index cafee8f..cd6d710 100644 --- a/data/chips/STM32H742XI.json +++ b/data/chips/STM32H742XI.json @@ -3325,6 +3325,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742ZG.json b/data/chips/STM32H742ZG.json index 84372b9..f306b43 100644 --- a/data/chips/STM32H742ZG.json +++ b/data/chips/STM32H742ZG.json @@ -2982,6 +2982,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H742ZI.json b/data/chips/STM32H742ZI.json index 487d52c..4e49552 100644 --- a/data/chips/STM32H742ZI.json +++ b/data/chips/STM32H742ZI.json @@ -2993,6 +2993,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743AG.json b/data/chips/STM32H743AG.json index f64f674..967c03b 100644 --- a/data/chips/STM32H743AG.json +++ b/data/chips/STM32H743AG.json @@ -3167,6 +3167,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743AI.json b/data/chips/STM32H743AI.json index 237c1e7..707a570 100644 --- a/data/chips/STM32H743AI.json +++ b/data/chips/STM32H743AI.json @@ -3178,6 +3178,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743BG.json b/data/chips/STM32H743BG.json index 2c1456f..c1ca37b 100644 --- a/data/chips/STM32H743BG.json +++ b/data/chips/STM32H743BG.json @@ -3292,6 +3292,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743BI.json b/data/chips/STM32H743BI.json index 9ce5070..d81d2c8 100644 --- a/data/chips/STM32H743BI.json +++ b/data/chips/STM32H743BI.json @@ -3303,6 +3303,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743IG.json b/data/chips/STM32H743IG.json index 595cd86..d94a0aa 100644 --- a/data/chips/STM32H743IG.json +++ b/data/chips/STM32H743IG.json @@ -3296,6 +3296,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743II.json b/data/chips/STM32H743II.json index d57fab7..d9cc77c 100644 --- a/data/chips/STM32H743II.json +++ b/data/chips/STM32H743II.json @@ -3307,6 +3307,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743VG.json b/data/chips/STM32H743VG.json index c386bd6..d89a6d8 100644 --- a/data/chips/STM32H743VG.json +++ b/data/chips/STM32H743VG.json @@ -2706,6 +2706,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743VI.json b/data/chips/STM32H743VI.json index 3bc650f..519029c 100644 --- a/data/chips/STM32H743VI.json +++ b/data/chips/STM32H743VI.json @@ -2717,6 +2717,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743XG.json b/data/chips/STM32H743XG.json index 264d90d..b21aed5 100644 --- a/data/chips/STM32H743XG.json +++ b/data/chips/STM32H743XG.json @@ -3356,6 +3356,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743XI.json b/data/chips/STM32H743XI.json index 82d1a0e..5d89506 100644 --- a/data/chips/STM32H743XI.json +++ b/data/chips/STM32H743XI.json @@ -3367,6 +3367,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743ZG.json b/data/chips/STM32H743ZG.json index f4b4aed..8f54798 100644 --- a/data/chips/STM32H743ZG.json +++ b/data/chips/STM32H743ZG.json @@ -3024,6 +3024,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H743ZI.json b/data/chips/STM32H743ZI.json index 3957687..c7d1969 100644 --- a/data/chips/STM32H743ZI.json +++ b/data/chips/STM32H743ZI.json @@ -3035,6 +3035,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745BG.json b/data/chips/STM32H745BG.json index 3c49175..5c84eff 100644 --- a/data/chips/STM32H745BG.json +++ b/data/chips/STM32H745BG.json @@ -3274,6 +3274,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13114,6 +13135,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745BI.json b/data/chips/STM32H745BI.json index aeb45e6..fdd41dc 100644 --- a/data/chips/STM32H745BI.json +++ b/data/chips/STM32H745BI.json @@ -3285,6 +3285,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13125,6 +13146,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745IG.json b/data/chips/STM32H745IG.json index d77ffc8..3e2acc9 100644 --- a/data/chips/STM32H745IG.json +++ b/data/chips/STM32H745IG.json @@ -3242,6 +3242,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12824,6 +12845,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745II.json b/data/chips/STM32H745II.json index 9ef7036..084297b 100644 --- a/data/chips/STM32H745II.json +++ b/data/chips/STM32H745II.json @@ -3253,6 +3253,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12835,6 +12856,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745XG.json b/data/chips/STM32H745XG.json index 2d6b720..84826f8 100644 --- a/data/chips/STM32H745XG.json +++ b/data/chips/STM32H745XG.json @@ -3338,6 +3338,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13347,6 +13368,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745XI.json b/data/chips/STM32H745XI.json index be0f65e..8084939 100644 --- a/data/chips/STM32H745XI.json +++ b/data/chips/STM32H745XI.json @@ -3349,6 +3349,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13358,6 +13379,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745ZG.json b/data/chips/STM32H745ZG.json index b0b0b5b..81e4346 100644 --- a/data/chips/STM32H745ZG.json +++ b/data/chips/STM32H745ZG.json @@ -2879,6 +2879,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -11654,6 +11675,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745ZI.json b/data/chips/STM32H745ZI.json index ed3c0fe..be4bc95 100644 --- a/data/chips/STM32H745ZI.json +++ b/data/chips/STM32H745ZI.json @@ -2890,6 +2890,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -11665,6 +11686,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index be2029e..175c9bb 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -3012,6 +3012,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12006,6 +12027,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index 38e4252..3998e29 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -3023,6 +3023,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12017,6 +12038,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index 164c5ed..467ff84 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -3280,6 +3280,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12949,6 +12970,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index 0d9129d..7caf30c 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -3291,6 +3291,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12960,6 +12981,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index ab5fef6..a8041dc 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -3012,6 +3012,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12006,6 +12027,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index f608c4c..49eb2de 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -3023,6 +3023,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12017,6 +12038,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index d61ce67..119c8ea 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -3344,6 +3344,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13357,6 +13378,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index 6e274fc..fd5d5f4 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -3355,6 +3355,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13368,6 +13389,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index b76b6f9..1bc5811 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -2871,6 +2871,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -11322,6 +11343,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H750IB.json b/data/chips/STM32H750IB.json index 0a5c507..be028f1 100644 --- a/data/chips/STM32H750IB.json +++ b/data/chips/STM32H750IB.json @@ -3357,6 +3357,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H750VB.json b/data/chips/STM32H750VB.json index b1b5c63..9c0788c 100644 --- a/data/chips/STM32H750VB.json +++ b/data/chips/STM32H750VB.json @@ -2763,6 +2763,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H750XB.json b/data/chips/STM32H750XB.json index 55c872e..444e0c4 100644 --- a/data/chips/STM32H750XB.json +++ b/data/chips/STM32H750XB.json @@ -3417,6 +3417,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H750ZB.json b/data/chips/STM32H750ZB.json index f255688..c3763ab 100644 --- a/data/chips/STM32H750ZB.json +++ b/data/chips/STM32H750ZB.json @@ -3073,6 +3073,22 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H753AI.json b/data/chips/STM32H753AI.json index 5ea5798..0b230cf 100644 --- a/data/chips/STM32H753AI.json +++ b/data/chips/STM32H753AI.json @@ -3257,6 +3257,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H753BI.json b/data/chips/STM32H753BI.json index 902627e..5b4aef8 100644 --- a/data/chips/STM32H753BI.json +++ b/data/chips/STM32H753BI.json @@ -3382,6 +3382,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H753II.json b/data/chips/STM32H753II.json index 47966ef..eb63554 100644 --- a/data/chips/STM32H753II.json +++ b/data/chips/STM32H753II.json @@ -3386,6 +3386,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H753VI.json b/data/chips/STM32H753VI.json index ede41fd..75c73fd 100644 --- a/data/chips/STM32H753VI.json +++ b/data/chips/STM32H753VI.json @@ -2796,6 +2796,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H753XI.json b/data/chips/STM32H753XI.json index 7cc03c5..15f5bf0 100644 --- a/data/chips/STM32H753XI.json +++ b/data/chips/STM32H753XI.json @@ -3446,6 +3446,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H753ZI.json b/data/chips/STM32H753ZI.json index 6f02c37..e892011 100644 --- a/data/chips/STM32H753ZI.json +++ b/data/chips/STM32H753ZI.json @@ -3114,6 +3114,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index ad04ec6..10437dc 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -3364,6 +3364,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13281,6 +13302,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index b7f2cfc..5043561 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -3332,6 +3332,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12991,6 +13012,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index 464da0a..fe5de1d 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -3428,6 +3428,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13514,6 +13535,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index 99aa289..87db591 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -2969,6 +2969,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -11821,6 +11842,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index d3b13b1..4e0cb35 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -3102,6 +3102,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12173,6 +12194,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index a2b291e..7d01f5f 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -3370,6 +3370,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13116,6 +13137,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 9d1e7d3..393c33a 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -3102,6 +3102,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12173,6 +12194,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 01a7f3d..69858ed 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -3434,6 +3434,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13524,6 +13545,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index a61017c..ad5deeb 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -2950,6 +2950,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -11478,6 +11499,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index 1e8b23e..c6e298c 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -2833,6 +2833,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index 5e52e9c..ae66b37 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -2844,6 +2844,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index 0efcae4..72c481b 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -2995,6 +2995,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index 36659cd..ce46505 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -3006,6 +3006,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index f291c4c..0a5377b 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -2977,6 +2977,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index e51034c..53450b5 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -2994,6 +2994,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index 6258ebb..9929f02 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -2939,6 +2939,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index e2ba26d..0779280 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -2950,6 +2950,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index 142c907..629db25 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -2574,6 +2574,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3RG.json b/data/chips/STM32H7A3RG.json index 6cac3bf..d29c831 100644 --- a/data/chips/STM32H7A3RG.json +++ b/data/chips/STM32H7A3RG.json @@ -1966,6 +1966,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3RI.json b/data/chips/STM32H7A3RI.json index 729446c..d93d71c 100644 --- a/data/chips/STM32H7A3RI.json +++ b/data/chips/STM32H7A3RI.json @@ -1977,6 +1977,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index ceaaffa..23041e6 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -2517,6 +2517,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index 45d907c..7270261 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -2528,6 +2528,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index b37249d..f8ca1da 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -2728,6 +2728,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index 7516ef0..3e2f4bb 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -2739,6 +2739,22 @@ } } }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index 39394b8..26697ab 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -2912,6 +2912,22 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index 0a653a9..a8bf74a 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -3066,6 +3066,22 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index 5664dad..601abe8 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -2045,6 +2045,22 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index 19cbcc7..d3c0bc9 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -2584,6 +2584,22 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index 4a52927..9a009b0 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -2803,6 +2803,22 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index b033957..bccc546 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -2929,6 +2929,27 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index b292ed6..7e42482 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -3091,6 +3091,27 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index a32d60e..f382b59 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -3079,6 +3079,27 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index f59970a..c2cbf1a 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -3035,6 +3035,27 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index f5cb10a..f4549e1 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -2659,6 +2659,27 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 226b6d9..32cde03 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -2062,6 +2062,27 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index 67218db..d5c3e2c 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -2613,6 +2613,27 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index af227a5..bb36da3 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -2824,6 +2824,27 @@ } ] }, + { + "name": "HSEM", + "address": 1208092672, + "registers": { + "kind": "hsem", + "version": "v2", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32WB55CC.json b/data/chips/STM32WB55CC.json index f9fb718..0627fcf 100644 --- a/data/chips/STM32WB55CC.json +++ b/data/chips/STM32WB55CC.json @@ -1050,6 +1050,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55CE.json b/data/chips/STM32WB55CE.json index ef58a8f..5ee4735 100644 --- a/data/chips/STM32WB55CE.json +++ b/data/chips/STM32WB55CE.json @@ -1050,6 +1050,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55CG.json b/data/chips/STM32WB55CG.json index 105179e..bfc7032 100644 --- a/data/chips/STM32WB55CG.json +++ b/data/chips/STM32WB55CG.json @@ -1050,6 +1050,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55RC.json b/data/chips/STM32WB55RC.json index 6f2e2d8..e9dec3f 100644 --- a/data/chips/STM32WB55RC.json +++ b/data/chips/STM32WB55RC.json @@ -1092,6 +1092,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55RE.json b/data/chips/STM32WB55RE.json index 6c2c0a1..59e2a8c 100644 --- a/data/chips/STM32WB55RE.json +++ b/data/chips/STM32WB55RE.json @@ -1092,6 +1092,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55RG.json b/data/chips/STM32WB55RG.json index b7cadc5..a891b01 100644 --- a/data/chips/STM32WB55RG.json +++ b/data/chips/STM32WB55RG.json @@ -1092,6 +1092,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VC.json b/data/chips/STM32WB55VC.json index 7f3493a..abb5fce 100644 --- a/data/chips/STM32WB55VC.json +++ b/data/chips/STM32WB55VC.json @@ -1096,6 +1096,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VE.json b/data/chips/STM32WB55VE.json index 2a5d0a5..5b13cd0 100644 --- a/data/chips/STM32WB55VE.json +++ b/data/chips/STM32WB55VE.json @@ -1096,6 +1096,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VG.json b/data/chips/STM32WB55VG.json index 18adc90..f8cf8a6 100644 --- a/data/chips/STM32WB55VG.json +++ b/data/chips/STM32WB55VG.json @@ -1096,6 +1096,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VY.json b/data/chips/STM32WB55VY.json index c24fa37..a41eef4 100644 --- a/data/chips/STM32WB55VY.json +++ b/data/chips/STM32WB55VY.json @@ -1074,6 +1074,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WL54CC.json b/data/chips/STM32WL54CC.json index a9c1f94..ca1c3e1 100644 --- a/data/chips/STM32WL54CC.json +++ b/data/chips/STM32WL54CC.json @@ -839,6 +839,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -3407,6 +3412,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WL54JC.json b/data/chips/STM32WL54JC.json index f7d07a2..b96aca6 100644 --- a/data/chips/STM32WL54JC.json +++ b/data/chips/STM32WL54JC.json @@ -865,6 +865,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -3684,6 +3689,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WL55CC.json b/data/chips/STM32WL55CC.json index 28607e0..80bc21c 100644 --- a/data/chips/STM32WL55CC.json +++ b/data/chips/STM32WL55CC.json @@ -845,6 +845,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -3413,6 +3418,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WL55JC.json b/data/chips/STM32WL55JC.json index 9768ad4..4c69486 100644 --- a/data/chips/STM32WL55JC.json +++ b/data/chips/STM32WL55JC.json @@ -871,6 +871,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -3690,6 +3695,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4C8.json b/data/chips/STM32WLE4C8.json index afc011a..df8c152 100644 --- a/data/chips/STM32WLE4C8.json +++ b/data/chips/STM32WLE4C8.json @@ -658,6 +658,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4CB.json b/data/chips/STM32WLE4CB.json index fe22475..7db9768 100644 --- a/data/chips/STM32WLE4CB.json +++ b/data/chips/STM32WLE4CB.json @@ -658,6 +658,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4CC.json b/data/chips/STM32WLE4CC.json index cd45c21..7ab9146 100644 --- a/data/chips/STM32WLE4CC.json +++ b/data/chips/STM32WLE4CC.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4J8.json b/data/chips/STM32WLE4J8.json index 112430f..a170f62 100644 --- a/data/chips/STM32WLE4J8.json +++ b/data/chips/STM32WLE4J8.json @@ -684,6 +684,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4JB.json b/data/chips/STM32WLE4JB.json index 6cda994..9a1fac0 100644 --- a/data/chips/STM32WLE4JB.json +++ b/data/chips/STM32WLE4JB.json @@ -684,6 +684,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4JC.json b/data/chips/STM32WLE4JC.json index cee029f..768f83f 100644 --- a/data/chips/STM32WLE4JC.json +++ b/data/chips/STM32WLE4JC.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5C8.json b/data/chips/STM32WLE5C8.json index 3452885..e342b6a 100644 --- a/data/chips/STM32WLE5C8.json +++ b/data/chips/STM32WLE5C8.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5CB.json b/data/chips/STM32WLE5CB.json index 7871ac2..c3144f9 100644 --- a/data/chips/STM32WLE5CB.json +++ b/data/chips/STM32WLE5CB.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5CC.json b/data/chips/STM32WLE5CC.json index 1d87b02..09c3ce1 100644 --- a/data/chips/STM32WLE5CC.json +++ b/data/chips/STM32WLE5CC.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5J8.json b/data/chips/STM32WLE5J8.json index 42a7b91..4a9bc89 100644 --- a/data/chips/STM32WLE5J8.json +++ b/data/chips/STM32WLE5J8.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5JB.json b/data/chips/STM32WLE5JB.json index e19af1f..ab18672 100644 --- a/data/chips/STM32WLE5JB.json +++ b/data/chips/STM32WLE5JB.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5JC.json b/data/chips/STM32WLE5JC.json index c963a86..44d1587 100644 --- a/data/chips/STM32WLE5JC.json +++ b/data/chips/STM32WLE5JC.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/registers/hsem_v1.json b/data/registers/hsem_v1.json new file mode 100644 index 0000000..6f933b7 --- /dev/null +++ b/data/registers/hsem_v1.json @@ -0,0 +1,216 @@ +{ + "block/HSEM": { + "description": "Hardware semaphore (HSEM).", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "IER", + "description": "HSEM Interrupt enable register.", + "array": { + "len": 2, + "stride": 16 + }, + "byte_offset": 256, + "fieldset": "IER" + }, + { + "name": "ICR", + "description": "HSEM Interrupt clear register.", + "array": { + "len": 2, + "stride": 16 + }, + "byte_offset": 260, + "fieldset": "ICR" + }, + { + "name": "ISR", + "description": "HSEM Interrupt status register.", + "array": { + "len": 2, + "stride": 16 + }, + "byte_offset": 264, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "MISR", + "description": "HSEM Masked interrupt status register.", + "array": { + "len": 2, + "stride": 16 + }, + "byte_offset": 268, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "COREID of semaphores to be cleared.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "Interrupt semaphore x clear bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "Interrupt semaphore x enable bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "Interrupt semaphore x status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "masked interrupt semaphore x status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v2.json b/data/registers/hsem_v2.json new file mode 100644 index 0000000..923d39d --- /dev/null +++ b/data/registers/hsem_v2.json @@ -0,0 +1,217 @@ +{ + "block/HSEM": { + "description": "HSEM.", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "IER", + "description": "HSEM Interrupt enable register.", + "array": { + "len": 1, + "stride": 16 + }, + "byte_offset": 256, + "fieldset": "IER" + }, + { + "name": "ICR", + "description": "HSEM Interrupt clear register.", + "array": { + "len": 1, + "stride": 16 + }, + "byte_offset": 260, + "access": "Read", + "fieldset": "ICR" + }, + { + "name": "ISR", + "description": "HSEM Interrupt status register.", + "array": { + "len": 1, + "stride": 16 + }, + "byte_offset": 264, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "MISR", + "description": "HSEM Masked interrupt status register.", + "array": { + "len": 1, + "stride": 16 + }, + "byte_offset": 268, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "COREID of semaphores to be cleared.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "Interrupt semaphore x clear bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "Interrupt semaphore x enable bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "Interrupt semaphore x status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "masked interrupt semaphore x status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v3.json b/data/registers/hsem_v3.json new file mode 100644 index 0000000..3744902 --- /dev/null +++ b/data/registers/hsem_v3.json @@ -0,0 +1,217 @@ +{ + "block/HSEM": { + "description": "Hardware semaphore.", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "IER", + "description": "HSEM Interrupt enable register.", + "array": { + "len": 2, + "stride": 16 + }, + "byte_offset": 256, + "fieldset": "IER" + }, + { + "name": "ICR", + "description": "HSEM Interrupt clear register.", + "array": { + "len": 2, + "stride": 16 + }, + "byte_offset": 260, + "fieldset": "ICR" + }, + { + "name": "ISR", + "description": "HSEM Interrupt status register.", + "array": { + "len": 2, + "stride": 16 + }, + "byte_offset": 264, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "MISR", + "description": "HSEM Masked interrupt status register.", + "array": { + "len": 2, + "stride": 16 + }, + "byte_offset": 268, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "access": "Write", + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "Interrupt semaphore x clear bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "Interrupt semaphore x enable bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "Interrupt semaphore x status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "masked interrupt semaphore x status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v4.json b/data/registers/hsem_v4.json new file mode 100644 index 0000000..65c86c1 --- /dev/null +++ b/data/registers/hsem_v4.json @@ -0,0 +1,217 @@ +{ + "block/HSEM": { + "description": "Hardware semaphore.", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "IER", + "description": "HSEM Interrupt enable register.", + "array": { + "len": 1, + "stride": 16 + }, + "byte_offset": 256, + "fieldset": "IER" + }, + { + "name": "ICR", + "description": "HSEM Interrupt clear register.", + "array": { + "len": 1, + "stride": 16 + }, + "byte_offset": 260, + "fieldset": "ICR" + }, + { + "name": "ISR", + "description": "HSEM Interrupt status register.", + "array": { + "len": 1, + "stride": 16 + }, + "byte_offset": 264, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "MISR", + "description": "HSEM Masked interrupt status register.", + "array": { + "len": 1, + "stride": 16 + }, + "byte_offset": 268, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "access": "Write", + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file