diff --git a/data/chips/STM32H503CB.json b/data/chips/STM32H503CB.json index 5019bb6..17de864 100644 --- a/data/chips/STM32H503CB.json +++ b/data/chips/STM32H503CB.json @@ -2635,6 +2635,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H503EB.json b/data/chips/STM32H503EB.json index 3320d99..731f440 100644 --- a/data/chips/STM32H503EB.json +++ b/data/chips/STM32H503EB.json @@ -2178,6 +2178,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H503KB.json b/data/chips/STM32H503KB.json index 81a5b14..e6b2ff5 100644 --- a/data/chips/STM32H503KB.json +++ b/data/chips/STM32H503KB.json @@ -2418,6 +2418,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H503RB.json b/data/chips/STM32H503RB.json index 84520cf..ba3a7c9 100644 --- a/data/chips/STM32H503RB.json +++ b/data/chips/STM32H503RB.json @@ -3047,6 +3047,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index 3ef2b31..600d431 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -5699,6 +5699,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index c338eb7..3e26c1b 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -5710,6 +5710,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index 3685ff0..d33cb18 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -5753,6 +5753,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index de15725..5101bab 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -5764,6 +5764,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index b75974e..1255ecd 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -3770,6 +3770,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index 7b5bd33..365261d 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -3781,6 +3781,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index 6965733..0c12cf7 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -4533,6 +4533,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index 6bc60f7..112f29f 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -4544,6 +4544,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index 8d9a304..f7f3f4c 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -5256,6 +5256,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index 9e6b0a7..74da45e 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -5267,6 +5267,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index 49da115..49229e4 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -6109,6 +6109,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index 240f5ac..24c568a 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -6159,6 +6159,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 2d46837..57afae9 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -6168,6 +6168,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index f9b0018..674601e 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -6187,6 +6187,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index ce0d4d6..b1a7947 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -4054,6 +4054,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index b688ed3..8ca7347 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -3988,6 +3988,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index f3deba4..3f6423f 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -3999,6 +3999,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index 2b0e826..614f77d 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -4756,6 +4756,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index 27b2164..16b62bd 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -4796,6 +4796,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index 4bac43e..52bcd22 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -5641,6 +5641,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index 703912a..804bd73 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -5706,6 +5706,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index a8ed64c..528eed3 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -6301,6 +6301,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index 1be47ef..3662f50 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -6329,6 +6329,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index d074222..a2323f6 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -4196,6 +4196,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index c6a7fd4..5f90f33 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -4141,6 +4141,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index b9d185f..e1d0c6c 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -4938,6 +4938,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index a0d3c29..e92f2f8 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -5848,6 +5848,11 @@ { "name": "TAMP", "address": 1140882432, + "registers": { + "kind": "tamp", + "version": "h5", + "block": "TAMP" + }, "pins": [ { "pin": "PA0", diff --git a/data/registers/tamp_h5.json b/data/registers/tamp_h5.json new file mode 100644 index 0000000..5706349 --- /dev/null +++ b/data/registers/tamp_h5.json @@ -0,0 +1,1036 @@ +{ + "block/TAMP": { + "description": "Tamper and backup.", + "items": [ + { + "name": "CR1", + "description": "TAMP control register 1.", + "byte_offset": 0, + "fieldset": "CR1" + }, + { + "name": "CR2", + "description": "TAMP control register 2.", + "byte_offset": 4, + "fieldset": "CR2" + }, + { + "name": "CR3", + "description": "TAMP control register 3.", + "byte_offset": 8, + "fieldset": "CR3" + }, + { + "name": "FLTCR", + "description": "TAMP filter control register.", + "byte_offset": 12, + "fieldset": "FLTCR" + }, + { + "name": "ATCR1", + "description": "TAMP active tamper control register 1.", + "byte_offset": 16, + "fieldset": "ATCR1" + }, + { + "name": "ATSEEDR", + "description": "TAMP active tamper seed register.", + "byte_offset": 20 + }, + { + "name": "ATOR", + "description": "TAMP active tamper output register.", + "byte_offset": 24, + "fieldset": "ATOR" + }, + { + "name": "ATCR2", + "description": "TAMP active tamper control register 2.", + "byte_offset": 28, + "fieldset": "ATCR2" + }, + { + "name": "SECCFGR", + "description": "TAMP secure mode register.", + "byte_offset": 32, + "fieldset": "SECCFGR" + }, + { + "name": "PRIVCFGR", + "description": "TAMP privilege mode control register.", + "byte_offset": 36, + "fieldset": "PRIVCFGR" + }, + { + "name": "IER", + "description": "TAMP interrupt enable register.", + "byte_offset": 44, + "fieldset": "IER" + }, + { + "name": "SR", + "description": "TAMP status register.", + "byte_offset": 48, + "fieldset": "SR" + }, + { + "name": "MISR", + "description": "TAMP non-secure masked interrupt status register.", + "byte_offset": 52, + "fieldset": "MISR" + }, + { + "name": "SMISR", + "description": "TAMP secure masked interrupt status register.", + "byte_offset": 56, + "fieldset": "SMISR" + }, + { + "name": "SCR", + "description": "TAMP status clear register.", + "byte_offset": 60, + "fieldset": "SCR" + }, + { + "name": "COUNT1R", + "description": "TAMP monotonic counter 1 register.", + "byte_offset": 64 + }, + { + "name": "OR", + "description": "TAMP option register.", + "byte_offset": 80, + "fieldset": "OR" + }, + { + "name": "RPCFGR", + "description": "TAMP resources protection configuration register.", + "byte_offset": 84, + "fieldset": "RPCFGR" + }, + { + "name": "BKPR", + "description": "TAMP backup x register. (x=0-31)", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 256 + } + ] + }, + "fieldset/ATCR1": { + "description": "TAMP active tamper control register 1.", + "fields": [ + { + "name": "TAMPAM", + "description": "Tamper x active mode. (x=1-8)", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 8, + "stride": 1 + } + }, + { + "name": "ATOSEL", + "description": "Active tamper shared output x selection The selected output must be available in the package pinout. (x=1-4)", + "bit_offset": 8, + "bit_size": 2, + "array": { + "len": 4, + "stride": 2 + } + }, + { + "name": "ATCKSEL", + "description": "Active tamper RTC asynchronous prescaler clock selection These bits selects the RTC asynchronous prescaler stage output.The selected clock is CK_ATPRE. fCK_ATPRE = fRTCCLK / 2ATCKSEL when (PREDIV_A+1) = 128. ... These bits can be written only when all active tampers are disabled. The write protection remains for up to 1.5 ck_atpre cycles after all the active tampers are disable.", + "bit_offset": 16, + "bit_size": 3 + }, + { + "name": "ATPER", + "description": "Active tamper output change period The tamper output is changed every CK_ATPER = (2ATPER x CK_ATPRE) cycles. Refer to.", + "bit_offset": 24, + "bit_size": 3 + }, + { + "name": "ATOSHARE", + "description": "Active tamper output sharing TAMP_IN1 is compared with TAMPOUTSEL1 TAMP_IN2 is compared with TAMPOUTSEL2 TAMP_IN3 is compared with TAMPOUTSEL3 TAMP_IN4 is compared with TAMPOUTSEL4 TAMP_IN5 is compared with TAMPOUTSEL5 TAMP_IN6 is compared with TAMPOUTSEL6 TAMP_IN7 is compared with TAMPOUTSEL7 TAMP_IN8 is compared with TAMPOUTSEL8.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "FLTEN", + "description": "Active tamper filter enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/ATCR2": { + "description": "TAMP active tamper control register 2.", + "fields": [ + { + "name": "ATOSEL", + "description": "Active tamper shared output x selection The selected output must be available in the package pinout. Bits 9:8 are the mirror of ATOSELx[1:0] in the TAMP_ATCR1, and so can also be read or written through TAMP_ATCR1. (x=1-8)", + "bit_offset": 8, + "bit_size": 3, + "array": { + "len": 8, + "stride": 3 + } + } + ] + }, + "fieldset/ATOR": { + "description": "TAMP active tamper output register.", + "fields": [ + { + "name": "PRNG", + "description": "Pseudo-random generator value This field provides the values of the PRNG output. Because of potential inconsistencies due to synchronization delays, PRNG must be read at least twice. The read value is correct if it is equal to previous read value. This field can only be read when the APB is in secure mode.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "SEEDF", + "description": "Seed running flag This flag is set by hardware when a new seed is written in the TAMP_ATSEEDR. It is cleared by hardware when the PRNG has absorbed this new seed, and by system reset. The TAMP APB cock must not be switched off as long as SEEDF is set.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "INITS", + "description": "Active tamper initialization status This flag is set by hardware when the PRNG has absorbed the first 128-bit seed, meaning that the enabled active tampers are functional. This flag is cleared when the active tampers are disabled.", + "bit_offset": 15, + "bit_size": 1 + } + ] + }, + "fieldset/CR1": { + "description": "TAMP control register 1.", + "fields": [ + { + "name": "TAMPE", + "description": "Tamper detection on TAMP_INx enable. (x=1-8)", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 8, + "stride": 1 + } + }, + { + "name": "ITAMP1E", + "description": "Internal tamper 1 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ITAMP2E", + "description": "Internal tamper 2 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ITAMP3E", + "description": "Internal tamper 3 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ITAMP4E", + "description": "Internal tamper 4 enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ITAMP5E", + "description": "Internal tamper 5 enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ITAMP6E", + "description": "Internal tamper 6 enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ITAMP7E", + "description": "Internal tamper 7 enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ITAMP8E", + "description": "Internal tamper 8 enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ITAMP9E", + "description": "Internal tamper 9 enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ITAMP11E", + "description": "Internal tamper 11 enable.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ITAMP12E", + "description": "Internal tamper 12 enable.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ITAMP13E", + "description": "Internal tamper 13 enable.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ITAMP15E", + "description": "Internal tamper 15 enable.", + "bit_offset": 30, + "bit_size": 1 + } + ] + }, + "fieldset/CR2": { + "description": "TAMP control register 2.", + "fields": [ + { + "name": "TAMPPOM", + "description": "Tamper x potential mode. (x=1-8)", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 8, + "stride": 1 + } + }, + { + "name": "TAMPMSK", + "description": "Tamper x mask. The tamper x interrupt must not be enabled when TAMPxMSK is set. (x=1-3)", + "bit_offset": 16, + "bit_size": 1, + "array": { + "len": 3, + "stride": 1 + } + }, + { + "name": "BKBLOCK", + "description": "Backup registers and device secrets access blocked.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "BKERASE", + "description": "Backup registers and device secrets erase Writing ‘1’ to this bit reset the backup registers and device secrets(1). Writing 0 has no effect. This bit is always read as 0.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "TAMPTRG", + "description": "Active level for tamper x input If TAMPFLT = 00 Tamper x input rising edge triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge triggers a tamper detection event. (x=1-8)", + "bit_offset": 24, + "bit_size": 1, + "array": { + "len": 8, + "stride": 1 + } + } + ] + }, + "fieldset/CR3": { + "description": "TAMP control register 3.", + "fields": [ + { + "name": "ITAMP1POM", + "description": "Internal tamper 1 potential mode.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ITAMP2POM", + "description": "Internal tamper 2 potential mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ITAMP3POM", + "description": "Internal tamper 3 potential mode.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ITAMP4POM", + "description": "Internal tamper 4 potential mode.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ITAMP5POM", + "description": "Internal tamper 5 potential mode.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ITAMP6POM", + "description": "Internal tamper 6 potential mode.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "ITAMP7POM", + "description": "Internal tamper 7 potential mode.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ITAMP8POM", + "description": "Internal tamper 8 potential mode.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "ITAMP9POM", + "description": "Internal tamper 9 potential mode.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "ITAMP11POM", + "description": "Internal tamper 11 potential mode.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "ITAMP12POM", + "description": "Internal tamper 12 potential mode.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "ITAMP13POM", + "description": "Internal tamper 13 potential mode.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "ITAMP15POM", + "description": "Internal tamper 15 potential mode.", + "bit_offset": 14, + "bit_size": 1 + } + ] + }, + "fieldset/FLTCR": { + "description": "TAMP filter control register.", + "fields": [ + { + "name": "TAMPFREQ", + "description": "Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled.", + "bit_offset": 0, + "bit_size": 3 + }, + { + "name": "TAMPFLT", + "description": "TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs.", + "bit_offset": 3, + "bit_size": 2 + }, + { + "name": "TAMPPRCH", + "description": "TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs.", + "bit_offset": 5, + "bit_size": 2 + }, + { + "name": "TAMPPUDIS", + "description": "TAMP_INx pull-up disable This bit determines if each of the TAMPx pins are precharged before each sample.", + "bit_offset": 7, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "TAMP interrupt enable register.", + "fields": [ + { + "name": "TAMPIE", + "description": "Tamper x interrupt enable. (x=1-8)", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 8, + "stride": 1 + } + }, + { + "name": "ITAMP1IE", + "description": "Internal tamper 1 interrupt enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ITAMP2IE", + "description": "Internal tamper 2 interrupt enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ITAMP3IE", + "description": "Internal tamper 3 interrupt enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ITAMP4IE", + "description": "Internal tamper 4 interrupt enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ITAMP5IE", + "description": "Internal tamper 5 interrupt enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ITAMP6IE", + "description": "Internal tamper 6 interrupt enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ITAMP7IE", + "description": "Internal tamper 7 interrupt enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ITAMP8IE", + "description": "Internal tamper 8 interrupt enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ITAMP9IE", + "description": "Internal tamper 9 interrupt enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ITAMP11IE", + "description": "Internal tamper 11 interrupt enable.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ITAMP12IE", + "description": "Internal tamper 12 interrupt enable.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ITAMP13IE", + "description": "Internal tamper 13 interrupt enable.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ITAMP15IE", + "description": "Internal tamper 15 interrupt enable.", + "bit_offset": 30, + "bit_size": 1 + } + ] + }, + "fieldset/MISR": { + "description": "TAMP non-secure masked interrupt status register.", + "fields": [ + { + "name": "TAMPMF", + "description": "TAMP1 non-secure interrupt masked flag This flag is set by hardware when the tamper 1 non-secure interrupt is raised.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 8, + "stride": 1 + } + }, + { + "name": "ITAMP1MF", + "description": "Internal tamper 1 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 1 non-secure interrupt is raised.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ITAMP2MF", + "description": "Internal tamper 2 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 2 non-secure interrupt is raised.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ITAMP3MF", + "description": "Internal tamper 3 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 3 non-secure interrupt is raised.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ITAMP4MF", + "description": "Internal tamper 4 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 4 non-secure interrupt is raised.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ITAMP5MF", + "description": "Internal tamper 5 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 5 non-secure interrupt is raised.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ITAMP6MF", + "description": "Internal tamper 6 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 6 non-secure interrupt is raised.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ITAMP7MF", + "description": "Internal tamper 7 tamper non-secure interrupt masked flag This flag is set by hardware when the internal tamper 7 non-secure interrupt is raised.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ITAMP8MF", + "description": "Internal tamper 8 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 8 non-secure interrupt is raised.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ITAMP9MF", + "description": "internal tamper 9 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 9 non-secure interrupt is raised.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ITAMP11MF", + "description": "internal tamper 11 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 11 non-secure interrupt is raised.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ITAMP12MF", + "description": "internal tamper 12 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 12 non-secure interrupt is raised.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ITAMP13MF", + "description": "internal tamper 13 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 13 non-secure interrupt is raised.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ITAMP15MF", + "description": "internal tamper 15 non-secure interrupt masked flag This flag is set by hardware when the internal tamper 15 non-secure interrupt is raised.", + "bit_offset": 30, + "bit_size": 1 + } + ] + }, + "fieldset/OR": { + "description": "TAMP option register.", + "fields": [ + { + "name": "OUT3_RMP", + "description": "TAMP_OUT3 mapping.", + "bit_offset": 1, + "bit_size": 2 + }, + { + "name": "OUT5_RMP", + "description": "TAMP_OUT5 mapping.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "IN2_RMP", + "description": "TAMP_IN2 mapping.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IN3_RMP", + "description": "TAMP_IN3 mapping.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IN4_RMP", + "description": "TAMP_IN4 mapping.", + "bit_offset": 10, + "bit_size": 1 + } + ] + }, + "fieldset/PRIVCFGR": { + "description": "TAMP privilege mode control register.", + "fields": [ + { + "name": "CNT1PRIV", + "description": "Monotonic counter 1 privilege protection.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "BKPRWPRIV", + "description": "Backup registers zone 1 privilege protection.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "BKPWPRIV", + "description": "Backup registers zone 2 privilege protection.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "TAMPPRIV", + "description": "Tamper privilege protection (excluding backup registers) Note: Refer to for details on the read protection.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RPCFGR": { + "description": "TAMP erase configuration register.", + "fields": [ + { + "name": "RPCFG0", + "description": "Configurable resource 0 protection.", + "bit_offset": 0, + "bit_size": 1 + } + ] + }, + "fieldset/SCR": { + "description": "TAMP status clear register.", + "fields": [ + { + "name": "CTAMPF", + "description": "Clear TAMPx detection flag. Writing 1 in this bit clears the TAMPxF bit in the TAMP_SR register. (x=1-8)", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 8, + "stride": 1 + } + }, + { + "name": "CITAMP1F", + "description": "Clear ITAMP1 detection flag Writing 1 in this bit clears the ITAMP1F bit in the TAMP_SR register.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "CITAMP2F", + "description": "Clear ITAMP2 detection flag Writing 1 in this bit clears the ITAMP2F bit in the TAMP_SR register.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "CITAMP3F", + "description": "Clear ITAMP3 detection flag Writing 1 in this bit clears the ITAMP3F bit in the TAMP_SR register.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "CITAMP4F", + "description": "Clear ITAMP4 detection flag Writing 1 in this bit clears the ITAMP4F bit in the TAMP_SR register.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "CITAMP5F", + "description": "Clear ITAMP5 detection flag Writing 1 in this bit clears the ITAMP5F bit in the TAMP_SR register.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "CITAMP6F", + "description": "Clear ITAMP6 detection flag Writing 1 in this bit clears the ITAMP6F bit in the TAMP_SR register.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "CITAMP7F", + "description": "Clear ITAMP7 detection flag Writing 1 in this bit clears the ITAMP7F bit in the TAMP_SR register.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "CITAMP8F", + "description": "Clear ITAMP8 detection flag Writing 1 in this bit clears the ITAMP8F bit in the TAMP_SR register.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "CITAMP9F", + "description": "Clear ITAMP9 detection flag Writing 1 in this bit clears the ITAMP9F bit in the TAMP_SR register.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "CITAMP11F", + "description": "Clear ITAMP11 detection flag Writing 1 in this bit clears the ITAMP11F bit in the TAMP_SR register.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "CITAMP12F", + "description": "Clear ITAMP12 detection flag Writing 1 in this bit clears the ITAMP12F bit in the TAMP_SR register.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "CITAMP13F", + "description": "Clear ITAMP13 detection flag Writing 1 in this bit clears the ITAMP13F bit in the TAMP_SR register.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "CITAMP15F", + "description": "Clear ITAMP15 detection flag Writing 1 in this bit clears the ITAMP15F bit in the TAMP_SR register.", + "bit_offset": 30, + "bit_size": 1 + } + ] + }, + "fieldset/SECCFGR": { + "description": "TAMP secure mode register.", + "fields": [ + { + "name": "BKPRWSEC", + "description": "Backup registers read/write protection offset Protection zone 1 is defined for backup registers from TAMP_BKP0R to TAMP_BKPxR (x = BKPRWSEC-1, from 0 to 128). if TZEN=1, these backup registers can be read and written only with secure access. If TZEN=0: the protection zone 1 can be read and written with non-secure access. If BKPRWSEC = 0: there is no protection zone 1. If BKPRWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "CNT1SEC", + "description": "Monotonic counter 1 secure protection.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "BKPWSEC", + "description": "Backup registers write protection offset Protection zone 2 is defined for backup registers from TAMP_BKPyR (y = BKPRWSEC, from 0 to 128) to TAMP_BKPzR (z = BKPWSEC-1, from 0 to 128, BKPWSEC ≥ BKPRWSEC): if TZEN=1, these backup registers can be written only with secure access. They can be read with secure or non-secure access. Protection zone 3 defined for backup registers from TAMP_BKPtR (t = BKPWSEC, from 0 to 127). They can be read or written with secure or non-secure access. If TZEN=0: the protection zone 2 can be read and written with non-secure access. If BKPWSEC = 0 or if BKPWSEC ≤ BKPRWSEC: there is no protection zone 2. If BKPWPRIV is set, BKPRWSEC[7:0] can be written only in privileged mode.", + "bit_offset": 16, + "bit_size": 8 + }, + { + "name": "BHKLOCK", + "description": "Boot hardware key lock This bit can be read and can only be written to 1 by software. It is cleared by hardware together with the backup registers following a tamper detection event or when the readout protection (RDP) is disabled.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "TAMPSEC", + "description": "Tamper protection (excluding monotonic counters and backup registers) Note: Refer to for details on the read protection.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/SMISR": { + "description": "TAMP secure masked interrupt status register.", + "fields": [ + { + "name": "TAMPMF", + "description": "TAMPx secure interrupt masked flag. This flag is set by hardware when the tamper x secure interrupt is raised. (x=1-8)", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 8, + "stride": 1 + } + }, + { + "name": "ITAMP1MF", + "description": "Internal tamper 1 secure interrupt masked flag This flag is set by hardware when the internal tamper 1 secure interrupt is raised.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ITAMP2MF", + "description": "Internal tamper 2 secure interrupt masked flag This flag is set by hardware when the internal tamper 2 secure interrupt is raised.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ITAMP3MF", + "description": "Internal tamper 3 secure interrupt masked flag This flag is set by hardware when the internal tamper 3 secure interrupt is raised.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ITAMP4MF", + "description": "Internal tamper 4 secure interrupt masked flag This flag is set by hardware when the internal tamper 4 secure interrupt is raised.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ITAMP5MF", + "description": "Internal tamper 5 secure interrupt masked flag This flag is set by hardware when the internal tamper 5 secure interrupt is raised.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ITAMP6MF", + "description": "Internal tamper 6 secure interrupt masked flag This flag is set by hardware when the internal tamper 6 secure interrupt is raised.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ITAMP7MF", + "description": "Internal tamper 7 secure interrupt masked flag This flag is set by hardware when the internal tamper 7 secure interrupt is raised.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ITAMP8MF", + "description": "Internal tamper 8 secure interrupt masked flag This flag is set by hardware when the internal tamper 8 secure interrupt is raised.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ITAMP9MF", + "description": "internal tamper 9 secure interrupt masked flag This flag is set by hardware when the internal tamper 9 secure interrupt is raised.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ITAMP11MF", + "description": "internal tamper 11 secure interrupt masked flag This flag is set by hardware when the internal tamper 11 secure interrupt is raised.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ITAMP12MF", + "description": "internal tamper 12 secure interrupt masked flag This flag is set by hardware when the internal tamper 12 secure interrupt is raised.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ITAMP13MF", + "description": "internal tamper 13 secure interrupt masked flag This flag is set by hardware when the internal tamper 13 secure interrupt is raised.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ITAMP15MF", + "description": "internal tamper 15 secure interrupt masked flag This flag is set by hardware when the internal tamper 15 secure interrupt is raised.", + "bit_offset": 30, + "bit_size": 1 + } + ] + }, + "fieldset/SR": { + "description": "TAMP status register.", + "fields": [ + { + "name": "TAMPF", + "description": "TAMPx detection flag. This flag is set by hardware when a tamper detection event is detected on the TAMPx input. (x=1-8)", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 8, + "stride": 1 + } + }, + { + "name": "ITAMP1F", + "description": "Internal tamper 1 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 1.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ITAMP2F", + "description": "Internal tamper 2 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 2.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ITAMP3F", + "description": "Internal tamper 3 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 3.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ITAMP4F", + "description": "Internal tamper 4 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 4.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ITAMP5F", + "description": "Internal tamper 5 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 5.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ITAMP6F", + "description": "Internal tamper 6 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 6.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ITAMP7F", + "description": "Internal tamper 7 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 7.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ITAMP8F", + "description": "Internal tamper 8 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 8.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ITAMP9F", + "description": "Internal tamper 9 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 9.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ITAMP11F", + "description": "Internal tamper 11 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 11.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ITAMP12F", + "description": "Internal tamper 12 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 12.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ITAMP13F", + "description": "Internal tamper 13 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 13.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ITAMP15F", + "description": "Internal tamper 15 flag This flag is set by hardware when a tamper detection event is detected on the internal tamper 15.", + "bit_offset": 30, + "bit_size": 1 + } + ] + } +} \ No newline at end of file