diff --git a/data/registers/timer_l0.json b/data/registers/timer_l0.json
index c1ad67d..9147c05 100644
--- a/data/registers/timer_l0.json
+++ b/data/registers/timer_l0.json
@@ -876,12 +876,6 @@
         "bit_offset": 6,
         "bit_size": 1
       },
-      {
-        "name": "BIE",
-        "description": "Break interrupt enable",
-        "bit_offset": 7,
-        "bit_size": 1
-      },
       {
         "name": "CCDE",
         "description": "Capture/Compare x (x=1-4) DMA request enable",
diff --git a/data/registers/timer_v1.json b/data/registers/timer_v1.json
index f41eeff..5d4ecf9 100644
--- a/data/registers/timer_v1.json
+++ b/data/registers/timer_v1.json
@@ -412,8 +412,7 @@
       {
         "name": "DMAR",
         "description": "DMA address for full transfer",
-        "byte_offset": 76,
-        "fieldset": "DMAR_ADV"
+        "byte_offset": 76
       },
       {
         "name": "CCMR3",
@@ -635,14 +634,12 @@
       {
         "name": "CNT",
         "description": "counter",
-        "byte_offset": 36,
-        "fieldset": "CNT_GP32"
+        "byte_offset": 36
       },
       {
         "name": "ARR",
         "description": "auto-reload register",
-        "byte_offset": 44,
-        "fieldset": "ARR_GP32"
+        "byte_offset": 44
       },
       {
         "name": "CCR",
@@ -651,8 +648,7 @@
           "len": 4,
           "stride": 4
         },
-        "byte_offset": 52,
-        "fieldset": "CCR_GP32"
+        "byte_offset": 52
       },
       {
         "name": "DCR",
@@ -786,17 +782,6 @@
       }
     ]
   },
-  "fieldset/ARR_GP32": {
-    "description": "auto-reload register",
-    "fields": [
-      {
-        "name": "ARR",
-        "description": "Auto-reload value",
-        "bit_offset": 0,
-        "bit_size": 32
-      }
-    ]
-  },
   "fieldset/BDTR_1CH_CMP": {
     "description": "break and dead-time register",
     "fields": [
@@ -1355,17 +1340,6 @@
       }
     ]
   },
-  "fieldset/CCR_GP32": {
-    "description": "capture/compare register x (x=1-4,6)",
-    "fields": [
-      {
-        "name": "CCR",
-        "description": "capture/compare x (x=1-4,6) value",
-        "bit_offset": 0,
-        "bit_size": 32
-      }
-    ]
-  },
   "fieldset/CNT_CORE": {
     "description": "counter",
     "fields": [
@@ -1383,17 +1357,6 @@
       }
     ]
   },
-  "fieldset/CNT_GP32": {
-    "description": "counter",
-    "fields": [
-      {
-        "name": "CNT",
-        "description": "counter value",
-        "bit_offset": 0,
-        "bit_size": 32
-      }
-    ]
-  },
   "fieldset/CR1_1CH": {
     "extends": "CR1_CORE",
     "description": "control register 1",
@@ -1768,6 +1731,12 @@
           "stride": 1
         }
       },
+      {
+        "name": "BIE",
+        "description": "Break interrupt enable",
+        "bit_offset": 7,
+        "bit_size": 1
+      },
       {
         "name": "CCDE",
         "description": "Capture/Compare x (x=1-4) DMA request enable",
@@ -1823,12 +1792,6 @@
         "bit_offset": 6,
         "bit_size": 1
       },
-      {
-        "name": "BIE",
-        "description": "Break interrupt enable",
-        "bit_offset": 7,
-        "bit_size": 1
-      },
       {
         "name": "CCDE",
         "description": "Capture/Compare x (x=1-4) DMA request enable",
@@ -1847,17 +1810,6 @@
       }
     ]
   },
-  "fieldset/DMAR_ADV": {
-    "description": "DMA address for full transfer",
-    "fields": [
-      {
-        "name": "DMAB",
-        "description": "DMA register for burst accesses",
-        "bit_offset": 0,
-        "bit_size": 32
-      }
-    ]
-  },
   "fieldset/DMAR_GP16": {
     "description": "DMA address for full transfer",
     "fields": [
diff --git a/data/registers/timer_v2.json b/data/registers/timer_v2.json
index 8dbb89a..4061550 100644
--- a/data/registers/timer_v2.json
+++ b/data/registers/timer_v2.json
@@ -161,8 +161,7 @@
       {
         "name": "DMAR",
         "description": "DMA address for full transfer",
-        "byte_offset": 992,
-        "fieldset": "DMAR_1CH_CMP"
+        "byte_offset": 992
       }
     ]
   },
@@ -677,8 +676,7 @@
       {
         "name": "DMAR",
         "description": "DMA address for full transfer",
-        "byte_offset": 992,
-        "fieldset": "DMAR_1CH_CMP"
+        "byte_offset": 992
       }
     ]
   },
@@ -689,8 +687,7 @@
       {
         "name": "CNT",
         "description": "counter (Dither mode disabled)",
-        "byte_offset": 36,
-        "fieldset": "CNT_GP32"
+        "byte_offset": 36
       },
       {
         "name": "CNT_DITHER",
@@ -701,8 +698,7 @@
       {
         "name": "ARR",
         "description": "auto-reload register (Dither mode disabled)",
-        "byte_offset": 44,
-        "fieldset": "ARR_GP32"
+        "byte_offset": 44
       },
       {
         "name": "ARR_DITHER",
@@ -717,8 +713,7 @@
           "len": 4,
           "stride": 4
         },
-        "byte_offset": 52,
-        "fieldset": "CCR_GP32"
+        "byte_offset": 52
       },
       {
         "name": "CCR_DITHER",
@@ -890,17 +885,6 @@
       }
     ]
   },
-  "fieldset/ARR_GP32": {
-    "description": "auto-reload register (Dither mode disabled)",
-    "fields": [
-      {
-        "name": "ARR",
-        "description": "Auto-reload value",
-        "bit_offset": 0,
-        "bit_size": 32
-      }
-    ]
-  },
   "fieldset/BDTR_1CH_CMP": {
     "description": "break and dead-time register",
     "fields": [
@@ -1581,17 +1565,6 @@
       }
     ]
   },
-  "fieldset/CCR_GP32": {
-    "description": "capture/compare register x (x=1-4,6) (Dither mode disabled)",
-    "fields": [
-      {
-        "name": "CCR",
-        "description": "capture/compare x (x=1-4,6) value",
-        "bit_offset": 0,
-        "bit_size": 32
-      }
-    ]
-  },
   "fieldset/CNT_CORE": {
     "description": "counter",
     "fields": [
@@ -1626,17 +1599,6 @@
       }
     ]
   },
-  "fieldset/CNT_GP32": {
-    "description": "counter (Dither mode disabled)",
-    "fields": [
-      {
-        "name": "CNT",
-        "description": "counter value",
-        "bit_offset": 0,
-        "bit_size": 32
-      }
-    ]
-  },
   "fieldset/CR1_1CH": {
     "extends": "CR1_CORE",
     "description": "control register 1",
@@ -2038,6 +2000,12 @@
           "stride": 1
         }
       },
+      {
+        "name": "BIE",
+        "description": "Break interrupt enable",
+        "bit_offset": 7,
+        "bit_size": 1
+      },
       {
         "name": "CCDE",
         "description": "Capture/Compare x (x=1) DMA request enable",
@@ -2117,12 +2085,6 @@
         "bit_offset": 6,
         "bit_size": 1
       },
-      {
-        "name": "BIE",
-        "description": "Break interrupt enable",
-        "bit_offset": 7,
-        "bit_size": 1
-      },
       {
         "name": "CCDE",
         "description": "Capture/Compare x (x=1-4) DMA request enable",
@@ -2165,17 +2127,6 @@
       }
     ]
   },
-  "fieldset/DMAR_1CH_CMP": {
-    "description": "DMA address for full transfer",
-    "fields": [
-      {
-        "name": "DMAB",
-        "description": "DMA register for burst accesses",
-        "bit_offset": 0,
-        "bit_size": 32
-      }
-    ]
-  },
   "fieldset/DTR2_1CH_CMP": {
     "description": "deadtime register 2",
     "fields": [