diff --git a/data/chips/STM32F042C4.json b/data/chips/STM32F042C4.json index 5eddf88..d170215 100644 --- a/data/chips/STM32F042C4.json +++ b/data/chips/STM32F042C4.json @@ -450,6 +450,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F042C6.json b/data/chips/STM32F042C6.json index 6713a08..ee3d378 100644 --- a/data/chips/STM32F042C6.json +++ b/data/chips/STM32F042C6.json @@ -450,6 +450,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F042F4.json b/data/chips/STM32F042F4.json index bc8fcef..6c57713 100644 --- a/data/chips/STM32F042F4.json +++ b/data/chips/STM32F042F4.json @@ -437,6 +437,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F042F6.json b/data/chips/STM32F042F6.json index b164580..e26256c 100644 --- a/data/chips/STM32F042F6.json +++ b/data/chips/STM32F042F6.json @@ -437,6 +437,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F042G4.json b/data/chips/STM32F042G4.json index ad09572..eb274d6 100644 --- a/data/chips/STM32F042G4.json +++ b/data/chips/STM32F042G4.json @@ -441,6 +441,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F042G6.json b/data/chips/STM32F042G6.json index d9a0656..32a590a 100644 --- a/data/chips/STM32F042G6.json +++ b/data/chips/STM32F042G6.json @@ -441,6 +441,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F042K4.json b/data/chips/STM32F042K4.json index 14c9727..7f6d027 100644 --- a/data/chips/STM32F042K4.json +++ b/data/chips/STM32F042K4.json @@ -445,6 +445,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F042K6.json b/data/chips/STM32F042K6.json index ed85d94..380f11c 100644 --- a/data/chips/STM32F042K6.json +++ b/data/chips/STM32F042K6.json @@ -445,6 +445,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F042T6.json b/data/chips/STM32F042T6.json index 289a523..52df8a2 100644 --- a/data/chips/STM32F042T6.json +++ b/data/chips/STM32F042T6.json @@ -441,6 +441,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F048C6.json b/data/chips/STM32F048C6.json index 3ed4212..34e0168 100644 --- a/data/chips/STM32F048C6.json +++ b/data/chips/STM32F048C6.json @@ -379,6 +379,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F048G6.json b/data/chips/STM32F048G6.json index 5c6cd3e..b26c5c4 100644 --- a/data/chips/STM32F048G6.json +++ b/data/chips/STM32F048G6.json @@ -375,6 +375,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F048T6.json b/data/chips/STM32F048T6.json index 5af2382..b820e9f 100644 --- a/data/chips/STM32F048T6.json +++ b/data/chips/STM32F048T6.json @@ -379,6 +379,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F051C4.json b/data/chips/STM32F051C4.json index 54c34e2..1988049 100644 --- a/data/chips/STM32F051C4.json +++ b/data/chips/STM32F051C4.json @@ -377,6 +377,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F051C6.json b/data/chips/STM32F051C6.json index 5b710c2..6f4ea86 100644 --- a/data/chips/STM32F051C6.json +++ b/data/chips/STM32F051C6.json @@ -377,6 +377,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F051C8.json b/data/chips/STM32F051C8.json index b5ddcca..3876a34 100644 --- a/data/chips/STM32F051C8.json +++ b/data/chips/STM32F051C8.json @@ -377,6 +377,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F051K4.json b/data/chips/STM32F051K4.json index 84cafcb..e58e94f 100644 --- a/data/chips/STM32F051K4.json +++ b/data/chips/STM32F051K4.json @@ -377,6 +377,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F051K6.json b/data/chips/STM32F051K6.json index 44a9a8a..e983cf8 100644 --- a/data/chips/STM32F051K6.json +++ b/data/chips/STM32F051K6.json @@ -377,6 +377,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F051K8.json b/data/chips/STM32F051K8.json index 89ed836..322f032 100644 --- a/data/chips/STM32F051K8.json +++ b/data/chips/STM32F051K8.json @@ -377,6 +377,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F051R4.json b/data/chips/STM32F051R4.json index ea7ba3d..151cfe3 100644 --- a/data/chips/STM32F051R4.json +++ b/data/chips/STM32F051R4.json @@ -397,6 +397,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F051R6.json b/data/chips/STM32F051R6.json index d8448a5..b97761f 100644 --- a/data/chips/STM32F051R6.json +++ b/data/chips/STM32F051R6.json @@ -397,6 +397,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F051R8.json b/data/chips/STM32F051R8.json index e5e7b1f..8849fca 100644 --- a/data/chips/STM32F051R8.json +++ b/data/chips/STM32F051R8.json @@ -401,6 +401,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F051T8.json b/data/chips/STM32F051T8.json index 678c5e0..add7841 100644 --- a/data/chips/STM32F051T8.json +++ b/data/chips/STM32F051T8.json @@ -367,6 +367,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F058C8.json b/data/chips/STM32F058C8.json index c574639..2df7d98 100644 --- a/data/chips/STM32F058C8.json +++ b/data/chips/STM32F058C8.json @@ -373,6 +373,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F058R8.json b/data/chips/STM32F058R8.json index a46ceaf..48222c1 100644 --- a/data/chips/STM32F058R8.json +++ b/data/chips/STM32F058R8.json @@ -401,6 +401,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F058T8.json b/data/chips/STM32F058T8.json index 0e9be71..b9fc656 100644 --- a/data/chips/STM32F058T8.json +++ b/data/chips/STM32F058T8.json @@ -367,6 +367,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F071C8.json b/data/chips/STM32F071C8.json index 0f66e3f..d47b3dd 100644 --- a/data/chips/STM32F071C8.json +++ b/data/chips/STM32F071C8.json @@ -365,6 +365,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F071CB.json b/data/chips/STM32F071CB.json index 99fe40d..f341622 100644 --- a/data/chips/STM32F071CB.json +++ b/data/chips/STM32F071CB.json @@ -381,6 +381,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F071RB.json b/data/chips/STM32F071RB.json index 673e690..4074f18 100644 --- a/data/chips/STM32F071RB.json +++ b/data/chips/STM32F071RB.json @@ -397,6 +397,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F071V8.json b/data/chips/STM32F071V8.json index f81ad49..af686a7 100644 --- a/data/chips/STM32F071V8.json +++ b/data/chips/STM32F071V8.json @@ -395,6 +395,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F071VB.json b/data/chips/STM32F071VB.json index 9427e2e..142c041 100644 --- a/data/chips/STM32F071VB.json +++ b/data/chips/STM32F071VB.json @@ -401,6 +401,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F072C8.json b/data/chips/STM32F072C8.json index 2199f1a..8eee354 100644 --- a/data/chips/STM32F072C8.json +++ b/data/chips/STM32F072C8.json @@ -450,6 +450,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F072CB.json b/data/chips/STM32F072CB.json index bdcb13f..ccb3620 100644 --- a/data/chips/STM32F072CB.json +++ b/data/chips/STM32F072CB.json @@ -454,6 +454,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F072R8.json b/data/chips/STM32F072R8.json index 48d1f7c..07355d5 100644 --- a/data/chips/STM32F072R8.json +++ b/data/chips/STM32F072R8.json @@ -470,6 +470,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F072RB.json b/data/chips/STM32F072RB.json index 5d15b16..96d17c0 100644 --- a/data/chips/STM32F072RB.json +++ b/data/chips/STM32F072RB.json @@ -478,6 +478,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F072V8.json b/data/chips/STM32F072V8.json index 4b550ce..f27e507 100644 --- a/data/chips/STM32F072V8.json +++ b/data/chips/STM32F072V8.json @@ -484,6 +484,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F072VB.json b/data/chips/STM32F072VB.json index cfc15c1..5e432a2 100644 --- a/data/chips/STM32F072VB.json +++ b/data/chips/STM32F072VB.json @@ -484,6 +484,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F078CB.json b/data/chips/STM32F078CB.json index 86c94cb..514d2f8 100644 --- a/data/chips/STM32F078CB.json +++ b/data/chips/STM32F078CB.json @@ -393,6 +393,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F078RB.json b/data/chips/STM32F078RB.json index 9e74aec..a16ca44 100644 --- a/data/chips/STM32F078RB.json +++ b/data/chips/STM32F078RB.json @@ -413,6 +413,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F078VB.json b/data/chips/STM32F078VB.json index 4ed65f8..5b0944f 100644 --- a/data/chips/STM32F078VB.json +++ b/data/chips/STM32F078VB.json @@ -413,6 +413,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F091CB.json b/data/chips/STM32F091CB.json index f72457e..54af868 100644 --- a/data/chips/STM32F091CB.json +++ b/data/chips/STM32F091CB.json @@ -445,6 +445,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F091CC.json b/data/chips/STM32F091CC.json index 80b2d07..f97ba06 100644 --- a/data/chips/STM32F091CC.json +++ b/data/chips/STM32F091CC.json @@ -445,6 +445,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F091RB.json b/data/chips/STM32F091RB.json index 19592ae..530b272 100644 --- a/data/chips/STM32F091RB.json +++ b/data/chips/STM32F091RB.json @@ -465,6 +465,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F091RC.json b/data/chips/STM32F091RC.json index 543f73a..3b8e7b7 100644 --- a/data/chips/STM32F091RC.json +++ b/data/chips/STM32F091RC.json @@ -473,6 +473,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F091VB.json b/data/chips/STM32F091VB.json index 02de950..c8d64c1 100644 --- a/data/chips/STM32F091VB.json +++ b/data/chips/STM32F091VB.json @@ -475,6 +475,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F091VC.json b/data/chips/STM32F091VC.json index 67b53af..cb0e028 100644 --- a/data/chips/STM32F091VC.json +++ b/data/chips/STM32F091VC.json @@ -479,6 +479,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F098CC.json b/data/chips/STM32F098CC.json index 886ba03..04a160f 100644 --- a/data/chips/STM32F098CC.json +++ b/data/chips/STM32F098CC.json @@ -445,6 +445,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F098RC.json b/data/chips/STM32F098RC.json index 4944117..cb923b6 100644 --- a/data/chips/STM32F098RC.json +++ b/data/chips/STM32F098RC.json @@ -473,6 +473,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F098VC.json b/data/chips/STM32F098VC.json index c980199..fa7833b 100644 --- a/data/chips/STM32F098VC.json +++ b/data/chips/STM32F098VC.json @@ -479,6 +479,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F100C4.json b/data/chips/STM32F100C4.json index 2e2177d..f074f41 100644 --- a/data/chips/STM32F100C4.json +++ b/data/chips/STM32F100C4.json @@ -393,6 +393,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100C6.json b/data/chips/STM32F100C6.json index aca9dbe..b413a37 100644 --- a/data/chips/STM32F100C6.json +++ b/data/chips/STM32F100C6.json @@ -393,6 +393,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100C8.json b/data/chips/STM32F100C8.json index befd240..70634f4 100644 --- a/data/chips/STM32F100C8.json +++ b/data/chips/STM32F100C8.json @@ -393,6 +393,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100CB.json b/data/chips/STM32F100CB.json index 1279452..35f64d4 100644 --- a/data/chips/STM32F100CB.json +++ b/data/chips/STM32F100CB.json @@ -393,6 +393,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100R4.json b/data/chips/STM32F100R4.json index f6e4f98..2129d09 100644 --- a/data/chips/STM32F100R4.json +++ b/data/chips/STM32F100R4.json @@ -421,6 +421,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100R6.json b/data/chips/STM32F100R6.json index ef58935..e615492 100644 --- a/data/chips/STM32F100R6.json +++ b/data/chips/STM32F100R6.json @@ -421,6 +421,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100R8.json b/data/chips/STM32F100R8.json index cd668e4..570baaf 100644 --- a/data/chips/STM32F100R8.json +++ b/data/chips/STM32F100R8.json @@ -421,6 +421,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100RB.json b/data/chips/STM32F100RB.json index df5420b..f392a83 100644 --- a/data/chips/STM32F100RB.json +++ b/data/chips/STM32F100RB.json @@ -421,6 +421,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100RC.json b/data/chips/STM32F100RC.json index f40877f..ec406a1 100644 --- a/data/chips/STM32F100RC.json +++ b/data/chips/STM32F100RC.json @@ -417,6 +417,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100RD.json b/data/chips/STM32F100RD.json index 10ecaf8..8222cd1 100644 --- a/data/chips/STM32F100RD.json +++ b/data/chips/STM32F100RD.json @@ -417,6 +417,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100RE.json b/data/chips/STM32F100RE.json index 58d4409..1e2a721 100644 --- a/data/chips/STM32F100RE.json +++ b/data/chips/STM32F100RE.json @@ -417,6 +417,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100V8.json b/data/chips/STM32F100V8.json index a57a77d..d52b91a 100644 --- a/data/chips/STM32F100V8.json +++ b/data/chips/STM32F100V8.json @@ -417,6 +417,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100VB.json b/data/chips/STM32F100VB.json index 7890a0c..f806f3f 100644 --- a/data/chips/STM32F100VB.json +++ b/data/chips/STM32F100VB.json @@ -417,6 +417,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100VC.json b/data/chips/STM32F100VC.json index 826c4ea..c67185e 100644 --- a/data/chips/STM32F100VC.json +++ b/data/chips/STM32F100VC.json @@ -417,6 +417,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100VD.json b/data/chips/STM32F100VD.json index f078e23..6124fd8 100644 --- a/data/chips/STM32F100VD.json +++ b/data/chips/STM32F100VD.json @@ -417,6 +417,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100VE.json b/data/chips/STM32F100VE.json index 5dff372..2549fcd 100644 --- a/data/chips/STM32F100VE.json +++ b/data/chips/STM32F100VE.json @@ -417,6 +417,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100ZC.json b/data/chips/STM32F100ZC.json index 1d799c2..be264cd 100644 --- a/data/chips/STM32F100ZC.json +++ b/data/chips/STM32F100ZC.json @@ -417,6 +417,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100ZD.json b/data/chips/STM32F100ZD.json index e8840f4..b75e99c 100644 --- a/data/chips/STM32F100ZD.json +++ b/data/chips/STM32F100ZD.json @@ -417,6 +417,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F100ZE.json b/data/chips/STM32F100ZE.json index f462f24..537e4c3 100644 --- a/data/chips/STM32F100ZE.json +++ b/data/chips/STM32F100ZE.json @@ -417,6 +417,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v1", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32F373C8.json b/data/chips/STM32F373C8.json index 0625b5b..30cb154 100644 --- a/data/chips/STM32F373C8.json +++ b/data/chips/STM32F373C8.json @@ -450,6 +450,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F373CB.json b/data/chips/STM32F373CB.json index 98fb9a4..78f15e6 100644 --- a/data/chips/STM32F373CB.json +++ b/data/chips/STM32F373CB.json @@ -450,6 +450,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F373CC.json b/data/chips/STM32F373CC.json index 6677bbc..9273aca 100644 --- a/data/chips/STM32F373CC.json +++ b/data/chips/STM32F373CC.json @@ -450,6 +450,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F373R8.json b/data/chips/STM32F373R8.json index c181bea..db462f1 100644 --- a/data/chips/STM32F373R8.json +++ b/data/chips/STM32F373R8.json @@ -478,6 +478,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F373RB.json b/data/chips/STM32F373RB.json index 380a646..6491eb5 100644 --- a/data/chips/STM32F373RB.json +++ b/data/chips/STM32F373RB.json @@ -478,6 +478,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F373RC.json b/data/chips/STM32F373RC.json index ca61eea..661a68b 100644 --- a/data/chips/STM32F373RC.json +++ b/data/chips/STM32F373RC.json @@ -478,6 +478,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F373V8.json b/data/chips/STM32F373V8.json index c5df850..c1a193a 100644 --- a/data/chips/STM32F373V8.json +++ b/data/chips/STM32F373V8.json @@ -492,6 +492,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F373VB.json b/data/chips/STM32F373VB.json index aa2449d..b2e681c 100644 --- a/data/chips/STM32F373VB.json +++ b/data/chips/STM32F373VB.json @@ -492,6 +492,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F373VC.json b/data/chips/STM32F373VC.json index 80a5101..3609756 100644 --- a/data/chips/STM32F373VC.json +++ b/data/chips/STM32F373VC.json @@ -492,6 +492,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F378CC.json b/data/chips/STM32F378CC.json index 493f8c8..ab8d487 100644 --- a/data/chips/STM32F378CC.json +++ b/data/chips/STM32F378CC.json @@ -432,6 +432,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F378RC.json b/data/chips/STM32F378RC.json index 23592a0..ac08bfc 100644 --- a/data/chips/STM32F378RC.json +++ b/data/chips/STM32F378RC.json @@ -464,6 +464,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F378VC.json b/data/chips/STM32F378VC.json index 445befb..ee5a598 100644 --- a/data/chips/STM32F378VC.json +++ b/data/chips/STM32F378VC.json @@ -474,6 +474,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F446MC.json b/data/chips/STM32F446MC.json index 248ee7f..f134cca 100644 --- a/data/chips/STM32F446MC.json +++ b/data/chips/STM32F446MC.json @@ -739,6 +739,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F446ME.json b/data/chips/STM32F446ME.json index 2ffa634..1c92911 100644 --- a/data/chips/STM32F446ME.json +++ b/data/chips/STM32F446ME.json @@ -739,6 +739,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F446RC.json b/data/chips/STM32F446RC.json index c721e28..eea4326 100644 --- a/data/chips/STM32F446RC.json +++ b/data/chips/STM32F446RC.json @@ -749,6 +749,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F446RE.json b/data/chips/STM32F446RE.json index 09c9843..2020fe9 100644 --- a/data/chips/STM32F446RE.json +++ b/data/chips/STM32F446RE.json @@ -749,6 +749,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F446VC.json b/data/chips/STM32F446VC.json index 7282a16..faf7cae 100644 --- a/data/chips/STM32F446VC.json +++ b/data/chips/STM32F446VC.json @@ -759,6 +759,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F446VE.json b/data/chips/STM32F446VE.json index 7ecebc0..4e8266c 100644 --- a/data/chips/STM32F446VE.json +++ b/data/chips/STM32F446VE.json @@ -759,6 +759,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F446ZC.json b/data/chips/STM32F446ZC.json index 251556a..7d62dc5 100644 --- a/data/chips/STM32F446ZC.json +++ b/data/chips/STM32F446ZC.json @@ -799,6 +799,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F446ZE.json b/data/chips/STM32F446ZE.json index f7c31ef..823360b 100644 --- a/data/chips/STM32F446ZE.json +++ b/data/chips/STM32F446ZE.json @@ -799,6 +799,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F745IE.json b/data/chips/STM32F745IE.json index 21367df..770d558 100644 --- a/data/chips/STM32F745IE.json +++ b/data/chips/STM32F745IE.json @@ -805,6 +805,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F745IG.json b/data/chips/STM32F745IG.json index 6b14fc6..198b003 100644 --- a/data/chips/STM32F745IG.json +++ b/data/chips/STM32F745IG.json @@ -805,6 +805,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F745VE.json b/data/chips/STM32F745VE.json index 2478aec..b78bdf1 100644 --- a/data/chips/STM32F745VE.json +++ b/data/chips/STM32F745VE.json @@ -763,6 +763,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F745VG.json b/data/chips/STM32F745VG.json index 3798d9a..050ecb9 100644 --- a/data/chips/STM32F745VG.json +++ b/data/chips/STM32F745VG.json @@ -763,6 +763,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F745ZE.json b/data/chips/STM32F745ZE.json index 26a9942..c73e354 100644 --- a/data/chips/STM32F745ZE.json +++ b/data/chips/STM32F745ZE.json @@ -791,6 +791,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F745ZG.json b/data/chips/STM32F745ZG.json index bdc6dc5..a85fdb5 100644 --- a/data/chips/STM32F745ZG.json +++ b/data/chips/STM32F745ZG.json @@ -791,6 +791,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F746BE.json b/data/chips/STM32F746BE.json index 3404a30..38ff111 100644 --- a/data/chips/STM32F746BE.json +++ b/data/chips/STM32F746BE.json @@ -807,6 +807,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F746BG.json b/data/chips/STM32F746BG.json index 655ccd5..23926ba 100644 --- a/data/chips/STM32F746BG.json +++ b/data/chips/STM32F746BG.json @@ -807,6 +807,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F746IE.json b/data/chips/STM32F746IE.json index c9db735..a5b404d 100644 --- a/data/chips/STM32F746IE.json +++ b/data/chips/STM32F746IE.json @@ -811,6 +811,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F746IG.json b/data/chips/STM32F746IG.json index 3f49816..b8a3a3e 100644 --- a/data/chips/STM32F746IG.json +++ b/data/chips/STM32F746IG.json @@ -811,6 +811,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F746NE.json b/data/chips/STM32F746NE.json index 85c907a..0731761 100644 --- a/data/chips/STM32F746NE.json +++ b/data/chips/STM32F746NE.json @@ -807,6 +807,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F746NG.json b/data/chips/STM32F746NG.json index 36fd9a8..335245a 100644 --- a/data/chips/STM32F746NG.json +++ b/data/chips/STM32F746NG.json @@ -807,6 +807,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F746VE.json b/data/chips/STM32F746VE.json index dcd6949..c1e7057 100644 --- a/data/chips/STM32F746VE.json +++ b/data/chips/STM32F746VE.json @@ -769,6 +769,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F746VG.json b/data/chips/STM32F746VG.json index 8d6fda4..7a2ff16 100644 --- a/data/chips/STM32F746VG.json +++ b/data/chips/STM32F746VG.json @@ -769,6 +769,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F746ZE.json b/data/chips/STM32F746ZE.json index 04c2fa2..1a12209 100644 --- a/data/chips/STM32F746ZE.json +++ b/data/chips/STM32F746ZE.json @@ -801,6 +801,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F746ZG.json b/data/chips/STM32F746ZG.json index 05bd8a8..bce8f2d 100644 --- a/data/chips/STM32F746ZG.json +++ b/data/chips/STM32F746ZG.json @@ -801,6 +801,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F750N8.json b/data/chips/STM32F750N8.json index f9b7941..3d88b82 100644 --- a/data/chips/STM32F750N8.json +++ b/data/chips/STM32F750N8.json @@ -761,6 +761,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F750V8.json b/data/chips/STM32F750V8.json index 9ed0683..879de04 100644 --- a/data/chips/STM32F750V8.json +++ b/data/chips/STM32F750V8.json @@ -719,6 +719,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F750Z8.json b/data/chips/STM32F750Z8.json index e6ccab3..38d5226 100644 --- a/data/chips/STM32F750Z8.json +++ b/data/chips/STM32F750Z8.json @@ -751,6 +751,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F756BG.json b/data/chips/STM32F756BG.json index c1e84a6..1c5f66b 100644 --- a/data/chips/STM32F756BG.json +++ b/data/chips/STM32F756BG.json @@ -807,6 +807,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F756IG.json b/data/chips/STM32F756IG.json index eaa051b..b8d1a11 100644 --- a/data/chips/STM32F756IG.json +++ b/data/chips/STM32F756IG.json @@ -811,6 +811,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F756NG.json b/data/chips/STM32F756NG.json index 99b3a9d..5c8f016 100644 --- a/data/chips/STM32F756NG.json +++ b/data/chips/STM32F756NG.json @@ -807,6 +807,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F756VG.json b/data/chips/STM32F756VG.json index 8ebe0a5..84f9977 100644 --- a/data/chips/STM32F756VG.json +++ b/data/chips/STM32F756VG.json @@ -769,6 +769,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F756ZG.json b/data/chips/STM32F756ZG.json index feea19e..de0a393 100644 --- a/data/chips/STM32F756ZG.json +++ b/data/chips/STM32F756ZG.json @@ -801,6 +801,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F765BG.json b/data/chips/STM32F765BG.json index 916c7dd..efeff08 100644 --- a/data/chips/STM32F765BG.json +++ b/data/chips/STM32F765BG.json @@ -861,6 +861,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F765BI.json b/data/chips/STM32F765BI.json index 993f8d9..eec2d4c 100644 --- a/data/chips/STM32F765BI.json +++ b/data/chips/STM32F765BI.json @@ -867,6 +867,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F765IG.json b/data/chips/STM32F765IG.json index 933bfe5..7cf0cc7 100644 --- a/data/chips/STM32F765IG.json +++ b/data/chips/STM32F765IG.json @@ -871,6 +871,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F765II.json b/data/chips/STM32F765II.json index 0f7c886..ac7ece3 100644 --- a/data/chips/STM32F765II.json +++ b/data/chips/STM32F765II.json @@ -871,6 +871,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F765NG.json b/data/chips/STM32F765NG.json index a3a189a..d898fe2 100644 --- a/data/chips/STM32F765NG.json +++ b/data/chips/STM32F765NG.json @@ -867,6 +867,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F765NI.json b/data/chips/STM32F765NI.json index 147face..d01d174 100644 --- a/data/chips/STM32F765NI.json +++ b/data/chips/STM32F765NI.json @@ -867,6 +867,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F765VG.json b/data/chips/STM32F765VG.json index 7dcf320..2aaeea9 100644 --- a/data/chips/STM32F765VG.json +++ b/data/chips/STM32F765VG.json @@ -824,6 +824,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F765VI.json b/data/chips/STM32F765VI.json index 7880aa9..084539d 100644 --- a/data/chips/STM32F765VI.json +++ b/data/chips/STM32F765VI.json @@ -824,6 +824,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F765ZG.json b/data/chips/STM32F765ZG.json index 488d19d..ef0e84a 100644 --- a/data/chips/STM32F765ZG.json +++ b/data/chips/STM32F765ZG.json @@ -852,6 +852,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F765ZI.json b/data/chips/STM32F765ZI.json index 6cd8cce..53a7a39 100644 --- a/data/chips/STM32F765ZI.json +++ b/data/chips/STM32F765ZI.json @@ -852,6 +852,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F767BG.json b/data/chips/STM32F767BG.json index 2668b0c..59f9034 100644 --- a/data/chips/STM32F767BG.json +++ b/data/chips/STM32F767BG.json @@ -873,6 +873,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F767BI.json b/data/chips/STM32F767BI.json index f0f16ba..76708a2 100644 --- a/data/chips/STM32F767BI.json +++ b/data/chips/STM32F767BI.json @@ -873,6 +873,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F767IG.json b/data/chips/STM32F767IG.json index c2194d8..e2da54b 100644 --- a/data/chips/STM32F767IG.json +++ b/data/chips/STM32F767IG.json @@ -877,6 +877,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F767II.json b/data/chips/STM32F767II.json index 5872fe6..42e3209 100644 --- a/data/chips/STM32F767II.json +++ b/data/chips/STM32F767II.json @@ -877,6 +877,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F767NG.json b/data/chips/STM32F767NG.json index 39b61a8..6d6e096 100644 --- a/data/chips/STM32F767NG.json +++ b/data/chips/STM32F767NG.json @@ -873,6 +873,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F767NI.json b/data/chips/STM32F767NI.json index ea4eacd..bb374fc 100644 --- a/data/chips/STM32F767NI.json +++ b/data/chips/STM32F767NI.json @@ -873,6 +873,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F767VG.json b/data/chips/STM32F767VG.json index b751a71..718883e 100644 --- a/data/chips/STM32F767VG.json +++ b/data/chips/STM32F767VG.json @@ -830,6 +830,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F767VI.json b/data/chips/STM32F767VI.json index 8dc99e4..260316a 100644 --- a/data/chips/STM32F767VI.json +++ b/data/chips/STM32F767VI.json @@ -830,6 +830,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F767ZG.json b/data/chips/STM32F767ZG.json index fea1d17..5616338 100644 --- a/data/chips/STM32F767ZG.json +++ b/data/chips/STM32F767ZG.json @@ -858,6 +858,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F767ZI.json b/data/chips/STM32F767ZI.json index 3f2cc7f..838aabe 100644 --- a/data/chips/STM32F767ZI.json +++ b/data/chips/STM32F767ZI.json @@ -858,6 +858,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F768AI.json b/data/chips/STM32F768AI.json index 870cd4f..760a85d 100644 --- a/data/chips/STM32F768AI.json +++ b/data/chips/STM32F768AI.json @@ -540,6 +540,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F769AG.json b/data/chips/STM32F769AG.json index ce69dd8..2b3b75b 100644 --- a/data/chips/STM32F769AG.json +++ b/data/chips/STM32F769AG.json @@ -540,6 +540,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F769AI.json b/data/chips/STM32F769AI.json index 64f4cdb..b97df00 100644 --- a/data/chips/STM32F769AI.json +++ b/data/chips/STM32F769AI.json @@ -829,6 +829,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F769BG.json b/data/chips/STM32F769BG.json index 0cb7258..7b6487f 100644 --- a/data/chips/STM32F769BG.json +++ b/data/chips/STM32F769BG.json @@ -885,6 +885,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F769BI.json b/data/chips/STM32F769BI.json index a89f5a4..5e067a1 100644 --- a/data/chips/STM32F769BI.json +++ b/data/chips/STM32F769BI.json @@ -885,6 +885,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F769IG.json b/data/chips/STM32F769IG.json index 22582df..32e6c3b 100644 --- a/data/chips/STM32F769IG.json +++ b/data/chips/STM32F769IG.json @@ -875,6 +875,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F769II.json b/data/chips/STM32F769II.json index 9693514..86a0b6c 100644 --- a/data/chips/STM32F769II.json +++ b/data/chips/STM32F769II.json @@ -875,6 +875,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F769NG.json b/data/chips/STM32F769NG.json index f6fe90a..e34af1b 100644 --- a/data/chips/STM32F769NG.json +++ b/data/chips/STM32F769NG.json @@ -885,6 +885,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F769NI.json b/data/chips/STM32F769NI.json index ad26a09..fe12472 100644 --- a/data/chips/STM32F769NI.json +++ b/data/chips/STM32F769NI.json @@ -885,6 +885,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F777BI.json b/data/chips/STM32F777BI.json index 5c43f5c..a6e853f 100644 --- a/data/chips/STM32F777BI.json +++ b/data/chips/STM32F777BI.json @@ -879,6 +879,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F777II.json b/data/chips/STM32F777II.json index e70d752..8df1ab5 100644 --- a/data/chips/STM32F777II.json +++ b/data/chips/STM32F777II.json @@ -883,6 +883,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F777NI.json b/data/chips/STM32F777NI.json index a3176b3..497cf55 100644 --- a/data/chips/STM32F777NI.json +++ b/data/chips/STM32F777NI.json @@ -879,6 +879,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F777VI.json b/data/chips/STM32F777VI.json index ad66dc4..bc89cda 100644 --- a/data/chips/STM32F777VI.json +++ b/data/chips/STM32F777VI.json @@ -836,6 +836,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F777ZI.json b/data/chips/STM32F777ZI.json index c03fdd0..b82df3b 100644 --- a/data/chips/STM32F777ZI.json +++ b/data/chips/STM32F777ZI.json @@ -864,6 +864,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F778AI.json b/data/chips/STM32F778AI.json index 755f6a4..94e53b4 100644 --- a/data/chips/STM32F778AI.json +++ b/data/chips/STM32F778AI.json @@ -823,6 +823,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F779AI.json b/data/chips/STM32F779AI.json index 5e32659..d5291b0 100644 --- a/data/chips/STM32F779AI.json +++ b/data/chips/STM32F779AI.json @@ -829,6 +829,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F779BI.json b/data/chips/STM32F779BI.json index 0a9c17d..053576f 100644 --- a/data/chips/STM32F779BI.json +++ b/data/chips/STM32F779BI.json @@ -885,6 +885,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F779II.json b/data/chips/STM32F779II.json index dfa566e..cd858c7 100644 --- a/data/chips/STM32F779II.json +++ b/data/chips/STM32F779II.json @@ -875,6 +875,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32F779NI.json b/data/chips/STM32F779NI.json index 2f31454..b0a1583 100644 --- a/data/chips/STM32F779NI.json +++ b/data/chips/STM32F779NI.json @@ -885,6 +885,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071C6.json b/data/chips/STM32G071C6.json index 486f0ab..39946f6 100644 --- a/data/chips/STM32G071C6.json +++ b/data/chips/STM32G071C6.json @@ -145,6 +145,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071C8.json b/data/chips/STM32G071C8.json index b92eee5..7567a99 100644 --- a/data/chips/STM32G071C8.json +++ b/data/chips/STM32G071C8.json @@ -320,6 +320,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071CB.json b/data/chips/STM32G071CB.json index eef0de5..2a060a4 100644 --- a/data/chips/STM32G071CB.json +++ b/data/chips/STM32G071CB.json @@ -320,6 +320,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071EB.json b/data/chips/STM32G071EB.json index ae480a3..f78bd25 100644 --- a/data/chips/STM32G071EB.json +++ b/data/chips/STM32G071EB.json @@ -300,6 +300,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071G6.json b/data/chips/STM32G071G6.json index 5006029..32a01d8 100644 --- a/data/chips/STM32G071G6.json +++ b/data/chips/STM32G071G6.json @@ -125,6 +125,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071G8.json b/data/chips/STM32G071G8.json index 6d4cb66..a64ef17 100644 --- a/data/chips/STM32G071G8.json +++ b/data/chips/STM32G071G8.json @@ -304,6 +304,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071GB.json b/data/chips/STM32G071GB.json index 76e0207..a93b888 100644 --- a/data/chips/STM32G071GB.json +++ b/data/chips/STM32G071GB.json @@ -304,6 +304,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071K6.json b/data/chips/STM32G071K6.json index 4823664..b9030eb 100644 --- a/data/chips/STM32G071K6.json +++ b/data/chips/STM32G071K6.json @@ -133,6 +133,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071K8.json b/data/chips/STM32G071K8.json index e5daf3b..7174eac 100644 --- a/data/chips/STM32G071K8.json +++ b/data/chips/STM32G071K8.json @@ -316,6 +316,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071KB.json b/data/chips/STM32G071KB.json index e224931..6924132 100644 --- a/data/chips/STM32G071KB.json +++ b/data/chips/STM32G071KB.json @@ -316,6 +316,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071R6.json b/data/chips/STM32G071R6.json index dcb7433..068b974 100644 --- a/data/chips/STM32G071R6.json +++ b/data/chips/STM32G071R6.json @@ -149,6 +149,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071R8.json b/data/chips/STM32G071R8.json index 41000c8..96f4ca2 100644 --- a/data/chips/STM32G071R8.json +++ b/data/chips/STM32G071R8.json @@ -324,6 +324,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G071RB.json b/data/chips/STM32G071RB.json index d1ae8ff..7ce8afa 100644 --- a/data/chips/STM32G071RB.json +++ b/data/chips/STM32G071RB.json @@ -328,6 +328,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G081CB.json b/data/chips/STM32G081CB.json index b75a0ed..1244d55 100644 --- a/data/chips/STM32G081CB.json +++ b/data/chips/STM32G081CB.json @@ -359,6 +359,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G081EB.json b/data/chips/STM32G081EB.json index a410b67..aff6578 100644 --- a/data/chips/STM32G081EB.json +++ b/data/chips/STM32G081EB.json @@ -339,6 +339,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G081GB.json b/data/chips/STM32G081GB.json index 2defdd7..27f9df3 100644 --- a/data/chips/STM32G081GB.json +++ b/data/chips/STM32G081GB.json @@ -343,6 +343,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G081KB.json b/data/chips/STM32G081KB.json index bc19221..46b9ef8 100644 --- a/data/chips/STM32G081KB.json +++ b/data/chips/STM32G081KB.json @@ -355,6 +355,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G081RB.json b/data/chips/STM32G081RB.json index df6043f..b4a3da0 100644 --- a/data/chips/STM32G081RB.json +++ b/data/chips/STM32G081RB.json @@ -367,6 +367,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1CB.json b/data/chips/STM32G0B1CB.json index 4c7b3a6..a8462e2 100644 --- a/data/chips/STM32G0B1CB.json +++ b/data/chips/STM32G0B1CB.json @@ -508,6 +508,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1CC.json b/data/chips/STM32G0B1CC.json index 7dcdeb2..8e06fa7 100644 --- a/data/chips/STM32G0B1CC.json +++ b/data/chips/STM32G0B1CC.json @@ -508,6 +508,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1CE.json b/data/chips/STM32G0B1CE.json index e22ba7b..d852994 100644 --- a/data/chips/STM32G0B1CE.json +++ b/data/chips/STM32G0B1CE.json @@ -519,6 +519,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1KB.json b/data/chips/STM32G0B1KB.json index dd7d208..29b0adc 100644 --- a/data/chips/STM32G0B1KB.json +++ b/data/chips/STM32G0B1KB.json @@ -496,6 +496,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1KC.json b/data/chips/STM32G0B1KC.json index 4be1e48..0f512d2 100644 --- a/data/chips/STM32G0B1KC.json +++ b/data/chips/STM32G0B1KC.json @@ -496,6 +496,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1KE.json b/data/chips/STM32G0B1KE.json index c6b7d1b..e9755fa 100644 --- a/data/chips/STM32G0B1KE.json +++ b/data/chips/STM32G0B1KE.json @@ -507,6 +507,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1MB.json b/data/chips/STM32G0B1MB.json index f488c62..952339f 100644 --- a/data/chips/STM32G0B1MB.json +++ b/data/chips/STM32G0B1MB.json @@ -504,6 +504,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1MC.json b/data/chips/STM32G0B1MC.json index 86142b0..0e85fbd 100644 --- a/data/chips/STM32G0B1MC.json +++ b/data/chips/STM32G0B1MC.json @@ -504,6 +504,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1ME.json b/data/chips/STM32G0B1ME.json index e270cfd..fcda554 100644 --- a/data/chips/STM32G0B1ME.json +++ b/data/chips/STM32G0B1ME.json @@ -515,6 +515,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1NE.json b/data/chips/STM32G0B1NE.json index 1949d16..c3c2ae1 100644 --- a/data/chips/STM32G0B1NE.json +++ b/data/chips/STM32G0B1NE.json @@ -160,6 +160,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1RB.json b/data/chips/STM32G0B1RB.json index 7cd432b..c16d211 100644 --- a/data/chips/STM32G0B1RB.json +++ b/data/chips/STM32G0B1RB.json @@ -512,6 +512,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1RC.json b/data/chips/STM32G0B1RC.json index 74f24bf..2b2d31d 100644 --- a/data/chips/STM32G0B1RC.json +++ b/data/chips/STM32G0B1RC.json @@ -512,6 +512,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1RE.json b/data/chips/STM32G0B1RE.json index 89ceb61..26ce16e 100644 --- a/data/chips/STM32G0B1RE.json +++ b/data/chips/STM32G0B1RE.json @@ -523,6 +523,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1VB.json b/data/chips/STM32G0B1VB.json index 01d8904..aebb8ae 100644 --- a/data/chips/STM32G0B1VB.json +++ b/data/chips/STM32G0B1VB.json @@ -508,6 +508,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1VC.json b/data/chips/STM32G0B1VC.json index b1d0755..ca35907 100644 --- a/data/chips/STM32G0B1VC.json +++ b/data/chips/STM32G0B1VC.json @@ -508,6 +508,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0B1VE.json b/data/chips/STM32G0B1VE.json index f5b1f57..9e940da 100644 --- a/data/chips/STM32G0B1VE.json +++ b/data/chips/STM32G0B1VE.json @@ -519,6 +519,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0C1CC.json b/data/chips/STM32G0C1CC.json index eb7f265..8f6f5c8 100644 --- a/data/chips/STM32G0C1CC.json +++ b/data/chips/STM32G0C1CC.json @@ -547,6 +547,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0C1CE.json b/data/chips/STM32G0C1CE.json index c416c2a..56eb9e2 100644 --- a/data/chips/STM32G0C1CE.json +++ b/data/chips/STM32G0C1CE.json @@ -558,6 +558,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0C1KC.json b/data/chips/STM32G0C1KC.json index 566c36e..f4e3bcb 100644 --- a/data/chips/STM32G0C1KC.json +++ b/data/chips/STM32G0C1KC.json @@ -535,6 +535,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0C1KE.json b/data/chips/STM32G0C1KE.json index 849f120..cada766 100644 --- a/data/chips/STM32G0C1KE.json +++ b/data/chips/STM32G0C1KE.json @@ -546,6 +546,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0C1MC.json b/data/chips/STM32G0C1MC.json index 1d09623..57c5170 100644 --- a/data/chips/STM32G0C1MC.json +++ b/data/chips/STM32G0C1MC.json @@ -543,6 +543,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0C1ME.json b/data/chips/STM32G0C1ME.json index a4e25c8..4df1836 100644 --- a/data/chips/STM32G0C1ME.json +++ b/data/chips/STM32G0C1ME.json @@ -554,6 +554,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0C1NE.json b/data/chips/STM32G0C1NE.json index d289ede..c97aed4 100644 --- a/data/chips/STM32G0C1NE.json +++ b/data/chips/STM32G0C1NE.json @@ -199,6 +199,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0C1RC.json b/data/chips/STM32G0C1RC.json index da6c50b..05db5be 100644 --- a/data/chips/STM32G0C1RC.json +++ b/data/chips/STM32G0C1RC.json @@ -551,6 +551,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0C1RE.json b/data/chips/STM32G0C1RE.json index 09559f4..7a30435 100644 --- a/data/chips/STM32G0C1RE.json +++ b/data/chips/STM32G0C1RE.json @@ -562,6 +562,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0C1VC.json b/data/chips/STM32G0C1VC.json index 26547d6..5e614fd 100644 --- a/data/chips/STM32G0C1VC.json +++ b/data/chips/STM32G0C1VC.json @@ -547,6 +547,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32G0C1VE.json b/data/chips/STM32G0C1VE.json index d34cf4a..b3fbf70 100644 --- a/data/chips/STM32G0C1VE.json +++ b/data/chips/STM32G0C1VE.json @@ -558,6 +558,11 @@ { "name": "CEC", "address": 1073772544, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index e5712ec..f6b2fa9 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -346,6 +346,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index 42fade0..75d06df 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -357,6 +357,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index f56a7b4..1015bb3 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -350,6 +350,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index 4d74d1f..ef2bc2d 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -361,6 +361,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index b558bdd..5862ab9 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -326,6 +326,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index 02d6854..24401d5 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -337,6 +337,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index 6c1cfcb..85163cc 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -322,6 +322,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index c13369b..976ba26 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -333,6 +333,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index e21806c..d94a126 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -346,6 +346,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index b22971e..0957775 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -357,6 +357,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index a8b2bfa..ed869d5 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -346,6 +346,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index 226b61b..1b06a08 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -361,6 +361,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index c4250ea..51c7770 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -350,6 +350,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index 5331028..064c7a2 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -369,6 +369,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index bf6ac83..78d2206 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -333,6 +333,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index 0f75b33..76e9c7a 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -326,6 +326,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index 623af5b..731c14f 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -337,6 +337,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index 73745b2..de79e8d 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -322,6 +322,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index 7963b94..7ca7079 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -337,6 +337,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index 596e651..dcb3afc 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -346,6 +346,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index cdf1157..b15783e 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -361,6 +361,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index e06ceb4..3e52c53 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -405,6 +405,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index 50cbca8..b331d31 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -413,6 +413,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index 4099acf..928fc19 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -377,6 +377,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index 1e86143..7ae974f 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -381,6 +381,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index 16e08e5..9e182f1 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -381,6 +381,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index 0f8d754..cadd4bf 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -405,6 +405,11 @@ { "name": "CEC", "address": 1073770496, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H723VE.json b/data/chips/STM32H723VE.json index 986abb3..aef4eb0 100644 --- a/data/chips/STM32H723VE.json +++ b/data/chips/STM32H723VE.json @@ -697,6 +697,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H723VG.json b/data/chips/STM32H723VG.json index 0214a63..bd335dd 100644 --- a/data/chips/STM32H723VG.json +++ b/data/chips/STM32H723VG.json @@ -697,6 +697,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H723ZE.json b/data/chips/STM32H723ZE.json index 7554c97..29cf5e3 100644 --- a/data/chips/STM32H723ZE.json +++ b/data/chips/STM32H723ZE.json @@ -809,6 +809,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H723ZG.json b/data/chips/STM32H723ZG.json index 95f629f..b08aa1b 100644 --- a/data/chips/STM32H723ZG.json +++ b/data/chips/STM32H723ZG.json @@ -809,6 +809,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H725AE.json b/data/chips/STM32H725AE.json index 98f90a1..3732f67 100644 --- a/data/chips/STM32H725AE.json +++ b/data/chips/STM32H725AE.json @@ -835,6 +835,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H725AG.json b/data/chips/STM32H725AG.json index a26b1c6..8993cb1 100644 --- a/data/chips/STM32H725AG.json +++ b/data/chips/STM32H725AG.json @@ -841,6 +841,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H725IE.json b/data/chips/STM32H725IE.json index 79a6308..7190ed7 100644 --- a/data/chips/STM32H725IE.json +++ b/data/chips/STM32H725IE.json @@ -855,6 +855,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H725IG.json b/data/chips/STM32H725IG.json index 45205ee..d6d6497 100644 --- a/data/chips/STM32H725IG.json +++ b/data/chips/STM32H725IG.json @@ -861,6 +861,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H725RE.json b/data/chips/STM32H725RE.json index 40b6364..6ca12ca 100644 --- a/data/chips/STM32H725RE.json +++ b/data/chips/STM32H725RE.json @@ -675,6 +675,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H725RG.json b/data/chips/STM32H725RG.json index 81a9a54..46fc031 100644 --- a/data/chips/STM32H725RG.json +++ b/data/chips/STM32H725RG.json @@ -681,6 +681,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H725VE.json b/data/chips/STM32H725VE.json index f41cc71..518aa8e 100644 --- a/data/chips/STM32H725VE.json +++ b/data/chips/STM32H725VE.json @@ -691,6 +691,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H725VG.json b/data/chips/STM32H725VG.json index b043995..97c4bd1 100644 --- a/data/chips/STM32H725VG.json +++ b/data/chips/STM32H725VG.json @@ -701,6 +701,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H725ZE.json b/data/chips/STM32H725ZE.json index a5f42e3..d83ca93 100644 --- a/data/chips/STM32H725ZE.json +++ b/data/chips/STM32H725ZE.json @@ -731,6 +731,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H725ZG.json b/data/chips/STM32H725ZG.json index 6ad4459..2fa438d 100644 --- a/data/chips/STM32H725ZG.json +++ b/data/chips/STM32H725ZG.json @@ -737,6 +737,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index a774c41..00b29cf 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -853,6 +853,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index 3c91928..ec82381 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -873,6 +873,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index 1cb849a..bade632 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -709,6 +709,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index 40aec1a..4a54be6 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -821,6 +821,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index 16c767b..e8e0326 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -709,6 +709,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index 5fbbd0e..38c4807 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -821,6 +821,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index 646e59a..88de682 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -853,6 +853,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index 86f1e77..cd7f8ca 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -873,6 +873,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H735RG.json b/data/chips/STM32H735RG.json index 243ea88..4091bd2 100644 --- a/data/chips/STM32H735RG.json +++ b/data/chips/STM32H735RG.json @@ -693,6 +693,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index 1b71245..ac4bfab 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -713,6 +713,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index 3b6f79d..f4ca46e 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -749,6 +749,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742AG.json b/data/chips/STM32H742AG.json index 9a55637..c1bb126 100644 --- a/data/chips/STM32H742AG.json +++ b/data/chips/STM32H742AG.json @@ -811,6 +811,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742AI.json b/data/chips/STM32H742AI.json index d6ab9bb..7c24d36 100644 --- a/data/chips/STM32H742AI.json +++ b/data/chips/STM32H742AI.json @@ -822,6 +822,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742BG.json b/data/chips/STM32H742BG.json index d23aeb4..e22f857 100644 --- a/data/chips/STM32H742BG.json +++ b/data/chips/STM32H742BG.json @@ -811,6 +811,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742BI.json b/data/chips/STM32H742BI.json index a8aa8ce..2995342 100644 --- a/data/chips/STM32H742BI.json +++ b/data/chips/STM32H742BI.json @@ -822,6 +822,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742IG.json b/data/chips/STM32H742IG.json index 59aa221..444b85a 100644 --- a/data/chips/STM32H742IG.json +++ b/data/chips/STM32H742IG.json @@ -815,6 +815,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742II.json b/data/chips/STM32H742II.json index 1b1c0d4..9b1fc08 100644 --- a/data/chips/STM32H742II.json +++ b/data/chips/STM32H742II.json @@ -826,6 +826,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742VG.json b/data/chips/STM32H742VG.json index 2120427..192fba3 100644 --- a/data/chips/STM32H742VG.json +++ b/data/chips/STM32H742VG.json @@ -715,6 +715,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742VI.json b/data/chips/STM32H742VI.json index 31456e5..ee9a1c9 100644 --- a/data/chips/STM32H742VI.json +++ b/data/chips/STM32H742VI.json @@ -726,6 +726,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742XG.json b/data/chips/STM32H742XG.json index a666be1..e7d0431 100644 --- a/data/chips/STM32H742XG.json +++ b/data/chips/STM32H742XG.json @@ -875,6 +875,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742XI.json b/data/chips/STM32H742XI.json index 72607a8..8492982 100644 --- a/data/chips/STM32H742XI.json +++ b/data/chips/STM32H742XI.json @@ -886,6 +886,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742ZG.json b/data/chips/STM32H742ZG.json index 2b8e44e..1dae99f 100644 --- a/data/chips/STM32H742ZG.json +++ b/data/chips/STM32H742ZG.json @@ -783,6 +783,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H742ZI.json b/data/chips/STM32H742ZI.json index 540452e..7d75eb8 100644 --- a/data/chips/STM32H742ZI.json +++ b/data/chips/STM32H742ZI.json @@ -794,6 +794,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743AG.json b/data/chips/STM32H743AG.json index 94137e3..00d6909 100644 --- a/data/chips/STM32H743AG.json +++ b/data/chips/STM32H743AG.json @@ -853,6 +853,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743AI.json b/data/chips/STM32H743AI.json index 3a28649..7ad25b8 100644 --- a/data/chips/STM32H743AI.json +++ b/data/chips/STM32H743AI.json @@ -864,6 +864,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743BG.json b/data/chips/STM32H743BG.json index a879de0..5c96a4f 100644 --- a/data/chips/STM32H743BG.json +++ b/data/chips/STM32H743BG.json @@ -853,6 +853,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743BI.json b/data/chips/STM32H743BI.json index 2e4a749..e42392d 100644 --- a/data/chips/STM32H743BI.json +++ b/data/chips/STM32H743BI.json @@ -864,6 +864,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743IG.json b/data/chips/STM32H743IG.json index d30c78f..b64e8f3 100644 --- a/data/chips/STM32H743IG.json +++ b/data/chips/STM32H743IG.json @@ -857,6 +857,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743II.json b/data/chips/STM32H743II.json index c1d49e3..b836eb6 100644 --- a/data/chips/STM32H743II.json +++ b/data/chips/STM32H743II.json @@ -868,6 +868,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743VG.json b/data/chips/STM32H743VG.json index 13df3a6..061b105 100644 --- a/data/chips/STM32H743VG.json +++ b/data/chips/STM32H743VG.json @@ -757,6 +757,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743VI.json b/data/chips/STM32H743VI.json index 99f9501..6efe6d5 100644 --- a/data/chips/STM32H743VI.json +++ b/data/chips/STM32H743VI.json @@ -768,6 +768,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743XG.json b/data/chips/STM32H743XG.json index 0beb3d6..7f9ac0a 100644 --- a/data/chips/STM32H743XG.json +++ b/data/chips/STM32H743XG.json @@ -917,6 +917,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743XI.json b/data/chips/STM32H743XI.json index e3a1807..daa2c67 100644 --- a/data/chips/STM32H743XI.json +++ b/data/chips/STM32H743XI.json @@ -928,6 +928,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743ZG.json b/data/chips/STM32H743ZG.json index cb4a58c..1da407e 100644 --- a/data/chips/STM32H743ZG.json +++ b/data/chips/STM32H743ZG.json @@ -825,6 +825,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H743ZI.json b/data/chips/STM32H743ZI.json index 587dc35..d377825 100644 --- a/data/chips/STM32H743ZI.json +++ b/data/chips/STM32H743ZI.json @@ -836,6 +836,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H745BG.json b/data/chips/STM32H745BG.json index d01321a..fc0b545 100644 --- a/data/chips/STM32H745BG.json +++ b/data/chips/STM32H745BG.json @@ -835,6 +835,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10633,6 +10638,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H745BI.json b/data/chips/STM32H745BI.json index 6b7b2c9..2043707 100644 --- a/data/chips/STM32H745BI.json +++ b/data/chips/STM32H745BI.json @@ -846,6 +846,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10644,6 +10649,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H745IG.json b/data/chips/STM32H745IG.json index da802f3..d61c752 100644 --- a/data/chips/STM32H745IG.json +++ b/data/chips/STM32H745IG.json @@ -903,6 +903,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10443,6 +10448,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H745II.json b/data/chips/STM32H745II.json index 1872c6a..758caf4 100644 --- a/data/chips/STM32H745II.json +++ b/data/chips/STM32H745II.json @@ -914,6 +914,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10454,6 +10459,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H745XG.json b/data/chips/STM32H745XG.json index 9a045b9..0d15bbf 100644 --- a/data/chips/STM32H745XG.json +++ b/data/chips/STM32H745XG.json @@ -899,6 +899,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10866,6 +10871,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H745XI.json b/data/chips/STM32H745XI.json index 8e86422..2924060 100644 --- a/data/chips/STM32H745XI.json +++ b/data/chips/STM32H745XI.json @@ -910,6 +910,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10877,6 +10882,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H745ZG.json b/data/chips/STM32H745ZG.json index f82195e..e0e04c0 100644 --- a/data/chips/STM32H745ZG.json +++ b/data/chips/STM32H745ZG.json @@ -775,6 +775,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -9508,6 +9513,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H745ZI.json b/data/chips/STM32H745ZI.json index be03630..74a0b6f 100644 --- a/data/chips/STM32H745ZI.json +++ b/data/chips/STM32H745ZI.json @@ -786,6 +786,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -9519,6 +9524,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index e464638..333560f 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -813,6 +813,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -9765,6 +9770,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index 10f16b9..9e64bbf 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -824,6 +824,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -9776,6 +9781,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index 84f23e9..7510134 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -841,6 +841,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10468,6 +10473,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index 36d7440..007b8b8 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -852,6 +852,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10479,6 +10484,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index 09473ea..91cfc7f 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -813,6 +813,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -9765,6 +9770,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index 5340956..8edfea3 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -824,6 +824,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -9776,6 +9781,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index 88f6309..83583e0 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -905,6 +905,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10876,6 +10881,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index 37f6ec9..fed57a0 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -916,6 +916,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10887,6 +10892,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index 7cb92aa..80f15f9 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -792,6 +792,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -9201,6 +9206,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H750IB.json b/data/chips/STM32H750IB.json index cadbb2b..f72d9e6 100644 --- a/data/chips/STM32H750IB.json +++ b/data/chips/STM32H750IB.json @@ -845,6 +845,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H750VB.json b/data/chips/STM32H750VB.json index 99e5382..b99c125 100644 --- a/data/chips/STM32H750VB.json +++ b/data/chips/STM32H750VB.json @@ -741,6 +741,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H750XB.json b/data/chips/STM32H750XB.json index a9887d1..804a125 100644 --- a/data/chips/STM32H750XB.json +++ b/data/chips/STM32H750XB.json @@ -905,6 +905,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H750ZB.json b/data/chips/STM32H750ZB.json index b9b0628..912e101 100644 --- a/data/chips/STM32H750ZB.json +++ b/data/chips/STM32H750ZB.json @@ -801,6 +801,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H753AI.json b/data/chips/STM32H753AI.json index 1e2c673..f7e00e9 100644 --- a/data/chips/STM32H753AI.json +++ b/data/chips/STM32H753AI.json @@ -870,6 +870,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H753BI.json b/data/chips/STM32H753BI.json index d6fecbc..30ce1e8 100644 --- a/data/chips/STM32H753BI.json +++ b/data/chips/STM32H753BI.json @@ -870,6 +870,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H753II.json b/data/chips/STM32H753II.json index 69c32f8..519793b 100644 --- a/data/chips/STM32H753II.json +++ b/data/chips/STM32H753II.json @@ -874,6 +874,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H753VI.json b/data/chips/STM32H753VI.json index 1cb935b..fdc7f72 100644 --- a/data/chips/STM32H753VI.json +++ b/data/chips/STM32H753VI.json @@ -774,6 +774,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H753XI.json b/data/chips/STM32H753XI.json index 67f0845..e92903a 100644 --- a/data/chips/STM32H753XI.json +++ b/data/chips/STM32H753XI.json @@ -934,6 +934,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H753ZI.json b/data/chips/STM32H753ZI.json index 33bc0a0..9ea3c33 100644 --- a/data/chips/STM32H753ZI.json +++ b/data/chips/STM32H753ZI.json @@ -842,6 +842,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index 6084b01..fcb021f 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -852,6 +852,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10715,6 +10720,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index d4c258d..077d868 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -920,6 +920,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10525,6 +10530,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index 234ea37..fcb970d 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -916,6 +916,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10948,6 +10953,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index 7cf0cb2..2dda677 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -792,6 +792,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -9590,6 +9595,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index a9f89e2..3d10d65 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -830,6 +830,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -9847,6 +9852,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index fd3579f..d7a1566 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -858,6 +858,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10550,6 +10555,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 717e943..a28ebec 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -830,6 +830,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -9847,6 +9852,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 6515bab..4ea7a37 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -922,6 +922,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -10958,6 +10963,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index c41cb96..8681c4c 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -798,6 +798,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -9272,6 +9277,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index 0a7a554..8750e9e 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -718,6 +718,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index c9b2749..b05c0b2 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -729,6 +729,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index ce33cb1..11a1bfd 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -730,6 +730,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index 83be68c..92fba73 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -741,6 +741,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index 1603813..073a9ff 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -712,6 +712,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index eda1315..4240d65 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -729,6 +729,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index bc2443e..52f1a7f 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -674,6 +674,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index 758cb6d..d7724db 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -685,6 +685,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index 060c328..6c29c0c 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -689,6 +689,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3RG.json b/data/chips/STM32H7A3RG.json index 6d6060b..32eff0a 100644 --- a/data/chips/STM32H7A3RG.json +++ b/data/chips/STM32H7A3RG.json @@ -670,6 +670,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3RI.json b/data/chips/STM32H7A3RI.json index e5de603..4ed46c0 100644 --- a/data/chips/STM32H7A3RI.json +++ b/data/chips/STM32H7A3RI.json @@ -681,6 +681,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index 4b45342..b59dc23 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -662,6 +662,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index ebba1a6..96b0bf3 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -673,6 +673,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index 9da3d10..90c5074 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -678,6 +678,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index b837a1b..8c28f75 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -689,6 +689,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index 662610d..29630b9 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -724,6 +724,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index a8f092e..866a999 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -728,6 +728,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index 5c3059d..afced08 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -676,6 +676,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index 1507f82..acc5bae 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -656,6 +656,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index a40f08a..6b632af 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -680,6 +680,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index dd8fa22..4a188c0 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -741,6 +741,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index 836e51e..76d5d05 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -753,6 +753,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index 56a72af..3d4c585 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -741,6 +741,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index b1cf27c..d81b669 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -697,6 +697,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index cb72029..71f45c6 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -701,6 +701,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 8c5055c..79840f0 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -693,6 +693,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index a4751d1..295f2ab 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -685,6 +685,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index 1bdb9b1..4f4dffb 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -701,6 +701,11 @@ { "name": "CEC", "address": 1073769472, + "registers": { + "kind": "cec", + "version": "v2", + "block": "CEC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { diff --git a/data/registers/cec_v1.json b/data/registers/cec_v1.json new file mode 100644 index 0000000..9a91b90 --- /dev/null +++ b/data/registers/cec_v1.json @@ -0,0 +1,224 @@ +{ + "block/CEC": { + "description": "HDMI-CEC controller.", + "items": [ + { + "name": "CFGR", + "description": "configuration register.", + "byte_offset": 0, + "fieldset": "CFGR" + }, + { + "name": "OAR", + "description": "CEC own address register.", + "byte_offset": 4, + "fieldset": "OAR" + }, + { + "name": "PRES", + "description": "Rx Data Register.", + "byte_offset": 8, + "fieldset": "PRES" + }, + { + "name": "ESR", + "description": "CEC error status register.", + "byte_offset": 12, + "access": "Read", + "fieldset": "ESR" + }, + { + "name": "CSR", + "description": "CEC control and status register.", + "byte_offset": 16, + "fieldset": "CSR" + }, + { + "name": "TXD", + "description": "CEC Tx data register.", + "byte_offset": 20, + "fieldset": "TXD" + }, + { + "name": "RXD", + "description": "CEC Rx data register.", + "byte_offset": 24, + "access": "Read", + "fieldset": "RXD" + } + ] + }, + "fieldset/CFGR": { + "description": "configuration register.", + "fields": [ + { + "name": "PE", + "description": "Peripheral enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "IE", + "description": "Interrupt enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BTEM", + "description": "Bit timing error mode.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BPEM", + "description": "Bit period error mode.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/CSR": { + "description": "CEC control and status register.", + "fields": [ + { + "name": "TSOM", + "description": "Tx start of message.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TEOM", + "description": "Tx end of message.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "TERR", + "description": "Tx error.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "TBTRF", + "description": "Tx byte transfer request or block transfer finished.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "RSOM", + "description": "Rx start of message.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "REOM", + "description": "Rx end of message.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "RERR", + "description": "Rx error.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "RBTF", + "description": "Rx byte/block transfer finished.", + "bit_offset": 7, + "bit_size": 1 + } + ] + }, + "fieldset/ESR": { + "description": "CEC error status register.", + "fields": [ + { + "name": "BTE", + "description": "Bit timing error.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BPE", + "description": "Bit period error.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "RBTFE", + "description": "Rx block transfer finished error.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "SBE", + "description": "Start bit error.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ACKE", + "description": "Block acknowledge error.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "LINE", + "description": "Line error.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "TBTFE", + "description": "Tx block transfer finished error.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/OAR": { + "description": "CEC own address register.", + "fields": [ + { + "name": "OA", + "description": "Own address.", + "bit_offset": 0, + "bit_size": 4 + } + ] + }, + "fieldset/PRES": { + "description": "Rx Data Register.", + "fields": [ + { + "name": "PRESC", + "description": "CEC Rx Data Register.", + "bit_offset": 0, + "bit_size": 14 + } + ] + }, + "fieldset/RXD": { + "description": "CEC Rx data register.", + "fields": [ + { + "name": "RXD", + "description": "Rx data.", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "fieldset/TXD": { + "description": "CEC Tx data register.", + "fields": [ + { + "name": "TXD", + "description": "Tx Data register.", + "bit_offset": 0, + "bit_size": 8 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/cec_v2.json b/data/registers/cec_v2.json new file mode 100644 index 0000000..c2efa05 --- /dev/null +++ b/data/registers/cec_v2.json @@ -0,0 +1,315 @@ +{ + "block/CEC": { + "description": "CEC.", + "items": [ + { + "name": "CR", + "description": "CEC control register.", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "CFGR", + "description": "This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.", + "byte_offset": 4, + "fieldset": "CFGR" + }, + { + "name": "TXDR", + "description": "CEC Tx data register.", + "byte_offset": 8, + "access": "Write", + "fieldset": "TXDR" + }, + { + "name": "RXDR", + "description": "CEC Rx Data Register.", + "byte_offset": 12, + "access": "Read", + "fieldset": "RXDR" + }, + { + "name": "ISR", + "description": "CEC Interrupt and Status Register.", + "byte_offset": 16, + "fieldset": "ISR" + }, + { + "name": "IER", + "description": "CEC interrupt enable register.", + "byte_offset": 20, + "fieldset": "IER" + } + ] + }, + "fieldset/CFGR": { + "description": "This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.", + "fields": [ + { + "name": "SFT", + "description": "Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods.", + "bit_offset": 0, + "bit_size": 3 + }, + { + "name": "RXTOL", + "description": "Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "BRESTP", + "description": "Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "BREGEN", + "description": "Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LBPEGEN", + "description": "Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "BRDNOGEN", + "description": "Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SFTOPT", + "description": "SFT Option Bit The SFTOPT bit is set and cleared by software.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "OAR", + "description": "Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received.", + "bit_offset": 16, + "bit_size": 15 + }, + { + "name": "LSTN", + "description": "Listen mode LSTN bit is set and cleared by software.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/CR": { + "description": "CEC control register.", + "fields": [ + { + "name": "CECEN", + "description": "CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TXSOM", + "description": "Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "TXEOM", + "description": "Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message).", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "CEC interrupt enable register.", + "fields": [ + { + "name": "RXBRIE", + "description": "Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "RXENDIE", + "description": "End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "RXOVRIE", + "description": "Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BREIE", + "description": "Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "SBPEIE", + "description": "Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "LBPEIE", + "description": "Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "RXACKIE", + "description": "Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ARBLSTIE", + "description": "Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "TXBRIE", + "description": "Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "TXENDIE", + "description": "Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "TXUDRIE", + "description": "Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "TXERRIE", + "description": "Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "TXACKIE", + "description": "Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "CEC Interrupt and Status Register.", + "fields": [ + { + "name": "RXBR", + "description": "Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "RXEND", + "description": "End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "RXOVR", + "description": "Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BRE", + "description": "Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "SBPE", + "description": "Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "LBPE", + "description": "Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "RXACKE", + "description": "Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ARBLST", + "description": "Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "TXBR", + "description": "Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "TXEND", + "description": "End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "TXUDR", + "description": "Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "TXERR", + "description": "Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "TXACKE", + "description": "Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/RXDR": { + "description": "CEC Rx Data Register.", + "fields": [ + { + "name": "RXD", + "description": "Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line.", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "fieldset/TXDR": { + "description": "CEC Tx data register.", + "fields": [ + { + "name": "TXD", + "description": "Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1.", + "bit_offset": 0, + "bit_size": 8 + } + ] + } +} \ No newline at end of file