block/PCNT:
  description: Pulse Count Controller.
  items:
  - name: U_CONF0
    array:
      len: 8
      stride: 12
    byte_offset: 0
    fieldset: U_CONF0
  - name: U_CONF1
    array:
      len: 8
      stride: 12
    byte_offset: 4
    fieldset: U_CONF1
  - name: U_CONF2
    array:
      len: 8
      stride: 12
    byte_offset: 8
    fieldset: U_CONF2
  - name: U_CNT
    array:
      len: 8
      stride: 4
    byte_offset: 96
    fieldset: U_CNT
  - name: INT_RAW
    byte_offset: 128
    fieldset: INT_RAW
  - name: INT_ST
    byte_offset: 132
    fieldset: INT_ST
  - name: INT_ENA
    byte_offset: 136
    fieldset: INT_ENA
  - name: INT_CLR
    byte_offset: 140
    fieldset: INT_CLR
  - name: U_STATUS
    array:
      len: 8
      stride: 4
    byte_offset: 144
    fieldset: U_STATUS
  - name: CTRL
    byte_offset: 176
    fieldset: CTRL
  - name: DATE
    byte_offset: 252
    fieldset: DATE
fieldset/CTRL:
  fields:
  - name: CNT_RST_U0
    description: Set this bit to clear unit0's counter.
    bit_offset: 0
    bit_size: 1
  - name: CNT_PAUSE_U0
    description: Set this bit to pause unit0's counter.
    bit_offset: 1
    bit_size: 1
  - name: CNT_RST_U1
    description: Set this bit to clear unit1's counter.
    bit_offset: 2
    bit_size: 1
  - name: CNT_PAUSE_U1
    description: Set this bit to pause unit1's counter.
    bit_offset: 3
    bit_size: 1
  - name: CNT_RST_U2
    description: Set this bit to clear unit2's counter.
    bit_offset: 4
    bit_size: 1
  - name: CNT_PAUSE_U2
    description: Set this bit to pause unit2's counter.
    bit_offset: 5
    bit_size: 1
  - name: CNT_RST_U3
    description: Set this bit to clear unit3's counter.
    bit_offset: 6
    bit_size: 1
  - name: CNT_PAUSE_U3
    description: Set this bit to pause unit3's counter.
    bit_offset: 7
    bit_size: 1
  - name: CNT_RST_U4
    description: Set this bit to clear unit4's counter.
    bit_offset: 8
    bit_size: 1
  - name: CNT_PAUSE_U4
    description: Set this bit to pause unit4's counter.
    bit_offset: 9
    bit_size: 1
  - name: CNT_RST_U5
    description: Set this bit to clear unit5's counter.
    bit_offset: 10
    bit_size: 1
  - name: CNT_PAUSE_U5
    description: Set this bit to pause unit5's counter.
    bit_offset: 11
    bit_size: 1
  - name: CNT_RST_U6
    description: Set this bit to clear unit6's counter.
    bit_offset: 12
    bit_size: 1
  - name: CNT_PAUSE_U6
    description: Set this bit to pause unit6's counter.
    bit_offset: 13
    bit_size: 1
  - name: CNT_RST_U7
    description: Set this bit to clear unit7's counter.
    bit_offset: 14
    bit_size: 1
  - name: CNT_PAUSE_U7
    description: Set this bit to pause unit7's counter.
    bit_offset: 15
    bit_size: 1
  - name: CLK_EN
    bit_offset: 16
    bit_size: 1
fieldset/DATE:
  fields:
  - name: DATE
    bit_offset: 0
    bit_size: 32
fieldset/INT_CLR:
  fields:
  - name: CNT_THR_EVENT_U0
    description: Set this bit to clear channel0 event interrupt.
    bit_offset: 0
    bit_size: 1
  - name: CNT_THR_EVENT_U1
    description: Set this bit to clear channel1 event interrupt.
    bit_offset: 1
    bit_size: 1
  - name: CNT_THR_EVENT_U2
    description: Set this bit to clear channel2 event interrupt.
    bit_offset: 2
    bit_size: 1
  - name: CNT_THR_EVENT_U3
    description: Set this bit to clear channel3 event interrupt.
    bit_offset: 3
    bit_size: 1
  - name: CNT_THR_EVENT_U4
    description: Set this bit to clear channel4 event interrupt.
    bit_offset: 4
    bit_size: 1
  - name: CNT_THR_EVENT_U5
    description: Set this bit to clear channel5 event interrupt.
    bit_offset: 5
    bit_size: 1
  - name: CNT_THR_EVENT_U6
    description: Set this bit to clear channel6 event interrupt.
    bit_offset: 6
    bit_size: 1
  - name: CNT_THR_EVENT_U7
    description: Set this bit to clear channel7 event interrupt.
    bit_offset: 7
    bit_size: 1
fieldset/INT_ENA:
  fields:
  - name: CNT_THR_EVENT_U0
    description: This is the interrupt enable bit for channel0 event.
    bit_offset: 0
    bit_size: 1
  - name: CNT_THR_EVENT_U1
    description: This is the interrupt enable bit for channel1 event.
    bit_offset: 1
    bit_size: 1
  - name: CNT_THR_EVENT_U2
    description: This is the interrupt enable bit for channel2 event.
    bit_offset: 2
    bit_size: 1
  - name: CNT_THR_EVENT_U3
    description: This is the interrupt enable bit for channel3 event.
    bit_offset: 3
    bit_size: 1
  - name: CNT_THR_EVENT_U4
    description: This is the interrupt enable bit for channel4 event.
    bit_offset: 4
    bit_size: 1
  - name: CNT_THR_EVENT_U5
    description: This is the interrupt enable bit for channel5 event.
    bit_offset: 5
    bit_size: 1
  - name: CNT_THR_EVENT_U6
    description: This is the interrupt enable bit for channel6 event.
    bit_offset: 6
    bit_size: 1
  - name: CNT_THR_EVENT_U7
    description: This is the interrupt enable bit for channel7 event.
    bit_offset: 7
    bit_size: 1
fieldset/INT_RAW:
  fields:
  - name: CNT_THR_EVENT_U0
    description: This is the interrupt raw bit for channel0 event.
    bit_offset: 0
    bit_size: 1
  - name: CNT_THR_EVENT_U1
    description: This is the interrupt raw bit for channel1 event.
    bit_offset: 1
    bit_size: 1
  - name: CNT_THR_EVENT_U2
    description: This is the interrupt raw bit for channel2 event.
    bit_offset: 2
    bit_size: 1
  - name: CNT_THR_EVENT_U3
    description: This is the interrupt raw bit for channel3 event.
    bit_offset: 3
    bit_size: 1
  - name: CNT_THR_EVENT_U4
    description: This is the interrupt raw bit for channel4 event.
    bit_offset: 4
    bit_size: 1
  - name: CNT_THR_EVENT_U5
    description: This is the interrupt raw bit for channel5 event.
    bit_offset: 5
    bit_size: 1
  - name: CNT_THR_EVENT_U6
    description: This is the interrupt raw bit for channel6 event.
    bit_offset: 6
    bit_size: 1
  - name: CNT_THR_EVENT_U7
    description: This is the interrupt raw bit for channel7 event.
    bit_offset: 7
    bit_size: 1
fieldset/INT_ST:
  fields:
  - name: CNT_THR_EVENT_U0
    description: This is the interrupt status bit for channel0 event.
    bit_offset: 0
    bit_size: 1
  - name: CNT_THR_EVENT_U1
    description: This is the interrupt status bit for channel1 event.
    bit_offset: 1
    bit_size: 1
  - name: CNT_THR_EVENT_U2
    description: This is the interrupt status bit for channel2 event.
    bit_offset: 2
    bit_size: 1
  - name: CNT_THR_EVENT_U3
    description: This is the interrupt status bit for channel3 event.
    bit_offset: 3
    bit_size: 1
  - name: CNT_THR_EVENT_U4
    description: This is the interrupt status bit for channel4 event.
    bit_offset: 4
    bit_size: 1
  - name: CNT_THR_EVENT_U5
    description: This is the interrupt status bit for channel5 event.
    bit_offset: 5
    bit_size: 1
  - name: CNT_THR_EVENT_U6
    description: This is the interrupt status bit for channel6 event.
    bit_offset: 6
    bit_size: 1
  - name: CNT_THR_EVENT_U7
    description: This is the interrupt status bit for channel7 event.
    bit_offset: 7
    bit_size: 1
fieldset/U_CNT:
  fields:
  - name: CNT
    description: This register stores the current pulse count value for unit0.
    bit_offset: 0
    bit_size: 16
fieldset/U_CONF0:
  fields:
  - name: FILTER_THRES
    description: This register is used to filter pluse whose width is smaller than this value for unit0.
    bit_offset: 0
    bit_size: 10
  - name: FILTER_EN
    description: This is the enable bit for filtering input signals for unit0.
    bit_offset: 10
    bit_size: 1
  - name: THR_ZERO_EN
    description: This is the enable bit for comparing unit0's count with 0 value.
    bit_offset: 11
    bit_size: 1
  - name: THR_H_LIM_EN
    description: This is the enable bit for comparing unit0's count with thr_h_lim value.
    bit_offset: 12
    bit_size: 1
  - name: THR_L_LIM_EN
    description: This is the enable bit for comparing unit0's count with thr_l_lim value.
    bit_offset: 13
    bit_size: 1
  - name: THR_THRES0_EN
    description: This is the enable bit for comparing unit0's count with thres0 value.
    bit_offset: 14
    bit_size: 1
  - name: THR_THRES1_EN
    description: This is the enable bit for comparing unit0's count with thres1 value.
    bit_offset: 15
    bit_size: 1
  - name: CH0_NEG_MODE
    description: 'This register is used to control the mode of channel0''s input negedge signal for unit0. 2''d1: increase at the negedge of input signal 2''d2:decrease at the negedge of input signal others:forbidden.'
    bit_offset: 16
    bit_size: 2
  - name: CH0_POS_MODE
    description: 'This register is used to control the mode of channel0''s input posedge signal for unit0. 2''d1: increase at the posedge of input signal 2''d2:decrease at the posedge of input signal others:forbidden.'
    bit_offset: 18
    bit_size: 2
  - name: CH0_HCTRL_MODE
    description: 'This register is used to control the mode of channel0''s high control signal for unit0. 2''d0:increase when control signal is low 2''d1: decrease when control signal is high others:forbidden.'
    bit_offset: 20
    bit_size: 2
  - name: CH0_LCTRL_MODE
    description: 'This register is used to control the mode of channel0''s low control signal for unit0. 2''d0:increase when control signal is low 2''d1: decrease when control signal is high others:forbidden.'
    bit_offset: 22
    bit_size: 2
  - name: CH1_NEG_MODE
    description: 'This register is used to control the mode of channel1''s input negedge signal for unit0. 2''d1: increase at the negedge of input signal 2''d2:decrease at the negedge of input signal others:forbidden.'
    bit_offset: 24
    bit_size: 2
  - name: CH1_POS_MODE
    description: 'This register is used to control the mode of channel1''s input posedge signal for unit0. 2''d1: increase at the posedge of input signal 2''d2:decrease at the posedge of input signal others:forbidden.'
    bit_offset: 26
    bit_size: 2
  - name: CH1_HCTRL_MODE
    description: 'This register is used to control the mode of channel1''s high control signal for unit0. 2''d0:increase when control signal is low 2''d1: decrease when control signal is high others:forbidden.'
    bit_offset: 28
    bit_size: 2
  - name: CH1_LCTRL_MODE
    description: 'This register is used to control the mode of channel1''s low control signal for unit0. 2''d0:increase when control signal is low 2''d1: decrease when control signal is high others:forbidden.'
    bit_offset: 30
    bit_size: 2
fieldset/U_CONF1:
  fields:
  - name: CNT_THRES0
    description: This register is used to configure thres0 value for unit0.
    bit_offset: 0
    bit_size: 16
  - name: CNT_THRES1
    description: This register is used to configure thres1 value for unit0.
    bit_offset: 16
    bit_size: 16
fieldset/U_CONF2:
  fields:
  - name: CNT_H_LIM
    description: This register is used to configure thr_h_lim value for unit0.
    bit_offset: 0
    bit_size: 16
  - name: CNT_L_LIM
    description: This register is used to confiugre thr_l_lim value for unit0.
    bit_offset: 16
    bit_size: 16
fieldset/U_STATUS:
  fields:
  - name: CORE_STATUS_U0
    bit_offset: 0
    bit_size: 32
  - name: ZERO_MODE
    bit_offset: 0
    bit_size: 2
  - name: THRES1
    bit_offset: 2
    bit_size: 1
  - name: THRES0
    bit_offset: 3
    bit_size: 1
  - name: L_LIM
    bit_offset: 4
    bit_size: 1
  - name: H_LIM
    bit_offset: 5
    bit_size: 1
  - name: ZERO
    bit_offset: 6
    bit_size: 1