diff --git a/data/chips/STM32F215RE.json b/data/chips/STM32F215RE.json index 4c5773d..1578157 100644 --- a/data/chips/STM32F215RE.json +++ b/data/chips/STM32F215RE.json @@ -1220,6 +1220,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F215RG.json b/data/chips/STM32F215RG.json index 820895f..dfafd93 100644 --- a/data/chips/STM32F215RG.json +++ b/data/chips/STM32F215RG.json @@ -1220,6 +1220,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F215VE.json b/data/chips/STM32F215VE.json index 27a82db..62856ea 100644 --- a/data/chips/STM32F215VE.json +++ b/data/chips/STM32F215VE.json @@ -1513,6 +1513,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F215VG.json b/data/chips/STM32F215VG.json index 4e44464..bcb5cf7 100644 --- a/data/chips/STM32F215VG.json +++ b/data/chips/STM32F215VG.json @@ -1513,6 +1513,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F215ZE.json b/data/chips/STM32F215ZE.json index cd702e0..b758f5b 100644 --- a/data/chips/STM32F215ZE.json +++ b/data/chips/STM32F215ZE.json @@ -1700,6 +1700,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F215ZG.json b/data/chips/STM32F215ZG.json index b2cee6c..ce5b838 100644 --- a/data/chips/STM32F215ZG.json +++ b/data/chips/STM32F215ZG.json @@ -1700,6 +1700,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F217IE.json b/data/chips/STM32F217IE.json index 5e0307a..94bbbf1 100644 --- a/data/chips/STM32F217IE.json +++ b/data/chips/STM32F217IE.json @@ -2131,6 +2131,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F217IG.json b/data/chips/STM32F217IG.json index 687f538..e098bb1 100644 --- a/data/chips/STM32F217IG.json +++ b/data/chips/STM32F217IG.json @@ -2131,6 +2131,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F217VE.json b/data/chips/STM32F217VE.json index b2c67ef..26db764 100644 --- a/data/chips/STM32F217VE.json +++ b/data/chips/STM32F217VE.json @@ -1800,6 +1800,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F217VG.json b/data/chips/STM32F217VG.json index cb6d7d8..5349571 100644 --- a/data/chips/STM32F217VG.json +++ b/data/chips/STM32F217VG.json @@ -1800,6 +1800,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F217ZE.json b/data/chips/STM32F217ZE.json index 6f405e7..52d1e4b 100644 --- a/data/chips/STM32F217ZE.json +++ b/data/chips/STM32F217ZE.json @@ -2017,6 +2017,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F217ZG.json b/data/chips/STM32F217ZG.json index 1e4ea17..a879598 100644 --- a/data/chips/STM32F217ZG.json +++ b/data/chips/STM32F217ZG.json @@ -2017,6 +2017,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F415OG.json b/data/chips/STM32F415OG.json index 73c2ad5..ed6aedb 100644 --- a/data/chips/STM32F415OG.json +++ b/data/chips/STM32F415OG.json @@ -1452,6 +1452,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F415RG.json b/data/chips/STM32F415RG.json index 91c449a..a60ffcb 100644 --- a/data/chips/STM32F415RG.json +++ b/data/chips/STM32F415RG.json @@ -1232,6 +1232,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F415VG.json b/data/chips/STM32F415VG.json index da79266..7e17c39 100644 --- a/data/chips/STM32F415VG.json +++ b/data/chips/STM32F415VG.json @@ -1525,6 +1525,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F415ZG.json b/data/chips/STM32F415ZG.json index 82d45eb..5a965d8 100644 --- a/data/chips/STM32F415ZG.json +++ b/data/chips/STM32F415ZG.json @@ -1712,6 +1712,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F417IE.json b/data/chips/STM32F417IE.json index 36f85d9..ad1d54b 100644 --- a/data/chips/STM32F417IE.json +++ b/data/chips/STM32F417IE.json @@ -2155,6 +2155,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F417IG.json b/data/chips/STM32F417IG.json index 69bff5c..14fdd50 100644 --- a/data/chips/STM32F417IG.json +++ b/data/chips/STM32F417IG.json @@ -2155,6 +2155,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F417VE.json b/data/chips/STM32F417VE.json index 4c863e7..5a69785 100644 --- a/data/chips/STM32F417VE.json +++ b/data/chips/STM32F417VE.json @@ -1824,6 +1824,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F417VG.json b/data/chips/STM32F417VG.json index b8b6023..cdbcd36 100644 --- a/data/chips/STM32F417VG.json +++ b/data/chips/STM32F417VG.json @@ -1824,6 +1824,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F417ZE.json b/data/chips/STM32F417ZE.json index 47e3b4e..5c5bf6d 100644 --- a/data/chips/STM32F417ZE.json +++ b/data/chips/STM32F417ZE.json @@ -2041,6 +2041,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F417ZG.json b/data/chips/STM32F417ZG.json index ec184b3..21b6e94 100644 --- a/data/chips/STM32F417ZG.json +++ b/data/chips/STM32F417ZG.json @@ -2041,6 +2041,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v1", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F437AI.json b/data/chips/STM32F437AI.json index 2144fb9..053db9c 100644 --- a/data/chips/STM32F437AI.json +++ b/data/chips/STM32F437AI.json @@ -2363,6 +2363,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F437IG.json b/data/chips/STM32F437IG.json index 4dd4533..87b7739 100644 --- a/data/chips/STM32F437IG.json +++ b/data/chips/STM32F437IG.json @@ -2442,6 +2442,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F437II.json b/data/chips/STM32F437II.json index ecc7f32..fb808e1 100644 --- a/data/chips/STM32F437II.json +++ b/data/chips/STM32F437II.json @@ -2475,6 +2475,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F437VG.json b/data/chips/STM32F437VG.json index 084b2a1..e4ccb64 100644 --- a/data/chips/STM32F437VG.json +++ b/data/chips/STM32F437VG.json @@ -1931,6 +1931,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F437VI.json b/data/chips/STM32F437VI.json index c4c6f81..cd46f56 100644 --- a/data/chips/STM32F437VI.json +++ b/data/chips/STM32F437VI.json @@ -1964,6 +1964,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F437ZG.json b/data/chips/STM32F437ZG.json index 0019e8b..3b4e623 100644 --- a/data/chips/STM32F437ZG.json +++ b/data/chips/STM32F437ZG.json @@ -2203,6 +2203,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F437ZI.json b/data/chips/STM32F437ZI.json index b4ae031..f1257c1 100644 --- a/data/chips/STM32F437ZI.json +++ b/data/chips/STM32F437ZI.json @@ -2236,6 +2236,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F439AI.json b/data/chips/STM32F439AI.json index a7cf5de..6240141 100644 --- a/data/chips/STM32F439AI.json +++ b/data/chips/STM32F439AI.json @@ -2375,6 +2375,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F439BG.json b/data/chips/STM32F439BG.json index dc8fcb9..ba854be 100644 --- a/data/chips/STM32F439BG.json +++ b/data/chips/STM32F439BG.json @@ -2444,6 +2444,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F439BI.json b/data/chips/STM32F439BI.json index 1f8a212..51a2ae0 100644 --- a/data/chips/STM32F439BI.json +++ b/data/chips/STM32F439BI.json @@ -2477,6 +2477,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F439IG.json b/data/chips/STM32F439IG.json index 38581fa..2094bca 100644 --- a/data/chips/STM32F439IG.json +++ b/data/chips/STM32F439IG.json @@ -2454,6 +2454,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F439II.json b/data/chips/STM32F439II.json index 09071d5..79f8e5d 100644 --- a/data/chips/STM32F439II.json +++ b/data/chips/STM32F439II.json @@ -2487,6 +2487,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F439NG.json b/data/chips/STM32F439NG.json index f96ea46..4a7f1b2 100644 --- a/data/chips/STM32F439NG.json +++ b/data/chips/STM32F439NG.json @@ -2444,6 +2444,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F439NI.json b/data/chips/STM32F439NI.json index 4a4b50b..2ce47b8 100644 --- a/data/chips/STM32F439NI.json +++ b/data/chips/STM32F439NI.json @@ -2477,6 +2477,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F439VG.json b/data/chips/STM32F439VG.json index d1a1291..37b98ff 100644 --- a/data/chips/STM32F439VG.json +++ b/data/chips/STM32F439VG.json @@ -1912,6 +1912,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F439VI.json b/data/chips/STM32F439VI.json index 013f8c9..c6e103b 100644 --- a/data/chips/STM32F439VI.json +++ b/data/chips/STM32F439VI.json @@ -1945,6 +1945,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F439ZG.json b/data/chips/STM32F439ZG.json index 36f2d8a..4623b01 100644 --- a/data/chips/STM32F439ZG.json +++ b/data/chips/STM32F439ZG.json @@ -2213,6 +2213,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F439ZI.json b/data/chips/STM32F439ZI.json index 6bb7504..076c515 100644 --- a/data/chips/STM32F439ZI.json +++ b/data/chips/STM32F439ZI.json @@ -2246,6 +2246,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479AG.json b/data/chips/STM32F479AG.json index 9a5183a..9e588df 100644 --- a/data/chips/STM32F479AG.json +++ b/data/chips/STM32F479AG.json @@ -2124,6 +2124,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479AI.json b/data/chips/STM32F479AI.json index 698750e..25e6fe2 100644 --- a/data/chips/STM32F479AI.json +++ b/data/chips/STM32F479AI.json @@ -2157,6 +2157,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479BG.json b/data/chips/STM32F479BG.json index a0cab94..cfa917b 100644 --- a/data/chips/STM32F479BG.json +++ b/data/chips/STM32F479BG.json @@ -2403,6 +2403,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479BI.json b/data/chips/STM32F479BI.json index cfa053e..9a8cfff 100644 --- a/data/chips/STM32F479BI.json +++ b/data/chips/STM32F479BI.json @@ -2436,6 +2436,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479IG.json b/data/chips/STM32F479IG.json index 7d1a938..c28074b 100644 --- a/data/chips/STM32F479IG.json +++ b/data/chips/STM32F479IG.json @@ -2317,6 +2317,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479II.json b/data/chips/STM32F479II.json index 079f5dc..6ca8aa0 100644 --- a/data/chips/STM32F479II.json +++ b/data/chips/STM32F479II.json @@ -2350,6 +2350,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479NG.json b/data/chips/STM32F479NG.json index 20ee64b..810f2a8 100644 --- a/data/chips/STM32F479NG.json +++ b/data/chips/STM32F479NG.json @@ -2403,6 +2403,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479NI.json b/data/chips/STM32F479NI.json index fe55081..d186435 100644 --- a/data/chips/STM32F479NI.json +++ b/data/chips/STM32F479NI.json @@ -2436,6 +2436,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479VG.json b/data/chips/STM32F479VG.json index e79759c..c4a3706 100644 --- a/data/chips/STM32F479VG.json +++ b/data/chips/STM32F479VG.json @@ -1687,6 +1687,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479VI.json b/data/chips/STM32F479VI.json index 2b86af0..e77e5de 100644 --- a/data/chips/STM32F479VI.json +++ b/data/chips/STM32F479VI.json @@ -1720,6 +1720,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479ZG.json b/data/chips/STM32F479ZG.json index 2cd3bac..fafef72 100644 --- a/data/chips/STM32F479ZG.json +++ b/data/chips/STM32F479ZG.json @@ -1969,6 +1969,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F479ZI.json b/data/chips/STM32F479ZI.json index b281902..95141cd 100644 --- a/data/chips/STM32F479ZI.json +++ b/data/chips/STM32F479ZI.json @@ -2002,6 +2002,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F750N8.json b/data/chips/STM32F750N8.json index 8690088..ade4116 100644 --- a/data/chips/STM32F750N8.json +++ b/data/chips/STM32F750N8.json @@ -2365,6 +2365,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F750V8.json b/data/chips/STM32F750V8.json index d504a19..bc9c4d0 100644 --- a/data/chips/STM32F750V8.json +++ b/data/chips/STM32F750V8.json @@ -1898,6 +1898,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F750Z8.json b/data/chips/STM32F750Z8.json index edf5a56..4efb56b 100644 --- a/data/chips/STM32F750Z8.json +++ b/data/chips/STM32F750Z8.json @@ -2130,6 +2130,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F756BG.json b/data/chips/STM32F756BG.json index a8c3db0..8a8d0dd 100644 --- a/data/chips/STM32F756BG.json +++ b/data/chips/STM32F756BG.json @@ -2411,6 +2411,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F756IG.json b/data/chips/STM32F756IG.json index 47af1e2..3cb5877 100644 --- a/data/chips/STM32F756IG.json +++ b/data/chips/STM32F756IG.json @@ -2415,6 +2415,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F756NG.json b/data/chips/STM32F756NG.json index 5ad25f3..bff1f3b 100644 --- a/data/chips/STM32F756NG.json +++ b/data/chips/STM32F756NG.json @@ -2411,6 +2411,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F756VG.json b/data/chips/STM32F756VG.json index 8d7c24c..797dc82 100644 --- a/data/chips/STM32F756VG.json +++ b/data/chips/STM32F756VG.json @@ -1948,6 +1948,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F756ZG.json b/data/chips/STM32F756ZG.json index d87caab..82c26e8 100644 --- a/data/chips/STM32F756ZG.json +++ b/data/chips/STM32F756ZG.json @@ -2180,6 +2180,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F777BI.json b/data/chips/STM32F777BI.json index 5c71cf8..28891e0 100644 --- a/data/chips/STM32F777BI.json +++ b/data/chips/STM32F777BI.json @@ -2821,6 +2821,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F777II.json b/data/chips/STM32F777II.json index d9323d5..e41a3f1 100644 --- a/data/chips/STM32F777II.json +++ b/data/chips/STM32F777II.json @@ -2825,6 +2825,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F777NI.json b/data/chips/STM32F777NI.json index 9d8a771..1563f88 100644 --- a/data/chips/STM32F777NI.json +++ b/data/chips/STM32F777NI.json @@ -2821,6 +2821,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F777VI.json b/data/chips/STM32F777VI.json index 442b50e..42e3a54 100644 --- a/data/chips/STM32F777VI.json +++ b/data/chips/STM32F777VI.json @@ -2338,6 +2338,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F777ZI.json b/data/chips/STM32F777ZI.json index c2abf1d..5efb88b 100644 --- a/data/chips/STM32F777ZI.json +++ b/data/chips/STM32F777ZI.json @@ -2581,6 +2581,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F778AI.json b/data/chips/STM32F778AI.json index 8eb3218..152f8fe 100644 --- a/data/chips/STM32F778AI.json +++ b/data/chips/STM32F778AI.json @@ -2513,6 +2513,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F779AI.json b/data/chips/STM32F779AI.json index b6fbd94..20d3d65 100644 --- a/data/chips/STM32F779AI.json +++ b/data/chips/STM32F779AI.json @@ -2519,6 +2519,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F779BI.json b/data/chips/STM32F779BI.json index 6a3aae1..18a04a0 100644 --- a/data/chips/STM32F779BI.json +++ b/data/chips/STM32F779BI.json @@ -2827,6 +2827,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F779II.json b/data/chips/STM32F779II.json index 6e680b6..d95ca5b 100644 --- a/data/chips/STM32F779II.json +++ b/data/chips/STM32F779II.json @@ -2732,6 +2732,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32F779NI.json b/data/chips/STM32F779NI.json index 84c555e..02c6312 100644 --- a/data/chips/STM32F779NI.json +++ b/data/chips/STM32F779NI.json @@ -2827,6 +2827,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H503CB.json b/data/chips/STM32H503CB.json index 5c6fb5f..f348ef1 100644 --- a/data/chips/STM32H503CB.json +++ b/data/chips/STM32H503CB.json @@ -760,6 +760,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H503EB.json b/data/chips/STM32H503EB.json index 4f2572a..910fa1d 100644 --- a/data/chips/STM32H503EB.json +++ b/data/chips/STM32H503EB.json @@ -688,6 +688,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H503KB.json b/data/chips/STM32H503KB.json index 14376de..127b040 100644 --- a/data/chips/STM32H503KB.json +++ b/data/chips/STM32H503KB.json @@ -737,6 +737,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H503RB.json b/data/chips/STM32H503RB.json index beea0d2..ddaeddb 100644 --- a/data/chips/STM32H503RB.json +++ b/data/chips/STM32H503RB.json @@ -830,6 +830,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index 430ceae..c431534 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -1962,6 +1962,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index 75fc78b..68544da 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -1973,6 +1973,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index db9d588..65ad782 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -1986,6 +1986,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index e279449..78c5204 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -1997,6 +1997,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index 2108c05..9ab50cc 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -1194,6 +1194,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index d3ba42c..72248ab 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -1205,6 +1205,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index 27d8d0e..ab20813 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -1613,6 +1613,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index 6930bd3..f85b975 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -1624,6 +1624,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index 1641d18..68b889d 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -1827,6 +1827,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index d257a3f..804fade 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -1838,6 +1838,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index e7a697e..fe2bb59 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -2234,6 +2234,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index d0735a0..eb1bc73 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -2259,6 +2259,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 40cb53c..a639c91 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -2263,6 +2263,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index 54eadd3..1a86c26 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -2282,6 +2282,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index bd3a547..c6b73fd 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -1606,6 +1606,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index 0c5fdca..f5d6509 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -1411,6 +1411,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index f6a6dd9..3070518 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -1422,6 +1422,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index 34bc092..a523971 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -1835,6 +1835,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index 5db7eaa..dc2c137 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -1855,6 +1855,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index b2ef5e7..5ea61c9 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -2074,6 +2074,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index 8b37b10..ce89221 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -2109,6 +2109,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 1576f79..a9559d2 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -2312,6 +2312,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index 53ca635..bba3b5f 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -2335,6 +2335,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index ced412d..08ea0d8 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -1659,6 +1659,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index a1b667c..effd1c8 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -1475,6 +1475,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index 7cc56c0..d96b8c7 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -1908,6 +1908,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index 3c87bde..ee85f55 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -2162,6 +2162,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index 3c2c7a9..560ddfc 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -3146,6 +3146,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index 9717673..c260cb7 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -3231,6 +3231,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index 408d940..2f7b34f 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -2634,6 +2634,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index b8f45e1..d3d7bfb 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -3019,6 +3019,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index fe8b838..0f39347 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -2634,6 +2634,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index 2ae2546..eedb1cb 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -3019,6 +3019,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index d22c177..e0b6d36 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -3146,6 +3146,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index 788ebfe..d60dffd 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -3231,6 +3231,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H735RG.json b/data/chips/STM32H735RG.json index 67da0ce..d0d3f56 100644 --- a/data/chips/STM32H735RG.json +++ b/data/chips/STM32H735RG.json @@ -1800,6 +1800,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index e4eae24..68dd3af 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -2559,6 +2559,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index 4eb6b91..82b164a 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -2819,6 +2819,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H750IB.json b/data/chips/STM32H750IB.json index 4616faa..4a523c4 100644 --- a/data/chips/STM32H750IB.json +++ b/data/chips/STM32H750IB.json @@ -2994,6 +2994,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H750VB.json b/data/chips/STM32H750VB.json index 07c49a1..f401c56 100644 --- a/data/chips/STM32H750VB.json +++ b/data/chips/STM32H750VB.json @@ -2430,6 +2430,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H750XB.json b/data/chips/STM32H750XB.json index 7b79ffa..c86b7f3 100644 --- a/data/chips/STM32H750XB.json +++ b/data/chips/STM32H750XB.json @@ -3104,6 +3104,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H750ZB.json b/data/chips/STM32H750ZB.json index 79afeeb..79f512d 100644 --- a/data/chips/STM32H750ZB.json +++ b/data/chips/STM32H750ZB.json @@ -2710,6 +2710,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H753AI.json b/data/chips/STM32H753AI.json index 1c4183c..24e43ab 100644 --- a/data/chips/STM32H753AI.json +++ b/data/chips/STM32H753AI.json @@ -2894,6 +2894,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H753BI.json b/data/chips/STM32H753BI.json index 112cabe..d446db8 100644 --- a/data/chips/STM32H753BI.json +++ b/data/chips/STM32H753BI.json @@ -3019,6 +3019,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H753II.json b/data/chips/STM32H753II.json index 2651d43..706c016 100644 --- a/data/chips/STM32H753II.json +++ b/data/chips/STM32H753II.json @@ -3023,6 +3023,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H753VI.json b/data/chips/STM32H753VI.json index 5fa1fd4..4ceac3c 100644 --- a/data/chips/STM32H753VI.json +++ b/data/chips/STM32H753VI.json @@ -2463,6 +2463,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H753XI.json b/data/chips/STM32H753XI.json index 0781333..ba66a8a 100644 --- a/data/chips/STM32H753XI.json +++ b/data/chips/STM32H753XI.json @@ -3133,6 +3133,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H753ZI.json b/data/chips/STM32H753ZI.json index 1e5e50e..1f48026 100644 --- a/data/chips/STM32H753ZI.json +++ b/data/chips/STM32H753ZI.json @@ -2751,6 +2751,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index 2457c0d..b2c71bd 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -3001,6 +3001,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { @@ -12622,6 +12627,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index 511e0ee..988d58e 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -3019,6 +3019,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { @@ -12574,6 +12579,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index 675b5cd..4063711 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -3115,6 +3115,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { @@ -13097,6 +13102,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index b12ed32..6af6fa7 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -2606,6 +2606,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { @@ -11162,6 +11167,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index c12db8d..044fac3 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -2739,6 +2739,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { @@ -11514,6 +11519,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index 63a6955..8e42ee9 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -3007,6 +3007,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { @@ -12457,6 +12462,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 7969218..37351cd 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -2739,6 +2739,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { @@ -11514,6 +11519,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 1c8a7fa..7621824 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -3121,6 +3121,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { @@ -13107,6 +13112,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index 239870d..30b2565 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -2617,6 +2617,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { @@ -10850,6 +10855,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index 9fd40ad..ec45005 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -2823,6 +2823,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index 04b171d..6f3cb67 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -2977,6 +2977,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index 893e98d..26066e8 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -1936,6 +1936,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index ffee852..55841cf 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -2470,6 +2470,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index e650893..f4091de 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -2689,6 +2689,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index 052eef2..eaadcbd 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -2840,6 +2840,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index ba5e8ef..f699876 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -3002,6 +3002,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index a1c8103..dad980c 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -2990,6 +2990,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index c7c695f..052c795 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -2921,6 +2921,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index c5121c3..f2c947f 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -2545,6 +2545,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 252c169..148031c 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -1953,6 +1953,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index 9ee0a19..a5a17ba 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -2499,6 +2499,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index ce685e3..455d14b 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -2710,6 +2710,11 @@ { "name": "HASH", "address": 1208095744, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4A6AG.json b/data/chips/STM32L4A6AG.json index 88336d0..29dbc60 100644 --- a/data/chips/STM32L4A6AG.json +++ b/data/chips/STM32L4A6AG.json @@ -2409,6 +2409,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4A6QG.json b/data/chips/STM32L4A6QG.json index 3e31e13..3eb7e89 100644 --- a/data/chips/STM32L4A6QG.json +++ b/data/chips/STM32L4A6QG.json @@ -2295,6 +2295,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4A6RG.json b/data/chips/STM32L4A6RG.json index f712562..642db57 100644 --- a/data/chips/STM32L4A6RG.json +++ b/data/chips/STM32L4A6RG.json @@ -1747,6 +1747,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4A6VG.json b/data/chips/STM32L4A6VG.json index aa8545d..f8b883a 100644 --- a/data/chips/STM32L4A6VG.json +++ b/data/chips/STM32L4A6VG.json @@ -2161,6 +2161,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4A6ZG.json b/data/chips/STM32L4A6ZG.json index 9be163a..95ef125 100644 --- a/data/chips/STM32L4A6ZG.json +++ b/data/chips/STM32L4A6ZG.json @@ -2320,6 +2320,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5AE.json b/data/chips/STM32L4P5AE.json index 8a9e7df..9c394e9 100644 --- a/data/chips/STM32L4P5AE.json +++ b/data/chips/STM32L4P5AE.json @@ -2155,6 +2155,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5AG.json b/data/chips/STM32L4P5AG.json index 478b88c..fbb2d8e 100644 --- a/data/chips/STM32L4P5AG.json +++ b/data/chips/STM32L4P5AG.json @@ -2159,6 +2159,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5CE.json b/data/chips/STM32L4P5CE.json index b0e9a33..0123bf7 100644 --- a/data/chips/STM32L4P5CE.json +++ b/data/chips/STM32L4P5CE.json @@ -1332,6 +1332,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5CG.json b/data/chips/STM32L4P5CG.json index 9caeabd..ade7201 100644 --- a/data/chips/STM32L4P5CG.json +++ b/data/chips/STM32L4P5CG.json @@ -1340,6 +1340,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5QE.json b/data/chips/STM32L4P5QE.json index 557c6ad..c0273ff 100644 --- a/data/chips/STM32L4P5QE.json +++ b/data/chips/STM32L4P5QE.json @@ -2040,6 +2040,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5QG.json b/data/chips/STM32L4P5QG.json index 1efa658..367e018 100644 --- a/data/chips/STM32L4P5QG.json +++ b/data/chips/STM32L4P5QG.json @@ -2048,6 +2048,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5RE.json b/data/chips/STM32L4P5RE.json index 0d4e921..7ba98ef 100644 --- a/data/chips/STM32L4P5RE.json +++ b/data/chips/STM32L4P5RE.json @@ -1534,6 +1534,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5RG.json b/data/chips/STM32L4P5RG.json index 22d13ab..7055ce8 100644 --- a/data/chips/STM32L4P5RG.json +++ b/data/chips/STM32L4P5RG.json @@ -1538,6 +1538,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5VE.json b/data/chips/STM32L4P5VE.json index f53da8b..003bb3d 100644 --- a/data/chips/STM32L4P5VE.json +++ b/data/chips/STM32L4P5VE.json @@ -1934,6 +1934,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5VG.json b/data/chips/STM32L4P5VG.json index 3a7e75f..4546c64 100644 --- a/data/chips/STM32L4P5VG.json +++ b/data/chips/STM32L4P5VG.json @@ -1942,6 +1942,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5ZE.json b/data/chips/STM32L4P5ZE.json index c416a05..707cfb7 100644 --- a/data/chips/STM32L4P5ZE.json +++ b/data/chips/STM32L4P5ZE.json @@ -2050,6 +2050,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4P5ZG.json b/data/chips/STM32L4P5ZG.json index 01aaab5..e52c720 100644 --- a/data/chips/STM32L4P5ZG.json +++ b/data/chips/STM32L4P5ZG.json @@ -2054,6 +2054,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4Q5AG.json b/data/chips/STM32L4Q5AG.json index 099b556..3a15c18 100644 --- a/data/chips/STM32L4Q5AG.json +++ b/data/chips/STM32L4Q5AG.json @@ -2197,6 +2197,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4Q5CG.json b/data/chips/STM32L4Q5CG.json index ced2790..257622e 100644 --- a/data/chips/STM32L4Q5CG.json +++ b/data/chips/STM32L4Q5CG.json @@ -1378,6 +1378,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4Q5QG.json b/data/chips/STM32L4Q5QG.json index 9c4fac5..92f22f2 100644 --- a/data/chips/STM32L4Q5QG.json +++ b/data/chips/STM32L4Q5QG.json @@ -2082,6 +2082,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4Q5RG.json b/data/chips/STM32L4Q5RG.json index d25f45b..c280142 100644 --- a/data/chips/STM32L4Q5RG.json +++ b/data/chips/STM32L4Q5RG.json @@ -1576,6 +1576,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4Q5VG.json b/data/chips/STM32L4Q5VG.json index ba969a2..04da2cd 100644 --- a/data/chips/STM32L4Q5VG.json +++ b/data/chips/STM32L4Q5VG.json @@ -1980,6 +1980,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4Q5ZG.json b/data/chips/STM32L4Q5ZG.json index 67d5e99..be43e6c 100644 --- a/data/chips/STM32L4Q5ZG.json +++ b/data/chips/STM32L4Q5ZG.json @@ -2092,6 +2092,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4S5AI.json b/data/chips/STM32L4S5AI.json index 1744884..e6f96b7 100644 --- a/data/chips/STM32L4S5AI.json +++ b/data/chips/STM32L4S5AI.json @@ -2189,6 +2189,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4S5QI.json b/data/chips/STM32L4S5QI.json index ea78577..218e08c 100644 --- a/data/chips/STM32L4S5QI.json +++ b/data/chips/STM32L4S5QI.json @@ -2074,6 +2074,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4S5VI.json b/data/chips/STM32L4S5VI.json index 10b35bd..5e90baa 100644 --- a/data/chips/STM32L4S5VI.json +++ b/data/chips/STM32L4S5VI.json @@ -1934,6 +1934,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4S5ZI.json b/data/chips/STM32L4S5ZI.json index a06db1e..63bd7eb 100644 --- a/data/chips/STM32L4S5ZI.json +++ b/data/chips/STM32L4S5ZI.json @@ -2088,6 +2088,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4S7AI.json b/data/chips/STM32L4S7AI.json index db4073e..19fdeee 100644 --- a/data/chips/STM32L4S7AI.json +++ b/data/chips/STM32L4S7AI.json @@ -2215,6 +2215,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4S7VI.json b/data/chips/STM32L4S7VI.json index 105ee96..9083290 100644 --- a/data/chips/STM32L4S7VI.json +++ b/data/chips/STM32L4S7VI.json @@ -1960,6 +1960,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4S7ZI.json b/data/chips/STM32L4S7ZI.json index 74549e8..682a0c3 100644 --- a/data/chips/STM32L4S7ZI.json +++ b/data/chips/STM32L4S7ZI.json @@ -2110,6 +2110,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4S9AI.json b/data/chips/STM32L4S9AI.json index 6822994..a52aaf1 100644 --- a/data/chips/STM32L4S9AI.json +++ b/data/chips/STM32L4S9AI.json @@ -2193,6 +2193,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4S9VI.json b/data/chips/STM32L4S9VI.json index d4ebc44..32d93da 100644 --- a/data/chips/STM32L4S9VI.json +++ b/data/chips/STM32L4S9VI.json @@ -1910,6 +1910,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L4S9ZI.json b/data/chips/STM32L4S9ZI.json index 1135337..557e496 100644 --- a/data/chips/STM32L4S9ZI.json +++ b/data/chips/STM32L4S9ZI.json @@ -2119,6 +2119,11 @@ { "name": "HASH", "address": 1342571520, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L552CC.json b/data/chips/STM32L552CC.json index c5b6e11..b49915d 100644 --- a/data/chips/STM32L552CC.json +++ b/data/chips/STM32L552CC.json @@ -1086,6 +1086,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L552CE.json b/data/chips/STM32L552CE.json index 33721e3..ec496f3 100644 --- a/data/chips/STM32L552CE.json +++ b/data/chips/STM32L552CE.json @@ -1094,6 +1094,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L552ME.json b/data/chips/STM32L552ME.json index 25b8c2c..763e43f 100644 --- a/data/chips/STM32L552ME.json +++ b/data/chips/STM32L552ME.json @@ -1130,6 +1130,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L552QC.json b/data/chips/STM32L552QC.json index 0adf19d..c839a6e 100644 --- a/data/chips/STM32L552QC.json +++ b/data/chips/STM32L552QC.json @@ -1539,6 +1539,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L552QE.json b/data/chips/STM32L552QE.json index 73ed994..76baf59 100644 --- a/data/chips/STM32L552QE.json +++ b/data/chips/STM32L552QE.json @@ -1547,6 +1547,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L552RC.json b/data/chips/STM32L552RC.json index bdb6808..9e01594 100644 --- a/data/chips/STM32L552RC.json +++ b/data/chips/STM32L552RC.json @@ -1138,6 +1138,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L552RE.json b/data/chips/STM32L552RE.json index bb5a4d1..6c6abf1 100644 --- a/data/chips/STM32L552RE.json +++ b/data/chips/STM32L552RE.json @@ -1146,6 +1146,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L552VC.json b/data/chips/STM32L552VC.json index 26c130b..0dee722 100644 --- a/data/chips/STM32L552VC.json +++ b/data/chips/STM32L552VC.json @@ -1424,6 +1424,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L552VE.json b/data/chips/STM32L552VE.json index 2fdb02b..51aff1b 100644 --- a/data/chips/STM32L552VE.json +++ b/data/chips/STM32L552VE.json @@ -1428,6 +1428,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L552ZC.json b/data/chips/STM32L552ZC.json index ca8ca7e..f659eda 100644 --- a/data/chips/STM32L552ZC.json +++ b/data/chips/STM32L552ZC.json @@ -1539,6 +1539,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L552ZE.json b/data/chips/STM32L552ZE.json index 1513349..f515360 100644 --- a/data/chips/STM32L552ZE.json +++ b/data/chips/STM32L552ZE.json @@ -1543,6 +1543,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index d0ac698..6e28515 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -1132,6 +1132,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index cca2826..5586243 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -1168,6 +1168,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index be07af7..f9394f6 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -1585,6 +1585,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index f7983ec..c1c131b 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -1184,6 +1184,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index 9b6172f..fb48c71 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -1466,6 +1466,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index 5b1c715..6ca22d4 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -1581,6 +1581,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index 590f0d9..92fc1b5 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -898,6 +898,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index 6b51edb..ece6bff 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -898,6 +898,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index 9864708..1a912b0 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -898,6 +898,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index aa1ebcb..e6711ed 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -889,6 +889,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index 2ebf38b..4b43c44 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -881,6 +881,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index 3ef3a5e..8ccdc6d 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -881,6 +881,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index b0fd2f1..8dc06f2 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -964,6 +964,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index 13e2213..c49d540 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -964,6 +964,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index f852c78..e78161a 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -964,6 +964,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index 543929e..46a70b1 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -1171,6 +1171,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index 2fc03e2..ef61e5a 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -1171,6 +1171,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index b0d283b..1376564 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -936,6 +936,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index 7698394..78510e8 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -927,6 +927,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 9b0911a..38fd332 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -919,6 +919,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index 3addd2a..7672597 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -1002,6 +1002,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index 7f58b14..0e59841 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -1209,6 +1209,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575AG.json b/data/chips/STM32U575AG.json index 309dc01..c3cc18d 100644 --- a/data/chips/STM32U575AG.json +++ b/data/chips/STM32U575AG.json @@ -2155,6 +2155,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575AI.json b/data/chips/STM32U575AI.json index 7f6da86..e431281 100644 --- a/data/chips/STM32U575AI.json +++ b/data/chips/STM32U575AI.json @@ -2155,6 +2155,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575CG.json b/data/chips/STM32U575CG.json index cbdcd63..58cb392 100644 --- a/data/chips/STM32U575CG.json +++ b/data/chips/STM32U575CG.json @@ -1352,6 +1352,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575CI.json b/data/chips/STM32U575CI.json index aace40d..100bbae 100644 --- a/data/chips/STM32U575CI.json +++ b/data/chips/STM32U575CI.json @@ -1352,6 +1352,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575OG.json b/data/chips/STM32U575OG.json index b4e59bf..c019f95 100644 --- a/data/chips/STM32U575OG.json +++ b/data/chips/STM32U575OG.json @@ -1721,6 +1721,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575OI.json b/data/chips/STM32U575OI.json index bfa4baf..c2cb6e9 100644 --- a/data/chips/STM32U575OI.json +++ b/data/chips/STM32U575OI.json @@ -1721,6 +1721,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575QG.json b/data/chips/STM32U575QG.json index 8efc839..605044c 100644 --- a/data/chips/STM32U575QG.json +++ b/data/chips/STM32U575QG.json @@ -2035,6 +2035,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575QI.json b/data/chips/STM32U575QI.json index 6a36c38..83bbf3c 100644 --- a/data/chips/STM32U575QI.json +++ b/data/chips/STM32U575QI.json @@ -2035,6 +2035,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575RG.json b/data/chips/STM32U575RG.json index d5189ab..e173af8 100644 --- a/data/chips/STM32U575RG.json +++ b/data/chips/STM32U575RG.json @@ -1540,6 +1540,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575RI.json b/data/chips/STM32U575RI.json index fe06dd9..5933305 100644 --- a/data/chips/STM32U575RI.json +++ b/data/chips/STM32U575RI.json @@ -1540,6 +1540,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575VG.json b/data/chips/STM32U575VG.json index 612a80d..31ff9e0 100644 --- a/data/chips/STM32U575VG.json +++ b/data/chips/STM32U575VG.json @@ -1894,6 +1894,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575VI.json b/data/chips/STM32U575VI.json index 57af6d7..c376ec4 100644 --- a/data/chips/STM32U575VI.json +++ b/data/chips/STM32U575VI.json @@ -1894,6 +1894,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575ZG.json b/data/chips/STM32U575ZG.json index df140c2..01fc3c3 100644 --- a/data/chips/STM32U575ZG.json +++ b/data/chips/STM32U575ZG.json @@ -2055,6 +2055,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U575ZI.json b/data/chips/STM32U575ZI.json index a545dff..c8103c2 100644 --- a/data/chips/STM32U575ZI.json +++ b/data/chips/STM32U575ZI.json @@ -2055,6 +2055,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index d3e7075..56f5508 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -2199,6 +2199,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index 8c145cd..d9e8165 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -1396,6 +1396,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index 6eebbef..db0a866 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -1765,6 +1765,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index 673ca44..77be3ac 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -2079,6 +2079,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index 3f9dccc..c1b8f96 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -1584,6 +1584,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index aa99b6b..21ce77e 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -1938,6 +1938,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index cee2bec..e48fee0 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -2099,6 +2099,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index 4bac985..accda58 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -1909,6 +1909,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index e8a330c..0b3da71 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -1909,6 +1909,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index 334e721..5fd022e 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -1789,6 +1789,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index c65842f..5ba359b 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -1789,6 +1789,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index 998ba38..1a932f8 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -1284,6 +1284,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index abf4609..393c2d9 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -1284,6 +1284,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index f5843fe..5eb1264 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -1638,6 +1638,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index 5a6451a..0392097 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -1638,6 +1638,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index 3d00ab9..5d074b9 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -1813,6 +1813,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index 9c99e2e..3f9dd0f 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -1813,6 +1813,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index 89d0ee8..2075a46 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -1969,6 +1969,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index 748743b..c51bf4f 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -1969,6 +1969,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index 969977f..5721ad4 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -1969,6 +1969,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index d9f2e5c..09a92a0 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -1656,6 +1656,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index 58c1c51..15c9347 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -1702,6 +1702,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index 0eac966..a17193d 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -1873,6 +1873,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index b7f3184..0c5067d 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -1873,6 +1873,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index 771b61f..459be25 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -1947,6 +1947,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index 8bff7cf..97962e2 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -1827,6 +1827,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index 1c3977b..b727acf 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -1322,6 +1322,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index c8c7925..26f0970 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -1676,6 +1676,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 8f7ce17..9edb2c2 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -1851,6 +1851,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index ccc91d0..a3b1113 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -2007,6 +2007,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index 6abce53..111d8ed 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -2007,6 +2007,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 38e6a5a..96a7ab5 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -1694,6 +1694,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index feb5919..1e4df84 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -1911,6 +1911,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v2", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32WBA52CE.json b/data/chips/STM32WBA52CE.json index f87bdc5..8759613 100644 --- a/data/chips/STM32WBA52CE.json +++ b/data/chips/STM32WBA52CE.json @@ -413,6 +413,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32WBA52CG.json b/data/chips/STM32WBA52CG.json index 2654c30..a6611b6 100644 --- a/data/chips/STM32WBA52CG.json +++ b/data/chips/STM32WBA52CG.json @@ -413,6 +413,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32WBA52KE.json b/data/chips/STM32WBA52KE.json index e1e5732..bbaec02 100644 --- a/data/chips/STM32WBA52KE.json +++ b/data/chips/STM32WBA52KE.json @@ -409,6 +409,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/chips/STM32WBA52KG.json b/data/chips/STM32WBA52KG.json index ffd69f0..47603cb 100644 --- a/data/chips/STM32WBA52KG.json +++ b/data/chips/STM32WBA52KG.json @@ -409,6 +409,11 @@ { "name": "HASH", "address": 1108083712, + "registers": { + "kind": "hash", + "version": "v3", + "block": "HASH" + }, "rcc": { "clock": "hclk2", "enable": { diff --git a/data/registers/hash_v1.json b/data/registers/hash_v1.json new file mode 100644 index 0000000..44c2eb8 --- /dev/null +++ b/data/registers/hash_v1.json @@ -0,0 +1,209 @@ +{ + "block/HASH": { + "description": "Hash processor.", + "items": [ + { + "name": "CR", + "description": "control register.", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "DIN", + "description": "data input register.", + "byte_offset": 4, + "access": "Write", + "fieldset": "DIN" + }, + { + "name": "STR", + "description": "start register.", + "byte_offset": 8, + "access": "Write", + "fieldset": "STR" + }, + { + "name": "HR", + "description": "digest registers.", + "array": { + "len": 5, + "stride": 4 + }, + "byte_offset": 12, + "access": "Read", + "fieldset": "HR" + }, + { + "name": "IMR", + "description": "interrupt enable register.", + "byte_offset": 32, + "fieldset": "IMR" + }, + { + "name": "SR", + "description": "status register.", + "byte_offset": 36, + "fieldset": "SR" + }, + { + "name": "CSR", + "description": "context swap registers.", + "array": { + "len": 51, + "stride": 4 + }, + "byte_offset": 248, + "fieldset": "CSR" + } + ] + }, + "fieldset/CR": { + "description": "control register.", + "fields": [ + { + "name": "INIT", + "description": "Initialize message digest calculation.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "DMAE", + "description": "DMA enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "DATATYPE", + "description": "Data type selection.", + "bit_offset": 4, + "bit_size": 2 + }, + { + "name": "MODE", + "description": "Mode selection.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ALGO", + "description": "Algorithm selection.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "NBW", + "description": "Number of words already pushed.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "DINNE", + "description": "DIN not empty.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "LKEY", + "description": "Long key selection.", + "bit_offset": 16, + "bit_size": 1 + } + ] + }, + "fieldset/CSR": { + "description": "context swap registers.", + "fields": [ + { + "name": "CSR", + "description": "CSR0.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/DIN": { + "description": "data input register.", + "fields": [ + { + "name": "DATAIN", + "description": "Data input.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HR": { + "description": "digest registers.", + "fields": [ + { + "name": "H", + "description": "H0.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/IMR": { + "description": "interrupt enable register.", + "fields": [ + { + "name": "DINIE", + "description": "Data input interrupt enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DCIE", + "description": "Digest calculation completion interrupt enable.", + "bit_offset": 1, + "bit_size": 1 + } + ] + }, + "fieldset/SR": { + "description": "status register.", + "fields": [ + { + "name": "DINIS", + "description": "Data input interrupt status.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DCIS", + "description": "Digest calculation completion interrupt status.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DMAS", + "description": "DMA Status.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSY", + "description": "Busy bit.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/STR": { + "description": "start register.", + "fields": [ + { + "name": "NBLW", + "description": "Number of valid bits in the last word of the message.", + "bit_offset": 0, + "bit_size": 5 + }, + { + "name": "DCAL", + "description": "Digest calculation.", + "bit_offset": 8, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hash_v2.json b/data/registers/hash_v2.json new file mode 100644 index 0000000..7d1b0cf --- /dev/null +++ b/data/registers/hash_v2.json @@ -0,0 +1,242 @@ +{ + "block/HASH": { + "description": "Hash processor.", + "items": [ + { + "name": "CR", + "description": "control register.", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "DIN", + "description": "data input register.", + "byte_offset": 4, + "access": "Write", + "fieldset": "DIN" + }, + { + "name": "STR", + "description": "start register.", + "byte_offset": 8, + "fieldset": "STR" + }, + { + "name": "HRA", + "description": "digest registers.", + "array": { + "len": 5, + "stride": 4 + }, + "byte_offset": 12, + "access": "Read", + "fieldset": "HRA" + }, + { + "name": "IMR", + "description": "interrupt enable register.", + "byte_offset": 32, + "fieldset": "IMR" + }, + { + "name": "SR", + "description": "status register.", + "byte_offset": 36, + "fieldset": "SR" + }, + { + "name": "CSR", + "description": "context swap registers.", + "array": { + "len": 54, + "stride": 4 + }, + "byte_offset": 248, + "fieldset": "CSR" + }, + { + "name": "HR", + "description": "HASH digest register.", + "array": { + "len": 8, + "stride": 4 + }, + "byte_offset": 784, + "access": "Read", + "fieldset": "HR" + } + ] + }, + "fieldset/CR": { + "description": "control register.", + "fields": [ + { + "name": "INIT", + "description": "Initialize message digest calculation.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "DMAE", + "description": "DMA enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "DATATYPE", + "description": "Data type selection.", + "bit_offset": 4, + "bit_size": 2 + }, + { + "name": "MODE", + "description": "Mode selection.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ALGO0", + "description": "Algorithm selection.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "NBW", + "description": "Number of words already pushed.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "DINNE", + "description": "DIN not empty.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "MDMAT", + "description": "Multiple DMA Transfers.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "LKEY", + "description": "Long key selection.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ALGO1", + "description": "ALGO.", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/CSR": { + "description": "context swap registers.", + "fields": [ + { + "name": "CSR", + "description": "CSR0.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/DIN": { + "description": "data input register.", + "fields": [ + { + "name": "DATAIN", + "description": "Data input.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HR": { + "description": "HASH digest register.", + "fields": [ + { + "name": "H", + "description": "H0.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HRA": { + "description": "digest registers.", + "fields": [ + { + "name": "H", + "description": "H0.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/IMR": { + "description": "interrupt enable register.", + "fields": [ + { + "name": "DINIE", + "description": "Data input interrupt enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DCIE", + "description": "Digest calculation completion interrupt enable.", + "bit_offset": 1, + "bit_size": 1 + } + ] + }, + "fieldset/SR": { + "description": "status register.", + "fields": [ + { + "name": "DINIS", + "description": "Data input interrupt status.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DCIS", + "description": "Digest calculation completion interrupt status.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DMAS", + "description": "DMA Status.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSY", + "description": "Busy bit.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/STR": { + "description": "start register.", + "fields": [ + { + "name": "NBLW", + "description": "Number of valid bits in the last word of the message.", + "bit_offset": 0, + "bit_size": 5 + }, + { + "name": "DCAL", + "description": "Digest calculation.", + "bit_offset": 8, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hash_v3.json b/data/registers/hash_v3.json new file mode 100644 index 0000000..4d21674 --- /dev/null +++ b/data/registers/hash_v3.json @@ -0,0 +1,254 @@ +{ + "block/HASH": { + "description": "Hash processor.", + "items": [ + { + "name": "CR", + "description": "control register.", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "DIN", + "description": "data input register.", + "byte_offset": 4, + "access": "Write", + "fieldset": "DIN" + }, + { + "name": "STR", + "description": "start register.", + "byte_offset": 8, + "fieldset": "STR" + }, + { + "name": "HRA", + "description": "digest registers.", + "array": { + "len": 5, + "stride": 4 + }, + "byte_offset": 12, + "access": "Read", + "fieldset": "HRA" + }, + { + "name": "IMR", + "description": "interrupt enable register.", + "byte_offset": 32, + "fieldset": "IMR" + }, + { + "name": "SR", + "description": "status register.", + "byte_offset": 36, + "fieldset": "SR" + }, + { + "name": "CSR", + "description": "context swap registers.", + "array": { + "len": 54, + "stride": 4 + }, + "byte_offset": 248, + "fieldset": "CSR" + }, + { + "name": "HR", + "description": "HASH digest register.", + "array": { + "len": 8, + "stride": 4 + }, + "byte_offset": 784, + "access": "Read", + "fieldset": "HR" + } + ] + }, + "fieldset/CR": { + "description": "control register.", + "fields": [ + { + "name": "INIT", + "description": "Initialize message digest calculation.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "DMAE", + "description": "DMA enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "DATATYPE", + "description": "Data type selection.", + "bit_offset": 4, + "bit_size": 2 + }, + { + "name": "MODE", + "description": "Mode selection.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "NBW", + "description": "Number of words already pushed.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "DINNE", + "description": "DIN not empty.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "MDMAT", + "description": "Multiple DMA Transfers.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "LKEY", + "description": "Long key selection.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ALGO", + "description": "Algorithm selection.", + "bit_offset": 17, + "bit_size": 2 + } + ] + }, + "fieldset/CSR": { + "description": "context swap registers.", + "fields": [ + { + "name": "CSR", + "description": "CSR0.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/DIN": { + "description": "data input register.", + "fields": [ + { + "name": "DATAIN", + "description": "Data input.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HR": { + "description": "HASH digest register.", + "fields": [ + { + "name": "H", + "description": "H0.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HRA": { + "description": "digest registers.", + "fields": [ + { + "name": "H", + "description": "H0.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/IMR": { + "description": "interrupt enable register.", + "fields": [ + { + "name": "DINIE", + "description": "Data input interrupt enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DCIE", + "description": "Digest calculation completion interrupt enable.", + "bit_offset": 1, + "bit_size": 1 + } + ] + }, + "fieldset/SR": { + "description": "status register.", + "fields": [ + { + "name": "DINIS", + "description": "Data input interrupt status.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DCIS", + "description": "Digest calculation completion interrupt status.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DMAS", + "description": "DMA Status.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSY", + "description": "Busy bit.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "NBWP", + "description": "Number of words already pushed.", + "bit_offset": 9, + "bit_size": 5 + }, + { + "name": "DINNE", + "description": "DIN not empty.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "NBWE", + "description": "Number of words expected.", + "bit_offset": 16, + "bit_size": 5 + } + ] + }, + "fieldset/STR": { + "description": "start register.", + "fields": [ + { + "name": "NBLW", + "description": "Number of valid bits in the last word of the message.", + "bit_offset": 0, + "bit_size": 5 + }, + { + "name": "DCAL", + "description": "Digest calculation.", + "bit_offset": 8, + "bit_size": 1 + } + ] + } +} \ No newline at end of file