diff --git a/data/chips/STM32F410C8.json b/data/chips/STM32F410C8.json index 6c22a7c..c446d6e 100644 --- a/data/chips/STM32F410C8.json +++ b/data/chips/STM32F410C8.json @@ -988,7 +988,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F410CB.json b/data/chips/STM32F410CB.json index d2bb02f..cf87332 100644 --- a/data/chips/STM32F410CB.json +++ b/data/chips/STM32F410CB.json @@ -999,7 +999,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F410R8.json b/data/chips/STM32F410R8.json index 651d51a..b676335 100644 --- a/data/chips/STM32F410R8.json +++ b/data/chips/STM32F410R8.json @@ -1037,7 +1037,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F410RB.json b/data/chips/STM32F410RB.json index b3bed44..1f05df9 100644 --- a/data/chips/STM32F410RB.json +++ b/data/chips/STM32F410RB.json @@ -1048,7 +1048,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F410T8.json b/data/chips/STM32F410T8.json index d143223..76eaefe 100644 --- a/data/chips/STM32F410T8.json +++ b/data/chips/STM32F410T8.json @@ -935,7 +935,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F410TB.json b/data/chips/STM32F410TB.json index 7005874..424353b 100644 --- a/data/chips/STM32F410TB.json +++ b/data/chips/STM32F410TB.json @@ -946,7 +946,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413CG.json b/data/chips/STM32F413CG.json index 95b306d..6397a13 100644 --- a/data/chips/STM32F413CG.json +++ b/data/chips/STM32F413CG.json @@ -1616,7 +1616,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413CH.json b/data/chips/STM32F413CH.json index b6ae5a7..0040ed4 100644 --- a/data/chips/STM32F413CH.json +++ b/data/chips/STM32F413CH.json @@ -1616,7 +1616,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413MG.json b/data/chips/STM32F413MG.json index c945f95..cf69d70 100644 --- a/data/chips/STM32F413MG.json +++ b/data/chips/STM32F413MG.json @@ -2028,7 +2028,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413MH.json b/data/chips/STM32F413MH.json index 67a5bdc..f7b5c85 100644 --- a/data/chips/STM32F413MH.json +++ b/data/chips/STM32F413MH.json @@ -2028,7 +2028,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413RG.json b/data/chips/STM32F413RG.json index 7555cb7..d680f03 100644 --- a/data/chips/STM32F413RG.json +++ b/data/chips/STM32F413RG.json @@ -1873,7 +1873,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413RH.json b/data/chips/STM32F413RH.json index 1f72cd9..26de1f2 100644 --- a/data/chips/STM32F413RH.json +++ b/data/chips/STM32F413RH.json @@ -1873,7 +1873,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413VG.json b/data/chips/STM32F413VG.json index d451852..93f091f 100644 --- a/data/chips/STM32F413VG.json +++ b/data/chips/STM32F413VG.json @@ -2282,7 +2282,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413VH.json b/data/chips/STM32F413VH.json index 39d4065..2c5bf20 100644 --- a/data/chips/STM32F413VH.json +++ b/data/chips/STM32F413VH.json @@ -2282,7 +2282,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413ZG.json b/data/chips/STM32F413ZG.json index 643f204..6aceaca 100644 --- a/data/chips/STM32F413ZG.json +++ b/data/chips/STM32F413ZG.json @@ -2437,7 +2437,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413ZH.json b/data/chips/STM32F413ZH.json index a184189..551e64b 100644 --- a/data/chips/STM32F413ZH.json +++ b/data/chips/STM32F413ZH.json @@ -2437,7 +2437,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F423CH.json b/data/chips/STM32F423CH.json index 4854749..338a43a 100644 --- a/data/chips/STM32F423CH.json +++ b/data/chips/STM32F423CH.json @@ -1643,7 +1643,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F423MH.json b/data/chips/STM32F423MH.json index 903e1d2..be8e716 100644 --- a/data/chips/STM32F423MH.json +++ b/data/chips/STM32F423MH.json @@ -2055,7 +2055,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F423RH.json b/data/chips/STM32F423RH.json index 23ba7e9..c256580 100644 --- a/data/chips/STM32F423RH.json +++ b/data/chips/STM32F423RH.json @@ -1900,7 +1900,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F423VH.json b/data/chips/STM32F423VH.json index b02b4ff..9501a30 100644 --- a/data/chips/STM32F423VH.json +++ b/data/chips/STM32F423VH.json @@ -2309,7 +2309,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F423ZH.json b/data/chips/STM32F423ZH.json index 490de3c..d2acd34 100644 --- a/data/chips/STM32F423ZH.json +++ b/data/chips/STM32F423ZH.json @@ -2464,7 +2464,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722IC.json b/data/chips/STM32F722IC.json index 658a56c..6039edd 100644 --- a/data/chips/STM32F722IC.json +++ b/data/chips/STM32F722IC.json @@ -2065,7 +2065,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722IE.json b/data/chips/STM32F722IE.json index e045d22..a618c3e 100644 --- a/data/chips/STM32F722IE.json +++ b/data/chips/STM32F722IE.json @@ -2065,7 +2065,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722VC.json b/data/chips/STM32F722VC.json index 82ff51a..88094a4 100644 --- a/data/chips/STM32F722VC.json +++ b/data/chips/STM32F722VC.json @@ -1709,7 +1709,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722VE.json b/data/chips/STM32F722VE.json index 5c799dc..3036a39 100644 --- a/data/chips/STM32F722VE.json +++ b/data/chips/STM32F722VE.json @@ -1709,7 +1709,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722ZC.json b/data/chips/STM32F722ZC.json index 44a8e35..1d80b5b 100644 --- a/data/chips/STM32F722ZC.json +++ b/data/chips/STM32F722ZC.json @@ -1901,7 +1901,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722ZE.json b/data/chips/STM32F722ZE.json index ea243c1..f55d83c 100644 --- a/data/chips/STM32F722ZE.json +++ b/data/chips/STM32F722ZE.json @@ -1901,7 +1901,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723IC.json b/data/chips/STM32F723IC.json index 7595ea0..2f5a4d2 100644 --- a/data/chips/STM32F723IC.json +++ b/data/chips/STM32F723IC.json @@ -2060,7 +2060,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723IE.json b/data/chips/STM32F723IE.json index 2ce0ca8..1534153 100644 --- a/data/chips/STM32F723IE.json +++ b/data/chips/STM32F723IE.json @@ -2060,7 +2060,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723VC.json b/data/chips/STM32F723VC.json index c8eccac..e876009 100644 --- a/data/chips/STM32F723VC.json +++ b/data/chips/STM32F723VC.json @@ -1683,7 +1683,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723VE.json b/data/chips/STM32F723VE.json index 1a5e205..7ed7e7d 100644 --- a/data/chips/STM32F723VE.json +++ b/data/chips/STM32F723VE.json @@ -1683,7 +1683,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723ZC.json b/data/chips/STM32F723ZC.json index f4a5092..a58a433 100644 --- a/data/chips/STM32F723ZC.json +++ b/data/chips/STM32F723ZC.json @@ -1900,7 +1900,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723ZE.json b/data/chips/STM32F723ZE.json index 946ee06..e61e7e0 100644 --- a/data/chips/STM32F723ZE.json +++ b/data/chips/STM32F723ZE.json @@ -1900,7 +1900,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F730I8.json b/data/chips/STM32F730I8.json index c54afd4..09b0986 100644 --- a/data/chips/STM32F730I8.json +++ b/data/chips/STM32F730I8.json @@ -2061,7 +2061,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F730V8.json b/data/chips/STM32F730V8.json index c8319a9..247d057 100644 --- a/data/chips/STM32F730V8.json +++ b/data/chips/STM32F730V8.json @@ -1714,7 +1714,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F730Z8.json b/data/chips/STM32F730Z8.json index 6cf326b..1d6757f 100644 --- a/data/chips/STM32F730Z8.json +++ b/data/chips/STM32F730Z8.json @@ -1901,7 +1901,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F732IE.json b/data/chips/STM32F732IE.json index 5f5fa85..aa3bf4c 100644 --- a/data/chips/STM32F732IE.json +++ b/data/chips/STM32F732IE.json @@ -2104,7 +2104,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F732VE.json b/data/chips/STM32F732VE.json index 3521518..1777c2a 100644 --- a/data/chips/STM32F732VE.json +++ b/data/chips/STM32F732VE.json @@ -1748,7 +1748,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F732ZE.json b/data/chips/STM32F732ZE.json index 19c18bf..da94534 100644 --- a/data/chips/STM32F732ZE.json +++ b/data/chips/STM32F732ZE.json @@ -1940,7 +1940,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F733IE.json b/data/chips/STM32F733IE.json index 0b32e29..8ad3988 100644 --- a/data/chips/STM32F733IE.json +++ b/data/chips/STM32F733IE.json @@ -2099,7 +2099,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F733VE.json b/data/chips/STM32F733VE.json index 855a815..ec00e5b 100644 --- a/data/chips/STM32F733VE.json +++ b/data/chips/STM32F733VE.json @@ -1722,7 +1722,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F733ZE.json b/data/chips/STM32F733ZE.json index 5d74651..0f865e0 100644 --- a/data/chips/STM32F733ZE.json +++ b/data/chips/STM32F733ZE.json @@ -1939,7 +1939,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745IE.json b/data/chips/STM32F745IE.json index c669ad5..f2e16f8 100644 --- a/data/chips/STM32F745IE.json +++ b/data/chips/STM32F745IE.json @@ -2797,7 +2797,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745IG.json b/data/chips/STM32F745IG.json index 2b91fac..2acd813 100644 --- a/data/chips/STM32F745IG.json +++ b/data/chips/STM32F745IG.json @@ -2797,7 +2797,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745VE.json b/data/chips/STM32F745VE.json index f3802fc..392821a 100644 --- a/data/chips/STM32F745VE.json +++ b/data/chips/STM32F745VE.json @@ -2255,7 +2255,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745VG.json b/data/chips/STM32F745VG.json index aa3b233..78da891 100644 --- a/data/chips/STM32F745VG.json +++ b/data/chips/STM32F745VG.json @@ -2255,7 +2255,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745ZE.json b/data/chips/STM32F745ZE.json index 5a08892..5f38a70 100644 --- a/data/chips/STM32F745ZE.json +++ b/data/chips/STM32F745ZE.json @@ -2513,7 +2513,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745ZG.json b/data/chips/STM32F745ZG.json index aec2e06..bee4346 100644 --- a/data/chips/STM32F745ZG.json +++ b/data/chips/STM32F745ZG.json @@ -2513,7 +2513,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746BE.json b/data/chips/STM32F746BE.json index 5a26a5a..f1616e2 100644 --- a/data/chips/STM32F746BE.json +++ b/data/chips/STM32F746BE.json @@ -2799,7 +2799,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746BG.json b/data/chips/STM32F746BG.json index e6b0850..8716477 100644 --- a/data/chips/STM32F746BG.json +++ b/data/chips/STM32F746BG.json @@ -2799,7 +2799,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746IE.json b/data/chips/STM32F746IE.json index e1fa458..06f37e1 100644 --- a/data/chips/STM32F746IE.json +++ b/data/chips/STM32F746IE.json @@ -2803,7 +2803,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746IG.json b/data/chips/STM32F746IG.json index 56a51f7..aafd2a4 100644 --- a/data/chips/STM32F746IG.json +++ b/data/chips/STM32F746IG.json @@ -2803,7 +2803,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746NE.json b/data/chips/STM32F746NE.json index c772699..b1fc7fd 100644 --- a/data/chips/STM32F746NE.json +++ b/data/chips/STM32F746NE.json @@ -2799,7 +2799,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746NG.json b/data/chips/STM32F746NG.json index 56dab61..ef501c8 100644 --- a/data/chips/STM32F746NG.json +++ b/data/chips/STM32F746NG.json @@ -2799,7 +2799,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746VE.json b/data/chips/STM32F746VE.json index b73b15f..42a9ba7 100644 --- a/data/chips/STM32F746VE.json +++ b/data/chips/STM32F746VE.json @@ -2261,7 +2261,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746VG.json b/data/chips/STM32F746VG.json index c90057b..abf0f5b 100644 --- a/data/chips/STM32F746VG.json +++ b/data/chips/STM32F746VG.json @@ -2261,7 +2261,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746ZE.json b/data/chips/STM32F746ZE.json index 1a086f5..827e819 100644 --- a/data/chips/STM32F746ZE.json +++ b/data/chips/STM32F746ZE.json @@ -2523,7 +2523,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746ZG.json b/data/chips/STM32F746ZG.json index 5c02699..92a5d1f 100644 --- a/data/chips/STM32F746ZG.json +++ b/data/chips/STM32F746ZG.json @@ -2523,7 +2523,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F750N8.json b/data/chips/STM32F750N8.json index 48f1b0d..839bf9e 100644 --- a/data/chips/STM32F750N8.json +++ b/data/chips/STM32F750N8.json @@ -2822,7 +2822,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F750V8.json b/data/chips/STM32F750V8.json index 56db08a..579d93a 100644 --- a/data/chips/STM32F750V8.json +++ b/data/chips/STM32F750V8.json @@ -2280,7 +2280,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F750Z8.json b/data/chips/STM32F750Z8.json index d6d9f70..91de042 100644 --- a/data/chips/STM32F750Z8.json +++ b/data/chips/STM32F750Z8.json @@ -2542,7 +2542,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F756BG.json b/data/chips/STM32F756BG.json index f5b11df..b61720f 100644 --- a/data/chips/STM32F756BG.json +++ b/data/chips/STM32F756BG.json @@ -2868,7 +2868,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F756IG.json b/data/chips/STM32F756IG.json index 2452d3c..1420c1d 100644 --- a/data/chips/STM32F756IG.json +++ b/data/chips/STM32F756IG.json @@ -2872,7 +2872,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F756NG.json b/data/chips/STM32F756NG.json index ed6c7d0..7060947 100644 --- a/data/chips/STM32F756NG.json +++ b/data/chips/STM32F756NG.json @@ -2868,7 +2868,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F756VG.json b/data/chips/STM32F756VG.json index 079941d..ee725b7 100644 --- a/data/chips/STM32F756VG.json +++ b/data/chips/STM32F756VG.json @@ -2330,7 +2330,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F756ZG.json b/data/chips/STM32F756ZG.json index 54f79a4..13a179c 100644 --- a/data/chips/STM32F756ZG.json +++ b/data/chips/STM32F756ZG.json @@ -2592,7 +2592,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765BG.json b/data/chips/STM32F765BG.json index 0ae2f30..41619ae 100644 --- a/data/chips/STM32F765BG.json +++ b/data/chips/STM32F765BG.json @@ -3221,7 +3221,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765BI.json b/data/chips/STM32F765BI.json index 09e32c5..a69f683 100644 --- a/data/chips/STM32F765BI.json +++ b/data/chips/STM32F765BI.json @@ -3227,7 +3227,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765IG.json b/data/chips/STM32F765IG.json index d733642..1867882 100644 --- a/data/chips/STM32F765IG.json +++ b/data/chips/STM32F765IG.json @@ -3231,7 +3231,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765II.json b/data/chips/STM32F765II.json index 0ef245b..b56317e 100644 --- a/data/chips/STM32F765II.json +++ b/data/chips/STM32F765II.json @@ -3231,7 +3231,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765NG.json b/data/chips/STM32F765NG.json index 23e6001..2dd02ff 100644 --- a/data/chips/STM32F765NG.json +++ b/data/chips/STM32F765NG.json @@ -3227,7 +3227,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765NI.json b/data/chips/STM32F765NI.json index 1a99a9e..be029a6 100644 --- a/data/chips/STM32F765NI.json +++ b/data/chips/STM32F765NI.json @@ -3227,7 +3227,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765VG.json b/data/chips/STM32F765VG.json index 3c9e36a..be6f4ca 100644 --- a/data/chips/STM32F765VG.json +++ b/data/chips/STM32F765VG.json @@ -2669,7 +2669,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765VI.json b/data/chips/STM32F765VI.json index 9dcf65f..3ec6513 100644 --- a/data/chips/STM32F765VI.json +++ b/data/chips/STM32F765VI.json @@ -2669,7 +2669,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765ZG.json b/data/chips/STM32F765ZG.json index aa002ca..b7059b0 100644 --- a/data/chips/STM32F765ZG.json +++ b/data/chips/STM32F765ZG.json @@ -2942,7 +2942,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765ZI.json b/data/chips/STM32F765ZI.json index caab9e0..ae99446 100644 --- a/data/chips/STM32F765ZI.json +++ b/data/chips/STM32F765ZI.json @@ -2942,7 +2942,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767BG.json b/data/chips/STM32F767BG.json index 73df9e1..ad28fe2 100644 --- a/data/chips/STM32F767BG.json +++ b/data/chips/STM32F767BG.json @@ -3278,7 +3278,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767BI.json b/data/chips/STM32F767BI.json index 6057d5a..f3c46a9 100644 --- a/data/chips/STM32F767BI.json +++ b/data/chips/STM32F767BI.json @@ -3278,7 +3278,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767IG.json b/data/chips/STM32F767IG.json index 81bee86..17aef43 100644 --- a/data/chips/STM32F767IG.json +++ b/data/chips/STM32F767IG.json @@ -3282,7 +3282,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767II.json b/data/chips/STM32F767II.json index 43921a9..be25d97 100644 --- a/data/chips/STM32F767II.json +++ b/data/chips/STM32F767II.json @@ -3282,7 +3282,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767NG.json b/data/chips/STM32F767NG.json index 2b539f5..acd5187 100644 --- a/data/chips/STM32F767NG.json +++ b/data/chips/STM32F767NG.json @@ -3278,7 +3278,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767NI.json b/data/chips/STM32F767NI.json index 137b005..44d9326 100644 --- a/data/chips/STM32F767NI.json +++ b/data/chips/STM32F767NI.json @@ -3278,7 +3278,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767VG.json b/data/chips/STM32F767VG.json index 4102c00..0ac582c 100644 --- a/data/chips/STM32F767VG.json +++ b/data/chips/STM32F767VG.json @@ -2720,7 +2720,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767VI.json b/data/chips/STM32F767VI.json index 872d104..eaa2d0b 100644 --- a/data/chips/STM32F767VI.json +++ b/data/chips/STM32F767VI.json @@ -2720,7 +2720,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767ZG.json b/data/chips/STM32F767ZG.json index c5891be..acba2ae 100644 --- a/data/chips/STM32F767ZG.json +++ b/data/chips/STM32F767ZG.json @@ -2993,7 +2993,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767ZI.json b/data/chips/STM32F767ZI.json index a57c745..2b61047 100644 --- a/data/chips/STM32F767ZI.json +++ b/data/chips/STM32F767ZI.json @@ -2993,7 +2993,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F768AI.json b/data/chips/STM32F768AI.json index 3142f28..41c7850 100644 --- a/data/chips/STM32F768AI.json +++ b/data/chips/STM32F768AI.json @@ -2682,7 +2682,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769AG.json b/data/chips/STM32F769AG.json index 1a7565c..f3c26b4 100644 --- a/data/chips/STM32F769AG.json +++ b/data/chips/STM32F769AG.json @@ -2682,7 +2682,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769AI.json b/data/chips/STM32F769AI.json index 6afad5b..37c04f5 100644 --- a/data/chips/STM32F769AI.json +++ b/data/chips/STM32F769AI.json @@ -2971,7 +2971,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769BG.json b/data/chips/STM32F769BG.json index 6958fd7..f78c438 100644 --- a/data/chips/STM32F769BG.json +++ b/data/chips/STM32F769BG.json @@ -3290,7 +3290,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769BI.json b/data/chips/STM32F769BI.json index 02657a3..0e9ef6a 100644 --- a/data/chips/STM32F769BI.json +++ b/data/chips/STM32F769BI.json @@ -3290,7 +3290,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769IG.json b/data/chips/STM32F769IG.json index 4e920d4..fb63692 100644 --- a/data/chips/STM32F769IG.json +++ b/data/chips/STM32F769IG.json @@ -3170,7 +3170,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769II.json b/data/chips/STM32F769II.json index 35d5f9e..99cd291 100644 --- a/data/chips/STM32F769II.json +++ b/data/chips/STM32F769II.json @@ -3170,7 +3170,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769NG.json b/data/chips/STM32F769NG.json index 22f019f..0520e08 100644 --- a/data/chips/STM32F769NG.json +++ b/data/chips/STM32F769NG.json @@ -3290,7 +3290,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769NI.json b/data/chips/STM32F769NI.json index c1d7857..5a74f84 100644 --- a/data/chips/STM32F769NI.json +++ b/data/chips/STM32F769NI.json @@ -3290,7 +3290,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F777BI.json b/data/chips/STM32F777BI.json index b2de4bd..7d10421 100644 --- a/data/chips/STM32F777BI.json +++ b/data/chips/STM32F777BI.json @@ -3353,7 +3353,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F777II.json b/data/chips/STM32F777II.json index 3da8bf2..db69aa1 100644 --- a/data/chips/STM32F777II.json +++ b/data/chips/STM32F777II.json @@ -3357,7 +3357,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F777NI.json b/data/chips/STM32F777NI.json index 3c5dc35..b1ca117 100644 --- a/data/chips/STM32F777NI.json +++ b/data/chips/STM32F777NI.json @@ -3353,7 +3353,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F777VI.json b/data/chips/STM32F777VI.json index b44bf5c..181fd7a 100644 --- a/data/chips/STM32F777VI.json +++ b/data/chips/STM32F777VI.json @@ -2795,7 +2795,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F777ZI.json b/data/chips/STM32F777ZI.json index 84f181b..9a1fb9e 100644 --- a/data/chips/STM32F777ZI.json +++ b/data/chips/STM32F777ZI.json @@ -3068,7 +3068,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F778AI.json b/data/chips/STM32F778AI.json index 2afec14..d673098 100644 --- a/data/chips/STM32F778AI.json +++ b/data/chips/STM32F778AI.json @@ -3034,7 +3034,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F779AI.json b/data/chips/STM32F779AI.json index 6594371..2227981 100644 --- a/data/chips/STM32F779AI.json +++ b/data/chips/STM32F779AI.json @@ -3040,7 +3040,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F779BI.json b/data/chips/STM32F779BI.json index 3c65eca..f7243f8 100644 --- a/data/chips/STM32F779BI.json +++ b/data/chips/STM32F779BI.json @@ -3359,7 +3359,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F779II.json b/data/chips/STM32F779II.json index 67b236a..9e46f41 100644 --- a/data/chips/STM32F779II.json +++ b/data/chips/STM32F779II.json @@ -3239,7 +3239,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F779NI.json b/data/chips/STM32F779NI.json index 40c28af..4f19fb6 100644 --- a/data/chips/STM32F779NI.json +++ b/data/chips/STM32F779NI.json @@ -3359,7 +3359,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031C4.json b/data/chips/STM32G031C4.json index 1b24fde..50c8d7a 100644 --- a/data/chips/STM32G031C4.json +++ b/data/chips/STM32G031C4.json @@ -791,7 +791,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -854,7 +854,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031C6.json b/data/chips/STM32G031C6.json index b434efa..d8ec603 100644 --- a/data/chips/STM32G031C6.json +++ b/data/chips/STM32G031C6.json @@ -791,7 +791,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -854,7 +854,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031C8.json b/data/chips/STM32G031C8.json index 0bd2b10..57329e5 100644 --- a/data/chips/STM32G031C8.json +++ b/data/chips/STM32G031C8.json @@ -791,7 +791,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -854,7 +854,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031F4.json b/data/chips/STM32G031F4.json index e6937d1..63e7217 100644 --- a/data/chips/STM32G031F4.json +++ b/data/chips/STM32G031F4.json @@ -767,7 +767,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -830,7 +830,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031F6.json b/data/chips/STM32G031F6.json index ab03f10..36902a2 100644 --- a/data/chips/STM32G031F6.json +++ b/data/chips/STM32G031F6.json @@ -767,7 +767,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -830,7 +830,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031F8.json b/data/chips/STM32G031F8.json index 92063b7..c6e7fe7 100644 --- a/data/chips/STM32G031F8.json +++ b/data/chips/STM32G031F8.json @@ -767,7 +767,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -830,7 +830,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031G4.json b/data/chips/STM32G031G4.json index ca7e447..08e318a 100644 --- a/data/chips/STM32G031G4.json +++ b/data/chips/STM32G031G4.json @@ -758,7 +758,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -816,7 +816,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031G6.json b/data/chips/STM32G031G6.json index 53f2197..866376a 100644 --- a/data/chips/STM32G031G6.json +++ b/data/chips/STM32G031G6.json @@ -758,7 +758,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -816,7 +816,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031G8.json b/data/chips/STM32G031G8.json index 83abea8..27c0117 100644 --- a/data/chips/STM32G031G8.json +++ b/data/chips/STM32G031G8.json @@ -758,7 +758,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -816,7 +816,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031J4.json b/data/chips/STM32G031J4.json index 5372325..5321b5a 100644 --- a/data/chips/STM32G031J4.json +++ b/data/chips/STM32G031J4.json @@ -743,7 +743,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -801,7 +801,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031J6.json b/data/chips/STM32G031J6.json index 8656e67..ae9e396 100644 --- a/data/chips/STM32G031J6.json +++ b/data/chips/STM32G031J6.json @@ -743,7 +743,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -801,7 +801,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031K4.json b/data/chips/STM32G031K4.json index 836c985..e21fc4d 100644 --- a/data/chips/STM32G031K4.json +++ b/data/chips/STM32G031K4.json @@ -771,7 +771,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -834,7 +834,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031K6.json b/data/chips/STM32G031K6.json index e465fa9..8e80f91 100644 --- a/data/chips/STM32G031K6.json +++ b/data/chips/STM32G031K6.json @@ -771,7 +771,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -834,7 +834,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031K8.json b/data/chips/STM32G031K8.json index 0829874..3dd8abd 100644 --- a/data/chips/STM32G031K8.json +++ b/data/chips/STM32G031K8.json @@ -771,7 +771,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -834,7 +834,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031Y8.json b/data/chips/STM32G031Y8.json index 79b52ff..7588730 100644 --- a/data/chips/STM32G031Y8.json +++ b/data/chips/STM32G031Y8.json @@ -767,7 +767,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -830,7 +830,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041C6.json b/data/chips/STM32G041C6.json index 23fc3d5..287f4b6 100644 --- a/data/chips/STM32G041C6.json +++ b/data/chips/STM32G041C6.json @@ -830,7 +830,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -893,7 +893,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041C8.json b/data/chips/STM32G041C8.json index 09272e5..d74d9de 100644 --- a/data/chips/STM32G041C8.json +++ b/data/chips/STM32G041C8.json @@ -830,7 +830,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -893,7 +893,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041F6.json b/data/chips/STM32G041F6.json index 2795b4c..b9f7fac 100644 --- a/data/chips/STM32G041F6.json +++ b/data/chips/STM32G041F6.json @@ -806,7 +806,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -869,7 +869,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041F8.json b/data/chips/STM32G041F8.json index 0d6774c..28e62ee 100644 --- a/data/chips/STM32G041F8.json +++ b/data/chips/STM32G041F8.json @@ -806,7 +806,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -869,7 +869,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041G6.json b/data/chips/STM32G041G6.json index d40effc..af77921 100644 --- a/data/chips/STM32G041G6.json +++ b/data/chips/STM32G041G6.json @@ -797,7 +797,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -855,7 +855,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041G8.json b/data/chips/STM32G041G8.json index 8156fe3..3d83288 100644 --- a/data/chips/STM32G041G8.json +++ b/data/chips/STM32G041G8.json @@ -797,7 +797,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -855,7 +855,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041J6.json b/data/chips/STM32G041J6.json index 488808f..2c04d8f 100644 --- a/data/chips/STM32G041J6.json +++ b/data/chips/STM32G041J6.json @@ -782,7 +782,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -840,7 +840,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041K6.json b/data/chips/STM32G041K6.json index f028caf..863eb28 100644 --- a/data/chips/STM32G041K6.json +++ b/data/chips/STM32G041K6.json @@ -810,7 +810,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -873,7 +873,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041K8.json b/data/chips/STM32G041K8.json index f668786..2d00f94 100644 --- a/data/chips/STM32G041K8.json +++ b/data/chips/STM32G041K8.json @@ -810,7 +810,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -873,7 +873,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041Y8.json b/data/chips/STM32G041Y8.json index 5411327..caee030 100644 --- a/data/chips/STM32G041Y8.json +++ b/data/chips/STM32G041Y8.json @@ -806,7 +806,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -869,7 +869,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051C6.json b/data/chips/STM32G051C6.json index fcfb326..996cb9a 100644 --- a/data/chips/STM32G051C6.json +++ b/data/chips/STM32G051C6.json @@ -1158,7 +1158,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1221,7 +1221,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051C8.json b/data/chips/STM32G051C8.json index 0732478..ad12f21 100644 --- a/data/chips/STM32G051C8.json +++ b/data/chips/STM32G051C8.json @@ -1158,7 +1158,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1221,7 +1221,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051F6.json b/data/chips/STM32G051F6.json index d611913..ffdd892 100644 --- a/data/chips/STM32G051F6.json +++ b/data/chips/STM32G051F6.json @@ -1124,7 +1124,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1187,7 +1187,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051F8.json b/data/chips/STM32G051F8.json index 7c20731..3ff06ef 100644 --- a/data/chips/STM32G051F8.json +++ b/data/chips/STM32G051F8.json @@ -1128,7 +1128,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1191,7 +1191,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051G6.json b/data/chips/STM32G051G6.json index 7cd60f3..593c335 100644 --- a/data/chips/STM32G051G6.json +++ b/data/chips/STM32G051G6.json @@ -1111,7 +1111,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1169,7 +1169,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051G8.json b/data/chips/STM32G051G8.json index 2e035f2..3405c13 100644 --- a/data/chips/STM32G051G8.json +++ b/data/chips/STM32G051G8.json @@ -1111,7 +1111,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1169,7 +1169,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051K6.json b/data/chips/STM32G051K6.json index 30c03fa..f68f934 100644 --- a/data/chips/STM32G051K6.json +++ b/data/chips/STM32G051K6.json @@ -1128,7 +1128,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1191,7 +1191,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051K8.json b/data/chips/STM32G051K8.json index 140dd13..fce5b8c 100644 --- a/data/chips/STM32G051K8.json +++ b/data/chips/STM32G051K8.json @@ -1128,7 +1128,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1191,7 +1191,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061C6.json b/data/chips/STM32G061C6.json index 6820913..e8129ae 100644 --- a/data/chips/STM32G061C6.json +++ b/data/chips/STM32G061C6.json @@ -1197,7 +1197,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1260,7 +1260,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061C8.json b/data/chips/STM32G061C8.json index 65aef8f..dba06ea 100644 --- a/data/chips/STM32G061C8.json +++ b/data/chips/STM32G061C8.json @@ -1197,7 +1197,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1260,7 +1260,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061F6.json b/data/chips/STM32G061F6.json index e9f5992..57c908d 100644 --- a/data/chips/STM32G061F6.json +++ b/data/chips/STM32G061F6.json @@ -1163,7 +1163,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1226,7 +1226,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061F8.json b/data/chips/STM32G061F8.json index 4b319a4..20d05a2 100644 --- a/data/chips/STM32G061F8.json +++ b/data/chips/STM32G061F8.json @@ -1167,7 +1167,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1230,7 +1230,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061G6.json b/data/chips/STM32G061G6.json index de1b413..56e4fc3 100644 --- a/data/chips/STM32G061G6.json +++ b/data/chips/STM32G061G6.json @@ -1150,7 +1150,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1208,7 +1208,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061G8.json b/data/chips/STM32G061G8.json index 94e4c2e..04ed313 100644 --- a/data/chips/STM32G061G8.json +++ b/data/chips/STM32G061G8.json @@ -1150,7 +1150,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1208,7 +1208,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061K6.json b/data/chips/STM32G061K6.json index c0b9786..41229cd 100644 --- a/data/chips/STM32G061K6.json +++ b/data/chips/STM32G061K6.json @@ -1167,7 +1167,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1230,7 +1230,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061K8.json b/data/chips/STM32G061K8.json index d321bff..bca4486 100644 --- a/data/chips/STM32G061K8.json +++ b/data/chips/STM32G061K8.json @@ -1167,7 +1167,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1230,7 +1230,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071C6.json b/data/chips/STM32G071C6.json index 39946f6..17612b0 100644 --- a/data/chips/STM32G071C6.json +++ b/data/chips/STM32G071C6.json @@ -813,7 +813,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -876,7 +876,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071C8.json b/data/chips/STM32G071C8.json index 7567a99..bd1a38c 100644 --- a/data/chips/STM32G071C8.json +++ b/data/chips/STM32G071C8.json @@ -988,7 +988,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1051,7 +1051,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071CB.json b/data/chips/STM32G071CB.json index 2a060a4..abde1d8 100644 --- a/data/chips/STM32G071CB.json +++ b/data/chips/STM32G071CB.json @@ -988,7 +988,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1051,7 +1051,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071EB.json b/data/chips/STM32G071EB.json index f78bd25..2fc85de 100644 --- a/data/chips/STM32G071EB.json +++ b/data/chips/STM32G071EB.json @@ -921,7 +921,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -979,7 +979,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071G6.json b/data/chips/STM32G071G6.json index 32a01d8..3c698e5 100644 --- a/data/chips/STM32G071G6.json +++ b/data/chips/STM32G071G6.json @@ -754,7 +754,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -812,7 +812,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071G8.json b/data/chips/STM32G071G8.json index a64ef17..df4a778 100644 --- a/data/chips/STM32G071G8.json +++ b/data/chips/STM32G071G8.json @@ -933,7 +933,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -991,7 +991,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071GB.json b/data/chips/STM32G071GB.json index a93b888..4d7c497 100644 --- a/data/chips/STM32G071GB.json +++ b/data/chips/STM32G071GB.json @@ -933,7 +933,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -991,7 +991,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071K6.json b/data/chips/STM32G071K6.json index b9030eb..09dee30 100644 --- a/data/chips/STM32G071K6.json +++ b/data/chips/STM32G071K6.json @@ -771,7 +771,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -834,7 +834,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071K8.json b/data/chips/STM32G071K8.json index 7174eac..c4bfda6 100644 --- a/data/chips/STM32G071K8.json +++ b/data/chips/STM32G071K8.json @@ -954,7 +954,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1017,7 +1017,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071KB.json b/data/chips/STM32G071KB.json index 6924132..213cfda 100644 --- a/data/chips/STM32G071KB.json +++ b/data/chips/STM32G071KB.json @@ -954,7 +954,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1017,7 +1017,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071R6.json b/data/chips/STM32G071R6.json index 068b974..659710e 100644 --- a/data/chips/STM32G071R6.json +++ b/data/chips/STM32G071R6.json @@ -825,7 +825,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -918,7 +918,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071R8.json b/data/chips/STM32G071R8.json index 96f4ca2..9c7d698 100644 --- a/data/chips/STM32G071R8.json +++ b/data/chips/STM32G071R8.json @@ -1000,7 +1000,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1093,7 +1093,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071RB.json b/data/chips/STM32G071RB.json index 7ce8afa..b38a83b 100644 --- a/data/chips/STM32G071RB.json +++ b/data/chips/STM32G071RB.json @@ -1004,7 +1004,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1097,7 +1097,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G081CB.json b/data/chips/STM32G081CB.json index 1244d55..fc3dc3a 100644 --- a/data/chips/STM32G081CB.json +++ b/data/chips/STM32G081CB.json @@ -1027,7 +1027,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1090,7 +1090,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G081EB.json b/data/chips/STM32G081EB.json index aff6578..e300a41 100644 --- a/data/chips/STM32G081EB.json +++ b/data/chips/STM32G081EB.json @@ -960,7 +960,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1018,7 +1018,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G081GB.json b/data/chips/STM32G081GB.json index 27f9df3..0793413 100644 --- a/data/chips/STM32G081GB.json +++ b/data/chips/STM32G081GB.json @@ -972,7 +972,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1030,7 +1030,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G081KB.json b/data/chips/STM32G081KB.json index 46b9ef8..6fcebb6 100644 --- a/data/chips/STM32G081KB.json +++ b/data/chips/STM32G081KB.json @@ -993,7 +993,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1056,7 +1056,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G081RB.json b/data/chips/STM32G081RB.json index b4a3da0..c0751bc 100644 --- a/data/chips/STM32G081RB.json +++ b/data/chips/STM32G081RB.json @@ -1043,7 +1043,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1136,7 +1136,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1CB.json b/data/chips/STM32G0B1CB.json index a8462e2..8d015e8 100644 --- a/data/chips/STM32G0B1CB.json +++ b/data/chips/STM32G0B1CB.json @@ -1539,7 +1539,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1602,7 +1602,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1CC.json b/data/chips/STM32G0B1CC.json index 8e06fa7..0698037 100644 --- a/data/chips/STM32G0B1CC.json +++ b/data/chips/STM32G0B1CC.json @@ -1539,7 +1539,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1602,7 +1602,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1CE.json b/data/chips/STM32G0B1CE.json index d852994..e736d2e 100644 --- a/data/chips/STM32G0B1CE.json +++ b/data/chips/STM32G0B1CE.json @@ -1550,7 +1550,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1613,7 +1613,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1KB.json b/data/chips/STM32G0B1KB.json index 29b0adc..1c155ba 100644 --- a/data/chips/STM32G0B1KB.json +++ b/data/chips/STM32G0B1KB.json @@ -1482,7 +1482,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1545,7 +1545,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1KC.json b/data/chips/STM32G0B1KC.json index 0f512d2..15c3763 100644 --- a/data/chips/STM32G0B1KC.json +++ b/data/chips/STM32G0B1KC.json @@ -1482,7 +1482,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1545,7 +1545,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1KE.json b/data/chips/STM32G0B1KE.json index e9755fa..e39b642 100644 --- a/data/chips/STM32G0B1KE.json +++ b/data/chips/STM32G0B1KE.json @@ -1493,7 +1493,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1556,7 +1556,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1MB.json b/data/chips/STM32G0B1MB.json index 952339f..b7891b3 100644 --- a/data/chips/STM32G0B1MB.json +++ b/data/chips/STM32G0B1MB.json @@ -1619,7 +1619,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1712,7 +1712,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1MC.json b/data/chips/STM32G0B1MC.json index 0e85fbd..f728841 100644 --- a/data/chips/STM32G0B1MC.json +++ b/data/chips/STM32G0B1MC.json @@ -1619,7 +1619,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1712,7 +1712,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1ME.json b/data/chips/STM32G0B1ME.json index fcda554..00115c5 100644 --- a/data/chips/STM32G0B1ME.json +++ b/data/chips/STM32G0B1ME.json @@ -1630,7 +1630,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1723,7 +1723,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1NE.json b/data/chips/STM32G0B1NE.json index c3c2ae1..937cef6 100644 --- a/data/chips/STM32G0B1NE.json +++ b/data/chips/STM32G0B1NE.json @@ -1209,7 +1209,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1272,7 +1272,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1RB.json b/data/chips/STM32G0B1RB.json index c16d211..8fc5d06 100644 --- a/data/chips/STM32G0B1RB.json +++ b/data/chips/STM32G0B1RB.json @@ -1599,7 +1599,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1692,7 +1692,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1RC.json b/data/chips/STM32G0B1RC.json index 2b2d31d..eeddb16 100644 --- a/data/chips/STM32G0B1RC.json +++ b/data/chips/STM32G0B1RC.json @@ -1599,7 +1599,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1692,7 +1692,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1RE.json b/data/chips/STM32G0B1RE.json index 26ce16e..6587eec 100644 --- a/data/chips/STM32G0B1RE.json +++ b/data/chips/STM32G0B1RE.json @@ -1610,7 +1610,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1703,7 +1703,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1VB.json b/data/chips/STM32G0B1VB.json index aebb8ae..be3ce11 100644 --- a/data/chips/STM32G0B1VB.json +++ b/data/chips/STM32G0B1VB.json @@ -1623,7 +1623,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1716,7 +1716,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1VC.json b/data/chips/STM32G0B1VC.json index ca35907..9d5aacc 100644 --- a/data/chips/STM32G0B1VC.json +++ b/data/chips/STM32G0B1VC.json @@ -1623,7 +1623,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1716,7 +1716,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1VE.json b/data/chips/STM32G0B1VE.json index 9e940da..574a5fc 100644 --- a/data/chips/STM32G0B1VE.json +++ b/data/chips/STM32G0B1VE.json @@ -1634,7 +1634,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1727,7 +1727,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1CC.json b/data/chips/STM32G0C1CC.json index 8f6f5c8..a858881 100644 --- a/data/chips/STM32G0C1CC.json +++ b/data/chips/STM32G0C1CC.json @@ -1578,7 +1578,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1641,7 +1641,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1CE.json b/data/chips/STM32G0C1CE.json index 56eb9e2..ccb2a21 100644 --- a/data/chips/STM32G0C1CE.json +++ b/data/chips/STM32G0C1CE.json @@ -1589,7 +1589,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1652,7 +1652,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1KC.json b/data/chips/STM32G0C1KC.json index f4e3bcb..50d642c 100644 --- a/data/chips/STM32G0C1KC.json +++ b/data/chips/STM32G0C1KC.json @@ -1521,7 +1521,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1584,7 +1584,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1KE.json b/data/chips/STM32G0C1KE.json index cada766..d08624e 100644 --- a/data/chips/STM32G0C1KE.json +++ b/data/chips/STM32G0C1KE.json @@ -1532,7 +1532,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1595,7 +1595,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1MC.json b/data/chips/STM32G0C1MC.json index 57c5170..a99738c 100644 --- a/data/chips/STM32G0C1MC.json +++ b/data/chips/STM32G0C1MC.json @@ -1658,7 +1658,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1751,7 +1751,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1ME.json b/data/chips/STM32G0C1ME.json index 4df1836..5cf95d4 100644 --- a/data/chips/STM32G0C1ME.json +++ b/data/chips/STM32G0C1ME.json @@ -1669,7 +1669,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1762,7 +1762,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1NE.json b/data/chips/STM32G0C1NE.json index c97aed4..bd58608 100644 --- a/data/chips/STM32G0C1NE.json +++ b/data/chips/STM32G0C1NE.json @@ -1248,7 +1248,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1311,7 +1311,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1RC.json b/data/chips/STM32G0C1RC.json index 05db5be..fa8ea17 100644 --- a/data/chips/STM32G0C1RC.json +++ b/data/chips/STM32G0C1RC.json @@ -1638,7 +1638,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1731,7 +1731,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1RE.json b/data/chips/STM32G0C1RE.json index 7a30435..b306ecb 100644 --- a/data/chips/STM32G0C1RE.json +++ b/data/chips/STM32G0C1RE.json @@ -1649,7 +1649,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1742,7 +1742,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1VC.json b/data/chips/STM32G0C1VC.json index 5e614fd..53c3d41 100644 --- a/data/chips/STM32G0C1VC.json +++ b/data/chips/STM32G0C1VC.json @@ -1662,7 +1662,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1755,7 +1755,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1VE.json b/data/chips/STM32G0C1VE.json index b3fbf70..29a09cb 100644 --- a/data/chips/STM32G0C1VE.json +++ b/data/chips/STM32G0C1VE.json @@ -1673,7 +1673,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1766,7 +1766,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431C6.json b/data/chips/STM32G431C6.json index cc8749d..76b1e2c 100644 --- a/data/chips/STM32G431C6.json +++ b/data/chips/STM32G431C6.json @@ -1504,7 +1504,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431C8.json b/data/chips/STM32G431C8.json index ac51750..5caace5 100644 --- a/data/chips/STM32G431C8.json +++ b/data/chips/STM32G431C8.json @@ -1504,7 +1504,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431CB.json b/data/chips/STM32G431CB.json index 6b89af6..aaa0556 100644 --- a/data/chips/STM32G431CB.json +++ b/data/chips/STM32G431CB.json @@ -1508,7 +1508,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431K6.json b/data/chips/STM32G431K6.json index f198ca6..1d6c006 100644 --- a/data/chips/STM32G431K6.json +++ b/data/chips/STM32G431K6.json @@ -1414,7 +1414,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431K8.json b/data/chips/STM32G431K8.json index b1930dd..8bab119 100644 --- a/data/chips/STM32G431K8.json +++ b/data/chips/STM32G431K8.json @@ -1414,7 +1414,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431KB.json b/data/chips/STM32G431KB.json index bc67b26..b1cd993 100644 --- a/data/chips/STM32G431KB.json +++ b/data/chips/STM32G431KB.json @@ -1414,7 +1414,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431M6.json b/data/chips/STM32G431M6.json index 8d4775d..bf5a1dd 100644 --- a/data/chips/STM32G431M6.json +++ b/data/chips/STM32G431M6.json @@ -1577,7 +1577,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431M8.json b/data/chips/STM32G431M8.json index 6b52d4c..d98332b 100644 --- a/data/chips/STM32G431M8.json +++ b/data/chips/STM32G431M8.json @@ -1577,7 +1577,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431MB.json b/data/chips/STM32G431MB.json index b1c7786..ee7aa20 100644 --- a/data/chips/STM32G431MB.json +++ b/data/chips/STM32G431MB.json @@ -1577,7 +1577,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431R6.json b/data/chips/STM32G431R6.json index 7217244..c863961 100644 --- a/data/chips/STM32G431R6.json +++ b/data/chips/STM32G431R6.json @@ -1563,7 +1563,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431R8.json b/data/chips/STM32G431R8.json index e0f78d9..33a439c 100644 --- a/data/chips/STM32G431R8.json +++ b/data/chips/STM32G431R8.json @@ -1563,7 +1563,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431RB.json b/data/chips/STM32G431RB.json index c402b7c..32b38e6 100644 --- a/data/chips/STM32G431RB.json +++ b/data/chips/STM32G431RB.json @@ -1563,7 +1563,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431V6.json b/data/chips/STM32G431V6.json index a6b5e47..55a53b0 100644 --- a/data/chips/STM32G431V6.json +++ b/data/chips/STM32G431V6.json @@ -1582,7 +1582,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431V8.json b/data/chips/STM32G431V8.json index 93bcb8a..ec6f884 100644 --- a/data/chips/STM32G431V8.json +++ b/data/chips/STM32G431V8.json @@ -1582,7 +1582,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431VB.json b/data/chips/STM32G431VB.json index e46d947..4f016fc 100644 --- a/data/chips/STM32G431VB.json +++ b/data/chips/STM32G431VB.json @@ -1582,7 +1582,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G441CB.json b/data/chips/STM32G441CB.json index 56e857d..c0b4b2d 100644 --- a/data/chips/STM32G441CB.json +++ b/data/chips/STM32G441CB.json @@ -1541,7 +1541,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G441KB.json b/data/chips/STM32G441KB.json index a42ce0b..f818789 100644 --- a/data/chips/STM32G441KB.json +++ b/data/chips/STM32G441KB.json @@ -1447,7 +1447,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G441MB.json b/data/chips/STM32G441MB.json index 56c1baf..4a9f7f9 100644 --- a/data/chips/STM32G441MB.json +++ b/data/chips/STM32G441MB.json @@ -1610,7 +1610,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G441RB.json b/data/chips/STM32G441RB.json index dbb101d..6ad822e 100644 --- a/data/chips/STM32G441RB.json +++ b/data/chips/STM32G441RB.json @@ -1596,7 +1596,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G441VB.json b/data/chips/STM32G441VB.json index cb3656e..477d4a5 100644 --- a/data/chips/STM32G441VB.json +++ b/data/chips/STM32G441VB.json @@ -1615,7 +1615,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471CC.json b/data/chips/STM32G471CC.json index 176fda1..0559fcf 100644 --- a/data/chips/STM32G471CC.json +++ b/data/chips/STM32G471CC.json @@ -1496,7 +1496,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471CE.json b/data/chips/STM32G471CE.json index ee0757f..a3b3c79 100644 --- a/data/chips/STM32G471CE.json +++ b/data/chips/STM32G471CE.json @@ -1496,7 +1496,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471MC.json b/data/chips/STM32G471MC.json index ad0718a..846ec2d 100644 --- a/data/chips/STM32G471MC.json +++ b/data/chips/STM32G471MC.json @@ -1615,7 +1615,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471ME.json b/data/chips/STM32G471ME.json index 5a37b59..d2314da 100644 --- a/data/chips/STM32G471ME.json +++ b/data/chips/STM32G471ME.json @@ -1619,7 +1619,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471QC.json b/data/chips/STM32G471QC.json index 8a77141..d37c1fe 100644 --- a/data/chips/STM32G471QC.json +++ b/data/chips/STM32G471QC.json @@ -1692,7 +1692,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471QE.json b/data/chips/STM32G471QE.json index b788440..f017f68 100644 --- a/data/chips/STM32G471QE.json +++ b/data/chips/STM32G471QE.json @@ -1692,7 +1692,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471RC.json b/data/chips/STM32G471RC.json index 1c5b7e5..911bd9b 100644 --- a/data/chips/STM32G471RC.json +++ b/data/chips/STM32G471RC.json @@ -1556,7 +1556,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471RE.json b/data/chips/STM32G471RE.json index 0666314..84c32dc 100644 --- a/data/chips/STM32G471RE.json +++ b/data/chips/STM32G471RE.json @@ -1556,7 +1556,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471VC.json b/data/chips/STM32G471VC.json index 22bce85..b3121dc 100644 --- a/data/chips/STM32G471VC.json +++ b/data/chips/STM32G471VC.json @@ -1640,7 +1640,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471VE.json b/data/chips/STM32G471VE.json index 8a3b432..a91d37d 100644 --- a/data/chips/STM32G471VE.json +++ b/data/chips/STM32G471VE.json @@ -1640,7 +1640,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473CB.json b/data/chips/STM32G473CB.json index fdb2fd1..571e378 100644 --- a/data/chips/STM32G473CB.json +++ b/data/chips/STM32G473CB.json @@ -2032,7 +2032,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473CC.json b/data/chips/STM32G473CC.json index 2869f16..b853888 100644 --- a/data/chips/STM32G473CC.json +++ b/data/chips/STM32G473CC.json @@ -2032,7 +2032,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473CE.json b/data/chips/STM32G473CE.json index aa48016..ac79a07 100644 --- a/data/chips/STM32G473CE.json +++ b/data/chips/STM32G473CE.json @@ -2032,7 +2032,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473MB.json b/data/chips/STM32G473MB.json index bf3f6f4..6727aea 100644 --- a/data/chips/STM32G473MB.json +++ b/data/chips/STM32G473MB.json @@ -2241,7 +2241,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473MC.json b/data/chips/STM32G473MC.json index 5139688..d0989f9 100644 --- a/data/chips/STM32G473MC.json +++ b/data/chips/STM32G473MC.json @@ -2241,7 +2241,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473ME.json b/data/chips/STM32G473ME.json index 0471469..c9e54c6 100644 --- a/data/chips/STM32G473ME.json +++ b/data/chips/STM32G473ME.json @@ -2245,7 +2245,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473PB.json b/data/chips/STM32G473PB.json index b4935d2..7deeb2e 100644 --- a/data/chips/STM32G473PB.json +++ b/data/chips/STM32G473PB.json @@ -2704,7 +2704,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473PC.json b/data/chips/STM32G473PC.json index d555957..6c3deb0 100644 --- a/data/chips/STM32G473PC.json +++ b/data/chips/STM32G473PC.json @@ -2704,7 +2704,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473PE.json b/data/chips/STM32G473PE.json index 46cc21f..4d5c0fe 100644 --- a/data/chips/STM32G473PE.json +++ b/data/chips/STM32G473PE.json @@ -2704,7 +2704,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473QB.json b/data/chips/STM32G473QB.json index 069fd18..2ac4506 100644 --- a/data/chips/STM32G473QB.json +++ b/data/chips/STM32G473QB.json @@ -2755,7 +2755,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473QC.json b/data/chips/STM32G473QC.json index 80cedcd..70cff40 100644 --- a/data/chips/STM32G473QC.json +++ b/data/chips/STM32G473QC.json @@ -2755,7 +2755,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473QE.json b/data/chips/STM32G473QE.json index 41675fd..5738d72 100644 --- a/data/chips/STM32G473QE.json +++ b/data/chips/STM32G473QE.json @@ -2755,7 +2755,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473RB.json b/data/chips/STM32G473RB.json index 66b3586..f1e03a8 100644 --- a/data/chips/STM32G473RB.json +++ b/data/chips/STM32G473RB.json @@ -2102,7 +2102,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473RC.json b/data/chips/STM32G473RC.json index 323bbb7..9f54611 100644 --- a/data/chips/STM32G473RC.json +++ b/data/chips/STM32G473RC.json @@ -2102,7 +2102,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473RE.json b/data/chips/STM32G473RE.json index ec552c7..20dd66b 100644 --- a/data/chips/STM32G473RE.json +++ b/data/chips/STM32G473RE.json @@ -2102,7 +2102,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473VB.json b/data/chips/STM32G473VB.json index 7c26027..a10f33f 100644 --- a/data/chips/STM32G473VB.json +++ b/data/chips/STM32G473VB.json @@ -2594,7 +2594,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473VC.json b/data/chips/STM32G473VC.json index bbc6211..260e2b8 100644 --- a/data/chips/STM32G473VC.json +++ b/data/chips/STM32G473VC.json @@ -2594,7 +2594,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473VE.json b/data/chips/STM32G473VE.json index 7474028..bf769b7 100644 --- a/data/chips/STM32G473VE.json +++ b/data/chips/STM32G473VE.json @@ -2594,7 +2594,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474CB.json b/data/chips/STM32G474CB.json index a6020b2..9af09df 100644 --- a/data/chips/STM32G474CB.json +++ b/data/chips/STM32G474CB.json @@ -2278,7 +2278,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474CC.json b/data/chips/STM32G474CC.json index e7dec88..e4d5ba9 100644 --- a/data/chips/STM32G474CC.json +++ b/data/chips/STM32G474CC.json @@ -2278,7 +2278,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474CE.json b/data/chips/STM32G474CE.json index c869c01..6acea5e 100644 --- a/data/chips/STM32G474CE.json +++ b/data/chips/STM32G474CE.json @@ -2278,7 +2278,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474MB.json b/data/chips/STM32G474MB.json index e725d0b..673e41d 100644 --- a/data/chips/STM32G474MB.json +++ b/data/chips/STM32G474MB.json @@ -2517,7 +2517,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474MC.json b/data/chips/STM32G474MC.json index 8608285..f4e8408 100644 --- a/data/chips/STM32G474MC.json +++ b/data/chips/STM32G474MC.json @@ -2517,7 +2517,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474ME.json b/data/chips/STM32G474ME.json index 4e0f739..19b43a1 100644 --- a/data/chips/STM32G474ME.json +++ b/data/chips/STM32G474ME.json @@ -2521,7 +2521,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474PB.json b/data/chips/STM32G474PB.json index 903430c..6d78843 100644 --- a/data/chips/STM32G474PB.json +++ b/data/chips/STM32G474PB.json @@ -2968,7 +2968,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474PC.json b/data/chips/STM32G474PC.json index f851b64..a10df50 100644 --- a/data/chips/STM32G474PC.json +++ b/data/chips/STM32G474PC.json @@ -2968,7 +2968,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474PE.json b/data/chips/STM32G474PE.json index 7567e5a..dec6ab9 100644 --- a/data/chips/STM32G474PE.json +++ b/data/chips/STM32G474PE.json @@ -2968,7 +2968,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474QB.json b/data/chips/STM32G474QB.json index cb820fe..7f7c977 100644 --- a/data/chips/STM32G474QB.json +++ b/data/chips/STM32G474QB.json @@ -3031,7 +3031,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474QC.json b/data/chips/STM32G474QC.json index aec0f3c..439fe4b 100644 --- a/data/chips/STM32G474QC.json +++ b/data/chips/STM32G474QC.json @@ -3031,7 +3031,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474QE.json b/data/chips/STM32G474QE.json index ae13b6b..9ae2ba3 100644 --- a/data/chips/STM32G474QE.json +++ b/data/chips/STM32G474QE.json @@ -3031,7 +3031,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474RB.json b/data/chips/STM32G474RB.json index 33ae23c..281d67f 100644 --- a/data/chips/STM32G474RB.json +++ b/data/chips/STM32G474RB.json @@ -2378,7 +2378,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474RC.json b/data/chips/STM32G474RC.json index 947f99f..9d2e358 100644 --- a/data/chips/STM32G474RC.json +++ b/data/chips/STM32G474RC.json @@ -2378,7 +2378,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474RE.json b/data/chips/STM32G474RE.json index 72b4706..85cd309 100644 --- a/data/chips/STM32G474RE.json +++ b/data/chips/STM32G474RE.json @@ -2378,7 +2378,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474VB.json b/data/chips/STM32G474VB.json index cb16274..595fe54 100644 --- a/data/chips/STM32G474VB.json +++ b/data/chips/STM32G474VB.json @@ -2870,7 +2870,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474VC.json b/data/chips/STM32G474VC.json index a29cc41..fcae400 100644 --- a/data/chips/STM32G474VC.json +++ b/data/chips/STM32G474VC.json @@ -2870,7 +2870,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474VE.json b/data/chips/STM32G474VE.json index 9cd1563..50d760b 100644 --- a/data/chips/STM32G474VE.json +++ b/data/chips/STM32G474VE.json @@ -2870,7 +2870,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483CE.json b/data/chips/STM32G483CE.json index 1e8a371..4ef35ec 100644 --- a/data/chips/STM32G483CE.json +++ b/data/chips/STM32G483CE.json @@ -2071,7 +2071,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483ME.json b/data/chips/STM32G483ME.json index 5a88abc..1339c08 100644 --- a/data/chips/STM32G483ME.json +++ b/data/chips/STM32G483ME.json @@ -2284,7 +2284,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483PE.json b/data/chips/STM32G483PE.json index 7a3b112..4249106 100644 --- a/data/chips/STM32G483PE.json +++ b/data/chips/STM32G483PE.json @@ -2743,7 +2743,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483QE.json b/data/chips/STM32G483QE.json index e541e7a..3afadb0 100644 --- a/data/chips/STM32G483QE.json +++ b/data/chips/STM32G483QE.json @@ -2794,7 +2794,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483RE.json b/data/chips/STM32G483RE.json index 2dd8440..899e816 100644 --- a/data/chips/STM32G483RE.json +++ b/data/chips/STM32G483RE.json @@ -2141,7 +2141,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483VE.json b/data/chips/STM32G483VE.json index f0a0aef..094b86c 100644 --- a/data/chips/STM32G483VE.json +++ b/data/chips/STM32G483VE.json @@ -2633,7 +2633,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484CE.json b/data/chips/STM32G484CE.json index e8b2c22..d732013 100644 --- a/data/chips/STM32G484CE.json +++ b/data/chips/STM32G484CE.json @@ -2311,7 +2311,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484ME.json b/data/chips/STM32G484ME.json index 666004e..81d4e09 100644 --- a/data/chips/STM32G484ME.json +++ b/data/chips/STM32G484ME.json @@ -2554,7 +2554,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484PE.json b/data/chips/STM32G484PE.json index c19146c..4103a0f 100644 --- a/data/chips/STM32G484PE.json +++ b/data/chips/STM32G484PE.json @@ -3007,7 +3007,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484QE.json b/data/chips/STM32G484QE.json index 3a35fff..d393ab2 100644 --- a/data/chips/STM32G484QE.json +++ b/data/chips/STM32G484QE.json @@ -3064,7 +3064,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484RE.json b/data/chips/STM32G484RE.json index 5e37669..f60a117 100644 --- a/data/chips/STM32G484RE.json +++ b/data/chips/STM32G484RE.json @@ -2411,7 +2411,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484VE.json b/data/chips/STM32G484VE.json index 1a5d366..0c5467f 100644 --- a/data/chips/STM32G484VE.json +++ b/data/chips/STM32G484VE.json @@ -2903,7 +2903,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491CC.json b/data/chips/STM32G491CC.json index b088778..419a6ca 100644 --- a/data/chips/STM32G491CC.json +++ b/data/chips/STM32G491CC.json @@ -1624,7 +1624,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491CE.json b/data/chips/STM32G491CE.json index 45e0f5a..e49d873 100644 --- a/data/chips/STM32G491CE.json +++ b/data/chips/STM32G491CE.json @@ -1624,7 +1624,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491KC.json b/data/chips/STM32G491KC.json index 12f2d24..1c1c244 100644 --- a/data/chips/STM32G491KC.json +++ b/data/chips/STM32G491KC.json @@ -1512,7 +1512,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491KE.json b/data/chips/STM32G491KE.json index 37bf336..4040687 100644 --- a/data/chips/STM32G491KE.json +++ b/data/chips/STM32G491KE.json @@ -1512,7 +1512,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491MC.json b/data/chips/STM32G491MC.json index 749d512..dfa2e13 100644 --- a/data/chips/STM32G491MC.json +++ b/data/chips/STM32G491MC.json @@ -1733,7 +1733,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491ME.json b/data/chips/STM32G491ME.json index c4e39ee..c5567ab 100644 --- a/data/chips/STM32G491ME.json +++ b/data/chips/STM32G491ME.json @@ -1733,7 +1733,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491RC.json b/data/chips/STM32G491RC.json index adb68e2..961f500 100644 --- a/data/chips/STM32G491RC.json +++ b/data/chips/STM32G491RC.json @@ -1683,7 +1683,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491RE.json b/data/chips/STM32G491RE.json index a3817d1..5707922 100644 --- a/data/chips/STM32G491RE.json +++ b/data/chips/STM32G491RE.json @@ -1687,7 +1687,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491VC.json b/data/chips/STM32G491VC.json index 5b52c70..2d2c3d2 100644 --- a/data/chips/STM32G491VC.json +++ b/data/chips/STM32G491VC.json @@ -1750,7 +1750,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491VE.json b/data/chips/STM32G491VE.json index 696be28..49efc8d 100644 --- a/data/chips/STM32G491VE.json +++ b/data/chips/STM32G491VE.json @@ -1750,7 +1750,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G4A1CE.json b/data/chips/STM32G4A1CE.json index d405a6b..c90540f 100644 --- a/data/chips/STM32G4A1CE.json +++ b/data/chips/STM32G4A1CE.json @@ -1663,7 +1663,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G4A1KE.json b/data/chips/STM32G4A1KE.json index 8d3f397..06664b4 100644 --- a/data/chips/STM32G4A1KE.json +++ b/data/chips/STM32G4A1KE.json @@ -1551,7 +1551,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G4A1ME.json b/data/chips/STM32G4A1ME.json index 8e61d04..7a0c4a6 100644 --- a/data/chips/STM32G4A1ME.json +++ b/data/chips/STM32G4A1ME.json @@ -1772,7 +1772,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G4A1RE.json b/data/chips/STM32G4A1RE.json index a92aa50..1c66ca9 100644 --- a/data/chips/STM32G4A1RE.json +++ b/data/chips/STM32G4A1RE.json @@ -1726,7 +1726,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G4A1VE.json b/data/chips/STM32G4A1VE.json index 02793d1..c000969 100644 --- a/data/chips/STM32G4A1VE.json +++ b/data/chips/STM32G4A1VE.json @@ -1789,7 +1789,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H503CB.json b/data/chips/STM32H503CB.json index 956d368..40718a8 100644 --- a/data/chips/STM32H503CB.json +++ b/data/chips/STM32H503CB.json @@ -1255,7 +1255,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1415,7 +1415,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H503EB.json b/data/chips/STM32H503EB.json index 66a1213..9542abe 100644 --- a/data/chips/STM32H503EB.json +++ b/data/chips/STM32H503EB.json @@ -1143,7 +1143,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1268,7 +1268,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H503KB.json b/data/chips/STM32H503KB.json index ef5375f..e31fa9a 100644 --- a/data/chips/STM32H503KB.json +++ b/data/chips/STM32H503KB.json @@ -1192,7 +1192,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1337,7 +1337,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H503RB.json b/data/chips/STM32H503RB.json index ea19f4b..b633593 100644 --- a/data/chips/STM32H503RB.json +++ b/data/chips/STM32H503RB.json @@ -1405,7 +1405,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1575,7 +1575,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index 95fb1e3..789297f 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -2659,7 +2659,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2804,7 +2804,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2929,7 +2929,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3069,7 +3069,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3127,7 +3127,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3257,7 +3257,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index 44bcf6f..eb8cdb5 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -2670,7 +2670,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2815,7 +2815,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2940,7 +2940,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3080,7 +3080,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3138,7 +3138,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3268,7 +3268,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index 041763c..e69c659 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -2688,7 +2688,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2833,7 +2833,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2958,7 +2958,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3098,7 +3098,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3156,7 +3156,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3286,7 +3286,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index 434c564..1396a8c 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -2699,7 +2699,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2844,7 +2844,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2969,7 +2969,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3109,7 +3109,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3167,7 +3167,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3297,7 +3297,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index 9f2ec9e..396a1f6 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -1765,7 +1765,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1860,7 +1860,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1975,7 +1975,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2085,7 +2085,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2123,7 +2123,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2193,7 +2193,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index 129cb78..e29ca85 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -1776,7 +1776,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1871,7 +1871,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1986,7 +1986,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2096,7 +2096,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2134,7 +2134,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2204,7 +2204,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index 7c5d587..7463cbf 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -2195,7 +2195,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2300,7 +2300,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2420,7 +2420,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2530,7 +2530,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2578,7 +2578,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2648,7 +2648,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index 7d9810a..9900cf9 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -2206,7 +2206,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2311,7 +2311,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2431,7 +2431,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2541,7 +2541,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2589,7 +2589,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2659,7 +2659,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index 3d19e96..12db487 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -2469,7 +2469,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2599,7 +2599,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2719,7 +2719,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2859,7 +2859,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2917,7 +2917,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3047,7 +3047,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index 8e1c0c5..70069bc 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -2480,7 +2480,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2610,7 +2610,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2730,7 +2730,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2870,7 +2870,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2928,7 +2928,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3058,7 +3058,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index 36f0aa0..ac35217 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -2932,7 +2932,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3077,7 +3077,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3202,7 +3202,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3342,7 +3342,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3400,7 +3400,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3530,7 +3530,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index bcc01bc..58e7af6 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -2962,7 +2962,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3107,7 +3107,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3232,7 +3232,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3372,7 +3372,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3430,7 +3430,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3560,7 +3560,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 46066b1..848bf7f 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -2966,7 +2966,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3111,7 +3111,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3236,7 +3236,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3376,7 +3376,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3434,7 +3434,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3564,7 +3564,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index 856e280..d679f30 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -2985,7 +2985,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3130,7 +3130,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3255,7 +3255,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3395,7 +3395,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3453,7 +3453,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3583,7 +3583,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index 77ce238..594b1d8 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -2149,7 +2149,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2234,7 +2234,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2324,7 +2324,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2434,7 +2434,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2472,7 +2472,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2542,7 +2542,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index a29458e..3823da1 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -1983,7 +1983,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2078,7 +2078,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2193,7 +2193,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2303,7 +2303,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2341,7 +2341,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2411,7 +2411,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index 9040b21..617d4ad 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -1994,7 +1994,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2089,7 +2089,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2204,7 +2204,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2314,7 +2314,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2352,7 +2352,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2422,7 +2422,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index eb7b782..940b5e8 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -2418,7 +2418,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2523,7 +2523,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2643,7 +2643,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2753,7 +2753,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2801,7 +2801,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2871,7 +2871,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index 639c002..e900eb1 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -2443,7 +2443,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2548,7 +2548,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2673,7 +2673,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2783,7 +2783,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2831,7 +2831,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2901,7 +2901,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index 966dc47..98837dc 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -2717,7 +2717,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2847,7 +2847,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2967,7 +2967,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3107,7 +3107,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3165,7 +3165,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3295,7 +3295,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index b326d3a..aeb66fe 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -2757,7 +2757,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2892,7 +2892,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3017,7 +3017,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3157,7 +3157,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3215,7 +3215,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3345,7 +3345,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 0bba33e..1d4af90 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -3021,7 +3021,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3166,7 +3166,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3291,7 +3291,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3431,7 +3431,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3489,7 +3489,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3619,7 +3619,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index da94f30..e4921ab 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -3044,7 +3044,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3189,7 +3189,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3314,7 +3314,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3454,7 +3454,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3512,7 +3512,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3642,7 +3642,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index f1bd971..19ee055 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -2208,7 +2208,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2293,7 +2293,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2383,7 +2383,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2493,7 +2493,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2531,7 +2531,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2601,7 +2601,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index 96e5bfa..4b87afe 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -2053,7 +2053,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2148,7 +2148,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2263,7 +2263,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2373,7 +2373,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2411,7 +2411,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2481,7 +2481,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index 68c7e8a..d8f4989 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -2502,7 +2502,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2607,7 +2607,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2732,7 +2732,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2842,7 +2842,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -2890,7 +2890,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2960,7 +2960,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index 75117e6..69685d7 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -2816,7 +2816,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2951,7 +2951,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3076,7 +3076,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3216,7 +3216,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { @@ -3274,7 +3274,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3404,7 +3404,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H723VE.json b/data/chips/STM32H723VE.json index 2cc3731..72c909b 100644 --- a/data/chips/STM32H723VE.json +++ b/data/chips/STM32H723VE.json @@ -3083,7 +3083,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3136,7 +3136,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3199,7 +3199,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3234,7 +3234,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3269,7 +3269,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H723VG.json b/data/chips/STM32H723VG.json index 88d3559..1631818 100644 --- a/data/chips/STM32H723VG.json +++ b/data/chips/STM32H723VG.json @@ -3083,7 +3083,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3136,7 +3136,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3199,7 +3199,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3234,7 +3234,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3269,7 +3269,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H723ZE.json b/data/chips/STM32H723ZE.json index 10805b7..7b191c7 100644 --- a/data/chips/STM32H723ZE.json +++ b/data/chips/STM32H723ZE.json @@ -3480,7 +3480,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3553,7 +3553,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3616,7 +3616,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3651,7 +3651,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3686,7 +3686,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H723ZG.json b/data/chips/STM32H723ZG.json index 9423d26..c056164 100644 --- a/data/chips/STM32H723ZG.json +++ b/data/chips/STM32H723ZG.json @@ -3480,7 +3480,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3553,7 +3553,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3616,7 +3616,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3651,7 +3651,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3686,7 +3686,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725AE.json b/data/chips/STM32H725AE.json index 5b9e47c..d9f822e 100644 --- a/data/chips/STM32H725AE.json +++ b/data/chips/STM32H725AE.json @@ -3596,7 +3596,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3674,7 +3674,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3737,7 +3737,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3772,7 +3772,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3807,7 +3807,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725AG.json b/data/chips/STM32H725AG.json index 5cae6a5..3691216 100644 --- a/data/chips/STM32H725AG.json +++ b/data/chips/STM32H725AG.json @@ -3602,7 +3602,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3680,7 +3680,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3743,7 +3743,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3778,7 +3778,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3813,7 +3813,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725IE.json b/data/chips/STM32H725IE.json index 4e6709b..1889675 100644 --- a/data/chips/STM32H725IE.json +++ b/data/chips/STM32H725IE.json @@ -3711,7 +3711,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3789,7 +3789,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3852,7 +3852,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3887,7 +3887,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3922,7 +3922,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725IG.json b/data/chips/STM32H725IG.json index d9fc4f2..10fefd8 100644 --- a/data/chips/STM32H725IG.json +++ b/data/chips/STM32H725IG.json @@ -3717,7 +3717,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3795,7 +3795,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3858,7 +3858,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3893,7 +3893,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3928,7 +3928,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725RE.json b/data/chips/STM32H725RE.json index 05ed7a5..35d04dd 100644 --- a/data/chips/STM32H725RE.json +++ b/data/chips/STM32H725RE.json @@ -2129,7 +2129,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2160,7 +2160,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2203,7 +2203,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2238,7 +2238,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2273,7 +2273,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725RG.json b/data/chips/STM32H725RG.json index 4e27aca..7c554b6 100644 --- a/data/chips/STM32H725RG.json +++ b/data/chips/STM32H725RG.json @@ -2135,7 +2135,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2166,7 +2166,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2209,7 +2209,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2244,7 +2244,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2279,7 +2279,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725VE.json b/data/chips/STM32H725VE.json index 63daba9..29e1def 100644 --- a/data/chips/STM32H725VE.json +++ b/data/chips/STM32H725VE.json @@ -2998,7 +2998,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3051,7 +3051,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3114,7 +3114,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3149,7 +3149,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3184,7 +3184,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725VG.json b/data/chips/STM32H725VG.json index 19b6534..9051f3e 100644 --- a/data/chips/STM32H725VG.json +++ b/data/chips/STM32H725VG.json @@ -3008,7 +3008,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3061,7 +3061,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3124,7 +3124,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3159,7 +3159,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3194,7 +3194,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725ZE.json b/data/chips/STM32H725ZE.json index dd0857e..1e5a5d7 100644 --- a/data/chips/STM32H725ZE.json +++ b/data/chips/STM32H725ZE.json @@ -3272,7 +3272,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3345,7 +3345,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3408,7 +3408,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3443,7 +3443,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3478,7 +3478,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725ZG.json b/data/chips/STM32H725ZG.json index d7527da..cad89a2 100644 --- a/data/chips/STM32H725ZG.json +++ b/data/chips/STM32H725ZG.json @@ -3278,7 +3278,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3351,7 +3351,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3414,7 +3414,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3449,7 +3449,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3484,7 +3484,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index 7ea1569..548b8d5 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -3687,7 +3687,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3765,7 +3765,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3828,7 +3828,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3863,7 +3863,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3898,7 +3898,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index 25b4252..424ebd7 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -3802,7 +3802,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3880,7 +3880,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3943,7 +3943,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3978,7 +3978,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4013,7 +4013,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index 3783f89..73817a6 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -3168,7 +3168,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3221,7 +3221,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3284,7 +3284,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3319,7 +3319,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3354,7 +3354,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index 4a3e75c..e57567c 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -3565,7 +3565,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3638,7 +3638,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3701,7 +3701,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3736,7 +3736,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3771,7 +3771,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index 5617e17..908bf3b 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -3168,7 +3168,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3221,7 +3221,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3284,7 +3284,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3319,7 +3319,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3354,7 +3354,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index 1632693..f19e5c6 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -3565,7 +3565,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3638,7 +3638,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3701,7 +3701,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3736,7 +3736,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3771,7 +3771,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index 4cc7b68..f77acb3 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -3692,7 +3692,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3770,7 +3770,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3833,7 +3833,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3868,7 +3868,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3903,7 +3903,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index 5a5054d..efe0f7b 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -3807,7 +3807,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3885,7 +3885,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3948,7 +3948,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3983,7 +3983,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4018,7 +4018,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H735RG.json b/data/chips/STM32H735RG.json index a773d79..7af06a9 100644 --- a/data/chips/STM32H735RG.json +++ b/data/chips/STM32H735RG.json @@ -2225,7 +2225,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2256,7 +2256,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2299,7 +2299,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2334,7 +2334,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2369,7 +2369,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index 2c16dea..8711158 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -3098,7 +3098,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3151,7 +3151,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3214,7 +3214,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3249,7 +3249,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3284,7 +3284,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index 23a211e..77e545d 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -3368,7 +3368,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3441,7 +3441,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3504,7 +3504,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3539,7 +3539,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3574,7 +3574,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742AG.json b/data/chips/STM32H742AG.json index 1b26619..ef77f8e 100644 --- a/data/chips/STM32H742AG.json +++ b/data/chips/STM32H742AG.json @@ -3502,7 +3502,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3580,7 +3580,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3643,7 +3643,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3678,7 +3678,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3713,7 +3713,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742AI.json b/data/chips/STM32H742AI.json index 26c7c16..b6dca28 100644 --- a/data/chips/STM32H742AI.json +++ b/data/chips/STM32H742AI.json @@ -3513,7 +3513,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3591,7 +3591,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3654,7 +3654,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3689,7 +3689,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3724,7 +3724,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742BG.json b/data/chips/STM32H742BG.json index 20cca59..dc4a8e1 100644 --- a/data/chips/STM32H742BG.json +++ b/data/chips/STM32H742BG.json @@ -3647,7 +3647,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3725,7 +3725,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3788,7 +3788,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3823,7 +3823,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3858,7 +3858,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742BI.json b/data/chips/STM32H742BI.json index 9f777ff..dd295b6 100644 --- a/data/chips/STM32H742BI.json +++ b/data/chips/STM32H742BI.json @@ -3658,7 +3658,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3736,7 +3736,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3799,7 +3799,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3834,7 +3834,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3869,7 +3869,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742IG.json b/data/chips/STM32H742IG.json index da5e0c7..0d982a4 100644 --- a/data/chips/STM32H742IG.json +++ b/data/chips/STM32H742IG.json @@ -3651,7 +3651,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3729,7 +3729,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3792,7 +3792,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3827,7 +3827,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3862,7 +3862,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742II.json b/data/chips/STM32H742II.json index 8e04f4f..841ed07 100644 --- a/data/chips/STM32H742II.json +++ b/data/chips/STM32H742II.json @@ -3662,7 +3662,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3740,7 +3740,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3803,7 +3803,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3838,7 +3838,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3873,7 +3873,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742VG.json b/data/chips/STM32H742VG.json index 8388926..a92c45f 100644 --- a/data/chips/STM32H742VG.json +++ b/data/chips/STM32H742VG.json @@ -2986,7 +2986,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3039,7 +3039,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3102,7 +3102,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3137,7 +3137,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3172,7 +3172,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742VI.json b/data/chips/STM32H742VI.json index 583d0c2..675df3c 100644 --- a/data/chips/STM32H742VI.json +++ b/data/chips/STM32H742VI.json @@ -2997,7 +2997,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3050,7 +3050,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3113,7 +3113,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3148,7 +3148,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3183,7 +3183,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742XG.json b/data/chips/STM32H742XG.json index fffbf8f..9623615 100644 --- a/data/chips/STM32H742XG.json +++ b/data/chips/STM32H742XG.json @@ -3711,7 +3711,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3789,7 +3789,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3852,7 +3852,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3887,7 +3887,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3922,7 +3922,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742XI.json b/data/chips/STM32H742XI.json index cd6d710..f159208 100644 --- a/data/chips/STM32H742XI.json +++ b/data/chips/STM32H742XI.json @@ -3722,7 +3722,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3800,7 +3800,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3863,7 +3863,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3898,7 +3898,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3933,7 +3933,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742ZG.json b/data/chips/STM32H742ZG.json index f306b43..cd9bc1e 100644 --- a/data/chips/STM32H742ZG.json +++ b/data/chips/STM32H742ZG.json @@ -3334,7 +3334,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3407,7 +3407,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3470,7 +3470,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3505,7 +3505,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3540,7 +3540,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742ZI.json b/data/chips/STM32H742ZI.json index 4e49552..906dc50 100644 --- a/data/chips/STM32H742ZI.json +++ b/data/chips/STM32H742ZI.json @@ -3345,7 +3345,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3418,7 +3418,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3481,7 +3481,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3516,7 +3516,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3551,7 +3551,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743AG.json b/data/chips/STM32H743AG.json index 967c03b..3c8e7fc 100644 --- a/data/chips/STM32H743AG.json +++ b/data/chips/STM32H743AG.json @@ -3564,7 +3564,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3642,7 +3642,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3705,7 +3705,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3740,7 +3740,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3775,7 +3775,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743AI.json b/data/chips/STM32H743AI.json index 707a570..8467108 100644 --- a/data/chips/STM32H743AI.json +++ b/data/chips/STM32H743AI.json @@ -3575,7 +3575,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3653,7 +3653,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3716,7 +3716,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3751,7 +3751,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3786,7 +3786,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743BG.json b/data/chips/STM32H743BG.json index c1ca37b..b7fc0e9 100644 --- a/data/chips/STM32H743BG.json +++ b/data/chips/STM32H743BG.json @@ -3709,7 +3709,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3787,7 +3787,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3850,7 +3850,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3885,7 +3885,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3920,7 +3920,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743BI.json b/data/chips/STM32H743BI.json index d81d2c8..ab08d24 100644 --- a/data/chips/STM32H743BI.json +++ b/data/chips/STM32H743BI.json @@ -3720,7 +3720,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3798,7 +3798,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3861,7 +3861,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3896,7 +3896,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3931,7 +3931,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743IG.json b/data/chips/STM32H743IG.json index d94a0aa..5785da3 100644 --- a/data/chips/STM32H743IG.json +++ b/data/chips/STM32H743IG.json @@ -3713,7 +3713,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3791,7 +3791,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3854,7 +3854,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3889,7 +3889,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3924,7 +3924,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743II.json b/data/chips/STM32H743II.json index d9cc77c..1083cbf 100644 --- a/data/chips/STM32H743II.json +++ b/data/chips/STM32H743II.json @@ -3724,7 +3724,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3802,7 +3802,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3865,7 +3865,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3900,7 +3900,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3935,7 +3935,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743VG.json b/data/chips/STM32H743VG.json index d89a6d8..fc2fd39 100644 --- a/data/chips/STM32H743VG.json +++ b/data/chips/STM32H743VG.json @@ -3048,7 +3048,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3101,7 +3101,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3164,7 +3164,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3199,7 +3199,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3234,7 +3234,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743VI.json b/data/chips/STM32H743VI.json index 519029c..9eb58ef 100644 --- a/data/chips/STM32H743VI.json +++ b/data/chips/STM32H743VI.json @@ -3059,7 +3059,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3112,7 +3112,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3175,7 +3175,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3210,7 +3210,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3245,7 +3245,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743XG.json b/data/chips/STM32H743XG.json index b21aed5..304e3f7 100644 --- a/data/chips/STM32H743XG.json +++ b/data/chips/STM32H743XG.json @@ -3773,7 +3773,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3851,7 +3851,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3914,7 +3914,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3949,7 +3949,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3984,7 +3984,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743XI.json b/data/chips/STM32H743XI.json index 5d89506..f232abe 100644 --- a/data/chips/STM32H743XI.json +++ b/data/chips/STM32H743XI.json @@ -3784,7 +3784,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3862,7 +3862,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3925,7 +3925,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3960,7 +3960,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3995,7 +3995,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743ZG.json b/data/chips/STM32H743ZG.json index 8f54798..0172732 100644 --- a/data/chips/STM32H743ZG.json +++ b/data/chips/STM32H743ZG.json @@ -3396,7 +3396,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3469,7 +3469,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3532,7 +3532,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3567,7 +3567,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3602,7 +3602,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743ZI.json b/data/chips/STM32H743ZI.json index c7d1969..cbe04cd 100644 --- a/data/chips/STM32H743ZI.json +++ b/data/chips/STM32H743ZI.json @@ -3407,7 +3407,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3480,7 +3480,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3543,7 +3543,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3578,7 +3578,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3613,7 +3613,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745BG.json b/data/chips/STM32H745BG.json index 5c84eff..d0eaa46 100644 --- a/data/chips/STM32H745BG.json +++ b/data/chips/STM32H745BG.json @@ -3700,7 +3700,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3778,7 +3778,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3841,7 +3841,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3876,7 +3876,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3911,7 +3911,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13561,7 +13561,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13639,7 +13639,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13702,7 +13702,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13737,7 +13737,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13772,7 +13772,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745BI.json b/data/chips/STM32H745BI.json index fdd41dc..92b7218 100644 --- a/data/chips/STM32H745BI.json +++ b/data/chips/STM32H745BI.json @@ -3711,7 +3711,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3789,7 +3789,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3852,7 +3852,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3887,7 +3887,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3922,7 +3922,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13572,7 +13572,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13650,7 +13650,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13713,7 +13713,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13748,7 +13748,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13783,7 +13783,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745IG.json b/data/chips/STM32H745IG.json index 3e2acc9..0309eed 100644 --- a/data/chips/STM32H745IG.json +++ b/data/chips/STM32H745IG.json @@ -3668,7 +3668,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3746,7 +3746,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3809,7 +3809,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3844,7 +3844,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3879,7 +3879,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13271,7 +13271,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13349,7 +13349,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13412,7 +13412,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13447,7 +13447,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13482,7 +13482,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745II.json b/data/chips/STM32H745II.json index 084297b..147617f 100644 --- a/data/chips/STM32H745II.json +++ b/data/chips/STM32H745II.json @@ -3679,7 +3679,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3757,7 +3757,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3820,7 +3820,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3855,7 +3855,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3890,7 +3890,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13282,7 +13282,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13360,7 +13360,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13423,7 +13423,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13458,7 +13458,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13493,7 +13493,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745XG.json b/data/chips/STM32H745XG.json index 84826f8..d683b21 100644 --- a/data/chips/STM32H745XG.json +++ b/data/chips/STM32H745XG.json @@ -3764,7 +3764,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3842,7 +3842,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3905,7 +3905,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3940,7 +3940,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3975,7 +3975,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13794,7 +13794,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13872,7 +13872,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13935,7 +13935,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13970,7 +13970,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14005,7 +14005,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745XI.json b/data/chips/STM32H745XI.json index 8084939..0498113 100644 --- a/data/chips/STM32H745XI.json +++ b/data/chips/STM32H745XI.json @@ -3775,7 +3775,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3853,7 +3853,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3916,7 +3916,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3951,7 +3951,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3986,7 +3986,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13805,7 +13805,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13883,7 +13883,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13946,7 +13946,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13981,7 +13981,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14016,7 +14016,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745ZG.json b/data/chips/STM32H745ZG.json index 81e4346..a3f1e41 100644 --- a/data/chips/STM32H745ZG.json +++ b/data/chips/STM32H745ZG.json @@ -3240,7 +3240,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3313,7 +3313,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3376,7 +3376,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3411,7 +3411,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3446,7 +3446,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12036,7 +12036,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12109,7 +12109,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12172,7 +12172,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12207,7 +12207,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12242,7 +12242,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745ZI.json b/data/chips/STM32H745ZI.json index be4bc95..a765744 100644 --- a/data/chips/STM32H745ZI.json +++ b/data/chips/STM32H745ZI.json @@ -3251,7 +3251,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3324,7 +3324,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3387,7 +3387,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3422,7 +3422,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3457,7 +3457,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12047,7 +12047,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12120,7 +12120,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12183,7 +12183,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12218,7 +12218,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12253,7 +12253,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index 175c9bb..0433d82 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -3393,7 +3393,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3466,7 +3466,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3529,7 +3529,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3564,7 +3564,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3599,7 +3599,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12408,7 +12408,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12481,7 +12481,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12544,7 +12544,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12579,7 +12579,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12614,7 +12614,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index 3998e29..178933c 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -3404,7 +3404,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3477,7 +3477,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3540,7 +3540,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3575,7 +3575,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3610,7 +3610,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12419,7 +12419,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12492,7 +12492,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12555,7 +12555,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12590,7 +12590,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12625,7 +12625,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index 467ff84..4e58aa0 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -3706,7 +3706,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3784,7 +3784,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3847,7 +3847,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3882,7 +3882,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3917,7 +3917,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13396,7 +13396,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13474,7 +13474,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13537,7 +13537,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13572,7 +13572,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13607,7 +13607,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index 7caf30c..8c0be5e 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -3717,7 +3717,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3795,7 +3795,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3858,7 +3858,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3893,7 +3893,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3928,7 +3928,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13407,7 +13407,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13485,7 +13485,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13548,7 +13548,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13583,7 +13583,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13618,7 +13618,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index a8041dc..a2922dd 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -3393,7 +3393,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3466,7 +3466,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3529,7 +3529,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3564,7 +3564,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3599,7 +3599,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12408,7 +12408,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12481,7 +12481,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12544,7 +12544,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12579,7 +12579,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12614,7 +12614,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index 49eb2de..501afaf 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -3404,7 +3404,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3477,7 +3477,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3540,7 +3540,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3575,7 +3575,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3610,7 +3610,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12419,7 +12419,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12492,7 +12492,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12555,7 +12555,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12590,7 +12590,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12625,7 +12625,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index 119c8ea..30c3270 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -3770,7 +3770,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3848,7 +3848,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3911,7 +3911,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3946,7 +3946,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3981,7 +3981,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13804,7 +13804,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13882,7 +13882,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13945,7 +13945,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13980,7 +13980,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14015,7 +14015,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index fd5d5f4..ef66337 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -3781,7 +3781,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3859,7 +3859,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3922,7 +3922,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3957,7 +3957,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3992,7 +3992,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13815,7 +13815,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13893,7 +13893,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13956,7 +13956,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13991,7 +13991,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14026,7 +14026,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index 1bc5811..8a35a56 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -3252,7 +3252,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3305,7 +3305,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3368,7 +3368,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3403,7 +3403,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3438,7 +3438,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11724,7 +11724,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11777,7 +11777,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11840,7 +11840,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11875,7 +11875,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11910,7 +11910,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H750IB.json b/data/chips/STM32H750IB.json index be028f1..79ff226 100644 --- a/data/chips/STM32H750IB.json +++ b/data/chips/STM32H750IB.json @@ -3769,7 +3769,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3847,7 +3847,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3910,7 +3910,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3945,7 +3945,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3980,7 +3980,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H750VB.json b/data/chips/STM32H750VB.json index 9c0788c..7d18796 100644 --- a/data/chips/STM32H750VB.json +++ b/data/chips/STM32H750VB.json @@ -3100,7 +3100,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3153,7 +3153,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3216,7 +3216,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3251,7 +3251,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3286,7 +3286,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H750XB.json b/data/chips/STM32H750XB.json index 444e0c4..d65e046 100644 --- a/data/chips/STM32H750XB.json +++ b/data/chips/STM32H750XB.json @@ -3829,7 +3829,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3907,7 +3907,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3970,7 +3970,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4005,7 +4005,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4040,7 +4040,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H750ZB.json b/data/chips/STM32H750ZB.json index c3763ab..7ff70f2 100644 --- a/data/chips/STM32H750ZB.json +++ b/data/chips/STM32H750ZB.json @@ -3440,7 +3440,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3513,7 +3513,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3576,7 +3576,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3611,7 +3611,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3646,7 +3646,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753AI.json b/data/chips/STM32H753AI.json index 0b230cf..5c08959 100644 --- a/data/chips/STM32H753AI.json +++ b/data/chips/STM32H753AI.json @@ -3654,7 +3654,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3732,7 +3732,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3795,7 +3795,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3830,7 +3830,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3865,7 +3865,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753BI.json b/data/chips/STM32H753BI.json index 5b4aef8..d20488a 100644 --- a/data/chips/STM32H753BI.json +++ b/data/chips/STM32H753BI.json @@ -3799,7 +3799,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3877,7 +3877,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3940,7 +3940,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3975,7 +3975,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4010,7 +4010,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753II.json b/data/chips/STM32H753II.json index eb63554..9852c01 100644 --- a/data/chips/STM32H753II.json +++ b/data/chips/STM32H753II.json @@ -3803,7 +3803,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3881,7 +3881,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3944,7 +3944,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3979,7 +3979,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4014,7 +4014,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753VI.json b/data/chips/STM32H753VI.json index 75c73fd..9fc5f67 100644 --- a/data/chips/STM32H753VI.json +++ b/data/chips/STM32H753VI.json @@ -3138,7 +3138,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3191,7 +3191,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3254,7 +3254,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3289,7 +3289,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3324,7 +3324,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753XI.json b/data/chips/STM32H753XI.json index 15f5bf0..f3184a5 100644 --- a/data/chips/STM32H753XI.json +++ b/data/chips/STM32H753XI.json @@ -3863,7 +3863,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3941,7 +3941,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4004,7 +4004,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4039,7 +4039,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4074,7 +4074,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753ZI.json b/data/chips/STM32H753ZI.json index e892011..1d551f8 100644 --- a/data/chips/STM32H753ZI.json +++ b/data/chips/STM32H753ZI.json @@ -3486,7 +3486,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3559,7 +3559,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3622,7 +3622,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3657,7 +3657,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3692,7 +3692,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index 10437dc..43fd551 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -3790,7 +3790,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3868,7 +3868,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3931,7 +3931,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3966,7 +3966,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4001,7 +4001,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13728,7 +13728,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13806,7 +13806,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13869,7 +13869,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13904,7 +13904,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13939,7 +13939,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index 5043561..89fd9ad 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -3758,7 +3758,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3836,7 +3836,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3899,7 +3899,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3934,7 +3934,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3969,7 +3969,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13438,7 +13438,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13516,7 +13516,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13579,7 +13579,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13614,7 +13614,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13649,7 +13649,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index fe5de1d..4139ce8 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -3854,7 +3854,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3932,7 +3932,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3995,7 +3995,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4030,7 +4030,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4065,7 +4065,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13961,7 +13961,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14039,7 +14039,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14102,7 +14102,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14137,7 +14137,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14172,7 +14172,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index 87db591..f47b07e 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -3330,7 +3330,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3403,7 +3403,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3466,7 +3466,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3501,7 +3501,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3536,7 +3536,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12203,7 +12203,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12276,7 +12276,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12339,7 +12339,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12374,7 +12374,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12409,7 +12409,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index 4e0cb35..7581c8f 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -3483,7 +3483,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3556,7 +3556,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3619,7 +3619,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3654,7 +3654,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3689,7 +3689,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12575,7 +12575,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12648,7 +12648,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12711,7 +12711,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12746,7 +12746,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12781,7 +12781,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index 7d01f5f..f8a6d21 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -3796,7 +3796,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3874,7 +3874,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3937,7 +3937,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3972,7 +3972,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4007,7 +4007,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13563,7 +13563,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13641,7 +13641,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13704,7 +13704,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13739,7 +13739,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13774,7 +13774,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 393c33a..d4dac16 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -3483,7 +3483,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3556,7 +3556,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3619,7 +3619,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3654,7 +3654,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3689,7 +3689,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12575,7 +12575,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12648,7 +12648,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12711,7 +12711,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12746,7 +12746,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12781,7 +12781,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 69858ed..3b3f260 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -3860,7 +3860,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3938,7 +3938,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4001,7 +4001,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4036,7 +4036,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4071,7 +4071,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13971,7 +13971,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14049,7 +14049,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14112,7 +14112,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14147,7 +14147,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14182,7 +14182,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index ad5deeb..0686f7d 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -3331,7 +3331,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3384,7 +3384,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3447,7 +3447,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3482,7 +3482,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3517,7 +3517,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11880,7 +11880,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11933,7 +11933,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11996,7 +11996,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12031,7 +12031,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12066,7 +12066,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index c6e298c..5f7f6ea 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -3215,7 +3215,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3293,7 +3293,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3356,7 +3356,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index ae66b37..fbe2a87 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -3226,7 +3226,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3304,7 +3304,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3367,7 +3367,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index 72c481b..1bcf17b 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -3407,7 +3407,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3485,7 +3485,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3548,7 +3548,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index ce46505..3a8adb5 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -3418,7 +3418,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3496,7 +3496,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3559,7 +3559,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index 0a5377b..a83abd0 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -3389,7 +3389,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3467,7 +3467,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3530,7 +3530,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index 53450b5..887784a 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -3406,7 +3406,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3484,7 +3484,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3547,7 +3547,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index 9929f02..e61e58b 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -3351,7 +3351,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3429,7 +3429,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3492,7 +3492,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index 0779280..c23048d 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -3362,7 +3362,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3440,7 +3440,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3503,7 +3503,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index 629db25..8f14792 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -2916,7 +2916,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2989,7 +2989,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3052,7 +3052,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3RG.json b/data/chips/STM32H7A3RG.json index d29c831..36ecec1 100644 --- a/data/chips/STM32H7A3RG.json +++ b/data/chips/STM32H7A3RG.json @@ -2225,7 +2225,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2256,7 +2256,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2299,7 +2299,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3RI.json b/data/chips/STM32H7A3RI.json index d93d71c..0ed1c8d 100644 --- a/data/chips/STM32H7A3RI.json +++ b/data/chips/STM32H7A3RI.json @@ -2236,7 +2236,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2267,7 +2267,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2310,7 +2310,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index 23041e6..e8b84f6 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -2854,7 +2854,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2907,7 +2907,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2970,7 +2970,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index 7270261..69f3b58 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -2865,7 +2865,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2918,7 +2918,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2981,7 +2981,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index f8ca1da..039877a 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -3095,7 +3095,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3168,7 +3168,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3231,7 +3231,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index 3e2f4bb..2749e5a 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -3106,7 +3106,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3179,7 +3179,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3242,7 +3242,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index 26697ab..b8bcbc0 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -3294,7 +3294,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3372,7 +3372,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3435,7 +3435,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index a8bf74a..c31f840 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -3478,7 +3478,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3556,7 +3556,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3619,7 +3619,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index 601abe8..1869492 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -2304,7 +2304,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2335,7 +2335,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2378,7 +2378,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index d3c0bc9..01a42fd 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -2921,7 +2921,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2974,7 +2974,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3037,7 +3037,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index 9a009b0..d0dfe7f 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -3170,7 +3170,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3243,7 +3243,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3306,7 +3306,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index bccc546..a8cb995 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -3316,7 +3316,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3394,7 +3394,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3457,7 +3457,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index 7e42482..8851f67 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -3508,7 +3508,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3586,7 +3586,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3649,7 +3649,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index f382b59..6d2a309 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -3496,7 +3496,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3574,7 +3574,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3637,7 +3637,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index c2cbf1a..57a24f5 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -3452,7 +3452,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3530,7 +3530,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3593,7 +3593,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index f4549e1..2113b71 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -3006,7 +3006,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3079,7 +3079,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3142,7 +3142,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 32cde03..48f161e 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -2326,7 +2326,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2357,7 +2357,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2400,7 +2400,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index d5c3e2c..525a688 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -2955,7 +2955,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3008,7 +3008,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3071,7 +3071,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index bb36da3..c70473c 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -3196,7 +3196,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3269,7 +3269,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3332,7 +3332,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412C8.json b/data/chips/STM32L412C8.json index 6a42a0f..fa4a692 100644 --- a/data/chips/STM32L412C8.json +++ b/data/chips/STM32L412C8.json @@ -1243,7 +1243,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1301,7 +1301,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412CB.json b/data/chips/STM32L412CB.json index 8bf9759..f2f96b1 100644 --- a/data/chips/STM32L412CB.json +++ b/data/chips/STM32L412CB.json @@ -1251,7 +1251,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1309,7 +1309,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412K8.json b/data/chips/STM32L412K8.json index 158c791..47a7148 100644 --- a/data/chips/STM32L412K8.json +++ b/data/chips/STM32L412K8.json @@ -1146,7 +1146,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1199,7 +1199,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412KB.json b/data/chips/STM32L412KB.json index 5317dad..cb75d46 100644 --- a/data/chips/STM32L412KB.json +++ b/data/chips/STM32L412KB.json @@ -1146,7 +1146,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1199,7 +1199,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412R8.json b/data/chips/STM32L412R8.json index 1653182..8dcf7b8 100644 --- a/data/chips/STM32L412R8.json +++ b/data/chips/STM32L412R8.json @@ -1309,7 +1309,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1387,7 +1387,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412RB.json b/data/chips/STM32L412RB.json index a92e224..013219e 100644 --- a/data/chips/STM32L412RB.json +++ b/data/chips/STM32L412RB.json @@ -1323,7 +1323,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1401,7 +1401,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412T8.json b/data/chips/STM32L412T8.json index 5e954ea..a479cf4 100644 --- a/data/chips/STM32L412T8.json +++ b/data/chips/STM32L412T8.json @@ -1161,7 +1161,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1219,7 +1219,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412TB.json b/data/chips/STM32L412TB.json index 9d6758c..e457053 100644 --- a/data/chips/STM32L412TB.json +++ b/data/chips/STM32L412TB.json @@ -1165,7 +1165,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1223,7 +1223,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L422CB.json b/data/chips/STM32L422CB.json index 72ff366..5978adf 100644 --- a/data/chips/STM32L422CB.json +++ b/data/chips/STM32L422CB.json @@ -1292,7 +1292,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1350,7 +1350,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L422KB.json b/data/chips/STM32L422KB.json index f593adb..72ade1c 100644 --- a/data/chips/STM32L422KB.json +++ b/data/chips/STM32L422KB.json @@ -1195,7 +1195,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1248,7 +1248,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L422RB.json b/data/chips/STM32L422RB.json index 00ee931..2c86c3c 100644 --- a/data/chips/STM32L422RB.json +++ b/data/chips/STM32L422RB.json @@ -1364,7 +1364,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1442,7 +1442,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L422TB.json b/data/chips/STM32L422TB.json index 4f4f9b2..9953eb7 100644 --- a/data/chips/STM32L422TB.json +++ b/data/chips/STM32L422TB.json @@ -1210,7 +1210,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1268,7 +1268,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431CB.json b/data/chips/STM32L431CB.json index 3c6a800..a4f1ea2 100644 --- a/data/chips/STM32L431CB.json +++ b/data/chips/STM32L431CB.json @@ -1367,7 +1367,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1430,7 +1430,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431CC.json b/data/chips/STM32L431CC.json index 2d642ad..b1f5019 100644 --- a/data/chips/STM32L431CC.json +++ b/data/chips/STM32L431CC.json @@ -1367,7 +1367,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1430,7 +1430,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431KB.json b/data/chips/STM32L431KB.json index 349ba94..e47e8dd 100644 --- a/data/chips/STM32L431KB.json +++ b/data/chips/STM32L431KB.json @@ -1243,7 +1243,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1296,7 +1296,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431KC.json b/data/chips/STM32L431KC.json index 34bdeec..76d6754 100644 --- a/data/chips/STM32L431KC.json +++ b/data/chips/STM32L431KC.json @@ -1243,7 +1243,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1296,7 +1296,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431RB.json b/data/chips/STM32L431RB.json index 128c157..9f5ae4f 100644 --- a/data/chips/STM32L431RB.json +++ b/data/chips/STM32L431RB.json @@ -1405,7 +1405,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1483,7 +1483,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431RC.json b/data/chips/STM32L431RC.json index f110d65..2aea8f7 100644 --- a/data/chips/STM32L431RC.json +++ b/data/chips/STM32L431RC.json @@ -1405,7 +1405,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1483,7 +1483,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431VC.json b/data/chips/STM32L431VC.json index ce2c5e3..abf76eb 100644 --- a/data/chips/STM32L431VC.json +++ b/data/chips/STM32L431VC.json @@ -1411,7 +1411,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1489,7 +1489,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L432KB.json b/data/chips/STM32L432KB.json index 86d6772..ea395fd 100644 --- a/data/chips/STM32L432KB.json +++ b/data/chips/STM32L432KB.json @@ -1214,7 +1214,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1267,7 +1267,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L432KC.json b/data/chips/STM32L432KC.json index ef16a9e..187b404 100644 --- a/data/chips/STM32L432KC.json +++ b/data/chips/STM32L432KC.json @@ -1214,7 +1214,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1267,7 +1267,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L433CB.json b/data/chips/STM32L433CB.json index 8658970..28f9053 100644 --- a/data/chips/STM32L433CB.json +++ b/data/chips/STM32L433CB.json @@ -1540,7 +1540,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1603,7 +1603,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L433CC.json b/data/chips/STM32L433CC.json index 1f33c3e..a624539 100644 --- a/data/chips/STM32L433CC.json +++ b/data/chips/STM32L433CC.json @@ -1540,7 +1540,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1603,7 +1603,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L433RB.json b/data/chips/STM32L433RB.json index 8598dae..471d66d 100644 --- a/data/chips/STM32L433RB.json +++ b/data/chips/STM32L433RB.json @@ -1683,7 +1683,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1761,7 +1761,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L433RC.json b/data/chips/STM32L433RC.json index 768583c..360f0ad 100644 --- a/data/chips/STM32L433RC.json +++ b/data/chips/STM32L433RC.json @@ -1693,7 +1693,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1771,7 +1771,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L433VC.json b/data/chips/STM32L433VC.json index 1125c08..ce641fd 100644 --- a/data/chips/STM32L433VC.json +++ b/data/chips/STM32L433VC.json @@ -1749,7 +1749,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1827,7 +1827,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L442KC.json b/data/chips/STM32L442KC.json index e35a374..54a4a11 100644 --- a/data/chips/STM32L442KC.json +++ b/data/chips/STM32L442KC.json @@ -1263,7 +1263,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1316,7 +1316,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L443CC.json b/data/chips/STM32L443CC.json index 8f80d3d..399db22 100644 --- a/data/chips/STM32L443CC.json +++ b/data/chips/STM32L443CC.json @@ -1593,7 +1593,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1656,7 +1656,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L443RC.json b/data/chips/STM32L443RC.json index 467427d..f0f39d4 100644 --- a/data/chips/STM32L443RC.json +++ b/data/chips/STM32L443RC.json @@ -1732,7 +1732,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1810,7 +1810,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L443VC.json b/data/chips/STM32L443VC.json index d9ff415..9c5919d 100644 --- a/data/chips/STM32L443VC.json +++ b/data/chips/STM32L443VC.json @@ -1798,7 +1798,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1876,7 +1876,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451CC.json b/data/chips/STM32L451CC.json index 41eda7a..4fd58ed 100644 --- a/data/chips/STM32L451CC.json +++ b/data/chips/STM32L451CC.json @@ -1549,7 +1549,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1607,7 +1607,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451CE.json b/data/chips/STM32L451CE.json index 190d728..eda5cc3 100644 --- a/data/chips/STM32L451CE.json +++ b/data/chips/STM32L451CE.json @@ -1553,7 +1553,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1611,7 +1611,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451RC.json b/data/chips/STM32L451RC.json index 4ad72ed..8c6e496 100644 --- a/data/chips/STM32L451RC.json +++ b/data/chips/STM32L451RC.json @@ -1624,7 +1624,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1702,7 +1702,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451RE.json b/data/chips/STM32L451RE.json index d324d46..4b1164e 100644 --- a/data/chips/STM32L451RE.json +++ b/data/chips/STM32L451RE.json @@ -1624,7 +1624,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1702,7 +1702,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451VC.json b/data/chips/STM32L451VC.json index 2c989b7..8dc676e 100644 --- a/data/chips/STM32L451VC.json +++ b/data/chips/STM32L451VC.json @@ -1690,7 +1690,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1768,7 +1768,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451VE.json b/data/chips/STM32L451VE.json index 390a2f0..06eecc3 100644 --- a/data/chips/STM32L451VE.json +++ b/data/chips/STM32L451VE.json @@ -1690,7 +1690,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1768,7 +1768,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452CC.json b/data/chips/STM32L452CC.json index d72f572..68c2c62 100644 --- a/data/chips/STM32L452CC.json +++ b/data/chips/STM32L452CC.json @@ -1562,7 +1562,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1620,7 +1620,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452CE.json b/data/chips/STM32L452CE.json index 62dbd75..0fd02a4 100644 --- a/data/chips/STM32L452CE.json +++ b/data/chips/STM32L452CE.json @@ -1570,7 +1570,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1628,7 +1628,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452RC.json b/data/chips/STM32L452RC.json index 58944f0..9db604d 100644 --- a/data/chips/STM32L452RC.json +++ b/data/chips/STM32L452RC.json @@ -1637,7 +1637,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1715,7 +1715,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452RE.json b/data/chips/STM32L452RE.json index 5682714..626b864 100644 --- a/data/chips/STM32L452RE.json +++ b/data/chips/STM32L452RE.json @@ -1651,7 +1651,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1729,7 +1729,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452VC.json b/data/chips/STM32L452VC.json index 233d6ef..b72c07c 100644 --- a/data/chips/STM32L452VC.json +++ b/data/chips/STM32L452VC.json @@ -1703,7 +1703,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1781,7 +1781,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452VE.json b/data/chips/STM32L452VE.json index 1e5b586..74e2e35 100644 --- a/data/chips/STM32L452VE.json +++ b/data/chips/STM32L452VE.json @@ -1703,7 +1703,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1781,7 +1781,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L462CE.json b/data/chips/STM32L462CE.json index ecaae09..cc44d3e 100644 --- a/data/chips/STM32L462CE.json +++ b/data/chips/STM32L462CE.json @@ -1621,7 +1621,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1679,7 +1679,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L462RE.json b/data/chips/STM32L462RE.json index 416752c..af2a7a6 100644 --- a/data/chips/STM32L462RE.json +++ b/data/chips/STM32L462RE.json @@ -1686,7 +1686,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1764,7 +1764,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L462VE.json b/data/chips/STM32L462VE.json index 4b5c28d..01d0fbe 100644 --- a/data/chips/STM32L462VE.json +++ b/data/chips/STM32L462VE.json @@ -1752,7 +1752,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1830,7 +1830,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471QE.json b/data/chips/STM32L471QE.json index bc52ec7..a4a9f1d 100644 --- a/data/chips/STM32L471QE.json +++ b/data/chips/STM32L471QE.json @@ -2184,7 +2184,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2277,7 +2277,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471QG.json b/data/chips/STM32L471QG.json index a2f20b3..398ceef 100644 --- a/data/chips/STM32L471QG.json +++ b/data/chips/STM32L471QG.json @@ -2195,7 +2195,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2288,7 +2288,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471RE.json b/data/chips/STM32L471RE.json index e3b7266..a6c2606 100644 --- a/data/chips/STM32L471RE.json +++ b/data/chips/STM32L471RE.json @@ -1645,7 +1645,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1718,7 +1718,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471RG.json b/data/chips/STM32L471RG.json index daaf551..f44917e 100644 --- a/data/chips/STM32L471RG.json +++ b/data/chips/STM32L471RG.json @@ -1656,7 +1656,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1729,7 +1729,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471VE.json b/data/chips/STM32L471VE.json index 932c054..069e177 100644 --- a/data/chips/STM32L471VE.json +++ b/data/chips/STM32L471VE.json @@ -2002,7 +2002,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2075,7 +2075,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471VG.json b/data/chips/STM32L471VG.json index ceac4a4..2e04d3a 100644 --- a/data/chips/STM32L471VG.json +++ b/data/chips/STM32L471VG.json @@ -2013,7 +2013,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2086,7 +2086,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471ZE.json b/data/chips/STM32L471ZE.json index f6c48ae..7046161 100644 --- a/data/chips/STM32L471ZE.json +++ b/data/chips/STM32L471ZE.json @@ -2208,7 +2208,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2301,7 +2301,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471ZG.json b/data/chips/STM32L471ZG.json index 51c9017..4a9591a 100644 --- a/data/chips/STM32L471ZG.json +++ b/data/chips/STM32L471ZG.json @@ -2219,7 +2219,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2312,7 +2312,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475RC.json b/data/chips/STM32L475RC.json index e4e3567..38765e4 100644 --- a/data/chips/STM32L475RC.json +++ b/data/chips/STM32L475RC.json @@ -1651,7 +1651,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1724,7 +1724,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475RE.json b/data/chips/STM32L475RE.json index 24bb7b9..6d52670 100644 --- a/data/chips/STM32L475RE.json +++ b/data/chips/STM32L475RE.json @@ -1651,7 +1651,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1724,7 +1724,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475RG.json b/data/chips/STM32L475RG.json index a14f747..354b294 100644 --- a/data/chips/STM32L475RG.json +++ b/data/chips/STM32L475RG.json @@ -1662,7 +1662,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1735,7 +1735,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475VC.json b/data/chips/STM32L475VC.json index 50f84ce..0b25b60 100644 --- a/data/chips/STM32L475VC.json +++ b/data/chips/STM32L475VC.json @@ -2008,7 +2008,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2081,7 +2081,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475VE.json b/data/chips/STM32L475VE.json index ff9b251..93d7af5 100644 --- a/data/chips/STM32L475VE.json +++ b/data/chips/STM32L475VE.json @@ -2008,7 +2008,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2081,7 +2081,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475VG.json b/data/chips/STM32L475VG.json index d7b90e5..0dbdc3e 100644 --- a/data/chips/STM32L475VG.json +++ b/data/chips/STM32L475VG.json @@ -2019,7 +2019,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2092,7 +2092,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476JE.json b/data/chips/STM32L476JE.json index 285a45e..fa040c3 100644 --- a/data/chips/STM32L476JE.json +++ b/data/chips/STM32L476JE.json @@ -1939,7 +1939,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2027,7 +2027,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476JG.json b/data/chips/STM32L476JG.json index 97d091c..eb9ea53 100644 --- a/data/chips/STM32L476JG.json +++ b/data/chips/STM32L476JG.json @@ -1960,7 +1960,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2048,7 +2048,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476ME.json b/data/chips/STM32L476ME.json index 9a9305f..7418196 100644 --- a/data/chips/STM32L476ME.json +++ b/data/chips/STM32L476ME.json @@ -1974,7 +1974,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2062,7 +2062,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476MG.json b/data/chips/STM32L476MG.json index af65818..ecbe60b 100644 --- a/data/chips/STM32L476MG.json +++ b/data/chips/STM32L476MG.json @@ -1985,7 +1985,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2073,7 +2073,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476QE.json b/data/chips/STM32L476QE.json index e5bbf7c..5128787 100644 --- a/data/chips/STM32L476QE.json +++ b/data/chips/STM32L476QE.json @@ -2534,7 +2534,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2627,7 +2627,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476QG.json b/data/chips/STM32L476QG.json index b69526b..94c47c4 100644 --- a/data/chips/STM32L476QG.json +++ b/data/chips/STM32L476QG.json @@ -2549,7 +2549,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2642,7 +2642,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476RC.json b/data/chips/STM32L476RC.json index 5f034ec..b1600e0 100644 --- a/data/chips/STM32L476RC.json +++ b/data/chips/STM32L476RC.json @@ -1929,7 +1929,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2002,7 +2002,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476RE.json b/data/chips/STM32L476RE.json index 68ad40a..023e735 100644 --- a/data/chips/STM32L476RE.json +++ b/data/chips/STM32L476RE.json @@ -1929,7 +1929,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2002,7 +2002,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476RG.json b/data/chips/STM32L476RG.json index 31c2bd8..940fdec 100644 --- a/data/chips/STM32L476RG.json +++ b/data/chips/STM32L476RG.json @@ -1940,7 +1940,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2013,7 +2013,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476VC.json b/data/chips/STM32L476VC.json index 84b26a3..75d5b2e 100644 --- a/data/chips/STM32L476VC.json +++ b/data/chips/STM32L476VC.json @@ -2382,7 +2382,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2475,7 +2475,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476VE.json b/data/chips/STM32L476VE.json index b991b7b..aaee28f 100644 --- a/data/chips/STM32L476VE.json +++ b/data/chips/STM32L476VE.json @@ -2382,7 +2382,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2475,7 +2475,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476VG.json b/data/chips/STM32L476VG.json index a97415d..5945c43 100644 --- a/data/chips/STM32L476VG.json +++ b/data/chips/STM32L476VG.json @@ -2397,7 +2397,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2490,7 +2490,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476ZE.json b/data/chips/STM32L476ZE.json index bf68517..d8e9c76 100644 --- a/data/chips/STM32L476ZE.json +++ b/data/chips/STM32L476ZE.json @@ -2554,7 +2554,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2647,7 +2647,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476ZG.json b/data/chips/STM32L476ZG.json index d5d8047..d6137ef 100644 --- a/data/chips/STM32L476ZG.json +++ b/data/chips/STM32L476ZG.json @@ -2579,7 +2579,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2672,7 +2672,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L486JG.json b/data/chips/STM32L486JG.json index 559a1cd..d9bbb10 100644 --- a/data/chips/STM32L486JG.json +++ b/data/chips/STM32L486JG.json @@ -1999,7 +1999,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2087,7 +2087,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L486QG.json b/data/chips/STM32L486QG.json index be366a4..465c137 100644 --- a/data/chips/STM32L486QG.json +++ b/data/chips/STM32L486QG.json @@ -2594,7 +2594,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2687,7 +2687,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L486RG.json b/data/chips/STM32L486RG.json index f81630f..d1f25db 100644 --- a/data/chips/STM32L486RG.json +++ b/data/chips/STM32L486RG.json @@ -1989,7 +1989,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2062,7 +2062,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L486VG.json b/data/chips/STM32L486VG.json index f30393b..c371435 100644 --- a/data/chips/STM32L486VG.json +++ b/data/chips/STM32L486VG.json @@ -2412,7 +2412,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2485,7 +2485,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L486ZG.json b/data/chips/STM32L486ZG.json index 195301a..4b7d72c 100644 --- a/data/chips/STM32L486ZG.json +++ b/data/chips/STM32L486ZG.json @@ -2614,7 +2614,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2707,7 +2707,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496AE.json b/data/chips/STM32L496AE.json index 3c2add7..36388d6 100644 --- a/data/chips/STM32L496AE.json +++ b/data/chips/STM32L496AE.json @@ -3129,7 +3129,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3227,7 +3227,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496AG.json b/data/chips/STM32L496AG.json index b8701ab..d0e9f89 100644 --- a/data/chips/STM32L496AG.json +++ b/data/chips/STM32L496AG.json @@ -3150,7 +3150,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3248,7 +3248,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496QE.json b/data/chips/STM32L496QE.json index 6a93537..a712998 100644 --- a/data/chips/STM32L496QE.json +++ b/data/chips/STM32L496QE.json @@ -2985,7 +2985,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3083,7 +3083,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496QG.json b/data/chips/STM32L496QG.json index 15b2340..2684cb6 100644 --- a/data/chips/STM32L496QG.json +++ b/data/chips/STM32L496QG.json @@ -3004,7 +3004,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3102,7 +3102,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496RE.json b/data/chips/STM32L496RE.json index 66d8786..f428ca1 100644 --- a/data/chips/STM32L496RE.json +++ b/data/chips/STM32L496RE.json @@ -2301,7 +2301,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2379,7 +2379,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496RG.json b/data/chips/STM32L496RG.json index d0e2841..95c00d9 100644 --- a/data/chips/STM32L496RG.json +++ b/data/chips/STM32L496RG.json @@ -2316,7 +2316,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2394,7 +2394,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496VE.json b/data/chips/STM32L496VE.json index d21bfde..265ff52 100644 --- a/data/chips/STM32L496VE.json +++ b/data/chips/STM32L496VE.json @@ -2783,7 +2783,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2876,7 +2876,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496VG.json b/data/chips/STM32L496VG.json index 2786050..3e2e328 100644 --- a/data/chips/STM32L496VG.json +++ b/data/chips/STM32L496VG.json @@ -2812,7 +2812,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2905,7 +2905,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496WG.json b/data/chips/STM32L496WG.json index 7bc88a9..c1f1809 100644 --- a/data/chips/STM32L496WG.json +++ b/data/chips/STM32L496WG.json @@ -2998,7 +2998,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3091,7 +3091,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496ZE.json b/data/chips/STM32L496ZE.json index 2e929bf..02809a5 100644 --- a/data/chips/STM32L496ZE.json +++ b/data/chips/STM32L496ZE.json @@ -3010,7 +3010,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3108,7 +3108,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496ZG.json b/data/chips/STM32L496ZG.json index 2be44e9..e4fc357 100644 --- a/data/chips/STM32L496ZG.json +++ b/data/chips/STM32L496ZG.json @@ -3031,7 +3031,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3129,7 +3129,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4A6AG.json b/data/chips/STM32L4A6AG.json index af33421..3527158 100644 --- a/data/chips/STM32L4A6AG.json +++ b/data/chips/STM32L4A6AG.json @@ -3227,7 +3227,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3325,7 +3325,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4A6QG.json b/data/chips/STM32L4A6QG.json index 38639e3..93abe1f 100644 --- a/data/chips/STM32L4A6QG.json +++ b/data/chips/STM32L4A6QG.json @@ -3083,7 +3083,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3181,7 +3181,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4A6RG.json b/data/chips/STM32L4A6RG.json index fd93c49..1a68251 100644 --- a/data/chips/STM32L4A6RG.json +++ b/data/chips/STM32L4A6RG.json @@ -2399,7 +2399,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2477,7 +2477,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4A6VG.json b/data/chips/STM32L4A6VG.json index 5bbcf8a..9c5146d 100644 --- a/data/chips/STM32L4A6VG.json +++ b/data/chips/STM32L4A6VG.json @@ -2889,7 +2889,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2982,7 +2982,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4A6ZG.json b/data/chips/STM32L4A6ZG.json index 4fb0b14..f64149f 100644 --- a/data/chips/STM32L4A6ZG.json +++ b/data/chips/STM32L4A6ZG.json @@ -3108,7 +3108,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3206,7 +3206,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5AE.json b/data/chips/STM32L4P5AE.json index 3417ec0..86131a2 100644 --- a/data/chips/STM32L4P5AE.json +++ b/data/chips/STM32L4P5AE.json @@ -2636,7 +2636,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2734,7 +2734,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5AG.json b/data/chips/STM32L4P5AG.json index f5a92e7..132e275 100644 --- a/data/chips/STM32L4P5AG.json +++ b/data/chips/STM32L4P5AG.json @@ -2640,7 +2640,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2738,7 +2738,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5CE.json b/data/chips/STM32L4P5CE.json index 5f28e7b..b4f184d 100644 --- a/data/chips/STM32L4P5CE.json +++ b/data/chips/STM32L4P5CE.json @@ -1691,7 +1691,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1749,7 +1749,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5CG.json b/data/chips/STM32L4P5CG.json index e5cd0db..2fcd5fe 100644 --- a/data/chips/STM32L4P5CG.json +++ b/data/chips/STM32L4P5CG.json @@ -1699,7 +1699,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1757,7 +1757,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5QE.json b/data/chips/STM32L4P5QE.json index a7b6d60..9ac51bf 100644 --- a/data/chips/STM32L4P5QE.json +++ b/data/chips/STM32L4P5QE.json @@ -2491,7 +2491,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2589,7 +2589,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5QG.json b/data/chips/STM32L4P5QG.json index de3eeb8..03cc8d8 100644 --- a/data/chips/STM32L4P5QG.json +++ b/data/chips/STM32L4P5QG.json @@ -2499,7 +2499,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2597,7 +2597,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5RE.json b/data/chips/STM32L4P5RE.json index 5eeee32..625f0eb 100644 --- a/data/chips/STM32L4P5RE.json +++ b/data/chips/STM32L4P5RE.json @@ -1909,7 +1909,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1987,7 +1987,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5RG.json b/data/chips/STM32L4P5RG.json index e574dcf..0642b2d 100644 --- a/data/chips/STM32L4P5RG.json +++ b/data/chips/STM32L4P5RG.json @@ -1913,7 +1913,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1991,7 +1991,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5VE.json b/data/chips/STM32L4P5VE.json index 213f12f..da53d17 100644 --- a/data/chips/STM32L4P5VE.json +++ b/data/chips/STM32L4P5VE.json @@ -2325,7 +2325,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2418,7 +2418,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5VG.json b/data/chips/STM32L4P5VG.json index 42b78de..696baa2 100644 --- a/data/chips/STM32L4P5VG.json +++ b/data/chips/STM32L4P5VG.json @@ -2333,7 +2333,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2426,7 +2426,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5ZE.json b/data/chips/STM32L4P5ZE.json index cb9a0c7..6c96f6d 100644 --- a/data/chips/STM32L4P5ZE.json +++ b/data/chips/STM32L4P5ZE.json @@ -2501,7 +2501,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2599,7 +2599,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5ZG.json b/data/chips/STM32L4P5ZG.json index e391bbc..5fdb0b6 100644 --- a/data/chips/STM32L4P5ZG.json +++ b/data/chips/STM32L4P5ZG.json @@ -2505,7 +2505,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2603,7 +2603,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5AG.json b/data/chips/STM32L4Q5AG.json index 916b536..e7f25e2 100644 --- a/data/chips/STM32L4Q5AG.json +++ b/data/chips/STM32L4Q5AG.json @@ -2679,7 +2679,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2777,7 +2777,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5CG.json b/data/chips/STM32L4Q5CG.json index 0d0f540..97f25e0 100644 --- a/data/chips/STM32L4Q5CG.json +++ b/data/chips/STM32L4Q5CG.json @@ -1738,7 +1738,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1796,7 +1796,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5QG.json b/data/chips/STM32L4Q5QG.json index 6ad7ab1..92f1f83 100644 --- a/data/chips/STM32L4Q5QG.json +++ b/data/chips/STM32L4Q5QG.json @@ -2534,7 +2534,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2632,7 +2632,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5RG.json b/data/chips/STM32L4Q5RG.json index b67fa3f..9c65536 100644 --- a/data/chips/STM32L4Q5RG.json +++ b/data/chips/STM32L4Q5RG.json @@ -1952,7 +1952,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2030,7 +2030,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5VG.json b/data/chips/STM32L4Q5VG.json index 94544d6..855425c 100644 --- a/data/chips/STM32L4Q5VG.json +++ b/data/chips/STM32L4Q5VG.json @@ -2372,7 +2372,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2465,7 +2465,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5ZG.json b/data/chips/STM32L4Q5ZG.json index 53c60f9..60a6cac 100644 --- a/data/chips/STM32L4Q5ZG.json +++ b/data/chips/STM32L4Q5ZG.json @@ -2544,7 +2544,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2642,7 +2642,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5AG.json b/data/chips/STM32L4R5AG.json index 7729dc3..7c6efc6 100644 --- a/data/chips/STM32L4R5AG.json +++ b/data/chips/STM32L4R5AG.json @@ -2598,7 +2598,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2696,7 +2696,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5AI.json b/data/chips/STM32L4R5AI.json index 4bf3a07..42d221f 100644 --- a/data/chips/STM32L4R5AI.json +++ b/data/chips/STM32L4R5AI.json @@ -2602,7 +2602,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2700,7 +2700,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5QG.json b/data/chips/STM32L4R5QG.json index f64598c..295c068 100644 --- a/data/chips/STM32L4R5QG.json +++ b/data/chips/STM32L4R5QG.json @@ -2457,7 +2457,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2555,7 +2555,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5QI.json b/data/chips/STM32L4R5QI.json index 03b23eb..6daa456 100644 --- a/data/chips/STM32L4R5QI.json +++ b/data/chips/STM32L4R5QI.json @@ -2457,7 +2457,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2555,7 +2555,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5VG.json b/data/chips/STM32L4R5VG.json index 8b8c57a..807e761 100644 --- a/data/chips/STM32L4R5VG.json +++ b/data/chips/STM32L4R5VG.json @@ -2253,7 +2253,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2331,7 +2331,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5VI.json b/data/chips/STM32L4R5VI.json index c56f18a..6377a24 100644 --- a/data/chips/STM32L4R5VI.json +++ b/data/chips/STM32L4R5VI.json @@ -2253,7 +2253,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2331,7 +2331,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5ZG.json b/data/chips/STM32L4R5ZG.json index 66f7af2..60da89b 100644 --- a/data/chips/STM32L4R5ZG.json +++ b/data/chips/STM32L4R5ZG.json @@ -2467,7 +2467,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2565,7 +2565,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5ZI.json b/data/chips/STM32L4R5ZI.json index 91ab29d..d7cc4c6 100644 --- a/data/chips/STM32L4R5ZI.json +++ b/data/chips/STM32L4R5ZI.json @@ -2477,7 +2477,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2575,7 +2575,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R7AI.json b/data/chips/STM32L4R7AI.json index 4b58715..b246c4f 100644 --- a/data/chips/STM32L4R7AI.json +++ b/data/chips/STM32L4R7AI.json @@ -2625,7 +2625,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2723,7 +2723,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R7VI.json b/data/chips/STM32L4R7VI.json index de35817..80a2d60 100644 --- a/data/chips/STM32L4R7VI.json +++ b/data/chips/STM32L4R7VI.json @@ -2280,7 +2280,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2358,7 +2358,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R7ZI.json b/data/chips/STM32L4R7ZI.json index fc20b19..b27b5fc 100644 --- a/data/chips/STM32L4R7ZI.json +++ b/data/chips/STM32L4R7ZI.json @@ -2490,7 +2490,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2588,7 +2588,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9AG.json b/data/chips/STM32L4R9AG.json index e3384c2..a3f459d 100644 --- a/data/chips/STM32L4R9AG.json +++ b/data/chips/STM32L4R9AG.json @@ -2588,7 +2588,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2686,7 +2686,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9AI.json b/data/chips/STM32L4R9AI.json index b9a6bb3..338f325 100644 --- a/data/chips/STM32L4R9AI.json +++ b/data/chips/STM32L4R9AI.json @@ -2588,7 +2588,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2686,7 +2686,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9VG.json b/data/chips/STM32L4R9VG.json index 406b346..5af26e8 100644 --- a/data/chips/STM32L4R9VG.json +++ b/data/chips/STM32L4R9VG.json @@ -2215,7 +2215,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2293,7 +2293,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9VI.json b/data/chips/STM32L4R9VI.json index 98fdfeb..11683df 100644 --- a/data/chips/STM32L4R9VI.json +++ b/data/chips/STM32L4R9VI.json @@ -2215,7 +2215,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2293,7 +2293,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9ZG.json b/data/chips/STM32L4R9ZG.json index a3440e5..b3472e9 100644 --- a/data/chips/STM32L4R9ZG.json +++ b/data/chips/STM32L4R9ZG.json @@ -2494,7 +2494,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2592,7 +2592,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9ZI.json b/data/chips/STM32L4R9ZI.json index 24a016c..1d883f9 100644 --- a/data/chips/STM32L4R9ZI.json +++ b/data/chips/STM32L4R9ZI.json @@ -2504,7 +2504,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2602,7 +2602,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S5AI.json b/data/chips/STM32L4S5AI.json index 3e04b0d..948cfcb 100644 --- a/data/chips/STM32L4S5AI.json +++ b/data/chips/STM32L4S5AI.json @@ -2671,7 +2671,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2769,7 +2769,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S5QI.json b/data/chips/STM32L4S5QI.json index 788d61d..cd74e8e 100644 --- a/data/chips/STM32L4S5QI.json +++ b/data/chips/STM32L4S5QI.json @@ -2526,7 +2526,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2624,7 +2624,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S5VI.json b/data/chips/STM32L4S5VI.json index f3196b7..77f4def 100644 --- a/data/chips/STM32L4S5VI.json +++ b/data/chips/STM32L4S5VI.json @@ -2326,7 +2326,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2404,7 +2404,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S5ZI.json b/data/chips/STM32L4S5ZI.json index e7af8dc..ef7f439 100644 --- a/data/chips/STM32L4S5ZI.json +++ b/data/chips/STM32L4S5ZI.json @@ -2540,7 +2540,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2638,7 +2638,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S7AI.json b/data/chips/STM32L4S7AI.json index 1213590..930659f 100644 --- a/data/chips/STM32L4S7AI.json +++ b/data/chips/STM32L4S7AI.json @@ -2698,7 +2698,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2796,7 +2796,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S7VI.json b/data/chips/STM32L4S7VI.json index 38fe885..6d7c5c2 100644 --- a/data/chips/STM32L4S7VI.json +++ b/data/chips/STM32L4S7VI.json @@ -2353,7 +2353,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2431,7 +2431,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S7ZI.json b/data/chips/STM32L4S7ZI.json index 32cb403..da60570 100644 --- a/data/chips/STM32L4S7ZI.json +++ b/data/chips/STM32L4S7ZI.json @@ -2563,7 +2563,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2661,7 +2661,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S9AI.json b/data/chips/STM32L4S9AI.json index 6cfb17e..56cb31f 100644 --- a/data/chips/STM32L4S9AI.json +++ b/data/chips/STM32L4S9AI.json @@ -2661,7 +2661,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2759,7 +2759,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S9VI.json b/data/chips/STM32L4S9VI.json index dcbf0e7..183fe8b 100644 --- a/data/chips/STM32L4S9VI.json +++ b/data/chips/STM32L4S9VI.json @@ -2288,7 +2288,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2366,7 +2366,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S9ZI.json b/data/chips/STM32L4S9ZI.json index 8edf531..bb494b9 100644 --- a/data/chips/STM32L4S9ZI.json +++ b/data/chips/STM32L4S9ZI.json @@ -2567,7 +2567,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2665,7 +2665,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552CC.json b/data/chips/STM32L552CC.json index 2dd0aa8..61541aa 100644 --- a/data/chips/STM32L552CC.json +++ b/data/chips/STM32L552CC.json @@ -1445,7 +1445,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1500,7 +1500,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1550,7 +1550,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552CE.json b/data/chips/STM32L552CE.json index a3c0d44..79d4d22 100644 --- a/data/chips/STM32L552CE.json +++ b/data/chips/STM32L552CE.json @@ -1453,7 +1453,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1508,7 +1508,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1558,7 +1558,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552ME.json b/data/chips/STM32L552ME.json index efbe5ff..cc7cf7f 100644 --- a/data/chips/STM32L552ME.json +++ b/data/chips/STM32L552ME.json @@ -1514,7 +1514,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1609,7 +1609,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1669,7 +1669,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552QC.json b/data/chips/STM32L552QC.json index d86558c..70dc76f 100644 --- a/data/chips/STM32L552QC.json +++ b/data/chips/STM32L552QC.json @@ -1984,7 +1984,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2079,7 +2079,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2154,7 +2154,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552QE.json b/data/chips/STM32L552QE.json index 6844408..ad2c749 100644 --- a/data/chips/STM32L552QE.json +++ b/data/chips/STM32L552QE.json @@ -1992,7 +1992,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2087,7 +2087,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2162,7 +2162,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552RC.json b/data/chips/STM32L552RC.json index 4229ebe..42341ad 100644 --- a/data/chips/STM32L552RC.json +++ b/data/chips/STM32L552RC.json @@ -1507,7 +1507,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1582,7 +1582,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1642,7 +1642,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552RE.json b/data/chips/STM32L552RE.json index 7b9a19b..01d4d08 100644 --- a/data/chips/STM32L552RE.json +++ b/data/chips/STM32L552RE.json @@ -1515,7 +1515,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1590,7 +1590,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1650,7 +1650,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552VC.json b/data/chips/STM32L552VC.json index 5a073e7..93840e1 100644 --- a/data/chips/STM32L552VC.json +++ b/data/chips/STM32L552VC.json @@ -1809,7 +1809,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1884,7 +1884,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1959,7 +1959,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552VE.json b/data/chips/STM32L552VE.json index 215f9b4..ea9d8be 100644 --- a/data/chips/STM32L552VE.json +++ b/data/chips/STM32L552VE.json @@ -1813,7 +1813,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1888,7 +1888,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1963,7 +1963,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552ZC.json b/data/chips/STM32L552ZC.json index 1bb35e9..3a851a6 100644 --- a/data/chips/STM32L552ZC.json +++ b/data/chips/STM32L552ZC.json @@ -1984,7 +1984,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2079,7 +2079,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2154,7 +2154,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552ZE.json b/data/chips/STM32L552ZE.json index d325df9..e881675 100644 --- a/data/chips/STM32L552ZE.json +++ b/data/chips/STM32L552ZE.json @@ -1988,7 +1988,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2083,7 +2083,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2158,7 +2158,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index 48f8a4a..b639923 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -1492,7 +1492,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1547,7 +1547,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1597,7 +1597,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index b3fe12a..3a33eb9 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -1553,7 +1553,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1648,7 +1648,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1708,7 +1708,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index 65fbbb0..6c8bf6e 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -2031,7 +2031,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2126,7 +2126,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2201,7 +2201,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index 6f8f7b6..7a10cd7 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -1554,7 +1554,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1629,7 +1629,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1689,7 +1689,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index 3c7d829..eac6480 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -1852,7 +1852,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1927,7 +1927,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2002,7 +2002,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index c9cdfb2..d4b29d0 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -2027,7 +2027,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2122,7 +2122,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2197,7 +2197,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index b5493d1..ba7451e 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -1334,7 +1334,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1424,7 +1424,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1509,7 +1509,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1581,7 +1581,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index 6040d83..f596a0e 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -1334,7 +1334,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1424,7 +1424,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1509,7 +1509,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1581,7 +1581,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index 2112c71..a5556a0 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -1334,7 +1334,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1424,7 +1424,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1509,7 +1509,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1581,7 +1581,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index 5b5d720..dbc22f7 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -1350,7 +1350,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1470,7 +1470,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1555,7 +1555,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1627,7 +1627,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index f24d0e6..615a7ee 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -1307,7 +1307,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1397,7 +1397,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1482,7 +1482,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1549,7 +1549,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index 16b5f1d..2f83e8a 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -1307,7 +1307,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1397,7 +1397,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1482,7 +1482,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1549,7 +1549,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index 8158549..baefadc 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -1410,7 +1410,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1520,7 +1520,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1620,7 +1620,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1717,7 +1717,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index 118fdba..9b329e4 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -1410,7 +1410,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1520,7 +1520,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1620,7 +1620,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1717,7 +1717,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index 8d58258..4cd6003 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -1410,7 +1410,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1520,7 +1520,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1620,7 +1620,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1717,7 +1717,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index ccdb925..b627c0c 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -1643,7 +1643,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1753,7 +1753,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1878,7 +1878,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1995,7 +1995,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index 9e7af51..cc738aa 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -1643,7 +1643,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1753,7 +1753,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1878,7 +1878,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1995,7 +1995,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index cbb404c..faad0ee 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -1373,7 +1373,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1463,7 +1463,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1548,7 +1548,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1620,7 +1620,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index afd55e6..510e078 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -1389,7 +1389,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1509,7 +1509,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1594,7 +1594,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1666,7 +1666,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 720e19a..eb1b2eb 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -1346,7 +1346,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1436,7 +1436,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1521,7 +1521,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1588,7 +1588,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index f2d6213..5bfcadf 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -1449,7 +1449,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1559,7 +1559,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1659,7 +1659,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1756,7 +1756,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index 35ced3b..de6c2e9 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -1682,7 +1682,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1792,7 +1792,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1917,7 +1917,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2034,7 +2034,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575AG.json b/data/chips/STM32U575AG.json index cde80d0..e53c718 100644 --- a/data/chips/STM32U575AG.json +++ b/data/chips/STM32U575AG.json @@ -2732,7 +2732,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2867,7 +2867,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2992,7 +2992,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3129,7 +3129,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575AI.json b/data/chips/STM32U575AI.json index f44a3bf..d0246fb 100644 --- a/data/chips/STM32U575AI.json +++ b/data/chips/STM32U575AI.json @@ -2732,7 +2732,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2867,7 +2867,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2992,7 +2992,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3129,7 +3129,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575CG.json b/data/chips/STM32U575CG.json index d36293b..f74394d 100644 --- a/data/chips/STM32U575CG.json +++ b/data/chips/STM32U575CG.json @@ -1803,7 +1803,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1893,7 +1893,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1978,7 +1978,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2050,7 +2050,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575CI.json b/data/chips/STM32U575CI.json index c26e1f9..fb0a1e6 100644 --- a/data/chips/STM32U575CI.json +++ b/data/chips/STM32U575CI.json @@ -1803,7 +1803,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1893,7 +1893,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1978,7 +1978,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2050,7 +2050,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575OG.json b/data/chips/STM32U575OG.json index b367f04..656caf0 100644 --- a/data/chips/STM32U575OG.json +++ b/data/chips/STM32U575OG.json @@ -2188,7 +2188,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2318,7 +2318,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2418,7 +2418,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2525,7 +2525,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575OI.json b/data/chips/STM32U575OI.json index b2f575f..5b67cfc 100644 --- a/data/chips/STM32U575OI.json +++ b/data/chips/STM32U575OI.json @@ -2188,7 +2188,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2318,7 +2318,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2418,7 +2418,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2525,7 +2525,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575QG.json b/data/chips/STM32U575QG.json index 3cbe4e2..2912624 100644 --- a/data/chips/STM32U575QG.json +++ b/data/chips/STM32U575QG.json @@ -2582,7 +2582,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2717,7 +2717,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2842,7 +2842,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2979,7 +2979,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575QI.json b/data/chips/STM32U575QI.json index 31a4cd9..ff99fec 100644 --- a/data/chips/STM32U575QI.json +++ b/data/chips/STM32U575QI.json @@ -2582,7 +2582,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2717,7 +2717,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2842,7 +2842,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2979,7 +2979,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575RG.json b/data/chips/STM32U575RG.json index c09e390..5bde263 100644 --- a/data/chips/STM32U575RG.json +++ b/data/chips/STM32U575RG.json @@ -2002,7 +2002,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2112,7 +2112,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2212,7 +2212,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2309,7 +2309,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575RI.json b/data/chips/STM32U575RI.json index df7314f..2fce614 100644 --- a/data/chips/STM32U575RI.json +++ b/data/chips/STM32U575RI.json @@ -2002,7 +2002,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2112,7 +2112,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2212,7 +2212,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2309,7 +2309,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575VG.json b/data/chips/STM32U575VG.json index 62c80c6..488dbd7 100644 --- a/data/chips/STM32U575VG.json +++ b/data/chips/STM32U575VG.json @@ -2381,7 +2381,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2491,7 +2491,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2616,7 +2616,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2733,7 +2733,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575VI.json b/data/chips/STM32U575VI.json index e123cb3..1ae92f6 100644 --- a/data/chips/STM32U575VI.json +++ b/data/chips/STM32U575VI.json @@ -2381,7 +2381,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2491,7 +2491,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2616,7 +2616,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2733,7 +2733,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575ZG.json b/data/chips/STM32U575ZG.json index d4b2820..5c0928a 100644 --- a/data/chips/STM32U575ZG.json +++ b/data/chips/STM32U575ZG.json @@ -2602,7 +2602,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2737,7 +2737,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2862,7 +2862,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2999,7 +2999,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575ZI.json b/data/chips/STM32U575ZI.json index 27f6626..6d575c1 100644 --- a/data/chips/STM32U575ZI.json +++ b/data/chips/STM32U575ZI.json @@ -2602,7 +2602,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2737,7 +2737,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2862,7 +2862,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2999,7 +2999,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index 2d8f357..b01233d 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -2777,7 +2777,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2912,7 +2912,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3037,7 +3037,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3174,7 +3174,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index 71d8241..7b0a25c 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -1848,7 +1848,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1938,7 +1938,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2023,7 +2023,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2095,7 +2095,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index aca36ce..614b260 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -2233,7 +2233,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2363,7 +2363,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2463,7 +2463,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2570,7 +2570,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index 97586b2..0ec352c 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -2627,7 +2627,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2762,7 +2762,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2887,7 +2887,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3024,7 +3024,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index dcd8769..882d5ca 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -2047,7 +2047,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2157,7 +2157,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2257,7 +2257,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2354,7 +2354,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index 9d6017b..a8e7e5c 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -2426,7 +2426,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2536,7 +2536,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2661,7 +2661,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2778,7 +2778,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index f36815d..cc25177 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -2647,7 +2647,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2782,7 +2782,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2907,7 +2907,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3044,7 +3044,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index 4e030c8..1e9b8c4 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -2633,7 +2633,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2768,7 +2768,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2893,7 +2893,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3030,7 +3030,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index 3dc1e6c..aa9cfd8 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -2633,7 +2633,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2768,7 +2768,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2893,7 +2893,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3030,7 +3030,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index b0bcfa5..62bfc1b 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -2468,7 +2468,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2603,7 +2603,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2728,7 +2728,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2865,7 +2865,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index a077985..ea0eb08 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -2468,7 +2468,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2603,7 +2603,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2728,7 +2728,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2865,7 +2865,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index 461b143..84512b4 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -1751,7 +1751,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1861,7 +1861,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1961,7 +1961,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2058,7 +2058,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index 8544dfd..f820927 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -1751,7 +1751,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1861,7 +1861,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1961,7 +1961,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2058,7 +2058,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index 513754d..658ab81 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -2247,7 +2247,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2357,7 +2357,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2482,7 +2482,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2599,7 +2599,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index 2b121ce..94e7540 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -2247,7 +2247,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2357,7 +2357,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2482,7 +2482,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2599,7 +2599,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index f47f907..a563fff 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -2492,7 +2492,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2627,7 +2627,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2752,7 +2752,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2889,7 +2889,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index 342e2ba..31b538f 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -2492,7 +2492,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2627,7 +2627,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2752,7 +2752,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2889,7 +2889,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index d94e25c..fb4c23d 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -2838,7 +2838,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2973,7 +2973,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3098,7 +3098,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3235,7 +3235,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index 40342e8..cf50f11 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -2863,7 +2863,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2998,7 +2998,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3123,7 +3123,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3260,7 +3260,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index f74a705..57d1ecb 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -2863,7 +2863,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2998,7 +2998,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3123,7 +3123,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3260,7 +3260,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index ea4926b..f518be6 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -2258,7 +2258,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2368,7 +2368,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2493,7 +2493,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2610,7 +2610,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index 360afad..23aae95 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -2319,7 +2319,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2429,7 +2429,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2554,7 +2554,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2671,7 +2671,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index acd596d..731a72a 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -2560,7 +2560,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2690,7 +2690,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2815,7 +2815,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2952,7 +2952,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index aa50195..d47126a 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -2560,7 +2560,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2690,7 +2690,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2815,7 +2815,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2952,7 +2952,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index 90c4f4d..ce6a5aa 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -2672,7 +2672,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2807,7 +2807,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2932,7 +2932,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3069,7 +3069,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index e7f6a21..dd80439 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -2507,7 +2507,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2642,7 +2642,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2767,7 +2767,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2904,7 +2904,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index 35f8e5a..3d00b57 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -1790,7 +1790,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -1900,7 +1900,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2000,7 +2000,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2097,7 +2097,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index 0cd5629..8f6d517 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -2286,7 +2286,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2396,7 +2396,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2521,7 +2521,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2638,7 +2638,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 01b09f6..9ab903e 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -2531,7 +2531,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2666,7 +2666,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2791,7 +2791,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2928,7 +2928,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 70fe072..0c3220b 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -2877,7 +2877,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3012,7 +3012,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3137,7 +3137,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3274,7 +3274,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index 3070243..6f6e395 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -2902,7 +2902,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3037,7 +3037,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3162,7 +3162,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -3299,7 +3299,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 61a608b..50a588b 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -2297,7 +2297,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2407,7 +2407,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2532,7 +2532,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2649,7 +2649,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index d267611..184bbd5 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -2599,7 +2599,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2729,7 +2729,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2854,7 +2854,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -2991,7 +2991,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32WB10CC.json b/data/chips/STM32WB10CC.json index 36d15c2..c7be49b 100644 --- a/data/chips/STM32WB10CC.json +++ b/data/chips/STM32WB10CC.json @@ -1114,7 +1114,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1172,7 +1172,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB15CC.json b/data/chips/STM32WB15CC.json index ad1cbe9..3bb9c33 100644 --- a/data/chips/STM32WB15CC.json +++ b/data/chips/STM32WB15CC.json @@ -1180,7 +1180,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1238,7 +1238,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB30CE.json b/data/chips/STM32WB30CE.json index b32ae3e..fa48b4f 100644 --- a/data/chips/STM32WB30CE.json +++ b/data/chips/STM32WB30CE.json @@ -950,7 +950,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1008,7 +1008,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB35CC.json b/data/chips/STM32WB35CC.json index c97e52a..bbc88c6 100644 --- a/data/chips/STM32WB35CC.json +++ b/data/chips/STM32WB35CC.json @@ -1249,7 +1249,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1307,7 +1307,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB35CE.json b/data/chips/STM32WB35CE.json index 59e0202..fbee787 100644 --- a/data/chips/STM32WB35CE.json +++ b/data/chips/STM32WB35CE.json @@ -1249,7 +1249,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1307,7 +1307,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB50CG.json b/data/chips/STM32WB50CG.json index 85fe212..07e223c 100644 --- a/data/chips/STM32WB50CG.json +++ b/data/chips/STM32WB50CG.json @@ -950,7 +950,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1008,7 +1008,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55CC.json b/data/chips/STM32WB55CC.json index 0627fcf..441a713 100644 --- a/data/chips/STM32WB55CC.json +++ b/data/chips/STM32WB55CC.json @@ -1399,7 +1399,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1457,7 +1457,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55CE.json b/data/chips/STM32WB55CE.json index 5ee4735..bc87e61 100644 --- a/data/chips/STM32WB55CE.json +++ b/data/chips/STM32WB55CE.json @@ -1399,7 +1399,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1457,7 +1457,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55CG.json b/data/chips/STM32WB55CG.json index bfc7032..52afcec 100644 --- a/data/chips/STM32WB55CG.json +++ b/data/chips/STM32WB55CG.json @@ -1399,7 +1399,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1457,7 +1457,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55RC.json b/data/chips/STM32WB55RC.json index e9dec3f..1293283 100644 --- a/data/chips/STM32WB55RC.json +++ b/data/chips/STM32WB55RC.json @@ -1586,7 +1586,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1664,7 +1664,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55RE.json b/data/chips/STM32WB55RE.json index 59e2a8c..48dd531 100644 --- a/data/chips/STM32WB55RE.json +++ b/data/chips/STM32WB55RE.json @@ -1586,7 +1586,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1664,7 +1664,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55RG.json b/data/chips/STM32WB55RG.json index a891b01..6391759 100644 --- a/data/chips/STM32WB55RG.json +++ b/data/chips/STM32WB55RG.json @@ -1586,7 +1586,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1664,7 +1664,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55VC.json b/data/chips/STM32WB55VC.json index abb5fce..b7f6606 100644 --- a/data/chips/STM32WB55VC.json +++ b/data/chips/STM32WB55VC.json @@ -1680,7 +1680,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1758,7 +1758,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55VE.json b/data/chips/STM32WB55VE.json index 5b13cd0..d88fcc2 100644 --- a/data/chips/STM32WB55VE.json +++ b/data/chips/STM32WB55VE.json @@ -1680,7 +1680,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1758,7 +1758,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55VG.json b/data/chips/STM32WB55VG.json index f8cf8a6..54f4ca7 100644 --- a/data/chips/STM32WB55VG.json +++ b/data/chips/STM32WB55VG.json @@ -1680,7 +1680,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1758,7 +1758,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55VY.json b/data/chips/STM32WB55VY.json index a41eef4..37c573b 100644 --- a/data/chips/STM32WB55VY.json +++ b/data/chips/STM32WB55VY.json @@ -1658,7 +1658,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1736,7 +1736,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WBA52CE.json b/data/chips/STM32WBA52CE.json index eb5ef3a..50851ad 100644 --- a/data/chips/STM32WBA52CE.json +++ b/data/chips/STM32WBA52CE.json @@ -674,7 +674,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -759,7 +759,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32WBA52CG.json b/data/chips/STM32WBA52CG.json index 162ead1..4715906 100644 --- a/data/chips/STM32WBA52CG.json +++ b/data/chips/STM32WBA52CG.json @@ -674,7 +674,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -759,7 +759,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32WBA52KE.json b/data/chips/STM32WBA52KE.json index c6dbd29..3ddb8db 100644 --- a/data/chips/STM32WBA52KE.json +++ b/data/chips/STM32WBA52KE.json @@ -650,7 +650,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -725,7 +725,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32WBA52KG.json b/data/chips/STM32WBA52KG.json index d72eb91..357d6c4 100644 --- a/data/chips/STM32WBA52KG.json +++ b/data/chips/STM32WBA52KG.json @@ -650,7 +650,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { @@ -725,7 +725,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32WL54CC.json b/data/chips/STM32WL54CC.json index ca1c3e1..829394a 100644 --- a/data/chips/STM32WL54CC.json +++ b/data/chips/STM32WL54CC.json @@ -1133,7 +1133,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1193,7 +1193,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1238,7 +1238,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3706,7 +3706,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3766,7 +3766,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3811,7 +3811,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WL54JC.json b/data/chips/STM32WL54JC.json index b96aca6..e628b5a 100644 --- a/data/chips/STM32WL54JC.json +++ b/data/chips/STM32WL54JC.json @@ -1199,7 +1199,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1279,7 +1279,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1339,7 +1339,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4023,7 +4023,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4103,7 +4103,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4163,7 +4163,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WL55CC.json b/data/chips/STM32WL55CC.json index 80bc21c..19d9ec6 100644 --- a/data/chips/STM32WL55CC.json +++ b/data/chips/STM32WL55CC.json @@ -1139,7 +1139,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1199,7 +1199,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1244,7 +1244,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3712,7 +3712,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3772,7 +3772,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3817,7 +3817,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WL55JC.json b/data/chips/STM32WL55JC.json index 4c69486..deafbfa 100644 --- a/data/chips/STM32WL55JC.json +++ b/data/chips/STM32WL55JC.json @@ -1205,7 +1205,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1285,7 +1285,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1345,7 +1345,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4029,7 +4029,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4109,7 +4109,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4169,7 +4169,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4C8.json b/data/chips/STM32WLE4C8.json index df8c152..cb32b51 100644 --- a/data/chips/STM32WLE4C8.json +++ b/data/chips/STM32WLE4C8.json @@ -921,7 +921,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -981,7 +981,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1026,7 +1026,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4CB.json b/data/chips/STM32WLE4CB.json index 7db9768..c84b9d9 100644 --- a/data/chips/STM32WLE4CB.json +++ b/data/chips/STM32WLE4CB.json @@ -921,7 +921,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -981,7 +981,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1026,7 +1026,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4CC.json b/data/chips/STM32WLE4CC.json index 7ab9146..fddf424 100644 --- a/data/chips/STM32WLE4CC.json +++ b/data/chips/STM32WLE4CC.json @@ -1096,7 +1096,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1156,7 +1156,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1201,7 +1201,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4J8.json b/data/chips/STM32WLE4J8.json index a170f62..d2b7aef 100644 --- a/data/chips/STM32WLE4J8.json +++ b/data/chips/STM32WLE4J8.json @@ -987,7 +987,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1067,7 +1067,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1127,7 +1127,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4JB.json b/data/chips/STM32WLE4JB.json index 9a1fac0..573845c 100644 --- a/data/chips/STM32WLE4JB.json +++ b/data/chips/STM32WLE4JB.json @@ -987,7 +987,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1067,7 +1067,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1127,7 +1127,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4JC.json b/data/chips/STM32WLE4JC.json index 768f83f..786e38d 100644 --- a/data/chips/STM32WLE4JC.json +++ b/data/chips/STM32WLE4JC.json @@ -1162,7 +1162,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1242,7 +1242,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1302,7 +1302,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5C8.json b/data/chips/STM32WLE5C8.json index e342b6a..2a690e5 100644 --- a/data/chips/STM32WLE5C8.json +++ b/data/chips/STM32WLE5C8.json @@ -1096,7 +1096,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1156,7 +1156,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1201,7 +1201,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5CB.json b/data/chips/STM32WLE5CB.json index c3144f9..2334c83 100644 --- a/data/chips/STM32WLE5CB.json +++ b/data/chips/STM32WLE5CB.json @@ -1096,7 +1096,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1156,7 +1156,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1201,7 +1201,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5CC.json b/data/chips/STM32WLE5CC.json index 09c3ce1..143c18d 100644 --- a/data/chips/STM32WLE5CC.json +++ b/data/chips/STM32WLE5CC.json @@ -1096,7 +1096,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1156,7 +1156,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1201,7 +1201,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5J8.json b/data/chips/STM32WLE5J8.json index 4a9bc89..15dbd17 100644 --- a/data/chips/STM32WLE5J8.json +++ b/data/chips/STM32WLE5J8.json @@ -1162,7 +1162,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1242,7 +1242,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1302,7 +1302,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5JB.json b/data/chips/STM32WLE5JB.json index ab18672..a2f55d0 100644 --- a/data/chips/STM32WLE5JB.json +++ b/data/chips/STM32WLE5JB.json @@ -1162,7 +1162,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1242,7 +1242,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1302,7 +1302,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5JC.json b/data/chips/STM32WLE5JC.json index 44d1587..658cc3c 100644 --- a/data/chips/STM32WLE5JC.json +++ b/data/chips/STM32WLE5JC.json @@ -1162,7 +1162,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1242,7 +1242,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1302,7 +1302,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/registers/lptim_v1.json b/data/registers/lptim_v1.json index d9b536a..ccf6e66 100644 --- a/data/registers/lptim_v1.json +++ b/data/registers/lptim_v1.json @@ -1,338 +1,500 @@ { "block/LPTIM": { - "description": "Low power timer", + "description": "Low power timer with Output Compare", "items": [ { "name": "ISR", - "description": "Interrupt and Status Register", + "description": "LPTIM interrupt and status register.", "byte_offset": 0, - "access": "Read", "fieldset": "ISR" }, { "name": "ICR", - "description": "Interrupt Clear Register", + "description": "LPTIM interrupt clear register.", "byte_offset": 4, - "access": "Write", "fieldset": "ICR" }, { "name": "IER", - "description": "Interrupt Enable Register", + "description": "LPTIM interrupt enable register.", "byte_offset": 8, "fieldset": "IER" }, { "name": "CFGR", - "description": "Configuration Register", + "description": "LPTIM configuration register.", "byte_offset": 12, "fieldset": "CFGR" }, { "name": "CR", - "description": "Control Register", + "description": "LPTIM control register.", "byte_offset": 16, "fieldset": "CR" }, { "name": "CMP", - "description": "Compare Register", + "description": "LPTIM compare register 1.", "byte_offset": 20, "fieldset": "CMP" }, { "name": "ARR", - "description": "Autoreload Register", + "description": "LPTIM autoreload register.", "byte_offset": 24, "fieldset": "ARR" }, { "name": "CNT", - "description": "Counter Register", + "description": "LPTIM counter register.", "byte_offset": 28, - "access": "Read", "fieldset": "CNT" } ] }, "fieldset/ARR": { - "description": "Autoreload Register", + "description": "LPTIM autoreload register.", "fields": [ { "name": "ARR", - "description": "Auto reload value", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", "bit_offset": 0, "bit_size": 16 } ] }, "fieldset/CFGR": { - "description": "Configuration Register", + "description": "LPTIM configuration register.", "fields": [ { "name": "CKSEL", - "description": "Clock selector", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 1, + "enum": "ClockSource" }, { "name": "CKPOL", - "description": "Clock Polarity", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", "bit_offset": 1, - "bit_size": 2 + "bit_size": 2, + "enum": "CKPOL" }, { "name": "CKFLT", - "description": "Configurable digital filter for external clock", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", "bit_offset": 3, - "bit_size": 2 + "bit_size": 2, + "enum": "Filter" }, { "name": "TRGFLT", - "description": "Configurable digital filter for trigger", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", "bit_offset": 6, - "bit_size": 2 + "bit_size": 2, + "enum": "Filter" }, { "name": "PRESC", - "description": "Clock prescaler", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", "bit_offset": 9, - "bit_size": 3 + "bit_size": 3, + "enum": "PRESC" }, { "name": "TRIGSEL", - "description": "Trigger selector", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", "bit_offset": 13, "bit_size": 3 }, { "name": "TRIGEN", - "description": "Trigger enable and polarity", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", "bit_offset": 17, - "bit_size": 2 + "bit_size": 2, + "enum": "TRIGEN" }, { "name": "TIMOUT", - "description": "Timeout enable", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", "bit_offset": 19, "bit_size": 1 }, { "name": "WAVE", - "description": "Waveform shape", + "description": "Waveform shape The WAVE bit controls the output shape.", "bit_offset": 20, "bit_size": 1 }, { "name": "WAVPOL", - "description": "Waveform shape polarity", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", "bit_offset": 21, - "bit_size": 1 + "bit_size": 1, + "enum": "WAVPOL" }, { "name": "PRELOAD", - "description": "Registers update mode", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", "bit_offset": 22, "bit_size": 1 }, { "name": "COUNTMODE", - "description": "counter mode enabled", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", "bit_offset": 23, - "bit_size": 1 + "bit_size": 1, + "enum": "ClockSource" }, { "name": "ENC", - "description": "Encoder mode enable", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 24, "bit_size": 1 } ] }, "fieldset/CMP": { - "description": "Compare Register", + "description": "LPTIM compare register 1.", "fields": [ { "name": "CMP", - "description": "Compare value", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", "bit_offset": 0, "bit_size": 16 } ] }, "fieldset/CNT": { - "description": "Counter Register", + "description": "LPTIM counter register.", "fields": [ { "name": "CNT", - "description": "Counter value", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", "bit_offset": 0, "bit_size": 16 } ] }, "fieldset/CR": { - "description": "Control Register", + "description": "LPTIM control register.", "fields": [ { "name": "ENABLE", - "description": "LPTIM Enable", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", "bit_offset": 0, "bit_size": 1 }, { "name": "SNGSTRT", - "description": "LPTIM start in single mode", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", "bit_offset": 1, "bit_size": 1 }, { "name": "CNTSTRT", - "description": "Timer start in continuous mode", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", "bit_offset": 2, "bit_size": 1 } ] }, "fieldset/ICR": { - "description": "Interrupt Clear Register", + "description": "LPTIM interrupt clear register.", "fields": [ { - "name": "CMPMCF", - "description": "compare match Clear Flag", + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } }, { "name": "ARRMCF", - "description": "Autoreload match Clear Flag", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", "bit_offset": 1, "bit_size": 1 }, { "name": "EXTTRIGCF", - "description": "External trigger valid edge Clear Flag", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", "bit_offset": 2, "bit_size": 1 }, { "name": "CMPOKCF", - "description": "Compare register update OK Clear Flag", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", "bit_offset": 3, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } }, { "name": "ARROKCF", - "description": "Autoreload register update OK Clear Flag", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", "bit_offset": 4, "bit_size": 1 }, { "name": "UPCF", - "description": "Direction change to UP Clear Flag", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 5, "bit_size": 1 }, { "name": "DOWNCF", - "description": "Direction change to down Clear Flag", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 6, "bit_size": 1 } ] }, "fieldset/IER": { - "description": "Interrupt Enable Register", + "description": "LPTIM interrupt enable register.", "fields": [ { - "name": "CMPMIE", - "description": "Compare match Interrupt Enable", + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } }, { "name": "ARRMIE", - "description": "Autoreload match Interrupt Enable", + "description": "Autoreload match Interrupt Enable.", "bit_offset": 1, "bit_size": 1 }, { "name": "EXTTRIGIE", - "description": "External trigger valid edge Interrupt Enable", + "description": "External trigger valid edge Interrupt Enable.", "bit_offset": 2, "bit_size": 1 }, { "name": "CMPOKIE", - "description": "Compare register update OK Interrupt Enable", + "description": "Compare register 1 update OK interrupt enable.", "bit_offset": 3, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } }, { "name": "ARROKIE", - "description": "Autoreload register update OK Interrupt Enable", + "description": "Autoreload register update OK Interrupt Enable.", "bit_offset": 4, "bit_size": 1 }, { "name": "UPIE", - "description": "Direction change to UP Interrupt Enable", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 5, "bit_size": 1 }, { "name": "DOWNIE", - "description": "Direction change to down Interrupt Enable", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 6, "bit_size": 1 } ] }, "fieldset/ISR": { - "description": "Interrupt and Status Register", + "description": "LPTIM interrupt and status register.", "fields": [ { - "name": "CMPM", - "description": "Compare match", + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } }, { "name": "ARRM", - "description": "Autoreload match", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", "bit_offset": 1, "bit_size": 1 }, { "name": "EXTTRIG", - "description": "External trigger edge event", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", "bit_offset": 2, "bit_size": 1 }, { "name": "CMPOK", - "description": "Compare register update OK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", "bit_offset": 3, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } }, { "name": "ARROK", - "description": "Autoreload register update OK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", "bit_offset": 4, "bit_size": 1 }, { "name": "UP", - "description": "Counter direction change down to up", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 5, "bit_size": 1 }, { "name": "DOWN", - "description": "Counter direction change up to down", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 6, "bit_size": 1 } ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] } } \ No newline at end of file diff --git a/data/registers/lptim_v1a.json b/data/registers/lptim_v1a.json new file mode 100644 index 0000000..5a7d7ff --- /dev/null +++ b/data/registers/lptim_v1a.json @@ -0,0 +1,505 @@ +{ + "block/LPTIM": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CMP", + "description": "LPTIM compare register 1.", + "byte_offset": 20, + "fieldset": "CMP" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "OR", + "description": "LPTIM option register.", + "byte_offset": 32 + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": 13, + "bit_size": 3 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1, + "enum": "WAVPOL" + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CMP": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CMP", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/lptim_v1b.json b/data/registers/lptim_v1b.json new file mode 100644 index 0000000..8f8ec12 --- /dev/null +++ b/data/registers/lptim_v1b.json @@ -0,0 +1,517 @@ +{ + "block/LPTIM": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CMP", + "description": "LPTIM compare register 1.", + "byte_offset": 20, + "fieldset": "CMP" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "OR", + "description": "LPTIM option register.", + "byte_offset": 32 + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": 13, + "bit_size": 3 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1, + "enum": "WAVPOL" + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CMP": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CMP", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "COUNTRST", + "description": "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "RSTARE", + "description": "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/lptim_v1b_g4.json b/data/registers/lptim_v1b_g4.json new file mode 100644 index 0000000..f52a658 --- /dev/null +++ b/data/registers/lptim_v1b_g4.json @@ -0,0 +1,526 @@ +{ + "block/LPTIM": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CMP", + "description": "LPTIM compare register 1.", + "byte_offset": 20, + "fieldset": "CMP" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "OR", + "description": "LPTIM option register.", + "byte_offset": 32 + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": [ + { + "start": 13, + "end": 15 + }, + { + "start": 29, + "end": 29 + } + ], + "bit_size": 4 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1, + "enum": "WAVPOL" + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CMP": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CMP", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "COUNTRST", + "description": "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "RSTARE", + "description": "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/lptim_v1b_h7.json b/data/registers/lptim_v1b_h7.json new file mode 100644 index 0000000..a154b4b --- /dev/null +++ b/data/registers/lptim_v1b_h7.json @@ -0,0 +1,533 @@ +{ + "block/LPTIM": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CMP", + "description": "LPTIM compare register 1.", + "byte_offset": 20, + "fieldset": "CMP" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "CFGR2", + "description": "LPTIM configuration register 2.", + "byte_offset": 36, + "fieldset": "CFGR2" + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": 13, + "bit_size": 3 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1, + "enum": "WAVPOL" + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR2": { + "description": "LPTIM configuration register 2.", + "fields": [ + { + "name": "INSEL", + "description": "LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to.", + "bit_offset": 0, + "bit_size": 2, + "array": { + "len": 2, + "stride": 4 + } + } + ] + }, + "fieldset/CMP": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CMP", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "COUNTRST", + "description": "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "RSTARE", + "description": "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/lptim_v1c.json b/data/registers/lptim_v1c.json new file mode 100644 index 0000000..5fe21f2 --- /dev/null +++ b/data/registers/lptim_v1c.json @@ -0,0 +1,570 @@ +{ + "block/LPTIM": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CMP", + "description": "LPTIM compare register 1.", + "byte_offset": 20, + "fieldset": "CMP" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "OR", + "description": "LPTIM option register.", + "byte_offset": 32 + }, + { + "name": "RCR", + "description": "LPTIM repetition register.", + "byte_offset": 40, + "fieldset": "RCR" + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": 13, + "bit_size": 3 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1, + "enum": "WAVPOL" + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CMP": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CMP", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "COUNTRST", + "description": "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "RSTARE", + "description": "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UECF", + "description": "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKCF", + "description": "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UEIE", + "description": "Update event interrupt enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKIE", + "description": "Repetition register update OK interrupt Enable.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UE", + "description": "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOK", + "description": "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/RCR": { + "description": "LPTIM repetition register.", + "fields": [ + { + "name": "REP", + "description": "Repetition register value REP is the repetition value for the LPTIM.", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/lptim_v2b.json b/data/registers/lptim_v2.json similarity index 97% rename from data/registers/lptim_v2b.json rename to data/registers/lptim_v2.json index db4fe37..b94eaee 100644 --- a/data/registers/lptim_v2b.json +++ b/data/registers/lptim_v2.json @@ -208,7 +208,7 @@ "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", "bit_offset": 0, "bit_size": 1, - "enum": "CKSEL" + "enum": "ClockSource" }, { "name": "CKPOL", @@ -267,7 +267,8 @@ "name": "WAVPOL", "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", "bit_offset": 21, - "bit_size": 1 + "bit_size": 1, + "enum": "WAVPOL" }, { "name": "PRELOAD", @@ -279,7 +280,8 @@ "name": "COUNTMODE", "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", "bit_offset": 23, - "bit_size": 1 + "bit_size": 1, + "enum": "ClockSource" }, { "name": "ENC", @@ -767,17 +769,17 @@ } ] }, - "enum/CKSEL": { + "enum/ClockSource": { "bit_size": 1, "variants": [ { "name": "Internal", - "description": "LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", "value": 0 }, { "name": "External", - "description": "LPTIM is clocked by an external clock source through the LPTIM external Input1", + "description": "clocked by an external clock source through the LPTIM external Input1", "value": 1 } ] @@ -864,5 +866,20 @@ "value": 3 } ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] } } \ No newline at end of file diff --git a/data/registers/lptim_v2a.json b/data/registers/lptim_v2a.json deleted file mode 100644 index 32d58c6..0000000 --- a/data/registers/lptim_v2a.json +++ /dev/null @@ -1,506 +0,0 @@ -{ - "block/LPTIM": { - "description": "Low power timer.", - "items": [ - { - "name": "ISR", - "description": "Interrupt and Status Register.", - "byte_offset": 0, - "access": "Read", - "fieldset": "ISR" - }, - { - "name": "ICR", - "description": "Interrupt Clear Register.", - "byte_offset": 4, - "access": "Write", - "fieldset": "ICR" - }, - { - "name": "IER", - "description": "Interrupt Enable Register.", - "byte_offset": 8, - "fieldset": "IER" - }, - { - "name": "CFGR", - "description": "Configuration Register.", - "byte_offset": 12, - "fieldset": "CFGR" - }, - { - "name": "CR", - "description": "Control Register.", - "byte_offset": 16, - "fieldset": "CR" - }, - { - "name": "CMP", - "description": "Compare Register.", - "byte_offset": 20, - "fieldset": "CMP" - }, - { - "name": "ARR", - "description": "Autoreload Register.", - "byte_offset": 24, - "fieldset": "ARR" - }, - { - "name": "CNT", - "description": "Counter Register.", - "byte_offset": 28, - "access": "Read", - "fieldset": "CNT" - }, - { - "name": "OR", - "description": "LPTIM option register.", - "byte_offset": 32 - }, - { - "name": "RCR", - "description": "LPTIM repetition register.", - "byte_offset": 40, - "fieldset": "RCR" - } - ] - }, - "fieldset/ARR": { - "description": "Autoreload Register.", - "fields": [ - { - "name": "ARR", - "description": "Auto reload value.", - "bit_offset": 0, - "bit_size": 16 - } - ] - }, - "fieldset/CFGR": { - "description": "Configuration Register.", - "fields": [ - { - "name": "CKSEL", - "description": "Clock selector.", - "bit_offset": 0, - "bit_size": 1, - "enum": "CKSEL" - }, - { - "name": "CKPOL", - "description": "Clock Polarity.", - "bit_offset": 1, - "bit_size": 2, - "enum": "CKPOL" - }, - { - "name": "CKFLT", - "description": "Configurable digital filter for external clock.", - "bit_offset": 3, - "bit_size": 2, - "enum": "Filter" - }, - { - "name": "TRGFLT", - "description": "Configurable digital filter for trigger.", - "bit_offset": 6, - "bit_size": 2, - "enum": "Filter" - }, - { - "name": "PRESC", - "description": "Clock prescaler.", - "bit_offset": 9, - "bit_size": 3, - "enum": "PRESC" - }, - { - "name": "TRIGSEL", - "description": "Trigger selector.", - "bit_offset": 13, - "bit_size": 3 - }, - { - "name": "TRIGEN", - "description": "Trigger enable and polarity.", - "bit_offset": 17, - "bit_size": 2 - }, - { - "name": "TIMOUT", - "description": "Timeout enable.", - "bit_offset": 19, - "bit_size": 1 - }, - { - "name": "WAVE", - "description": "Waveform shape.", - "bit_offset": 20, - "bit_size": 1 - }, - { - "name": "WAVPOL", - "description": "Waveform shape polarity.", - "bit_offset": 21, - "bit_size": 1 - }, - { - "name": "PRELOAD", - "description": "Registers update mode.", - "bit_offset": 22, - "bit_size": 1 - }, - { - "name": "COUNTMODE", - "description": "counter mode enabled.", - "bit_offset": 23, - "bit_size": 1 - }, - { - "name": "ENC", - "description": "Encoder mode enable.", - "bit_offset": 24, - "bit_size": 1 - } - ] - }, - "fieldset/CMP": { - "description": "Compare Register.", - "fields": [ - { - "name": "CMP", - "description": "Compare value.", - "bit_offset": 0, - "bit_size": 16 - } - ] - }, - "fieldset/CNT": { - "description": "Counter Register.", - "fields": [ - { - "name": "CNT", - "description": "Counter value.", - "bit_offset": 0, - "bit_size": 16 - } - ] - }, - "fieldset/CR": { - "description": "Control Register.", - "fields": [ - { - "name": "ENABLE", - "description": "LPTIM Enable.", - "bit_offset": 0, - "bit_size": 1 - }, - { - "name": "SNGSTRT", - "description": "LPTIM start in single mode.", - "bit_offset": 1, - "bit_size": 1 - }, - { - "name": "CNTSTRT", - "description": "Timer start in continuous mode.", - "bit_offset": 2, - "bit_size": 1 - }, - { - "name": "RSTARE", - "description": "Reset after read enable.", - "bit_offset": 3, - "bit_size": 1 - }, - { - "name": "COUNTRST", - "description": "Counter reset.", - "bit_offset": 4, - "bit_size": 1 - } - ] - }, - "fieldset/ICR": { - "description": "Interrupt Clear Register.", - "fields": [ - { - "name": "CMPMCF", - "description": "compare match Clear Flag.", - "bit_offset": 0, - "bit_size": 1 - }, - { - "name": "ARRMCF", - "description": "Autoreload match Clear Flag.", - "bit_offset": 1, - "bit_size": 1 - }, - { - "name": "EXTTRIGCF", - "description": "External trigger valid edge Clear Flag.", - "bit_offset": 2, - "bit_size": 1 - }, - { - "name": "CMPOKCF", - "description": "Compare register update OK Clear Flag.", - "bit_offset": 3, - "bit_size": 1 - }, - { - "name": "ARROKCF", - "description": "Autoreload register update OK Clear Flag.", - "bit_offset": 4, - "bit_size": 1 - }, - { - "name": "UPCF", - "description": "Direction change to UP Clear Flag.", - "bit_offset": 5, - "bit_size": 1 - }, - { - "name": "DOWNCF", - "description": "Direction change to down Clear Flag.", - "bit_offset": 6, - "bit_size": 1 - }, - { - "name": "UECF", - "description": "Update event clear flag.", - "bit_offset": 7, - "bit_size": 1 - }, - { - "name": "REPOKCF", - "description": "Repetition register update OK clear flag.", - "bit_offset": 8, - "bit_size": 1 - } - ] - }, - "fieldset/IER": { - "description": "Interrupt Enable Register.", - "fields": [ - { - "name": "CMPMIE", - "description": "Compare match Interrupt Enable.", - "bit_offset": 0, - "bit_size": 1 - }, - { - "name": "ARRMIE", - "description": "Autoreload match Interrupt Enable.", - "bit_offset": 1, - "bit_size": 1 - }, - { - "name": "EXTTRIGIE", - "description": "External trigger valid edge Interrupt Enable.", - "bit_offset": 2, - "bit_size": 1 - }, - { - "name": "CMPOKIE", - "description": "Compare register update OK Interrupt Enable.", - "bit_offset": 3, - "bit_size": 1 - }, - { - "name": "ARROKIE", - "description": "Autoreload register update OK Interrupt Enable.", - "bit_offset": 4, - "bit_size": 1 - }, - { - "name": "UPIE", - "description": "Direction change to UP Interrupt Enable.", - "bit_offset": 5, - "bit_size": 1 - }, - { - "name": "DOWNIE", - "description": "Direction change to down Interrupt Enable.", - "bit_offset": 6, - "bit_size": 1 - }, - { - "name": "UEIE", - "description": "Update event interrupt enable.", - "bit_offset": 7, - "bit_size": 1 - }, - { - "name": "REPOKIE", - "description": "REPOKIE.", - "bit_offset": 8, - "bit_size": 1 - } - ] - }, - "fieldset/ISR": { - "description": "Interrupt and Status Register.", - "fields": [ - { - "name": "CMPM", - "description": "Compare match.", - "bit_offset": 0, - "bit_size": 1 - }, - { - "name": "ARRM", - "description": "Autoreload match.", - "bit_offset": 1, - "bit_size": 1 - }, - { - "name": "EXTTRIG", - "description": "External trigger edge event.", - "bit_offset": 2, - "bit_size": 1 - }, - { - "name": "CMPOK", - "description": "Compare register update OK.", - "bit_offset": 3, - "bit_size": 1 - }, - { - "name": "ARROK", - "description": "Autoreload register update OK.", - "bit_offset": 4, - "bit_size": 1 - }, - { - "name": "UP", - "description": "Counter direction change down to up.", - "bit_offset": 5, - "bit_size": 1 - }, - { - "name": "DOWN", - "description": "Counter direction change up to down.", - "bit_offset": 6, - "bit_size": 1 - }, - { - "name": "UE", - "description": "LPTIM update event occurred.", - "bit_offset": 7, - "bit_size": 1 - }, - { - "name": "REPOK", - "description": "Repetition register update Ok.", - "bit_offset": 8, - "bit_size": 1 - } - ] - }, - "fieldset/RCR": { - "description": "LPTIM repetition register.", - "fields": [ - { - "name": "REP", - "description": "Repetition register value.", - "bit_offset": 0, - "bit_size": 8 - } - ] - }, - "enum/CKPOL": { - "bit_size": 2, - "variants": [ - { - "name": "Rising", - "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", - "value": 0 - }, - { - "name": "Falling", - "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", - "value": 1 - }, - { - "name": "Both", - "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", - "value": 2 - } - ] - }, - "enum/CKSEL": { - "bit_size": 1, - "variants": [ - { - "name": "Internal", - "description": "LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)", - "value": 0 - }, - { - "name": "External", - "description": "LPTIM is clocked by an external clock source through the LPTIM external Input1", - "value": 1 - } - ] - }, - "enum/Filter": { - "bit_size": 2, - "variants": [ - { - "name": "Count1", - "value": 0 - }, - { - "name": "Count2", - "value": 1 - }, - { - "name": "Count4", - "value": 2 - }, - { - "name": "Count8", - "value": 3 - } - ] - }, - "enum/PRESC": { - "bit_size": 3, - "variants": [ - { - "name": "Div1", - "value": 0 - }, - { - "name": "Div2", - "value": 1 - }, - { - "name": "Div4", - "value": 2 - }, - { - "name": "Div8", - "value": 3 - }, - { - "name": "Div16", - "value": 4 - }, - { - "name": "Div32", - "value": 5 - }, - { - "name": "Div64", - "value": 6 - }, - { - "name": "Div128", - "value": 7 - } - ] - } -} \ No newline at end of file