diff --git a/data/chips/STM32F410C8.json b/data/chips/STM32F410C8.json index adfeecf..c4bce2f 100644 --- a/data/chips/STM32F410C8.json +++ b/data/chips/STM32F410C8.json @@ -977,7 +977,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F410CB.json b/data/chips/STM32F410CB.json index 535aa02..fd37c85 100644 --- a/data/chips/STM32F410CB.json +++ b/data/chips/STM32F410CB.json @@ -988,7 +988,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F410R8.json b/data/chips/STM32F410R8.json index 4899b8a..28a2752 100644 --- a/data/chips/STM32F410R8.json +++ b/data/chips/STM32F410R8.json @@ -1026,7 +1026,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F410RB.json b/data/chips/STM32F410RB.json index 33afe3d..a739d10 100644 --- a/data/chips/STM32F410RB.json +++ b/data/chips/STM32F410RB.json @@ -1037,7 +1037,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F410T8.json b/data/chips/STM32F410T8.json index ba66f91..ae2d070 100644 --- a/data/chips/STM32F410T8.json +++ b/data/chips/STM32F410T8.json @@ -924,7 +924,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F410TB.json b/data/chips/STM32F410TB.json index 290c69b..73d9844 100644 --- a/data/chips/STM32F410TB.json +++ b/data/chips/STM32F410TB.json @@ -935,7 +935,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413CG.json b/data/chips/STM32F413CG.json index e96a30d..45edd8c 100644 --- a/data/chips/STM32F413CG.json +++ b/data/chips/STM32F413CG.json @@ -1605,7 +1605,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413CH.json b/data/chips/STM32F413CH.json index 231af08..a41a50e 100644 --- a/data/chips/STM32F413CH.json +++ b/data/chips/STM32F413CH.json @@ -1605,7 +1605,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413MG.json b/data/chips/STM32F413MG.json index 485c90b..dd2ed17 100644 --- a/data/chips/STM32F413MG.json +++ b/data/chips/STM32F413MG.json @@ -2017,7 +2017,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413MH.json b/data/chips/STM32F413MH.json index 7073152..c5e7cc1 100644 --- a/data/chips/STM32F413MH.json +++ b/data/chips/STM32F413MH.json @@ -2017,7 +2017,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413RG.json b/data/chips/STM32F413RG.json index f3ef1ac..71b5e39 100644 --- a/data/chips/STM32F413RG.json +++ b/data/chips/STM32F413RG.json @@ -1862,7 +1862,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413RH.json b/data/chips/STM32F413RH.json index 660d396..dd4b921 100644 --- a/data/chips/STM32F413RH.json +++ b/data/chips/STM32F413RH.json @@ -1862,7 +1862,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413VG.json b/data/chips/STM32F413VG.json index c094847..170d2d2 100644 --- a/data/chips/STM32F413VG.json +++ b/data/chips/STM32F413VG.json @@ -2271,7 +2271,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413VH.json b/data/chips/STM32F413VH.json index 918de24..f4a149d 100644 --- a/data/chips/STM32F413VH.json +++ b/data/chips/STM32F413VH.json @@ -2271,7 +2271,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413ZG.json b/data/chips/STM32F413ZG.json index 1ac6089..56d979a 100644 --- a/data/chips/STM32F413ZG.json +++ b/data/chips/STM32F413ZG.json @@ -2426,7 +2426,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F413ZH.json b/data/chips/STM32F413ZH.json index f949682..98baeb2 100644 --- a/data/chips/STM32F413ZH.json +++ b/data/chips/STM32F413ZH.json @@ -2426,7 +2426,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F423CH.json b/data/chips/STM32F423CH.json index b161e0a..90dcc39 100644 --- a/data/chips/STM32F423CH.json +++ b/data/chips/STM32F423CH.json @@ -1632,7 +1632,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F423MH.json b/data/chips/STM32F423MH.json index 20e9516..473108d 100644 --- a/data/chips/STM32F423MH.json +++ b/data/chips/STM32F423MH.json @@ -2044,7 +2044,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F423RH.json b/data/chips/STM32F423RH.json index eb0aef7..9789a94 100644 --- a/data/chips/STM32F423RH.json +++ b/data/chips/STM32F423RH.json @@ -1889,7 +1889,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F423VH.json b/data/chips/STM32F423VH.json index 167f870..968cbf4 100644 --- a/data/chips/STM32F423VH.json +++ b/data/chips/STM32F423VH.json @@ -2298,7 +2298,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F423ZH.json b/data/chips/STM32F423ZH.json index b558d19..a70017e 100644 --- a/data/chips/STM32F423ZH.json +++ b/data/chips/STM32F423ZH.json @@ -2453,7 +2453,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722IC.json b/data/chips/STM32F722IC.json index 117aa5a..f119bc5 100644 --- a/data/chips/STM32F722IC.json +++ b/data/chips/STM32F722IC.json @@ -2054,7 +2054,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722IE.json b/data/chips/STM32F722IE.json index 5471f93..ae86a52 100644 --- a/data/chips/STM32F722IE.json +++ b/data/chips/STM32F722IE.json @@ -2054,7 +2054,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722VC.json b/data/chips/STM32F722VC.json index a1dfc5a..51512ed 100644 --- a/data/chips/STM32F722VC.json +++ b/data/chips/STM32F722VC.json @@ -1698,7 +1698,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722VE.json b/data/chips/STM32F722VE.json index baa6f4f..acda677 100644 --- a/data/chips/STM32F722VE.json +++ b/data/chips/STM32F722VE.json @@ -1698,7 +1698,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722ZC.json b/data/chips/STM32F722ZC.json index 89c5005..c1806e9 100644 --- a/data/chips/STM32F722ZC.json +++ b/data/chips/STM32F722ZC.json @@ -1890,7 +1890,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F722ZE.json b/data/chips/STM32F722ZE.json index dc6cd73..947dde0 100644 --- a/data/chips/STM32F722ZE.json +++ b/data/chips/STM32F722ZE.json @@ -1890,7 +1890,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723IC.json b/data/chips/STM32F723IC.json index 4c6d74a..1463256 100644 --- a/data/chips/STM32F723IC.json +++ b/data/chips/STM32F723IC.json @@ -2049,7 +2049,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723IE.json b/data/chips/STM32F723IE.json index e70ecee..7f7e536 100644 --- a/data/chips/STM32F723IE.json +++ b/data/chips/STM32F723IE.json @@ -2049,7 +2049,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723VC.json b/data/chips/STM32F723VC.json index 0f69556..a1340a8 100644 --- a/data/chips/STM32F723VC.json +++ b/data/chips/STM32F723VC.json @@ -1672,7 +1672,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723VE.json b/data/chips/STM32F723VE.json index d8ea44a..5979b7b 100644 --- a/data/chips/STM32F723VE.json +++ b/data/chips/STM32F723VE.json @@ -1672,7 +1672,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723ZC.json b/data/chips/STM32F723ZC.json index bf35a11..6c0129a 100644 --- a/data/chips/STM32F723ZC.json +++ b/data/chips/STM32F723ZC.json @@ -1889,7 +1889,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F723ZE.json b/data/chips/STM32F723ZE.json index 5ddb959..837ce08 100644 --- a/data/chips/STM32F723ZE.json +++ b/data/chips/STM32F723ZE.json @@ -1889,7 +1889,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F730I8.json b/data/chips/STM32F730I8.json index 5f883b6..ff1d35e 100644 --- a/data/chips/STM32F730I8.json +++ b/data/chips/STM32F730I8.json @@ -2050,7 +2050,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F730V8.json b/data/chips/STM32F730V8.json index a2cd288..54bda17 100644 --- a/data/chips/STM32F730V8.json +++ b/data/chips/STM32F730V8.json @@ -1703,7 +1703,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F730Z8.json b/data/chips/STM32F730Z8.json index af7673d..e1dd10c 100644 --- a/data/chips/STM32F730Z8.json +++ b/data/chips/STM32F730Z8.json @@ -1890,7 +1890,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F732IE.json b/data/chips/STM32F732IE.json index 58db4ca..46a12b9 100644 --- a/data/chips/STM32F732IE.json +++ b/data/chips/STM32F732IE.json @@ -2093,7 +2093,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F732VE.json b/data/chips/STM32F732VE.json index 4b1eca1..8678a04 100644 --- a/data/chips/STM32F732VE.json +++ b/data/chips/STM32F732VE.json @@ -1737,7 +1737,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F732ZE.json b/data/chips/STM32F732ZE.json index 986af43..46f948b 100644 --- a/data/chips/STM32F732ZE.json +++ b/data/chips/STM32F732ZE.json @@ -1929,7 +1929,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F733IE.json b/data/chips/STM32F733IE.json index 7868998..3f9f546 100644 --- a/data/chips/STM32F733IE.json +++ b/data/chips/STM32F733IE.json @@ -2088,7 +2088,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F733VE.json b/data/chips/STM32F733VE.json index 11ed775..da08e09 100644 --- a/data/chips/STM32F733VE.json +++ b/data/chips/STM32F733VE.json @@ -1711,7 +1711,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F733ZE.json b/data/chips/STM32F733ZE.json index 0b16ef4..a4fbdc9 100644 --- a/data/chips/STM32F733ZE.json +++ b/data/chips/STM32F733ZE.json @@ -1928,7 +1928,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745IE.json b/data/chips/STM32F745IE.json index 3e08c1c..85bbebe 100644 --- a/data/chips/STM32F745IE.json +++ b/data/chips/STM32F745IE.json @@ -2786,7 +2786,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745IG.json b/data/chips/STM32F745IG.json index c963426..6b61b42 100644 --- a/data/chips/STM32F745IG.json +++ b/data/chips/STM32F745IG.json @@ -2786,7 +2786,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745VE.json b/data/chips/STM32F745VE.json index d6ddb87..97720df 100644 --- a/data/chips/STM32F745VE.json +++ b/data/chips/STM32F745VE.json @@ -2244,7 +2244,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745VG.json b/data/chips/STM32F745VG.json index 223894a..d196204 100644 --- a/data/chips/STM32F745VG.json +++ b/data/chips/STM32F745VG.json @@ -2244,7 +2244,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745ZE.json b/data/chips/STM32F745ZE.json index 5330a4b..4f7d741 100644 --- a/data/chips/STM32F745ZE.json +++ b/data/chips/STM32F745ZE.json @@ -2502,7 +2502,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F745ZG.json b/data/chips/STM32F745ZG.json index 45f3916..6fdc485 100644 --- a/data/chips/STM32F745ZG.json +++ b/data/chips/STM32F745ZG.json @@ -2502,7 +2502,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746BE.json b/data/chips/STM32F746BE.json index a10ca51..68531d9 100644 --- a/data/chips/STM32F746BE.json +++ b/data/chips/STM32F746BE.json @@ -2788,7 +2788,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746BG.json b/data/chips/STM32F746BG.json index b8d9d46..439f65f 100644 --- a/data/chips/STM32F746BG.json +++ b/data/chips/STM32F746BG.json @@ -2788,7 +2788,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746IE.json b/data/chips/STM32F746IE.json index ded93a9..816367d 100644 --- a/data/chips/STM32F746IE.json +++ b/data/chips/STM32F746IE.json @@ -2792,7 +2792,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746IG.json b/data/chips/STM32F746IG.json index 6efb9bc..ed8e155 100644 --- a/data/chips/STM32F746IG.json +++ b/data/chips/STM32F746IG.json @@ -2792,7 +2792,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746NE.json b/data/chips/STM32F746NE.json index 0995cb8..2282d2c 100644 --- a/data/chips/STM32F746NE.json +++ b/data/chips/STM32F746NE.json @@ -2788,7 +2788,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746NG.json b/data/chips/STM32F746NG.json index 680be61..0421e4a 100644 --- a/data/chips/STM32F746NG.json +++ b/data/chips/STM32F746NG.json @@ -2788,7 +2788,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746VE.json b/data/chips/STM32F746VE.json index fbe4ba6..ab73c1e 100644 --- a/data/chips/STM32F746VE.json +++ b/data/chips/STM32F746VE.json @@ -2250,7 +2250,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746VG.json b/data/chips/STM32F746VG.json index c95b049..8b02aee 100644 --- a/data/chips/STM32F746VG.json +++ b/data/chips/STM32F746VG.json @@ -2250,7 +2250,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746ZE.json b/data/chips/STM32F746ZE.json index 604df9a..c9ef4b4 100644 --- a/data/chips/STM32F746ZE.json +++ b/data/chips/STM32F746ZE.json @@ -2512,7 +2512,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F746ZG.json b/data/chips/STM32F746ZG.json index 74768fc..0ab43b4 100644 --- a/data/chips/STM32F746ZG.json +++ b/data/chips/STM32F746ZG.json @@ -2512,7 +2512,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F750N8.json b/data/chips/STM32F750N8.json index 925984a..cc50c36 100644 --- a/data/chips/STM32F750N8.json +++ b/data/chips/STM32F750N8.json @@ -2811,7 +2811,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F750V8.json b/data/chips/STM32F750V8.json index a7c5592..46e27ed 100644 --- a/data/chips/STM32F750V8.json +++ b/data/chips/STM32F750V8.json @@ -2269,7 +2269,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F750Z8.json b/data/chips/STM32F750Z8.json index d7863a5..28d43e8 100644 --- a/data/chips/STM32F750Z8.json +++ b/data/chips/STM32F750Z8.json @@ -2531,7 +2531,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F756BG.json b/data/chips/STM32F756BG.json index e946cfb..3483b69 100644 --- a/data/chips/STM32F756BG.json +++ b/data/chips/STM32F756BG.json @@ -2857,7 +2857,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F756IG.json b/data/chips/STM32F756IG.json index 55df7e2..e642841 100644 --- a/data/chips/STM32F756IG.json +++ b/data/chips/STM32F756IG.json @@ -2861,7 +2861,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F756NG.json b/data/chips/STM32F756NG.json index 6886d86..af4c2cc 100644 --- a/data/chips/STM32F756NG.json +++ b/data/chips/STM32F756NG.json @@ -2857,7 +2857,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F756VG.json b/data/chips/STM32F756VG.json index 7270f6e..01ee22d 100644 --- a/data/chips/STM32F756VG.json +++ b/data/chips/STM32F756VG.json @@ -2319,7 +2319,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F756ZG.json b/data/chips/STM32F756ZG.json index 46cefea..e815c8d 100644 --- a/data/chips/STM32F756ZG.json +++ b/data/chips/STM32F756ZG.json @@ -2581,7 +2581,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765BG.json b/data/chips/STM32F765BG.json index aaf3933..2ba24ae 100644 --- a/data/chips/STM32F765BG.json +++ b/data/chips/STM32F765BG.json @@ -3210,7 +3210,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765BI.json b/data/chips/STM32F765BI.json index b68b562..6679474 100644 --- a/data/chips/STM32F765BI.json +++ b/data/chips/STM32F765BI.json @@ -3216,7 +3216,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765IG.json b/data/chips/STM32F765IG.json index dbd1a41..5666ef3 100644 --- a/data/chips/STM32F765IG.json +++ b/data/chips/STM32F765IG.json @@ -3220,7 +3220,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765II.json b/data/chips/STM32F765II.json index d89ecaa..691c336 100644 --- a/data/chips/STM32F765II.json +++ b/data/chips/STM32F765II.json @@ -3220,7 +3220,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765NG.json b/data/chips/STM32F765NG.json index f96d5ed..51b5c6b 100644 --- a/data/chips/STM32F765NG.json +++ b/data/chips/STM32F765NG.json @@ -3216,7 +3216,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765NI.json b/data/chips/STM32F765NI.json index f438f88..d2cb1dd 100644 --- a/data/chips/STM32F765NI.json +++ b/data/chips/STM32F765NI.json @@ -3216,7 +3216,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765VG.json b/data/chips/STM32F765VG.json index ebc25c0..97de7d1 100644 --- a/data/chips/STM32F765VG.json +++ b/data/chips/STM32F765VG.json @@ -2658,7 +2658,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765VI.json b/data/chips/STM32F765VI.json index 1be74ec..646dd3a 100644 --- a/data/chips/STM32F765VI.json +++ b/data/chips/STM32F765VI.json @@ -2658,7 +2658,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765ZG.json b/data/chips/STM32F765ZG.json index 05f7e73..452300f 100644 --- a/data/chips/STM32F765ZG.json +++ b/data/chips/STM32F765ZG.json @@ -2931,7 +2931,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F765ZI.json b/data/chips/STM32F765ZI.json index ae2b204..7720f0b 100644 --- a/data/chips/STM32F765ZI.json +++ b/data/chips/STM32F765ZI.json @@ -2931,7 +2931,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767BG.json b/data/chips/STM32F767BG.json index ac2eaf5..9ac40fc 100644 --- a/data/chips/STM32F767BG.json +++ b/data/chips/STM32F767BG.json @@ -3267,7 +3267,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767BI.json b/data/chips/STM32F767BI.json index 2fec007..53cfb9c 100644 --- a/data/chips/STM32F767BI.json +++ b/data/chips/STM32F767BI.json @@ -3267,7 +3267,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767IG.json b/data/chips/STM32F767IG.json index 619f700..9bfa69f 100644 --- a/data/chips/STM32F767IG.json +++ b/data/chips/STM32F767IG.json @@ -3271,7 +3271,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767II.json b/data/chips/STM32F767II.json index bead47a..566c82b 100644 --- a/data/chips/STM32F767II.json +++ b/data/chips/STM32F767II.json @@ -3271,7 +3271,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767NG.json b/data/chips/STM32F767NG.json index 125b314..f0201ce 100644 --- a/data/chips/STM32F767NG.json +++ b/data/chips/STM32F767NG.json @@ -3267,7 +3267,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767NI.json b/data/chips/STM32F767NI.json index 66d2dbc..cfab1e8 100644 --- a/data/chips/STM32F767NI.json +++ b/data/chips/STM32F767NI.json @@ -3267,7 +3267,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767VG.json b/data/chips/STM32F767VG.json index ac04375..f8abf7f 100644 --- a/data/chips/STM32F767VG.json +++ b/data/chips/STM32F767VG.json @@ -2709,7 +2709,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767VI.json b/data/chips/STM32F767VI.json index 8ce7ced..0250470 100644 --- a/data/chips/STM32F767VI.json +++ b/data/chips/STM32F767VI.json @@ -2709,7 +2709,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767ZG.json b/data/chips/STM32F767ZG.json index 6006487..201ac21 100644 --- a/data/chips/STM32F767ZG.json +++ b/data/chips/STM32F767ZG.json @@ -2982,7 +2982,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F767ZI.json b/data/chips/STM32F767ZI.json index 60ec226..1275073 100644 --- a/data/chips/STM32F767ZI.json +++ b/data/chips/STM32F767ZI.json @@ -2982,7 +2982,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F768AI.json b/data/chips/STM32F768AI.json index 6b26052..bf16259 100644 --- a/data/chips/STM32F768AI.json +++ b/data/chips/STM32F768AI.json @@ -2671,7 +2671,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769AG.json b/data/chips/STM32F769AG.json index c673501..fa6a438 100644 --- a/data/chips/STM32F769AG.json +++ b/data/chips/STM32F769AG.json @@ -2671,7 +2671,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769AI.json b/data/chips/STM32F769AI.json index 23c96fc..8644092 100644 --- a/data/chips/STM32F769AI.json +++ b/data/chips/STM32F769AI.json @@ -2960,7 +2960,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769BG.json b/data/chips/STM32F769BG.json index 140b429..0a34194 100644 --- a/data/chips/STM32F769BG.json +++ b/data/chips/STM32F769BG.json @@ -3279,7 +3279,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769BI.json b/data/chips/STM32F769BI.json index 6ac6073..d488062 100644 --- a/data/chips/STM32F769BI.json +++ b/data/chips/STM32F769BI.json @@ -3279,7 +3279,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769IG.json b/data/chips/STM32F769IG.json index b6ecc59..79e268f 100644 --- a/data/chips/STM32F769IG.json +++ b/data/chips/STM32F769IG.json @@ -3159,7 +3159,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769II.json b/data/chips/STM32F769II.json index d8b5503..bc72a9d 100644 --- a/data/chips/STM32F769II.json +++ b/data/chips/STM32F769II.json @@ -3159,7 +3159,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769NG.json b/data/chips/STM32F769NG.json index 31bcbf0..2b2bf38 100644 --- a/data/chips/STM32F769NG.json +++ b/data/chips/STM32F769NG.json @@ -3279,7 +3279,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F769NI.json b/data/chips/STM32F769NI.json index 665f947..a9b851a 100644 --- a/data/chips/STM32F769NI.json +++ b/data/chips/STM32F769NI.json @@ -3279,7 +3279,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F777BI.json b/data/chips/STM32F777BI.json index 33d8451..dffddca 100644 --- a/data/chips/STM32F777BI.json +++ b/data/chips/STM32F777BI.json @@ -3342,7 +3342,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F777II.json b/data/chips/STM32F777II.json index 3f466ae..125f27e 100644 --- a/data/chips/STM32F777II.json +++ b/data/chips/STM32F777II.json @@ -3346,7 +3346,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F777NI.json b/data/chips/STM32F777NI.json index bdc2c36..5b0bff4 100644 --- a/data/chips/STM32F777NI.json +++ b/data/chips/STM32F777NI.json @@ -3342,7 +3342,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F777VI.json b/data/chips/STM32F777VI.json index dd9ba8f..077a30f 100644 --- a/data/chips/STM32F777VI.json +++ b/data/chips/STM32F777VI.json @@ -2784,7 +2784,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F777ZI.json b/data/chips/STM32F777ZI.json index 03d794a..e428d0f 100644 --- a/data/chips/STM32F777ZI.json +++ b/data/chips/STM32F777ZI.json @@ -3057,7 +3057,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F778AI.json b/data/chips/STM32F778AI.json index db86e54..2390a10 100644 --- a/data/chips/STM32F778AI.json +++ b/data/chips/STM32F778AI.json @@ -3023,7 +3023,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F779AI.json b/data/chips/STM32F779AI.json index 3551454..ad183a0 100644 --- a/data/chips/STM32F779AI.json +++ b/data/chips/STM32F779AI.json @@ -3029,7 +3029,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F779BI.json b/data/chips/STM32F779BI.json index 9056031..e511277 100644 --- a/data/chips/STM32F779BI.json +++ b/data/chips/STM32F779BI.json @@ -3348,7 +3348,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F779II.json b/data/chips/STM32F779II.json index ae9177f..9a3bcd1 100644 --- a/data/chips/STM32F779II.json +++ b/data/chips/STM32F779II.json @@ -3228,7 +3228,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32F779NI.json b/data/chips/STM32F779NI.json index 1d949a9..24b42b7 100644 --- a/data/chips/STM32F779NI.json +++ b/data/chips/STM32F779NI.json @@ -3348,7 +3348,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031C4.json b/data/chips/STM32G031C4.json index 1b24fde..50c8d7a 100644 --- a/data/chips/STM32G031C4.json +++ b/data/chips/STM32G031C4.json @@ -791,7 +791,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -854,7 +854,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031C6.json b/data/chips/STM32G031C6.json index b434efa..d8ec603 100644 --- a/data/chips/STM32G031C6.json +++ b/data/chips/STM32G031C6.json @@ -791,7 +791,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -854,7 +854,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031C8.json b/data/chips/STM32G031C8.json index 0bd2b10..57329e5 100644 --- a/data/chips/STM32G031C8.json +++ b/data/chips/STM32G031C8.json @@ -791,7 +791,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -854,7 +854,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031F4.json b/data/chips/STM32G031F4.json index e6937d1..63e7217 100644 --- a/data/chips/STM32G031F4.json +++ b/data/chips/STM32G031F4.json @@ -767,7 +767,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -830,7 +830,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031F6.json b/data/chips/STM32G031F6.json index ab03f10..36902a2 100644 --- a/data/chips/STM32G031F6.json +++ b/data/chips/STM32G031F6.json @@ -767,7 +767,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -830,7 +830,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031F8.json b/data/chips/STM32G031F8.json index 92063b7..c6e7fe7 100644 --- a/data/chips/STM32G031F8.json +++ b/data/chips/STM32G031F8.json @@ -767,7 +767,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -830,7 +830,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031G4.json b/data/chips/STM32G031G4.json index ca7e447..08e318a 100644 --- a/data/chips/STM32G031G4.json +++ b/data/chips/STM32G031G4.json @@ -758,7 +758,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -816,7 +816,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031G6.json b/data/chips/STM32G031G6.json index 53f2197..866376a 100644 --- a/data/chips/STM32G031G6.json +++ b/data/chips/STM32G031G6.json @@ -758,7 +758,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -816,7 +816,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031G8.json b/data/chips/STM32G031G8.json index 83abea8..27c0117 100644 --- a/data/chips/STM32G031G8.json +++ b/data/chips/STM32G031G8.json @@ -758,7 +758,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -816,7 +816,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031J4.json b/data/chips/STM32G031J4.json index 5372325..5321b5a 100644 --- a/data/chips/STM32G031J4.json +++ b/data/chips/STM32G031J4.json @@ -743,7 +743,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -801,7 +801,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031J6.json b/data/chips/STM32G031J6.json index 8656e67..ae9e396 100644 --- a/data/chips/STM32G031J6.json +++ b/data/chips/STM32G031J6.json @@ -743,7 +743,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -801,7 +801,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031K4.json b/data/chips/STM32G031K4.json index 836c985..e21fc4d 100644 --- a/data/chips/STM32G031K4.json +++ b/data/chips/STM32G031K4.json @@ -771,7 +771,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -834,7 +834,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031K6.json b/data/chips/STM32G031K6.json index e465fa9..8e80f91 100644 --- a/data/chips/STM32G031K6.json +++ b/data/chips/STM32G031K6.json @@ -771,7 +771,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -834,7 +834,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031K8.json b/data/chips/STM32G031K8.json index 0829874..3dd8abd 100644 --- a/data/chips/STM32G031K8.json +++ b/data/chips/STM32G031K8.json @@ -771,7 +771,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -834,7 +834,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G031Y8.json b/data/chips/STM32G031Y8.json index 79b52ff..7588730 100644 --- a/data/chips/STM32G031Y8.json +++ b/data/chips/STM32G031Y8.json @@ -767,7 +767,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -830,7 +830,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041C6.json b/data/chips/STM32G041C6.json index 23fc3d5..287f4b6 100644 --- a/data/chips/STM32G041C6.json +++ b/data/chips/STM32G041C6.json @@ -830,7 +830,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -893,7 +893,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041C8.json b/data/chips/STM32G041C8.json index 09272e5..d74d9de 100644 --- a/data/chips/STM32G041C8.json +++ b/data/chips/STM32G041C8.json @@ -830,7 +830,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -893,7 +893,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041F6.json b/data/chips/STM32G041F6.json index 2795b4c..b9f7fac 100644 --- a/data/chips/STM32G041F6.json +++ b/data/chips/STM32G041F6.json @@ -806,7 +806,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -869,7 +869,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041F8.json b/data/chips/STM32G041F8.json index 0d6774c..28e62ee 100644 --- a/data/chips/STM32G041F8.json +++ b/data/chips/STM32G041F8.json @@ -806,7 +806,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -869,7 +869,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041G6.json b/data/chips/STM32G041G6.json index d40effc..af77921 100644 --- a/data/chips/STM32G041G6.json +++ b/data/chips/STM32G041G6.json @@ -797,7 +797,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -855,7 +855,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041G8.json b/data/chips/STM32G041G8.json index 8156fe3..3d83288 100644 --- a/data/chips/STM32G041G8.json +++ b/data/chips/STM32G041G8.json @@ -797,7 +797,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -855,7 +855,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041J6.json b/data/chips/STM32G041J6.json index 488808f..2c04d8f 100644 --- a/data/chips/STM32G041J6.json +++ b/data/chips/STM32G041J6.json @@ -782,7 +782,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -840,7 +840,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041K6.json b/data/chips/STM32G041K6.json index f028caf..863eb28 100644 --- a/data/chips/STM32G041K6.json +++ b/data/chips/STM32G041K6.json @@ -810,7 +810,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -873,7 +873,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041K8.json b/data/chips/STM32G041K8.json index f668786..2d00f94 100644 --- a/data/chips/STM32G041K8.json +++ b/data/chips/STM32G041K8.json @@ -810,7 +810,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -873,7 +873,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G041Y8.json b/data/chips/STM32G041Y8.json index 5411327..caee030 100644 --- a/data/chips/STM32G041Y8.json +++ b/data/chips/STM32G041Y8.json @@ -806,7 +806,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -869,7 +869,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051C6.json b/data/chips/STM32G051C6.json index fcfb326..996cb9a 100644 --- a/data/chips/STM32G051C6.json +++ b/data/chips/STM32G051C6.json @@ -1158,7 +1158,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1221,7 +1221,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051C8.json b/data/chips/STM32G051C8.json index 0732478..ad12f21 100644 --- a/data/chips/STM32G051C8.json +++ b/data/chips/STM32G051C8.json @@ -1158,7 +1158,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1221,7 +1221,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051F6.json b/data/chips/STM32G051F6.json index d611913..ffdd892 100644 --- a/data/chips/STM32G051F6.json +++ b/data/chips/STM32G051F6.json @@ -1124,7 +1124,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1187,7 +1187,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051F8.json b/data/chips/STM32G051F8.json index 7c20731..3ff06ef 100644 --- a/data/chips/STM32G051F8.json +++ b/data/chips/STM32G051F8.json @@ -1128,7 +1128,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1191,7 +1191,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051G6.json b/data/chips/STM32G051G6.json index 7cd60f3..593c335 100644 --- a/data/chips/STM32G051G6.json +++ b/data/chips/STM32G051G6.json @@ -1111,7 +1111,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1169,7 +1169,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051G8.json b/data/chips/STM32G051G8.json index 2e035f2..3405c13 100644 --- a/data/chips/STM32G051G8.json +++ b/data/chips/STM32G051G8.json @@ -1111,7 +1111,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1169,7 +1169,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051K6.json b/data/chips/STM32G051K6.json index 30c03fa..f68f934 100644 --- a/data/chips/STM32G051K6.json +++ b/data/chips/STM32G051K6.json @@ -1128,7 +1128,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1191,7 +1191,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G051K8.json b/data/chips/STM32G051K8.json index 140dd13..fce5b8c 100644 --- a/data/chips/STM32G051K8.json +++ b/data/chips/STM32G051K8.json @@ -1128,7 +1128,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1191,7 +1191,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061C6.json b/data/chips/STM32G061C6.json index 6820913..e8129ae 100644 --- a/data/chips/STM32G061C6.json +++ b/data/chips/STM32G061C6.json @@ -1197,7 +1197,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1260,7 +1260,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061C8.json b/data/chips/STM32G061C8.json index 65aef8f..dba06ea 100644 --- a/data/chips/STM32G061C8.json +++ b/data/chips/STM32G061C8.json @@ -1197,7 +1197,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1260,7 +1260,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061F6.json b/data/chips/STM32G061F6.json index e9f5992..57c908d 100644 --- a/data/chips/STM32G061F6.json +++ b/data/chips/STM32G061F6.json @@ -1163,7 +1163,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1226,7 +1226,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061F8.json b/data/chips/STM32G061F8.json index 4b319a4..20d05a2 100644 --- a/data/chips/STM32G061F8.json +++ b/data/chips/STM32G061F8.json @@ -1167,7 +1167,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1230,7 +1230,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061G6.json b/data/chips/STM32G061G6.json index de1b413..56e4fc3 100644 --- a/data/chips/STM32G061G6.json +++ b/data/chips/STM32G061G6.json @@ -1150,7 +1150,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1208,7 +1208,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061G8.json b/data/chips/STM32G061G8.json index 94e4c2e..04ed313 100644 --- a/data/chips/STM32G061G8.json +++ b/data/chips/STM32G061G8.json @@ -1150,7 +1150,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1208,7 +1208,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061K6.json b/data/chips/STM32G061K6.json index c0b9786..41229cd 100644 --- a/data/chips/STM32G061K6.json +++ b/data/chips/STM32G061K6.json @@ -1167,7 +1167,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1230,7 +1230,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G061K8.json b/data/chips/STM32G061K8.json index d321bff..bca4486 100644 --- a/data/chips/STM32G061K8.json +++ b/data/chips/STM32G061K8.json @@ -1167,7 +1167,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1230,7 +1230,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071C6.json b/data/chips/STM32G071C6.json index 39946f6..17612b0 100644 --- a/data/chips/STM32G071C6.json +++ b/data/chips/STM32G071C6.json @@ -813,7 +813,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -876,7 +876,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071C8.json b/data/chips/STM32G071C8.json index 7567a99..bd1a38c 100644 --- a/data/chips/STM32G071C8.json +++ b/data/chips/STM32G071C8.json @@ -988,7 +988,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1051,7 +1051,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071CB.json b/data/chips/STM32G071CB.json index 2a060a4..abde1d8 100644 --- a/data/chips/STM32G071CB.json +++ b/data/chips/STM32G071CB.json @@ -988,7 +988,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1051,7 +1051,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071EB.json b/data/chips/STM32G071EB.json index f78bd25..2fc85de 100644 --- a/data/chips/STM32G071EB.json +++ b/data/chips/STM32G071EB.json @@ -921,7 +921,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -979,7 +979,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071G6.json b/data/chips/STM32G071G6.json index 32a01d8..3c698e5 100644 --- a/data/chips/STM32G071G6.json +++ b/data/chips/STM32G071G6.json @@ -754,7 +754,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -812,7 +812,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071G8.json b/data/chips/STM32G071G8.json index a64ef17..df4a778 100644 --- a/data/chips/STM32G071G8.json +++ b/data/chips/STM32G071G8.json @@ -933,7 +933,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -991,7 +991,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071GB.json b/data/chips/STM32G071GB.json index a93b888..4d7c497 100644 --- a/data/chips/STM32G071GB.json +++ b/data/chips/STM32G071GB.json @@ -933,7 +933,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -991,7 +991,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071K6.json b/data/chips/STM32G071K6.json index b9030eb..09dee30 100644 --- a/data/chips/STM32G071K6.json +++ b/data/chips/STM32G071K6.json @@ -771,7 +771,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -834,7 +834,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071K8.json b/data/chips/STM32G071K8.json index 7174eac..c4bfda6 100644 --- a/data/chips/STM32G071K8.json +++ b/data/chips/STM32G071K8.json @@ -954,7 +954,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1017,7 +1017,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071KB.json b/data/chips/STM32G071KB.json index 6924132..213cfda 100644 --- a/data/chips/STM32G071KB.json +++ b/data/chips/STM32G071KB.json @@ -954,7 +954,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1017,7 +1017,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071R6.json b/data/chips/STM32G071R6.json index 068b974..659710e 100644 --- a/data/chips/STM32G071R6.json +++ b/data/chips/STM32G071R6.json @@ -825,7 +825,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -918,7 +918,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071R8.json b/data/chips/STM32G071R8.json index 96f4ca2..9c7d698 100644 --- a/data/chips/STM32G071R8.json +++ b/data/chips/STM32G071R8.json @@ -1000,7 +1000,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1093,7 +1093,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G071RB.json b/data/chips/STM32G071RB.json index 7ce8afa..b38a83b 100644 --- a/data/chips/STM32G071RB.json +++ b/data/chips/STM32G071RB.json @@ -1004,7 +1004,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1097,7 +1097,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G081CB.json b/data/chips/STM32G081CB.json index 1244d55..fc3dc3a 100644 --- a/data/chips/STM32G081CB.json +++ b/data/chips/STM32G081CB.json @@ -1027,7 +1027,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1090,7 +1090,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G081EB.json b/data/chips/STM32G081EB.json index aff6578..e300a41 100644 --- a/data/chips/STM32G081EB.json +++ b/data/chips/STM32G081EB.json @@ -960,7 +960,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1018,7 +1018,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G081GB.json b/data/chips/STM32G081GB.json index 27f9df3..0793413 100644 --- a/data/chips/STM32G081GB.json +++ b/data/chips/STM32G081GB.json @@ -972,7 +972,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1030,7 +1030,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G081KB.json b/data/chips/STM32G081KB.json index 46b9ef8..6fcebb6 100644 --- a/data/chips/STM32G081KB.json +++ b/data/chips/STM32G081KB.json @@ -993,7 +993,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1056,7 +1056,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G081RB.json b/data/chips/STM32G081RB.json index b4a3da0..c0751bc 100644 --- a/data/chips/STM32G081RB.json +++ b/data/chips/STM32G081RB.json @@ -1043,7 +1043,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1136,7 +1136,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1CB.json b/data/chips/STM32G0B1CB.json index a8462e2..8d015e8 100644 --- a/data/chips/STM32G0B1CB.json +++ b/data/chips/STM32G0B1CB.json @@ -1539,7 +1539,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1602,7 +1602,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1CC.json b/data/chips/STM32G0B1CC.json index 8e06fa7..0698037 100644 --- a/data/chips/STM32G0B1CC.json +++ b/data/chips/STM32G0B1CC.json @@ -1539,7 +1539,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1602,7 +1602,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1CE.json b/data/chips/STM32G0B1CE.json index d852994..e736d2e 100644 --- a/data/chips/STM32G0B1CE.json +++ b/data/chips/STM32G0B1CE.json @@ -1550,7 +1550,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1613,7 +1613,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1KB.json b/data/chips/STM32G0B1KB.json index 29b0adc..1c155ba 100644 --- a/data/chips/STM32G0B1KB.json +++ b/data/chips/STM32G0B1KB.json @@ -1482,7 +1482,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1545,7 +1545,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1KC.json b/data/chips/STM32G0B1KC.json index 0f512d2..15c3763 100644 --- a/data/chips/STM32G0B1KC.json +++ b/data/chips/STM32G0B1KC.json @@ -1482,7 +1482,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1545,7 +1545,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1KE.json b/data/chips/STM32G0B1KE.json index e9755fa..e39b642 100644 --- a/data/chips/STM32G0B1KE.json +++ b/data/chips/STM32G0B1KE.json @@ -1493,7 +1493,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1556,7 +1556,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1MB.json b/data/chips/STM32G0B1MB.json index 952339f..b7891b3 100644 --- a/data/chips/STM32G0B1MB.json +++ b/data/chips/STM32G0B1MB.json @@ -1619,7 +1619,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1712,7 +1712,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1MC.json b/data/chips/STM32G0B1MC.json index 0e85fbd..f728841 100644 --- a/data/chips/STM32G0B1MC.json +++ b/data/chips/STM32G0B1MC.json @@ -1619,7 +1619,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1712,7 +1712,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1ME.json b/data/chips/STM32G0B1ME.json index fcda554..00115c5 100644 --- a/data/chips/STM32G0B1ME.json +++ b/data/chips/STM32G0B1ME.json @@ -1630,7 +1630,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1723,7 +1723,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1NE.json b/data/chips/STM32G0B1NE.json index c3c2ae1..937cef6 100644 --- a/data/chips/STM32G0B1NE.json +++ b/data/chips/STM32G0B1NE.json @@ -1209,7 +1209,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1272,7 +1272,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1RB.json b/data/chips/STM32G0B1RB.json index c16d211..8fc5d06 100644 --- a/data/chips/STM32G0B1RB.json +++ b/data/chips/STM32G0B1RB.json @@ -1599,7 +1599,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1692,7 +1692,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1RC.json b/data/chips/STM32G0B1RC.json index 2b2d31d..eeddb16 100644 --- a/data/chips/STM32G0B1RC.json +++ b/data/chips/STM32G0B1RC.json @@ -1599,7 +1599,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1692,7 +1692,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1RE.json b/data/chips/STM32G0B1RE.json index 26ce16e..6587eec 100644 --- a/data/chips/STM32G0B1RE.json +++ b/data/chips/STM32G0B1RE.json @@ -1610,7 +1610,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1703,7 +1703,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1VB.json b/data/chips/STM32G0B1VB.json index aebb8ae..be3ce11 100644 --- a/data/chips/STM32G0B1VB.json +++ b/data/chips/STM32G0B1VB.json @@ -1623,7 +1623,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1716,7 +1716,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1VC.json b/data/chips/STM32G0B1VC.json index ca35907..9d5aacc 100644 --- a/data/chips/STM32G0B1VC.json +++ b/data/chips/STM32G0B1VC.json @@ -1623,7 +1623,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1716,7 +1716,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0B1VE.json b/data/chips/STM32G0B1VE.json index 9e940da..574a5fc 100644 --- a/data/chips/STM32G0B1VE.json +++ b/data/chips/STM32G0B1VE.json @@ -1634,7 +1634,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1727,7 +1727,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1CC.json b/data/chips/STM32G0C1CC.json index 8f6f5c8..a858881 100644 --- a/data/chips/STM32G0C1CC.json +++ b/data/chips/STM32G0C1CC.json @@ -1578,7 +1578,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1641,7 +1641,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1CE.json b/data/chips/STM32G0C1CE.json index 56eb9e2..ccb2a21 100644 --- a/data/chips/STM32G0C1CE.json +++ b/data/chips/STM32G0C1CE.json @@ -1589,7 +1589,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1652,7 +1652,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1KC.json b/data/chips/STM32G0C1KC.json index f4e3bcb..50d642c 100644 --- a/data/chips/STM32G0C1KC.json +++ b/data/chips/STM32G0C1KC.json @@ -1521,7 +1521,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1584,7 +1584,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1KE.json b/data/chips/STM32G0C1KE.json index cada766..d08624e 100644 --- a/data/chips/STM32G0C1KE.json +++ b/data/chips/STM32G0C1KE.json @@ -1532,7 +1532,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1595,7 +1595,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1MC.json b/data/chips/STM32G0C1MC.json index 57c5170..a99738c 100644 --- a/data/chips/STM32G0C1MC.json +++ b/data/chips/STM32G0C1MC.json @@ -1658,7 +1658,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1751,7 +1751,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1ME.json b/data/chips/STM32G0C1ME.json index 4df1836..5cf95d4 100644 --- a/data/chips/STM32G0C1ME.json +++ b/data/chips/STM32G0C1ME.json @@ -1669,7 +1669,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1762,7 +1762,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1NE.json b/data/chips/STM32G0C1NE.json index c97aed4..bd58608 100644 --- a/data/chips/STM32G0C1NE.json +++ b/data/chips/STM32G0C1NE.json @@ -1248,7 +1248,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1311,7 +1311,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1RC.json b/data/chips/STM32G0C1RC.json index 05db5be..fa8ea17 100644 --- a/data/chips/STM32G0C1RC.json +++ b/data/chips/STM32G0C1RC.json @@ -1638,7 +1638,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1731,7 +1731,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1RE.json b/data/chips/STM32G0C1RE.json index 7a30435..b306ecb 100644 --- a/data/chips/STM32G0C1RE.json +++ b/data/chips/STM32G0C1RE.json @@ -1649,7 +1649,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1742,7 +1742,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1VC.json b/data/chips/STM32G0C1VC.json index 5e614fd..53c3d41 100644 --- a/data/chips/STM32G0C1VC.json +++ b/data/chips/STM32G0C1VC.json @@ -1662,7 +1662,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1755,7 +1755,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G0C1VE.json b/data/chips/STM32G0C1VE.json index b3fbf70..29a09cb 100644 --- a/data/chips/STM32G0C1VE.json +++ b/data/chips/STM32G0C1VE.json @@ -1673,7 +1673,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1766,7 +1766,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431C6.json b/data/chips/STM32G431C6.json index 52b4cf8..807ebea 100644 --- a/data/chips/STM32G431C6.json +++ b/data/chips/STM32G431C6.json @@ -1504,7 +1504,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431C8.json b/data/chips/STM32G431C8.json index 86ab0c8..821cf04 100644 --- a/data/chips/STM32G431C8.json +++ b/data/chips/STM32G431C8.json @@ -1504,7 +1504,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431CB.json b/data/chips/STM32G431CB.json index 5bde89e..a463940 100644 --- a/data/chips/STM32G431CB.json +++ b/data/chips/STM32G431CB.json @@ -1508,7 +1508,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431K6.json b/data/chips/STM32G431K6.json index f198ca6..1d6c006 100644 --- a/data/chips/STM32G431K6.json +++ b/data/chips/STM32G431K6.json @@ -1414,7 +1414,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431K8.json b/data/chips/STM32G431K8.json index b1930dd..8bab119 100644 --- a/data/chips/STM32G431K8.json +++ b/data/chips/STM32G431K8.json @@ -1414,7 +1414,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431KB.json b/data/chips/STM32G431KB.json index bc67b26..b1cd993 100644 --- a/data/chips/STM32G431KB.json +++ b/data/chips/STM32G431KB.json @@ -1414,7 +1414,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431M6.json b/data/chips/STM32G431M6.json index 8d4775d..bf5a1dd 100644 --- a/data/chips/STM32G431M6.json +++ b/data/chips/STM32G431M6.json @@ -1577,7 +1577,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431M8.json b/data/chips/STM32G431M8.json index 6b52d4c..d98332b 100644 --- a/data/chips/STM32G431M8.json +++ b/data/chips/STM32G431M8.json @@ -1577,7 +1577,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431MB.json b/data/chips/STM32G431MB.json index b1c7786..ee7aa20 100644 --- a/data/chips/STM32G431MB.json +++ b/data/chips/STM32G431MB.json @@ -1577,7 +1577,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431R6.json b/data/chips/STM32G431R6.json index 7217244..c863961 100644 --- a/data/chips/STM32G431R6.json +++ b/data/chips/STM32G431R6.json @@ -1563,7 +1563,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431R8.json b/data/chips/STM32G431R8.json index e0f78d9..33a439c 100644 --- a/data/chips/STM32G431R8.json +++ b/data/chips/STM32G431R8.json @@ -1563,7 +1563,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431RB.json b/data/chips/STM32G431RB.json index c402b7c..32b38e6 100644 --- a/data/chips/STM32G431RB.json +++ b/data/chips/STM32G431RB.json @@ -1563,7 +1563,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431V6.json b/data/chips/STM32G431V6.json index a6b5e47..55a53b0 100644 --- a/data/chips/STM32G431V6.json +++ b/data/chips/STM32G431V6.json @@ -1582,7 +1582,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431V8.json b/data/chips/STM32G431V8.json index 93bcb8a..ec6f884 100644 --- a/data/chips/STM32G431V8.json +++ b/data/chips/STM32G431V8.json @@ -1582,7 +1582,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G431VB.json b/data/chips/STM32G431VB.json index e46d947..4f016fc 100644 --- a/data/chips/STM32G431VB.json +++ b/data/chips/STM32G431VB.json @@ -1582,7 +1582,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G441CB.json b/data/chips/STM32G441CB.json index 1825841..2680790 100644 --- a/data/chips/STM32G441CB.json +++ b/data/chips/STM32G441CB.json @@ -1541,7 +1541,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G441KB.json b/data/chips/STM32G441KB.json index a42ce0b..f818789 100644 --- a/data/chips/STM32G441KB.json +++ b/data/chips/STM32G441KB.json @@ -1447,7 +1447,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G441MB.json b/data/chips/STM32G441MB.json index 56c1baf..4a9f7f9 100644 --- a/data/chips/STM32G441MB.json +++ b/data/chips/STM32G441MB.json @@ -1610,7 +1610,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G441RB.json b/data/chips/STM32G441RB.json index dbb101d..6ad822e 100644 --- a/data/chips/STM32G441RB.json +++ b/data/chips/STM32G441RB.json @@ -1596,7 +1596,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G441VB.json b/data/chips/STM32G441VB.json index cb3656e..477d4a5 100644 --- a/data/chips/STM32G441VB.json +++ b/data/chips/STM32G441VB.json @@ -1615,7 +1615,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471CC.json b/data/chips/STM32G471CC.json index 176fda1..0559fcf 100644 --- a/data/chips/STM32G471CC.json +++ b/data/chips/STM32G471CC.json @@ -1496,7 +1496,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471CE.json b/data/chips/STM32G471CE.json index ee0757f..a3b3c79 100644 --- a/data/chips/STM32G471CE.json +++ b/data/chips/STM32G471CE.json @@ -1496,7 +1496,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471MC.json b/data/chips/STM32G471MC.json index ad0718a..846ec2d 100644 --- a/data/chips/STM32G471MC.json +++ b/data/chips/STM32G471MC.json @@ -1615,7 +1615,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471ME.json b/data/chips/STM32G471ME.json index 5a37b59..d2314da 100644 --- a/data/chips/STM32G471ME.json +++ b/data/chips/STM32G471ME.json @@ -1619,7 +1619,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471QC.json b/data/chips/STM32G471QC.json index 8a77141..d37c1fe 100644 --- a/data/chips/STM32G471QC.json +++ b/data/chips/STM32G471QC.json @@ -1692,7 +1692,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471QE.json b/data/chips/STM32G471QE.json index b788440..f017f68 100644 --- a/data/chips/STM32G471QE.json +++ b/data/chips/STM32G471QE.json @@ -1692,7 +1692,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471RC.json b/data/chips/STM32G471RC.json index 1c5b7e5..911bd9b 100644 --- a/data/chips/STM32G471RC.json +++ b/data/chips/STM32G471RC.json @@ -1556,7 +1556,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471RE.json b/data/chips/STM32G471RE.json index 0666314..84c32dc 100644 --- a/data/chips/STM32G471RE.json +++ b/data/chips/STM32G471RE.json @@ -1556,7 +1556,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471VC.json b/data/chips/STM32G471VC.json index 22bce85..b3121dc 100644 --- a/data/chips/STM32G471VC.json +++ b/data/chips/STM32G471VC.json @@ -1640,7 +1640,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G471VE.json b/data/chips/STM32G471VE.json index 8a3b432..a91d37d 100644 --- a/data/chips/STM32G471VE.json +++ b/data/chips/STM32G471VE.json @@ -1640,7 +1640,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473CB.json b/data/chips/STM32G473CB.json index fdb2fd1..571e378 100644 --- a/data/chips/STM32G473CB.json +++ b/data/chips/STM32G473CB.json @@ -2032,7 +2032,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473CC.json b/data/chips/STM32G473CC.json index 2869f16..b853888 100644 --- a/data/chips/STM32G473CC.json +++ b/data/chips/STM32G473CC.json @@ -2032,7 +2032,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473CE.json b/data/chips/STM32G473CE.json index aa48016..ac79a07 100644 --- a/data/chips/STM32G473CE.json +++ b/data/chips/STM32G473CE.json @@ -2032,7 +2032,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473MB.json b/data/chips/STM32G473MB.json index bf3f6f4..6727aea 100644 --- a/data/chips/STM32G473MB.json +++ b/data/chips/STM32G473MB.json @@ -2241,7 +2241,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473MC.json b/data/chips/STM32G473MC.json index 5139688..d0989f9 100644 --- a/data/chips/STM32G473MC.json +++ b/data/chips/STM32G473MC.json @@ -2241,7 +2241,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473ME.json b/data/chips/STM32G473ME.json index 0471469..c9e54c6 100644 --- a/data/chips/STM32G473ME.json +++ b/data/chips/STM32G473ME.json @@ -2245,7 +2245,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473PB.json b/data/chips/STM32G473PB.json index b4935d2..7deeb2e 100644 --- a/data/chips/STM32G473PB.json +++ b/data/chips/STM32G473PB.json @@ -2704,7 +2704,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473PC.json b/data/chips/STM32G473PC.json index d555957..6c3deb0 100644 --- a/data/chips/STM32G473PC.json +++ b/data/chips/STM32G473PC.json @@ -2704,7 +2704,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473PE.json b/data/chips/STM32G473PE.json index 46cc21f..4d5c0fe 100644 --- a/data/chips/STM32G473PE.json +++ b/data/chips/STM32G473PE.json @@ -2704,7 +2704,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473QB.json b/data/chips/STM32G473QB.json index 069fd18..2ac4506 100644 --- a/data/chips/STM32G473QB.json +++ b/data/chips/STM32G473QB.json @@ -2755,7 +2755,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473QC.json b/data/chips/STM32G473QC.json index 80cedcd..70cff40 100644 --- a/data/chips/STM32G473QC.json +++ b/data/chips/STM32G473QC.json @@ -2755,7 +2755,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473QE.json b/data/chips/STM32G473QE.json index 41675fd..5738d72 100644 --- a/data/chips/STM32G473QE.json +++ b/data/chips/STM32G473QE.json @@ -2755,7 +2755,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473RB.json b/data/chips/STM32G473RB.json index 66b3586..f1e03a8 100644 --- a/data/chips/STM32G473RB.json +++ b/data/chips/STM32G473RB.json @@ -2102,7 +2102,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473RC.json b/data/chips/STM32G473RC.json index 323bbb7..9f54611 100644 --- a/data/chips/STM32G473RC.json +++ b/data/chips/STM32G473RC.json @@ -2102,7 +2102,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473RE.json b/data/chips/STM32G473RE.json index ec552c7..20dd66b 100644 --- a/data/chips/STM32G473RE.json +++ b/data/chips/STM32G473RE.json @@ -2102,7 +2102,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473VB.json b/data/chips/STM32G473VB.json index 7c26027..a10f33f 100644 --- a/data/chips/STM32G473VB.json +++ b/data/chips/STM32G473VB.json @@ -2594,7 +2594,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473VC.json b/data/chips/STM32G473VC.json index bbc6211..260e2b8 100644 --- a/data/chips/STM32G473VC.json +++ b/data/chips/STM32G473VC.json @@ -2594,7 +2594,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G473VE.json b/data/chips/STM32G473VE.json index 7474028..bf769b7 100644 --- a/data/chips/STM32G473VE.json +++ b/data/chips/STM32G473VE.json @@ -2594,7 +2594,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474CB.json b/data/chips/STM32G474CB.json index a6020b2..9af09df 100644 --- a/data/chips/STM32G474CB.json +++ b/data/chips/STM32G474CB.json @@ -2278,7 +2278,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474CC.json b/data/chips/STM32G474CC.json index e7dec88..e4d5ba9 100644 --- a/data/chips/STM32G474CC.json +++ b/data/chips/STM32G474CC.json @@ -2278,7 +2278,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474CE.json b/data/chips/STM32G474CE.json index c869c01..6acea5e 100644 --- a/data/chips/STM32G474CE.json +++ b/data/chips/STM32G474CE.json @@ -2278,7 +2278,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474MB.json b/data/chips/STM32G474MB.json index e725d0b..673e41d 100644 --- a/data/chips/STM32G474MB.json +++ b/data/chips/STM32G474MB.json @@ -2517,7 +2517,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474MC.json b/data/chips/STM32G474MC.json index 8608285..f4e8408 100644 --- a/data/chips/STM32G474MC.json +++ b/data/chips/STM32G474MC.json @@ -2517,7 +2517,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474ME.json b/data/chips/STM32G474ME.json index 4e0f739..19b43a1 100644 --- a/data/chips/STM32G474ME.json +++ b/data/chips/STM32G474ME.json @@ -2521,7 +2521,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474PB.json b/data/chips/STM32G474PB.json index 903430c..6d78843 100644 --- a/data/chips/STM32G474PB.json +++ b/data/chips/STM32G474PB.json @@ -2968,7 +2968,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474PC.json b/data/chips/STM32G474PC.json index f851b64..a10df50 100644 --- a/data/chips/STM32G474PC.json +++ b/data/chips/STM32G474PC.json @@ -2968,7 +2968,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474PE.json b/data/chips/STM32G474PE.json index 7567e5a..dec6ab9 100644 --- a/data/chips/STM32G474PE.json +++ b/data/chips/STM32G474PE.json @@ -2968,7 +2968,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474QB.json b/data/chips/STM32G474QB.json index cb820fe..7f7c977 100644 --- a/data/chips/STM32G474QB.json +++ b/data/chips/STM32G474QB.json @@ -3031,7 +3031,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474QC.json b/data/chips/STM32G474QC.json index aec0f3c..439fe4b 100644 --- a/data/chips/STM32G474QC.json +++ b/data/chips/STM32G474QC.json @@ -3031,7 +3031,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474QE.json b/data/chips/STM32G474QE.json index ae13b6b..9ae2ba3 100644 --- a/data/chips/STM32G474QE.json +++ b/data/chips/STM32G474QE.json @@ -3031,7 +3031,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474RB.json b/data/chips/STM32G474RB.json index 33ae23c..281d67f 100644 --- a/data/chips/STM32G474RB.json +++ b/data/chips/STM32G474RB.json @@ -2378,7 +2378,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474RC.json b/data/chips/STM32G474RC.json index 947f99f..9d2e358 100644 --- a/data/chips/STM32G474RC.json +++ b/data/chips/STM32G474RC.json @@ -2378,7 +2378,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474RE.json b/data/chips/STM32G474RE.json index 72b4706..85cd309 100644 --- a/data/chips/STM32G474RE.json +++ b/data/chips/STM32G474RE.json @@ -2378,7 +2378,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474VB.json b/data/chips/STM32G474VB.json index cb16274..595fe54 100644 --- a/data/chips/STM32G474VB.json +++ b/data/chips/STM32G474VB.json @@ -2870,7 +2870,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474VC.json b/data/chips/STM32G474VC.json index a29cc41..fcae400 100644 --- a/data/chips/STM32G474VC.json +++ b/data/chips/STM32G474VC.json @@ -2870,7 +2870,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G474VE.json b/data/chips/STM32G474VE.json index 9cd1563..50d760b 100644 --- a/data/chips/STM32G474VE.json +++ b/data/chips/STM32G474VE.json @@ -2870,7 +2870,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483CE.json b/data/chips/STM32G483CE.json index 1e8a371..4ef35ec 100644 --- a/data/chips/STM32G483CE.json +++ b/data/chips/STM32G483CE.json @@ -2071,7 +2071,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483ME.json b/data/chips/STM32G483ME.json index 5a88abc..1339c08 100644 --- a/data/chips/STM32G483ME.json +++ b/data/chips/STM32G483ME.json @@ -2284,7 +2284,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483PE.json b/data/chips/STM32G483PE.json index 7a3b112..4249106 100644 --- a/data/chips/STM32G483PE.json +++ b/data/chips/STM32G483PE.json @@ -2743,7 +2743,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483QE.json b/data/chips/STM32G483QE.json index e541e7a..3afadb0 100644 --- a/data/chips/STM32G483QE.json +++ b/data/chips/STM32G483QE.json @@ -2794,7 +2794,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483RE.json b/data/chips/STM32G483RE.json index 2dd8440..899e816 100644 --- a/data/chips/STM32G483RE.json +++ b/data/chips/STM32G483RE.json @@ -2141,7 +2141,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G483VE.json b/data/chips/STM32G483VE.json index f0a0aef..094b86c 100644 --- a/data/chips/STM32G483VE.json +++ b/data/chips/STM32G483VE.json @@ -2633,7 +2633,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484CE.json b/data/chips/STM32G484CE.json index e8b2c22..d732013 100644 --- a/data/chips/STM32G484CE.json +++ b/data/chips/STM32G484CE.json @@ -2311,7 +2311,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484ME.json b/data/chips/STM32G484ME.json index 666004e..81d4e09 100644 --- a/data/chips/STM32G484ME.json +++ b/data/chips/STM32G484ME.json @@ -2554,7 +2554,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484PE.json b/data/chips/STM32G484PE.json index c19146c..4103a0f 100644 --- a/data/chips/STM32G484PE.json +++ b/data/chips/STM32G484PE.json @@ -3007,7 +3007,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484QE.json b/data/chips/STM32G484QE.json index 3a35fff..d393ab2 100644 --- a/data/chips/STM32G484QE.json +++ b/data/chips/STM32G484QE.json @@ -3064,7 +3064,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484RE.json b/data/chips/STM32G484RE.json index 5e37669..f60a117 100644 --- a/data/chips/STM32G484RE.json +++ b/data/chips/STM32G484RE.json @@ -2411,7 +2411,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G484VE.json b/data/chips/STM32G484VE.json index 1a5d366..0c5467f 100644 --- a/data/chips/STM32G484VE.json +++ b/data/chips/STM32G484VE.json @@ -2903,7 +2903,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491CC.json b/data/chips/STM32G491CC.json index c401ff5..9bfc18a 100644 --- a/data/chips/STM32G491CC.json +++ b/data/chips/STM32G491CC.json @@ -1624,7 +1624,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491CE.json b/data/chips/STM32G491CE.json index 02542fd..b7c54fe 100644 --- a/data/chips/STM32G491CE.json +++ b/data/chips/STM32G491CE.json @@ -1624,7 +1624,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491KC.json b/data/chips/STM32G491KC.json index 5b4bab0..2480c38 100644 --- a/data/chips/STM32G491KC.json +++ b/data/chips/STM32G491KC.json @@ -1512,7 +1512,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491KE.json b/data/chips/STM32G491KE.json index 53db4d7..79839d1 100644 --- a/data/chips/STM32G491KE.json +++ b/data/chips/STM32G491KE.json @@ -1512,7 +1512,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491MC.json b/data/chips/STM32G491MC.json index e98dbcc..48325b1 100644 --- a/data/chips/STM32G491MC.json +++ b/data/chips/STM32G491MC.json @@ -1733,7 +1733,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491ME.json b/data/chips/STM32G491ME.json index ac2ceca..cd34294 100644 --- a/data/chips/STM32G491ME.json +++ b/data/chips/STM32G491ME.json @@ -1733,7 +1733,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491RC.json b/data/chips/STM32G491RC.json index 53584c2..2c217cf 100644 --- a/data/chips/STM32G491RC.json +++ b/data/chips/STM32G491RC.json @@ -1683,7 +1683,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491RE.json b/data/chips/STM32G491RE.json index 8f70c0d..4b5751e 100644 --- a/data/chips/STM32G491RE.json +++ b/data/chips/STM32G491RE.json @@ -1687,7 +1687,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491VC.json b/data/chips/STM32G491VC.json index 14e9c9f..beecbae 100644 --- a/data/chips/STM32G491VC.json +++ b/data/chips/STM32G491VC.json @@ -1750,7 +1750,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G491VE.json b/data/chips/STM32G491VE.json index a2ab9bd..a597990 100644 --- a/data/chips/STM32G491VE.json +++ b/data/chips/STM32G491VE.json @@ -1750,7 +1750,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G4A1CE.json b/data/chips/STM32G4A1CE.json index 91270ff..8554f46 100644 --- a/data/chips/STM32G4A1CE.json +++ b/data/chips/STM32G4A1CE.json @@ -1663,7 +1663,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G4A1KE.json b/data/chips/STM32G4A1KE.json index 78981b2..2618b7f 100644 --- a/data/chips/STM32G4A1KE.json +++ b/data/chips/STM32G4A1KE.json @@ -1551,7 +1551,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G4A1ME.json b/data/chips/STM32G4A1ME.json index 81a38b0..6e1b7e2 100644 --- a/data/chips/STM32G4A1ME.json +++ b/data/chips/STM32G4A1ME.json @@ -1772,7 +1772,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G4A1RE.json b/data/chips/STM32G4A1RE.json index 5de3bd1..e588acb 100644 --- a/data/chips/STM32G4A1RE.json +++ b/data/chips/STM32G4A1RE.json @@ -1726,7 +1726,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32G4A1VE.json b/data/chips/STM32G4A1VE.json index 0f9e42a..5dee6e5 100644 --- a/data/chips/STM32G4A1VE.json +++ b/data/chips/STM32G4A1VE.json @@ -1789,7 +1789,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_g4", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H503CB.json b/data/chips/STM32H503CB.json index 2a01d32..8e98d4e 100644 --- a/data/chips/STM32H503CB.json +++ b/data/chips/STM32H503CB.json @@ -1244,7 +1244,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1404,7 +1404,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H503EB.json b/data/chips/STM32H503EB.json index 3f0ad68..165f5d4 100644 --- a/data/chips/STM32H503EB.json +++ b/data/chips/STM32H503EB.json @@ -1132,7 +1132,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1257,7 +1257,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H503KB.json b/data/chips/STM32H503KB.json index 0c1924d..25fa49c 100644 --- a/data/chips/STM32H503KB.json +++ b/data/chips/STM32H503KB.json @@ -1181,7 +1181,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1326,7 +1326,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H503RB.json b/data/chips/STM32H503RB.json index 0a6033d..3c1a924 100644 --- a/data/chips/STM32H503RB.json +++ b/data/chips/STM32H503RB.json @@ -1394,7 +1394,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1564,7 +1564,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index 1848465..098d742 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -2648,7 +2648,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2793,7 +2793,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2918,7 +2918,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3058,7 +3058,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3116,7 +3116,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3246,7 +3246,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index 384edf8..825364a 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -2659,7 +2659,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2804,7 +2804,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2929,7 +2929,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3069,7 +3069,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3127,7 +3127,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3257,7 +3257,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index 245f540..adfa74a 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -2677,7 +2677,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2822,7 +2822,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2947,7 +2947,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3087,7 +3087,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3145,7 +3145,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3275,7 +3275,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index d3aa9d4..481dc6e 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -2688,7 +2688,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2833,7 +2833,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2958,7 +2958,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3098,7 +3098,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3156,7 +3156,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3286,7 +3286,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index 9fe6ef0..0ae556a 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -1754,7 +1754,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1849,7 +1849,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1964,7 +1964,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2074,7 +2074,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2112,7 +2112,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2182,7 +2182,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index e957504..f557ad7 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -1765,7 +1765,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1860,7 +1860,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1975,7 +1975,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2085,7 +2085,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2123,7 +2123,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2193,7 +2193,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index f1bcb5d..504eab4 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -2184,7 +2184,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2289,7 +2289,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2409,7 +2409,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2519,7 +2519,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2567,7 +2567,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2637,7 +2637,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index 13c8d8a..cc843bc 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -2195,7 +2195,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2300,7 +2300,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2420,7 +2420,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2530,7 +2530,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2578,7 +2578,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2648,7 +2648,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index d0abf82..ed1c524 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -2458,7 +2458,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2588,7 +2588,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2708,7 +2708,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2848,7 +2848,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2906,7 +2906,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3036,7 +3036,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index 56b0806..65c3ff1 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -2469,7 +2469,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2599,7 +2599,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2719,7 +2719,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2859,7 +2859,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2917,7 +2917,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3047,7 +3047,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index 75682bc..457b43e 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -2921,7 +2921,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3066,7 +3066,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3191,7 +3191,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3331,7 +3331,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3389,7 +3389,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3519,7 +3519,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index e061e82..0f26264 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -2951,7 +2951,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3096,7 +3096,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3221,7 +3221,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3361,7 +3361,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3419,7 +3419,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3549,7 +3549,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 4294633..2a2dead 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -2955,7 +2955,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3100,7 +3100,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3225,7 +3225,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3365,7 +3365,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3423,7 +3423,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3553,7 +3553,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index 87b3799..fba16b6 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -2974,7 +2974,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3119,7 +3119,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3244,7 +3244,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3384,7 +3384,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3442,7 +3442,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3572,7 +3572,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index df65131..653b2f8 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -2138,7 +2138,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2223,7 +2223,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2313,7 +2313,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2423,7 +2423,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2461,7 +2461,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2531,7 +2531,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index bea9b94..fdbea20 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -1972,7 +1972,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2067,7 +2067,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2182,7 +2182,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2292,7 +2292,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2330,7 +2330,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2400,7 +2400,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index 97f73e3..e6060bb 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -1983,7 +1983,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2078,7 +2078,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2193,7 +2193,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2303,7 +2303,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2341,7 +2341,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2411,7 +2411,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index acfb79f..d5fa752 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -2407,7 +2407,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2512,7 +2512,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2632,7 +2632,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2742,7 +2742,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2790,7 +2790,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2860,7 +2860,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index 943005c..311dfdc 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -2437,7 +2437,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2542,7 +2542,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2667,7 +2667,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2777,7 +2777,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2825,7 +2825,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2895,7 +2895,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index 34a39a4..8132c69 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -2706,7 +2706,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2836,7 +2836,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2956,7 +2956,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3096,7 +3096,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3154,7 +3154,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3284,7 +3284,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index 50e46b6..feb0203 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -2751,7 +2751,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2886,7 +2886,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3011,7 +3011,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3151,7 +3151,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3209,7 +3209,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3339,7 +3339,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 6736774..f7a7c4a 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -3000,7 +3000,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3145,7 +3145,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3270,7 +3270,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3410,7 +3410,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3468,7 +3468,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3598,7 +3598,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index 36b4492..942902e 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -3023,7 +3023,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3168,7 +3168,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3293,7 +3293,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3433,7 +3433,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3491,7 +3491,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3621,7 +3621,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index e36d0d9..21d81ed 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -2187,7 +2187,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2272,7 +2272,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2362,7 +2362,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2472,7 +2472,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2510,7 +2510,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2580,7 +2580,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index e14cb45..b3ffb95 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -2032,7 +2032,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2127,7 +2127,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2242,7 +2242,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2352,7 +2352,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2390,7 +2390,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2460,7 +2460,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index 56c2839..d94dc67 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -2486,7 +2486,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2591,7 +2591,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2716,7 +2716,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2826,7 +2826,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -2874,7 +2874,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2944,7 +2944,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index 3780d16..9483f7d 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -2800,7 +2800,7 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2935,7 +2935,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3060,7 +3060,7 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3200,7 +3200,7 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { @@ -3258,7 +3258,7 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3388,7 +3388,7 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32H723VE.json b/data/chips/STM32H723VE.json index 79fff38..cc35a5a 100644 --- a/data/chips/STM32H723VE.json +++ b/data/chips/STM32H723VE.json @@ -3047,7 +3047,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3100,7 +3100,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3163,7 +3163,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3198,7 +3198,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3233,7 +3233,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H723VG.json b/data/chips/STM32H723VG.json index 862e2f8..cfeb062 100644 --- a/data/chips/STM32H723VG.json +++ b/data/chips/STM32H723VG.json @@ -3047,7 +3047,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3100,7 +3100,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3163,7 +3163,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3198,7 +3198,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3233,7 +3233,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H723ZE.json b/data/chips/STM32H723ZE.json index 62bc7cf..244a752 100644 --- a/data/chips/STM32H723ZE.json +++ b/data/chips/STM32H723ZE.json @@ -3444,7 +3444,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3517,7 +3517,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3580,7 +3580,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3615,7 +3615,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3650,7 +3650,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H723ZG.json b/data/chips/STM32H723ZG.json index a22aefb..bd4fdb6 100644 --- a/data/chips/STM32H723ZG.json +++ b/data/chips/STM32H723ZG.json @@ -3444,7 +3444,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3517,7 +3517,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3580,7 +3580,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3615,7 +3615,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3650,7 +3650,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725AE.json b/data/chips/STM32H725AE.json index 085d9ac..15eb2c9 100644 --- a/data/chips/STM32H725AE.json +++ b/data/chips/STM32H725AE.json @@ -3560,7 +3560,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3638,7 +3638,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3701,7 +3701,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3736,7 +3736,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3771,7 +3771,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725AG.json b/data/chips/STM32H725AG.json index e674e4b..78d3601 100644 --- a/data/chips/STM32H725AG.json +++ b/data/chips/STM32H725AG.json @@ -3566,7 +3566,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3644,7 +3644,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3707,7 +3707,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3742,7 +3742,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3777,7 +3777,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725IE.json b/data/chips/STM32H725IE.json index 2504139..d919f2e 100644 --- a/data/chips/STM32H725IE.json +++ b/data/chips/STM32H725IE.json @@ -3671,7 +3671,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3749,7 +3749,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3812,7 +3812,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3847,7 +3847,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3882,7 +3882,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725IG.json b/data/chips/STM32H725IG.json index 917a42d..bda53f0 100644 --- a/data/chips/STM32H725IG.json +++ b/data/chips/STM32H725IG.json @@ -3677,7 +3677,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3755,7 +3755,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3818,7 +3818,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3853,7 +3853,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3888,7 +3888,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725RE.json b/data/chips/STM32H725RE.json index cdb78a2..f3916d4 100644 --- a/data/chips/STM32H725RE.json +++ b/data/chips/STM32H725RE.json @@ -2093,7 +2093,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2124,7 +2124,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2167,7 +2167,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2202,7 +2202,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2237,7 +2237,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725RG.json b/data/chips/STM32H725RG.json index 91ab1b0..955cda7 100644 --- a/data/chips/STM32H725RG.json +++ b/data/chips/STM32H725RG.json @@ -2099,7 +2099,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2130,7 +2130,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2173,7 +2173,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2208,7 +2208,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2243,7 +2243,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725VE.json b/data/chips/STM32H725VE.json index 6ff894e..cba3e2f 100644 --- a/data/chips/STM32H725VE.json +++ b/data/chips/STM32H725VE.json @@ -2962,7 +2962,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3015,7 +3015,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3078,7 +3078,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3113,7 +3113,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3148,7 +3148,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725VG.json b/data/chips/STM32H725VG.json index 13be9af..17ef3b7 100644 --- a/data/chips/STM32H725VG.json +++ b/data/chips/STM32H725VG.json @@ -2972,7 +2972,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3025,7 +3025,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3088,7 +3088,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3123,7 +3123,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3158,7 +3158,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725ZE.json b/data/chips/STM32H725ZE.json index 87eb922..766fb3b 100644 --- a/data/chips/STM32H725ZE.json +++ b/data/chips/STM32H725ZE.json @@ -3236,7 +3236,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3309,7 +3309,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3372,7 +3372,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3407,7 +3407,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3442,7 +3442,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H725ZG.json b/data/chips/STM32H725ZG.json index 0ebd529..5708294 100644 --- a/data/chips/STM32H725ZG.json +++ b/data/chips/STM32H725ZG.json @@ -3242,7 +3242,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3315,7 +3315,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3378,7 +3378,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3413,7 +3413,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3448,7 +3448,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index 55cdd8c..86198dd 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -3651,7 +3651,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3729,7 +3729,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3792,7 +3792,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3827,7 +3827,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3862,7 +3862,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index 3be00a2..56e8f5c 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -3762,7 +3762,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3840,7 +3840,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3903,7 +3903,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3938,7 +3938,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3973,7 +3973,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index fb203f6..c4f5693 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -3132,7 +3132,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3185,7 +3185,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3248,7 +3248,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3283,7 +3283,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3318,7 +3318,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index 9c0c3ae..6c7f363 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -3529,7 +3529,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3602,7 +3602,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3665,7 +3665,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3700,7 +3700,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3735,7 +3735,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index 771e2ab..436fa63 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -3132,7 +3132,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3185,7 +3185,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3248,7 +3248,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3283,7 +3283,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3318,7 +3318,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index 011a82d..44ff0b9 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -3529,7 +3529,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3602,7 +3602,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3665,7 +3665,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3700,7 +3700,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3735,7 +3735,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index 1d87a5e..b1c0a75 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -3656,7 +3656,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3734,7 +3734,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3797,7 +3797,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3832,7 +3832,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3867,7 +3867,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index 8ef7f33..24a10bc 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -3767,7 +3767,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3845,7 +3845,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3908,7 +3908,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3943,7 +3943,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3978,7 +3978,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H735RG.json b/data/chips/STM32H735RG.json index b91a524..2149d3b 100644 --- a/data/chips/STM32H735RG.json +++ b/data/chips/STM32H735RG.json @@ -2189,7 +2189,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2220,7 +2220,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2263,7 +2263,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2298,7 +2298,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2333,7 +2333,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index b303e65..4072d30 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -3062,7 +3062,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3115,7 +3115,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3178,7 +3178,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3213,7 +3213,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3248,7 +3248,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index b29fa96..953787a 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -3332,7 +3332,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3405,7 +3405,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3468,7 +3468,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3503,7 +3503,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3538,7 +3538,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742AG.json b/data/chips/STM32H742AG.json index 87ffe11..a3f5396 100644 --- a/data/chips/STM32H742AG.json +++ b/data/chips/STM32H742AG.json @@ -3475,7 +3475,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3553,7 +3553,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3616,7 +3616,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3651,7 +3651,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3686,7 +3686,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742AI.json b/data/chips/STM32H742AI.json index b90f6c0..ec6e5a4 100644 --- a/data/chips/STM32H742AI.json +++ b/data/chips/STM32H742AI.json @@ -3486,7 +3486,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3564,7 +3564,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3627,7 +3627,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3662,7 +3662,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3697,7 +3697,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742BG.json b/data/chips/STM32H742BG.json index 363b982..b2e6857 100644 --- a/data/chips/STM32H742BG.json +++ b/data/chips/STM32H742BG.json @@ -3620,7 +3620,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3698,7 +3698,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3761,7 +3761,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3796,7 +3796,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3831,7 +3831,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742BI.json b/data/chips/STM32H742BI.json index a8fdf33..05ab9bf 100644 --- a/data/chips/STM32H742BI.json +++ b/data/chips/STM32H742BI.json @@ -3631,7 +3631,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3709,7 +3709,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3772,7 +3772,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3807,7 +3807,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3842,7 +3842,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742IG.json b/data/chips/STM32H742IG.json index b0d53b2..f2308f8 100644 --- a/data/chips/STM32H742IG.json +++ b/data/chips/STM32H742IG.json @@ -3619,7 +3619,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3697,7 +3697,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3760,7 +3760,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3795,7 +3795,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3830,7 +3830,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742II.json b/data/chips/STM32H742II.json index 94022b6..3c1d40f 100644 --- a/data/chips/STM32H742II.json +++ b/data/chips/STM32H742II.json @@ -3630,7 +3630,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3708,7 +3708,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3771,7 +3771,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3806,7 +3806,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3841,7 +3841,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742VG.json b/data/chips/STM32H742VG.json index 45a3743..10bd586 100644 --- a/data/chips/STM32H742VG.json +++ b/data/chips/STM32H742VG.json @@ -2954,7 +2954,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3007,7 +3007,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3070,7 +3070,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3105,7 +3105,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3140,7 +3140,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742VI.json b/data/chips/STM32H742VI.json index d6cd513..81e14d7 100644 --- a/data/chips/STM32H742VI.json +++ b/data/chips/STM32H742VI.json @@ -2965,7 +2965,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3018,7 +3018,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3081,7 +3081,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3116,7 +3116,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3151,7 +3151,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742XG.json b/data/chips/STM32H742XG.json index f273545..10af4c6 100644 --- a/data/chips/STM32H742XG.json +++ b/data/chips/STM32H742XG.json @@ -3684,7 +3684,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3762,7 +3762,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3825,7 +3825,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3860,7 +3860,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3895,7 +3895,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742XI.json b/data/chips/STM32H742XI.json index 58ae1d4..19795f4 100644 --- a/data/chips/STM32H742XI.json +++ b/data/chips/STM32H742XI.json @@ -3695,7 +3695,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3773,7 +3773,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3836,7 +3836,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3871,7 +3871,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3906,7 +3906,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742ZG.json b/data/chips/STM32H742ZG.json index 4e2e2bd..483b364 100644 --- a/data/chips/STM32H742ZG.json +++ b/data/chips/STM32H742ZG.json @@ -3302,7 +3302,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3375,7 +3375,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3438,7 +3438,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3473,7 +3473,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3508,7 +3508,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H742ZI.json b/data/chips/STM32H742ZI.json index 82686de..0da292e 100644 --- a/data/chips/STM32H742ZI.json +++ b/data/chips/STM32H742ZI.json @@ -3313,7 +3313,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3386,7 +3386,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3449,7 +3449,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3484,7 +3484,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3519,7 +3519,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743AG.json b/data/chips/STM32H743AG.json index 5a708de..a2055ca 100644 --- a/data/chips/STM32H743AG.json +++ b/data/chips/STM32H743AG.json @@ -3537,7 +3537,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3615,7 +3615,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3678,7 +3678,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3713,7 +3713,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3748,7 +3748,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743AI.json b/data/chips/STM32H743AI.json index a80fc4e..1889628 100644 --- a/data/chips/STM32H743AI.json +++ b/data/chips/STM32H743AI.json @@ -3548,7 +3548,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3626,7 +3626,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3689,7 +3689,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3724,7 +3724,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3759,7 +3759,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743BG.json b/data/chips/STM32H743BG.json index edc306c..0bdc43a 100644 --- a/data/chips/STM32H743BG.json +++ b/data/chips/STM32H743BG.json @@ -3682,7 +3682,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3760,7 +3760,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3823,7 +3823,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3858,7 +3858,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3893,7 +3893,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743BI.json b/data/chips/STM32H743BI.json index 63bb0f4..0a234a1 100644 --- a/data/chips/STM32H743BI.json +++ b/data/chips/STM32H743BI.json @@ -3693,7 +3693,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3771,7 +3771,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3834,7 +3834,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3869,7 +3869,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3904,7 +3904,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743IG.json b/data/chips/STM32H743IG.json index cda6dc3..9215134 100644 --- a/data/chips/STM32H743IG.json +++ b/data/chips/STM32H743IG.json @@ -3681,7 +3681,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3759,7 +3759,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3822,7 +3822,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3857,7 +3857,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3892,7 +3892,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743II.json b/data/chips/STM32H743II.json index 1c8f903..0a7f178 100644 --- a/data/chips/STM32H743II.json +++ b/data/chips/STM32H743II.json @@ -3692,7 +3692,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3770,7 +3770,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3833,7 +3833,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3868,7 +3868,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3903,7 +3903,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743VG.json b/data/chips/STM32H743VG.json index 1149550..8618dee 100644 --- a/data/chips/STM32H743VG.json +++ b/data/chips/STM32H743VG.json @@ -3016,7 +3016,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3069,7 +3069,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3132,7 +3132,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3167,7 +3167,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3202,7 +3202,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743VI.json b/data/chips/STM32H743VI.json index fb41f4d..c4bfe2a 100644 --- a/data/chips/STM32H743VI.json +++ b/data/chips/STM32H743VI.json @@ -3027,7 +3027,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3080,7 +3080,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3143,7 +3143,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3178,7 +3178,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3213,7 +3213,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743XG.json b/data/chips/STM32H743XG.json index 21b7f15..0c6586d 100644 --- a/data/chips/STM32H743XG.json +++ b/data/chips/STM32H743XG.json @@ -3746,7 +3746,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3824,7 +3824,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3887,7 +3887,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3922,7 +3922,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3957,7 +3957,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743XI.json b/data/chips/STM32H743XI.json index 5a851f8..3e2edcb 100644 --- a/data/chips/STM32H743XI.json +++ b/data/chips/STM32H743XI.json @@ -3757,7 +3757,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3835,7 +3835,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3898,7 +3898,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3933,7 +3933,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3968,7 +3968,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743ZG.json b/data/chips/STM32H743ZG.json index d556045..75d8308 100644 --- a/data/chips/STM32H743ZG.json +++ b/data/chips/STM32H743ZG.json @@ -3364,7 +3364,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3437,7 +3437,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3500,7 +3500,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3535,7 +3535,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3570,7 +3570,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H743ZI.json b/data/chips/STM32H743ZI.json index 98649b3..e9f72fa 100644 --- a/data/chips/STM32H743ZI.json +++ b/data/chips/STM32H743ZI.json @@ -3375,7 +3375,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3448,7 +3448,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3511,7 +3511,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3546,7 +3546,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3581,7 +3581,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745BG.json b/data/chips/STM32H745BG.json index 1e98e40..9020efc 100644 --- a/data/chips/STM32H745BG.json +++ b/data/chips/STM32H745BG.json @@ -3668,7 +3668,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3746,7 +3746,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3809,7 +3809,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3844,7 +3844,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3879,7 +3879,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13539,7 +13539,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13617,7 +13617,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13680,7 +13680,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13715,7 +13715,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13750,7 +13750,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745BI.json b/data/chips/STM32H745BI.json index b4117fb..a9b1b9f 100644 --- a/data/chips/STM32H745BI.json +++ b/data/chips/STM32H745BI.json @@ -3679,7 +3679,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3757,7 +3757,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3820,7 +3820,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3855,7 +3855,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3890,7 +3890,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13550,7 +13550,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13628,7 +13628,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13691,7 +13691,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13726,7 +13726,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13761,7 +13761,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745IG.json b/data/chips/STM32H745IG.json index ba7327d..fe224a6 100644 --- a/data/chips/STM32H745IG.json +++ b/data/chips/STM32H745IG.json @@ -3636,7 +3636,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3714,7 +3714,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3777,7 +3777,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3812,7 +3812,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3847,7 +3847,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13249,7 +13249,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13327,7 +13327,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13390,7 +13390,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13425,7 +13425,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13460,7 +13460,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745II.json b/data/chips/STM32H745II.json index 8e3f027..dd5ff99 100644 --- a/data/chips/STM32H745II.json +++ b/data/chips/STM32H745II.json @@ -3647,7 +3647,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3725,7 +3725,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3788,7 +3788,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3823,7 +3823,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3858,7 +3858,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13260,7 +13260,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13338,7 +13338,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13401,7 +13401,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13436,7 +13436,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13471,7 +13471,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745XG.json b/data/chips/STM32H745XG.json index 8014bcd..35ea33a 100644 --- a/data/chips/STM32H745XG.json +++ b/data/chips/STM32H745XG.json @@ -3737,7 +3737,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3815,7 +3815,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3878,7 +3878,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3913,7 +3913,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3948,7 +3948,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13782,7 +13782,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13860,7 +13860,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13923,7 +13923,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13958,7 +13958,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13993,7 +13993,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745XI.json b/data/chips/STM32H745XI.json index 7a5adab..46286a4 100644 --- a/data/chips/STM32H745XI.json +++ b/data/chips/STM32H745XI.json @@ -3748,7 +3748,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3826,7 +3826,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3889,7 +3889,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3924,7 +3924,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3959,7 +3959,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13793,7 +13793,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13871,7 +13871,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13934,7 +13934,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13969,7 +13969,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14004,7 +14004,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745ZG.json b/data/chips/STM32H745ZG.json index 8b446b2..5659d3c 100644 --- a/data/chips/STM32H745ZG.json +++ b/data/chips/STM32H745ZG.json @@ -3208,7 +3208,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3281,7 +3281,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3344,7 +3344,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3379,7 +3379,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3414,7 +3414,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12014,7 +12014,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12087,7 +12087,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12150,7 +12150,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12185,7 +12185,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12220,7 +12220,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H745ZI.json b/data/chips/STM32H745ZI.json index 1dda843..a2bb7d7 100644 --- a/data/chips/STM32H745ZI.json +++ b/data/chips/STM32H745ZI.json @@ -3219,7 +3219,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3292,7 +3292,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3355,7 +3355,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3390,7 +3390,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3425,7 +3425,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12025,7 +12025,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12098,7 +12098,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12161,7 +12161,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12196,7 +12196,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12231,7 +12231,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index ef4bb81..d5bf17c 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -3361,7 +3361,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3434,7 +3434,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3497,7 +3497,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3532,7 +3532,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3567,7 +3567,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12386,7 +12386,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12459,7 +12459,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12522,7 +12522,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12557,7 +12557,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12592,7 +12592,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index 56ceb5a..5283156 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -3372,7 +3372,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3445,7 +3445,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3508,7 +3508,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3543,7 +3543,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3578,7 +3578,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12397,7 +12397,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12470,7 +12470,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12533,7 +12533,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12568,7 +12568,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12603,7 +12603,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index 24b6f59..4f3318a 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -3674,7 +3674,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3752,7 +3752,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3815,7 +3815,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3850,7 +3850,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3885,7 +3885,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13374,7 +13374,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13452,7 +13452,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13515,7 +13515,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13550,7 +13550,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13585,7 +13585,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index 582c1a1..77cc876 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -3685,7 +3685,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3763,7 +3763,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3826,7 +3826,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3861,7 +3861,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3896,7 +3896,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13385,7 +13385,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13463,7 +13463,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13526,7 +13526,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13561,7 +13561,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13596,7 +13596,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index 8f95239..5f43d8d 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -3361,7 +3361,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3434,7 +3434,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3497,7 +3497,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3532,7 +3532,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3567,7 +3567,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12386,7 +12386,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12459,7 +12459,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12522,7 +12522,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12557,7 +12557,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12592,7 +12592,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index 7a5956b..f7f8c95 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -3372,7 +3372,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3445,7 +3445,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3508,7 +3508,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3543,7 +3543,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3578,7 +3578,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12397,7 +12397,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12470,7 +12470,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12533,7 +12533,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12568,7 +12568,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12603,7 +12603,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index c86ef55..2de6d2a 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -3743,7 +3743,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3821,7 +3821,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3884,7 +3884,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3919,7 +3919,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3954,7 +3954,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13792,7 +13792,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13870,7 +13870,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13933,7 +13933,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13968,7 +13968,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14003,7 +14003,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index 3254037..d698116 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -3754,7 +3754,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3832,7 +3832,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3895,7 +3895,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3930,7 +3930,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3965,7 +3965,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13803,7 +13803,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13881,7 +13881,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13944,7 +13944,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13979,7 +13979,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14014,7 +14014,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index 098e59a..9ca4ed9 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -3220,7 +3220,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3273,7 +3273,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3336,7 +3336,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3371,7 +3371,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3406,7 +3406,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11702,7 +11702,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11755,7 +11755,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11818,7 +11818,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11853,7 +11853,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11888,7 +11888,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H750IB.json b/data/chips/STM32H750IB.json index fa1c3ee..8069c67 100644 --- a/data/chips/STM32H750IB.json +++ b/data/chips/STM32H750IB.json @@ -3737,7 +3737,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3815,7 +3815,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3878,7 +3878,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3913,7 +3913,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3948,7 +3948,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H750VB.json b/data/chips/STM32H750VB.json index 1509070..00f24e1 100644 --- a/data/chips/STM32H750VB.json +++ b/data/chips/STM32H750VB.json @@ -3068,7 +3068,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3121,7 +3121,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3184,7 +3184,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3219,7 +3219,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3254,7 +3254,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H750XB.json b/data/chips/STM32H750XB.json index 25ce75f..948c959 100644 --- a/data/chips/STM32H750XB.json +++ b/data/chips/STM32H750XB.json @@ -3802,7 +3802,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3880,7 +3880,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3943,7 +3943,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3978,7 +3978,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4013,7 +4013,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H750ZB.json b/data/chips/STM32H750ZB.json index 7e66917..80f5896 100644 --- a/data/chips/STM32H750ZB.json +++ b/data/chips/STM32H750ZB.json @@ -3408,7 +3408,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3481,7 +3481,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3544,7 +3544,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3579,7 +3579,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3614,7 +3614,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753AI.json b/data/chips/STM32H753AI.json index 8736724..4d8e451 100644 --- a/data/chips/STM32H753AI.json +++ b/data/chips/STM32H753AI.json @@ -3627,7 +3627,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3705,7 +3705,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3768,7 +3768,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3803,7 +3803,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3838,7 +3838,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753BI.json b/data/chips/STM32H753BI.json index 9c0c554..fc3891c 100644 --- a/data/chips/STM32H753BI.json +++ b/data/chips/STM32H753BI.json @@ -3772,7 +3772,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3850,7 +3850,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3913,7 +3913,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3948,7 +3948,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3983,7 +3983,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753II.json b/data/chips/STM32H753II.json index 4d59d07..c4978a6 100644 --- a/data/chips/STM32H753II.json +++ b/data/chips/STM32H753II.json @@ -3771,7 +3771,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3849,7 +3849,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3912,7 +3912,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3947,7 +3947,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3982,7 +3982,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753VI.json b/data/chips/STM32H753VI.json index 2aeca62..4b18def 100644 --- a/data/chips/STM32H753VI.json +++ b/data/chips/STM32H753VI.json @@ -3106,7 +3106,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3159,7 +3159,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3222,7 +3222,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3257,7 +3257,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3292,7 +3292,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753XI.json b/data/chips/STM32H753XI.json index 7f5a024..369bace 100644 --- a/data/chips/STM32H753XI.json +++ b/data/chips/STM32H753XI.json @@ -3836,7 +3836,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3914,7 +3914,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3977,7 +3977,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4012,7 +4012,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4047,7 +4047,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H753ZI.json b/data/chips/STM32H753ZI.json index 16d36bb..1c9ba37 100644 --- a/data/chips/STM32H753ZI.json +++ b/data/chips/STM32H753ZI.json @@ -3454,7 +3454,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3527,7 +3527,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3590,7 +3590,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3625,7 +3625,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3660,7 +3660,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index 46e95c9..0247ff5 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -3758,7 +3758,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3836,7 +3836,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3899,7 +3899,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3934,7 +3934,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3969,7 +3969,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13706,7 +13706,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13784,7 +13784,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13847,7 +13847,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13882,7 +13882,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13917,7 +13917,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index 4cde37c..cb9117e 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -3726,7 +3726,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3804,7 +3804,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3867,7 +3867,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3902,7 +3902,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3937,7 +3937,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13416,7 +13416,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13494,7 +13494,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13557,7 +13557,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13592,7 +13592,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13627,7 +13627,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index 8ce335a..0deae0a 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -3827,7 +3827,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3905,7 +3905,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3968,7 +3968,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4003,7 +4003,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4038,7 +4038,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13949,7 +13949,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14027,7 +14027,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14090,7 +14090,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14125,7 +14125,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14160,7 +14160,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index 5e654ae..0322932 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -3298,7 +3298,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3371,7 +3371,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3434,7 +3434,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3469,7 +3469,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3504,7 +3504,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12181,7 +12181,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12254,7 +12254,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12317,7 +12317,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12352,7 +12352,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12387,7 +12387,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index a88ef25..45a1104 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -3451,7 +3451,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3524,7 +3524,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3587,7 +3587,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3622,7 +3622,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3657,7 +3657,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12553,7 +12553,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12626,7 +12626,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12689,7 +12689,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12724,7 +12724,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12759,7 +12759,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index 9274149..bac5550 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -3764,7 +3764,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3842,7 +3842,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3905,7 +3905,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3940,7 +3940,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3975,7 +3975,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13541,7 +13541,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13619,7 +13619,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13682,7 +13682,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13717,7 +13717,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13752,7 +13752,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 4b12380..df285bd 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -3451,7 +3451,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3524,7 +3524,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3587,7 +3587,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3622,7 +3622,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3657,7 +3657,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12553,7 +12553,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12626,7 +12626,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12689,7 +12689,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12724,7 +12724,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12759,7 +12759,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 8ae953a..2da0bed 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -3833,7 +3833,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3911,7 +3911,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3974,7 +3974,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4009,7 +4009,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -4044,7 +4044,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -13959,7 +13959,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14037,7 +14037,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14100,7 +14100,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14135,7 +14135,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -14170,7 +14170,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index 6208d82..baa56eb 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -3299,7 +3299,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3352,7 +3352,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3415,7 +3415,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3450,7 +3450,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3485,7 +3485,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11858,7 +11858,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11911,7 +11911,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -11974,7 +11974,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12009,7 +12009,7 @@ "address": 1476406272, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -12044,7 +12044,7 @@ "address": 1476407296, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index 672b2aa..374166e 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -3204,7 +3204,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3282,7 +3282,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3345,7 +3345,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index db90cd6..3e6b145 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -3215,7 +3215,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3293,7 +3293,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3356,7 +3356,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index 36db5a5..6e76a8e 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -3396,7 +3396,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3474,7 +3474,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3537,7 +3537,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index 66af27e..158402c 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -3407,7 +3407,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3485,7 +3485,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3548,7 +3548,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index 3ccd957..da5cdf9 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -3378,7 +3378,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3456,7 +3456,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3519,7 +3519,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index ef6f162..f09cf41 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -3395,7 +3395,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3473,7 +3473,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3536,7 +3536,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index ba07a78..bd739e3 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -3340,7 +3340,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3418,7 +3418,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3481,7 +3481,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index f0ca16b..da4eeff 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -3351,7 +3351,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3429,7 +3429,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3492,7 +3492,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index 48f3c27..e1daf04 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -2905,7 +2905,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2978,7 +2978,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3041,7 +3041,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3RG.json b/data/chips/STM32H7A3RG.json index c44745b..21f57ac 100644 --- a/data/chips/STM32H7A3RG.json +++ b/data/chips/STM32H7A3RG.json @@ -2214,7 +2214,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2245,7 +2245,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2288,7 +2288,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3RI.json b/data/chips/STM32H7A3RI.json index e96a228..9cb69c8 100644 --- a/data/chips/STM32H7A3RI.json +++ b/data/chips/STM32H7A3RI.json @@ -2225,7 +2225,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2256,7 +2256,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2299,7 +2299,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index 655909f..7de83de 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -2843,7 +2843,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2896,7 +2896,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2959,7 +2959,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index 115814d..de5fd43 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -2854,7 +2854,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2907,7 +2907,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2970,7 +2970,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index fe5395a..8ceb09c 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -3084,7 +3084,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3157,7 +3157,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3220,7 +3220,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index 0d5045f..3eeb1ed 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -3095,7 +3095,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3168,7 +3168,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3231,7 +3231,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index 023641b..3051123 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -3283,7 +3283,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3361,7 +3361,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3424,7 +3424,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index b0cd0c5..4ba9b4e 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -3467,7 +3467,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3545,7 +3545,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3608,7 +3608,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index d7c4ee3..13467d4 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -2293,7 +2293,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2324,7 +2324,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2367,7 +2367,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index 923f9f3..a45fa34 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -2910,7 +2910,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2963,7 +2963,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3026,7 +3026,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index c9b9211..d5099c1 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -3159,7 +3159,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3232,7 +3232,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3295,7 +3295,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index 6d6995f..cff1904 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -3305,7 +3305,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3383,7 +3383,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3446,7 +3446,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index 322e66a..fc88750 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -3497,7 +3497,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3575,7 +3575,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3638,7 +3638,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index 8f18a2b..09a15be 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -3485,7 +3485,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3563,7 +3563,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3626,7 +3626,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index 14eabbe..b34cdeb 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -3441,7 +3441,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3519,7 +3519,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3582,7 +3582,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index f8bc86c..5a41103 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -2995,7 +2995,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3068,7 +3068,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3131,7 +3131,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 6ba7e27..24f6a1c 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -2315,7 +2315,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2346,7 +2346,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2389,7 +2389,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index a948861..40e52da 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -2944,7 +2944,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -2997,7 +2997,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3060,7 +3060,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index 6b4eeaf..c79f6ff 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -3185,7 +3185,7 @@ "address": 1073751040, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3258,7 +3258,7 @@ "address": 1476404224, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { @@ -3321,7 +3321,7 @@ "address": 1476405248, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b_h7", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412C8.json b/data/chips/STM32L412C8.json index 2af667a..c62c63a 100644 --- a/data/chips/STM32L412C8.json +++ b/data/chips/STM32L412C8.json @@ -1237,7 +1237,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1295,7 +1295,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412CB.json b/data/chips/STM32L412CB.json index eb8abd0..b719b10 100644 --- a/data/chips/STM32L412CB.json +++ b/data/chips/STM32L412CB.json @@ -1245,7 +1245,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1303,7 +1303,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412K8.json b/data/chips/STM32L412K8.json index b9c5b49..11d97fc 100644 --- a/data/chips/STM32L412K8.json +++ b/data/chips/STM32L412K8.json @@ -1140,7 +1140,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1193,7 +1193,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412KB.json b/data/chips/STM32L412KB.json index 6f94bc2..f832a3f 100644 --- a/data/chips/STM32L412KB.json +++ b/data/chips/STM32L412KB.json @@ -1140,7 +1140,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1193,7 +1193,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412R8.json b/data/chips/STM32L412R8.json index ccd7153..eda397b 100644 --- a/data/chips/STM32L412R8.json +++ b/data/chips/STM32L412R8.json @@ -1303,7 +1303,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1381,7 +1381,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412RB.json b/data/chips/STM32L412RB.json index 1e10666..dee7772 100644 --- a/data/chips/STM32L412RB.json +++ b/data/chips/STM32L412RB.json @@ -1317,7 +1317,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1395,7 +1395,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412T8.json b/data/chips/STM32L412T8.json index 6bfc202..d2bec19 100644 --- a/data/chips/STM32L412T8.json +++ b/data/chips/STM32L412T8.json @@ -1155,7 +1155,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1213,7 +1213,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L412TB.json b/data/chips/STM32L412TB.json index 47268c5..05fea31 100644 --- a/data/chips/STM32L412TB.json +++ b/data/chips/STM32L412TB.json @@ -1159,7 +1159,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1217,7 +1217,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L422CB.json b/data/chips/STM32L422CB.json index 7c48b05..c855451 100644 --- a/data/chips/STM32L422CB.json +++ b/data/chips/STM32L422CB.json @@ -1286,7 +1286,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1344,7 +1344,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L422KB.json b/data/chips/STM32L422KB.json index 159d5f4..8e9d63e 100644 --- a/data/chips/STM32L422KB.json +++ b/data/chips/STM32L422KB.json @@ -1189,7 +1189,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1242,7 +1242,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L422RB.json b/data/chips/STM32L422RB.json index b2d921c..9fbad9c 100644 --- a/data/chips/STM32L422RB.json +++ b/data/chips/STM32L422RB.json @@ -1358,7 +1358,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1436,7 +1436,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L422TB.json b/data/chips/STM32L422TB.json index 78e145a..e008849 100644 --- a/data/chips/STM32L422TB.json +++ b/data/chips/STM32L422TB.json @@ -1204,7 +1204,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1262,7 +1262,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431CB.json b/data/chips/STM32L431CB.json index 80b7e9a..453299e 100644 --- a/data/chips/STM32L431CB.json +++ b/data/chips/STM32L431CB.json @@ -1361,7 +1361,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1424,7 +1424,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431CC.json b/data/chips/STM32L431CC.json index 0089b9b..366629a 100644 --- a/data/chips/STM32L431CC.json +++ b/data/chips/STM32L431CC.json @@ -1361,7 +1361,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1424,7 +1424,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431KB.json b/data/chips/STM32L431KB.json index ff85f03..8d50b3e 100644 --- a/data/chips/STM32L431KB.json +++ b/data/chips/STM32L431KB.json @@ -1237,7 +1237,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1290,7 +1290,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431KC.json b/data/chips/STM32L431KC.json index 54cc70d..f19ec82 100644 --- a/data/chips/STM32L431KC.json +++ b/data/chips/STM32L431KC.json @@ -1237,7 +1237,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1290,7 +1290,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431RB.json b/data/chips/STM32L431RB.json index 000ef79..7f7d5f0 100644 --- a/data/chips/STM32L431RB.json +++ b/data/chips/STM32L431RB.json @@ -1399,7 +1399,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1477,7 +1477,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431RC.json b/data/chips/STM32L431RC.json index b0f8f6e..92f0d86 100644 --- a/data/chips/STM32L431RC.json +++ b/data/chips/STM32L431RC.json @@ -1399,7 +1399,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1477,7 +1477,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L431VC.json b/data/chips/STM32L431VC.json index 7bec5cb..a7caf6b 100644 --- a/data/chips/STM32L431VC.json +++ b/data/chips/STM32L431VC.json @@ -1405,7 +1405,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1483,7 +1483,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L432KB.json b/data/chips/STM32L432KB.json index f34eebc..48e4764 100644 --- a/data/chips/STM32L432KB.json +++ b/data/chips/STM32L432KB.json @@ -1208,7 +1208,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1261,7 +1261,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L432KC.json b/data/chips/STM32L432KC.json index ac01ea0..5833461 100644 --- a/data/chips/STM32L432KC.json +++ b/data/chips/STM32L432KC.json @@ -1208,7 +1208,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1261,7 +1261,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L433CB.json b/data/chips/STM32L433CB.json index fbb067e..fb691e5 100644 --- a/data/chips/STM32L433CB.json +++ b/data/chips/STM32L433CB.json @@ -1534,7 +1534,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1597,7 +1597,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L433CC.json b/data/chips/STM32L433CC.json index 8e4ac9a..a030539 100644 --- a/data/chips/STM32L433CC.json +++ b/data/chips/STM32L433CC.json @@ -1534,7 +1534,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1597,7 +1597,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L433RB.json b/data/chips/STM32L433RB.json index 959abc0..e5781e6 100644 --- a/data/chips/STM32L433RB.json +++ b/data/chips/STM32L433RB.json @@ -1677,7 +1677,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1755,7 +1755,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L433RC.json b/data/chips/STM32L433RC.json index 2d7e2a5..8fdcc29 100644 --- a/data/chips/STM32L433RC.json +++ b/data/chips/STM32L433RC.json @@ -1687,7 +1687,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1765,7 +1765,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L433VC.json b/data/chips/STM32L433VC.json index 1c3594e..78ad857 100644 --- a/data/chips/STM32L433VC.json +++ b/data/chips/STM32L433VC.json @@ -1743,7 +1743,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1821,7 +1821,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L442KC.json b/data/chips/STM32L442KC.json index c995621..7673cc0 100644 --- a/data/chips/STM32L442KC.json +++ b/data/chips/STM32L442KC.json @@ -1257,7 +1257,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1310,7 +1310,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L443CC.json b/data/chips/STM32L443CC.json index eff8a00..3b83e9a 100644 --- a/data/chips/STM32L443CC.json +++ b/data/chips/STM32L443CC.json @@ -1587,7 +1587,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1650,7 +1650,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L443RC.json b/data/chips/STM32L443RC.json index db3d654..6ffd0b7 100644 --- a/data/chips/STM32L443RC.json +++ b/data/chips/STM32L443RC.json @@ -1726,7 +1726,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1804,7 +1804,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L443VC.json b/data/chips/STM32L443VC.json index 91b1a3b..e8e93fb 100644 --- a/data/chips/STM32L443VC.json +++ b/data/chips/STM32L443VC.json @@ -1792,7 +1792,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1870,7 +1870,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451CC.json b/data/chips/STM32L451CC.json index efcfc78..71823de 100644 --- a/data/chips/STM32L451CC.json +++ b/data/chips/STM32L451CC.json @@ -1543,7 +1543,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1601,7 +1601,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451CE.json b/data/chips/STM32L451CE.json index d5c0cc3..a1e579a 100644 --- a/data/chips/STM32L451CE.json +++ b/data/chips/STM32L451CE.json @@ -1547,7 +1547,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1605,7 +1605,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451RC.json b/data/chips/STM32L451RC.json index a03d9b4..9264731 100644 --- a/data/chips/STM32L451RC.json +++ b/data/chips/STM32L451RC.json @@ -1618,7 +1618,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1696,7 +1696,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451RE.json b/data/chips/STM32L451RE.json index a7ca893..1fb4b94 100644 --- a/data/chips/STM32L451RE.json +++ b/data/chips/STM32L451RE.json @@ -1618,7 +1618,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1696,7 +1696,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451VC.json b/data/chips/STM32L451VC.json index 94b2333..df85560 100644 --- a/data/chips/STM32L451VC.json +++ b/data/chips/STM32L451VC.json @@ -1684,7 +1684,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1762,7 +1762,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L451VE.json b/data/chips/STM32L451VE.json index e438237..f279e06 100644 --- a/data/chips/STM32L451VE.json +++ b/data/chips/STM32L451VE.json @@ -1684,7 +1684,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1762,7 +1762,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452CC.json b/data/chips/STM32L452CC.json index a7748ae..a475411 100644 --- a/data/chips/STM32L452CC.json +++ b/data/chips/STM32L452CC.json @@ -1556,7 +1556,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1614,7 +1614,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452CE.json b/data/chips/STM32L452CE.json index 10cf3f5..71fc586 100644 --- a/data/chips/STM32L452CE.json +++ b/data/chips/STM32L452CE.json @@ -1564,7 +1564,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1622,7 +1622,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452RC.json b/data/chips/STM32L452RC.json index 19505a5..7bad44c 100644 --- a/data/chips/STM32L452RC.json +++ b/data/chips/STM32L452RC.json @@ -1631,7 +1631,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1709,7 +1709,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452RE.json b/data/chips/STM32L452RE.json index f22abc0..aecfcb1 100644 --- a/data/chips/STM32L452RE.json +++ b/data/chips/STM32L452RE.json @@ -1645,7 +1645,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1723,7 +1723,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452VC.json b/data/chips/STM32L452VC.json index 9bdceb8..97f55c5 100644 --- a/data/chips/STM32L452VC.json +++ b/data/chips/STM32L452VC.json @@ -1697,7 +1697,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1775,7 +1775,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L452VE.json b/data/chips/STM32L452VE.json index 69177a8..81adf1f 100644 --- a/data/chips/STM32L452VE.json +++ b/data/chips/STM32L452VE.json @@ -1697,7 +1697,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1775,7 +1775,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L462CE.json b/data/chips/STM32L462CE.json index be5f30d..cfc3298 100644 --- a/data/chips/STM32L462CE.json +++ b/data/chips/STM32L462CE.json @@ -1615,7 +1615,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1673,7 +1673,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L462RE.json b/data/chips/STM32L462RE.json index b21605a..d93f443 100644 --- a/data/chips/STM32L462RE.json +++ b/data/chips/STM32L462RE.json @@ -1680,7 +1680,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1758,7 +1758,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L462VE.json b/data/chips/STM32L462VE.json index c799d86..4a54b4b 100644 --- a/data/chips/STM32L462VE.json +++ b/data/chips/STM32L462VE.json @@ -1746,7 +1746,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1824,7 +1824,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471QE.json b/data/chips/STM32L471QE.json index b6c4355..eed7406 100644 --- a/data/chips/STM32L471QE.json +++ b/data/chips/STM32L471QE.json @@ -2178,7 +2178,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2271,7 +2271,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471QG.json b/data/chips/STM32L471QG.json index c46b377..1bea483 100644 --- a/data/chips/STM32L471QG.json +++ b/data/chips/STM32L471QG.json @@ -2189,7 +2189,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2282,7 +2282,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471RE.json b/data/chips/STM32L471RE.json index cf74e2c..0f21d87 100644 --- a/data/chips/STM32L471RE.json +++ b/data/chips/STM32L471RE.json @@ -1639,7 +1639,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1712,7 +1712,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471RG.json b/data/chips/STM32L471RG.json index 7424bb9..1df0273 100644 --- a/data/chips/STM32L471RG.json +++ b/data/chips/STM32L471RG.json @@ -1650,7 +1650,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1723,7 +1723,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471VE.json b/data/chips/STM32L471VE.json index 87a64a5..10c52bc 100644 --- a/data/chips/STM32L471VE.json +++ b/data/chips/STM32L471VE.json @@ -1996,7 +1996,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2069,7 +2069,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471VG.json b/data/chips/STM32L471VG.json index 9a50c5e..afe35f9 100644 --- a/data/chips/STM32L471VG.json +++ b/data/chips/STM32L471VG.json @@ -2007,7 +2007,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2080,7 +2080,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471ZE.json b/data/chips/STM32L471ZE.json index b27569a..fd7e961 100644 --- a/data/chips/STM32L471ZE.json +++ b/data/chips/STM32L471ZE.json @@ -2202,7 +2202,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2295,7 +2295,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L471ZG.json b/data/chips/STM32L471ZG.json index fffd6dc..fcfa584 100644 --- a/data/chips/STM32L471ZG.json +++ b/data/chips/STM32L471ZG.json @@ -2213,7 +2213,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2306,7 +2306,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475RC.json b/data/chips/STM32L475RC.json index 73021eb..ab064c2 100644 --- a/data/chips/STM32L475RC.json +++ b/data/chips/STM32L475RC.json @@ -1645,7 +1645,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1718,7 +1718,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475RE.json b/data/chips/STM32L475RE.json index 20b8fc3..fb9ccad 100644 --- a/data/chips/STM32L475RE.json +++ b/data/chips/STM32L475RE.json @@ -1645,7 +1645,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1718,7 +1718,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475RG.json b/data/chips/STM32L475RG.json index f8a1381..f014d68 100644 --- a/data/chips/STM32L475RG.json +++ b/data/chips/STM32L475RG.json @@ -1656,7 +1656,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1729,7 +1729,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475VC.json b/data/chips/STM32L475VC.json index 01e8267..fc7e52f 100644 --- a/data/chips/STM32L475VC.json +++ b/data/chips/STM32L475VC.json @@ -2002,7 +2002,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2075,7 +2075,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475VE.json b/data/chips/STM32L475VE.json index 0b655fa..12f315b 100644 --- a/data/chips/STM32L475VE.json +++ b/data/chips/STM32L475VE.json @@ -2002,7 +2002,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2075,7 +2075,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L475VG.json b/data/chips/STM32L475VG.json index 673c636..eaa5f87 100644 --- a/data/chips/STM32L475VG.json +++ b/data/chips/STM32L475VG.json @@ -2013,7 +2013,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2086,7 +2086,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476JE.json b/data/chips/STM32L476JE.json index c486f7a..45fd67e 100644 --- a/data/chips/STM32L476JE.json +++ b/data/chips/STM32L476JE.json @@ -1933,7 +1933,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2021,7 +2021,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476JG.json b/data/chips/STM32L476JG.json index 0619743..1371f83 100644 --- a/data/chips/STM32L476JG.json +++ b/data/chips/STM32L476JG.json @@ -1954,7 +1954,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2042,7 +2042,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476ME.json b/data/chips/STM32L476ME.json index 7d22908..252981a 100644 --- a/data/chips/STM32L476ME.json +++ b/data/chips/STM32L476ME.json @@ -1968,7 +1968,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2056,7 +2056,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476MG.json b/data/chips/STM32L476MG.json index 71bb39d..cb59592 100644 --- a/data/chips/STM32L476MG.json +++ b/data/chips/STM32L476MG.json @@ -1979,7 +1979,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2067,7 +2067,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476QE.json b/data/chips/STM32L476QE.json index 9ced9c5..67b3e74 100644 --- a/data/chips/STM32L476QE.json +++ b/data/chips/STM32L476QE.json @@ -2528,7 +2528,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2621,7 +2621,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476QG.json b/data/chips/STM32L476QG.json index b740503..1433f70 100644 --- a/data/chips/STM32L476QG.json +++ b/data/chips/STM32L476QG.json @@ -2543,7 +2543,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2636,7 +2636,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476RC.json b/data/chips/STM32L476RC.json index b7a9ca8..97964e0 100644 --- a/data/chips/STM32L476RC.json +++ b/data/chips/STM32L476RC.json @@ -1923,7 +1923,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1996,7 +1996,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476RE.json b/data/chips/STM32L476RE.json index 41fd280..2fae658 100644 --- a/data/chips/STM32L476RE.json +++ b/data/chips/STM32L476RE.json @@ -1923,7 +1923,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -1996,7 +1996,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476RG.json b/data/chips/STM32L476RG.json index 714992a..d20ac7c 100644 --- a/data/chips/STM32L476RG.json +++ b/data/chips/STM32L476RG.json @@ -1934,7 +1934,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2007,7 +2007,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476VC.json b/data/chips/STM32L476VC.json index ce92dc8..55575a1 100644 --- a/data/chips/STM32L476VC.json +++ b/data/chips/STM32L476VC.json @@ -2376,7 +2376,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2469,7 +2469,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476VE.json b/data/chips/STM32L476VE.json index eec2878..7a84331 100644 --- a/data/chips/STM32L476VE.json +++ b/data/chips/STM32L476VE.json @@ -2376,7 +2376,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2469,7 +2469,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476VG.json b/data/chips/STM32L476VG.json index f55a71e..915fc97 100644 --- a/data/chips/STM32L476VG.json +++ b/data/chips/STM32L476VG.json @@ -2391,7 +2391,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2484,7 +2484,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476ZE.json b/data/chips/STM32L476ZE.json index 223861a..2df48cc 100644 --- a/data/chips/STM32L476ZE.json +++ b/data/chips/STM32L476ZE.json @@ -2548,7 +2548,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2641,7 +2641,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L476ZG.json b/data/chips/STM32L476ZG.json index 344b4c0..72212f4 100644 --- a/data/chips/STM32L476ZG.json +++ b/data/chips/STM32L476ZG.json @@ -2573,7 +2573,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2666,7 +2666,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L486JG.json b/data/chips/STM32L486JG.json index 24e8259..aeaee72 100644 --- a/data/chips/STM32L486JG.json +++ b/data/chips/STM32L486JG.json @@ -1993,7 +1993,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2081,7 +2081,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L486QG.json b/data/chips/STM32L486QG.json index b3261f2..da854a3 100644 --- a/data/chips/STM32L486QG.json +++ b/data/chips/STM32L486QG.json @@ -2588,7 +2588,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2681,7 +2681,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L486RG.json b/data/chips/STM32L486RG.json index b4328c4..c77c82f 100644 --- a/data/chips/STM32L486RG.json +++ b/data/chips/STM32L486RG.json @@ -1983,7 +1983,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2056,7 +2056,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L486VG.json b/data/chips/STM32L486VG.json index 88e27d0..ada9683 100644 --- a/data/chips/STM32L486VG.json +++ b/data/chips/STM32L486VG.json @@ -2406,7 +2406,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2479,7 +2479,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L486ZG.json b/data/chips/STM32L486ZG.json index 38e1b73..8c55966 100644 --- a/data/chips/STM32L486ZG.json +++ b/data/chips/STM32L486ZG.json @@ -2608,7 +2608,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2701,7 +2701,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496AE.json b/data/chips/STM32L496AE.json index b35b08b..9101917 100644 --- a/data/chips/STM32L496AE.json +++ b/data/chips/STM32L496AE.json @@ -3123,7 +3123,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3221,7 +3221,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496AG.json b/data/chips/STM32L496AG.json index ee0daa6..64531b6 100644 --- a/data/chips/STM32L496AG.json +++ b/data/chips/STM32L496AG.json @@ -3144,7 +3144,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3242,7 +3242,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496QE.json b/data/chips/STM32L496QE.json index f39fe88..04938c7 100644 --- a/data/chips/STM32L496QE.json +++ b/data/chips/STM32L496QE.json @@ -2979,7 +2979,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3077,7 +3077,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496QG.json b/data/chips/STM32L496QG.json index 0aa0ab8..2c3d262 100644 --- a/data/chips/STM32L496QG.json +++ b/data/chips/STM32L496QG.json @@ -2998,7 +2998,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3096,7 +3096,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496RE.json b/data/chips/STM32L496RE.json index a290dff..75af341 100644 --- a/data/chips/STM32L496RE.json +++ b/data/chips/STM32L496RE.json @@ -2295,7 +2295,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2373,7 +2373,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496RG.json b/data/chips/STM32L496RG.json index 6cd37ef..8d30103 100644 --- a/data/chips/STM32L496RG.json +++ b/data/chips/STM32L496RG.json @@ -2310,7 +2310,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2388,7 +2388,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496VE.json b/data/chips/STM32L496VE.json index 8005829..e6fd36a 100644 --- a/data/chips/STM32L496VE.json +++ b/data/chips/STM32L496VE.json @@ -2777,7 +2777,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2870,7 +2870,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496VG.json b/data/chips/STM32L496VG.json index 4b070ba..35514e9 100644 --- a/data/chips/STM32L496VG.json +++ b/data/chips/STM32L496VG.json @@ -2806,7 +2806,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2899,7 +2899,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496WG.json b/data/chips/STM32L496WG.json index e95dd92..00258a5 100644 --- a/data/chips/STM32L496WG.json +++ b/data/chips/STM32L496WG.json @@ -2992,7 +2992,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3085,7 +3085,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496ZE.json b/data/chips/STM32L496ZE.json index 9d8f801..99397fe 100644 --- a/data/chips/STM32L496ZE.json +++ b/data/chips/STM32L496ZE.json @@ -3004,7 +3004,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3102,7 +3102,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L496ZG.json b/data/chips/STM32L496ZG.json index a2d16f3..ed3ff62 100644 --- a/data/chips/STM32L496ZG.json +++ b/data/chips/STM32L496ZG.json @@ -3025,7 +3025,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3123,7 +3123,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4A6AG.json b/data/chips/STM32L4A6AG.json index f54352c..d84cbf0 100644 --- a/data/chips/STM32L4A6AG.json +++ b/data/chips/STM32L4A6AG.json @@ -3221,7 +3221,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3319,7 +3319,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4A6QG.json b/data/chips/STM32L4A6QG.json index 7b5f013..fcb9ad9 100644 --- a/data/chips/STM32L4A6QG.json +++ b/data/chips/STM32L4A6QG.json @@ -3077,7 +3077,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3175,7 +3175,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4A6RG.json b/data/chips/STM32L4A6RG.json index e561299..1e75185 100644 --- a/data/chips/STM32L4A6RG.json +++ b/data/chips/STM32L4A6RG.json @@ -2393,7 +2393,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2471,7 +2471,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4A6VG.json b/data/chips/STM32L4A6VG.json index 67375fd..ee1ccd1 100644 --- a/data/chips/STM32L4A6VG.json +++ b/data/chips/STM32L4A6VG.json @@ -2883,7 +2883,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -2976,7 +2976,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4A6ZG.json b/data/chips/STM32L4A6ZG.json index 912aeb0..77ee1e8 100644 --- a/data/chips/STM32L4A6ZG.json +++ b/data/chips/STM32L4A6ZG.json @@ -3102,7 +3102,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { @@ -3200,7 +3200,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5AE.json b/data/chips/STM32L4P5AE.json index d161ae6..199d8a7 100644 --- a/data/chips/STM32L4P5AE.json +++ b/data/chips/STM32L4P5AE.json @@ -2630,7 +2630,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2728,7 +2728,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5AG.json b/data/chips/STM32L4P5AG.json index 7a0c067..1db9945 100644 --- a/data/chips/STM32L4P5AG.json +++ b/data/chips/STM32L4P5AG.json @@ -2634,7 +2634,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2732,7 +2732,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5CE.json b/data/chips/STM32L4P5CE.json index 0325468..03ef4b0 100644 --- a/data/chips/STM32L4P5CE.json +++ b/data/chips/STM32L4P5CE.json @@ -1685,7 +1685,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1743,7 +1743,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5CG.json b/data/chips/STM32L4P5CG.json index 2b8a2ee..1765a85 100644 --- a/data/chips/STM32L4P5CG.json +++ b/data/chips/STM32L4P5CG.json @@ -1693,7 +1693,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1751,7 +1751,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5QE.json b/data/chips/STM32L4P5QE.json index da882b1..cb53767 100644 --- a/data/chips/STM32L4P5QE.json +++ b/data/chips/STM32L4P5QE.json @@ -2485,7 +2485,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2583,7 +2583,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5QG.json b/data/chips/STM32L4P5QG.json index 5e4809a..1707cc6 100644 --- a/data/chips/STM32L4P5QG.json +++ b/data/chips/STM32L4P5QG.json @@ -2493,7 +2493,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2591,7 +2591,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5RE.json b/data/chips/STM32L4P5RE.json index b376dec..c8ee40a 100644 --- a/data/chips/STM32L4P5RE.json +++ b/data/chips/STM32L4P5RE.json @@ -1903,7 +1903,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1981,7 +1981,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5RG.json b/data/chips/STM32L4P5RG.json index 7e0dfb1..025a626 100644 --- a/data/chips/STM32L4P5RG.json +++ b/data/chips/STM32L4P5RG.json @@ -1907,7 +1907,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1985,7 +1985,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5VE.json b/data/chips/STM32L4P5VE.json index 8b248b3..a30e426 100644 --- a/data/chips/STM32L4P5VE.json +++ b/data/chips/STM32L4P5VE.json @@ -2319,7 +2319,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2412,7 +2412,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5VG.json b/data/chips/STM32L4P5VG.json index 0c12a0c..60a0e05 100644 --- a/data/chips/STM32L4P5VG.json +++ b/data/chips/STM32L4P5VG.json @@ -2327,7 +2327,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2420,7 +2420,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5ZE.json b/data/chips/STM32L4P5ZE.json index 679b19d..28f968f 100644 --- a/data/chips/STM32L4P5ZE.json +++ b/data/chips/STM32L4P5ZE.json @@ -2495,7 +2495,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2593,7 +2593,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4P5ZG.json b/data/chips/STM32L4P5ZG.json index 4365c79..c3bf04c 100644 --- a/data/chips/STM32L4P5ZG.json +++ b/data/chips/STM32L4P5ZG.json @@ -2499,7 +2499,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2597,7 +2597,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5AG.json b/data/chips/STM32L4Q5AG.json index 7071769..8d4afa8 100644 --- a/data/chips/STM32L4Q5AG.json +++ b/data/chips/STM32L4Q5AG.json @@ -2673,7 +2673,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2771,7 +2771,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5CG.json b/data/chips/STM32L4Q5CG.json index c6e2c7e..6d2ff1e 100644 --- a/data/chips/STM32L4Q5CG.json +++ b/data/chips/STM32L4Q5CG.json @@ -1732,7 +1732,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1790,7 +1790,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5QG.json b/data/chips/STM32L4Q5QG.json index a0355f9..76c3407 100644 --- a/data/chips/STM32L4Q5QG.json +++ b/data/chips/STM32L4Q5QG.json @@ -2528,7 +2528,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2626,7 +2626,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5RG.json b/data/chips/STM32L4Q5RG.json index d051f7b..1e6a375 100644 --- a/data/chips/STM32L4Q5RG.json +++ b/data/chips/STM32L4Q5RG.json @@ -1946,7 +1946,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2024,7 +2024,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5VG.json b/data/chips/STM32L4Q5VG.json index 2f7de38..8ad6327 100644 --- a/data/chips/STM32L4Q5VG.json +++ b/data/chips/STM32L4Q5VG.json @@ -2366,7 +2366,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2459,7 +2459,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4Q5ZG.json b/data/chips/STM32L4Q5ZG.json index b235cbe..f700719 100644 --- a/data/chips/STM32L4Q5ZG.json +++ b/data/chips/STM32L4Q5ZG.json @@ -2538,7 +2538,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2636,7 +2636,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5AG.json b/data/chips/STM32L4R5AG.json index 857b534..51308b4 100644 --- a/data/chips/STM32L4R5AG.json +++ b/data/chips/STM32L4R5AG.json @@ -2592,7 +2592,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2690,7 +2690,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5AI.json b/data/chips/STM32L4R5AI.json index f09da11..e2124d5 100644 --- a/data/chips/STM32L4R5AI.json +++ b/data/chips/STM32L4R5AI.json @@ -2596,7 +2596,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2694,7 +2694,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5QG.json b/data/chips/STM32L4R5QG.json index e79ddf0..93b8371 100644 --- a/data/chips/STM32L4R5QG.json +++ b/data/chips/STM32L4R5QG.json @@ -2451,7 +2451,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2549,7 +2549,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5QI.json b/data/chips/STM32L4R5QI.json index e483ff7..c78f2f4 100644 --- a/data/chips/STM32L4R5QI.json +++ b/data/chips/STM32L4R5QI.json @@ -2451,7 +2451,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2549,7 +2549,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5VG.json b/data/chips/STM32L4R5VG.json index 4cbe56a..cc2c20e 100644 --- a/data/chips/STM32L4R5VG.json +++ b/data/chips/STM32L4R5VG.json @@ -2247,7 +2247,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2325,7 +2325,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5VI.json b/data/chips/STM32L4R5VI.json index 8f53128..81b77bf 100644 --- a/data/chips/STM32L4R5VI.json +++ b/data/chips/STM32L4R5VI.json @@ -2247,7 +2247,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2325,7 +2325,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5ZG.json b/data/chips/STM32L4R5ZG.json index addaa52..172fbb3 100644 --- a/data/chips/STM32L4R5ZG.json +++ b/data/chips/STM32L4R5ZG.json @@ -2461,7 +2461,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2559,7 +2559,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R5ZI.json b/data/chips/STM32L4R5ZI.json index 1a6ccfe..d831474 100644 --- a/data/chips/STM32L4R5ZI.json +++ b/data/chips/STM32L4R5ZI.json @@ -2471,7 +2471,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2569,7 +2569,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R7AI.json b/data/chips/STM32L4R7AI.json index b782c8e..34b40f8 100644 --- a/data/chips/STM32L4R7AI.json +++ b/data/chips/STM32L4R7AI.json @@ -2619,7 +2619,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2717,7 +2717,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R7VI.json b/data/chips/STM32L4R7VI.json index 8b81c57..ff0a9d0 100644 --- a/data/chips/STM32L4R7VI.json +++ b/data/chips/STM32L4R7VI.json @@ -2274,7 +2274,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2352,7 +2352,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R7ZI.json b/data/chips/STM32L4R7ZI.json index 3660fc1..1e2b596 100644 --- a/data/chips/STM32L4R7ZI.json +++ b/data/chips/STM32L4R7ZI.json @@ -2484,7 +2484,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2582,7 +2582,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9AG.json b/data/chips/STM32L4R9AG.json index bee84f1..06dc74b 100644 --- a/data/chips/STM32L4R9AG.json +++ b/data/chips/STM32L4R9AG.json @@ -2582,7 +2582,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2680,7 +2680,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9AI.json b/data/chips/STM32L4R9AI.json index 7e17353..1c19b01 100644 --- a/data/chips/STM32L4R9AI.json +++ b/data/chips/STM32L4R9AI.json @@ -2582,7 +2582,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2680,7 +2680,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9VG.json b/data/chips/STM32L4R9VG.json index c699a68..11fef68 100644 --- a/data/chips/STM32L4R9VG.json +++ b/data/chips/STM32L4R9VG.json @@ -2209,7 +2209,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2287,7 +2287,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9VI.json b/data/chips/STM32L4R9VI.json index 8af6085..049c9d4 100644 --- a/data/chips/STM32L4R9VI.json +++ b/data/chips/STM32L4R9VI.json @@ -2209,7 +2209,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2287,7 +2287,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9ZG.json b/data/chips/STM32L4R9ZG.json index ff03e55..9898291 100644 --- a/data/chips/STM32L4R9ZG.json +++ b/data/chips/STM32L4R9ZG.json @@ -2488,7 +2488,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2586,7 +2586,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4R9ZI.json b/data/chips/STM32L4R9ZI.json index 27e19c7..ecc7a39 100644 --- a/data/chips/STM32L4R9ZI.json +++ b/data/chips/STM32L4R9ZI.json @@ -2498,7 +2498,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2596,7 +2596,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S5AI.json b/data/chips/STM32L4S5AI.json index bb5ad20..6322b7f 100644 --- a/data/chips/STM32L4S5AI.json +++ b/data/chips/STM32L4S5AI.json @@ -2665,7 +2665,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2763,7 +2763,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S5QI.json b/data/chips/STM32L4S5QI.json index 9c9a224..4dc3085 100644 --- a/data/chips/STM32L4S5QI.json +++ b/data/chips/STM32L4S5QI.json @@ -2520,7 +2520,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2618,7 +2618,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S5VI.json b/data/chips/STM32L4S5VI.json index 47f6dd5..236ce3e 100644 --- a/data/chips/STM32L4S5VI.json +++ b/data/chips/STM32L4S5VI.json @@ -2320,7 +2320,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2398,7 +2398,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S5ZI.json b/data/chips/STM32L4S5ZI.json index a0f231e..d59cf88 100644 --- a/data/chips/STM32L4S5ZI.json +++ b/data/chips/STM32L4S5ZI.json @@ -2534,7 +2534,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2632,7 +2632,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S7AI.json b/data/chips/STM32L4S7AI.json index 879a681..045c593 100644 --- a/data/chips/STM32L4S7AI.json +++ b/data/chips/STM32L4S7AI.json @@ -2692,7 +2692,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2790,7 +2790,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S7VI.json b/data/chips/STM32L4S7VI.json index 6b60919..c73b01a 100644 --- a/data/chips/STM32L4S7VI.json +++ b/data/chips/STM32L4S7VI.json @@ -2347,7 +2347,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2425,7 +2425,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S7ZI.json b/data/chips/STM32L4S7ZI.json index 0f23ef7..d5fc37b 100644 --- a/data/chips/STM32L4S7ZI.json +++ b/data/chips/STM32L4S7ZI.json @@ -2557,7 +2557,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2655,7 +2655,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S9AI.json b/data/chips/STM32L4S9AI.json index 5166957..9e2ce4d 100644 --- a/data/chips/STM32L4S9AI.json +++ b/data/chips/STM32L4S9AI.json @@ -2655,7 +2655,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2753,7 +2753,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S9VI.json b/data/chips/STM32L4S9VI.json index 6790a3f..0c74500 100644 --- a/data/chips/STM32L4S9VI.json +++ b/data/chips/STM32L4S9VI.json @@ -2282,7 +2282,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2360,7 +2360,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L4S9ZI.json b/data/chips/STM32L4S9ZI.json index 5b321dd..8fc678c 100644 --- a/data/chips/STM32L4S9ZI.json +++ b/data/chips/STM32L4S9ZI.json @@ -2561,7 +2561,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -2659,7 +2659,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552CC.json b/data/chips/STM32L552CC.json index 2dd0aa8..61541aa 100644 --- a/data/chips/STM32L552CC.json +++ b/data/chips/STM32L552CC.json @@ -1445,7 +1445,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1500,7 +1500,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1550,7 +1550,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552CE.json b/data/chips/STM32L552CE.json index a3c0d44..79d4d22 100644 --- a/data/chips/STM32L552CE.json +++ b/data/chips/STM32L552CE.json @@ -1453,7 +1453,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1508,7 +1508,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1558,7 +1558,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552ME.json b/data/chips/STM32L552ME.json index efbe5ff..cc7cf7f 100644 --- a/data/chips/STM32L552ME.json +++ b/data/chips/STM32L552ME.json @@ -1514,7 +1514,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1609,7 +1609,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1669,7 +1669,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552QC.json b/data/chips/STM32L552QC.json index d86558c..70dc76f 100644 --- a/data/chips/STM32L552QC.json +++ b/data/chips/STM32L552QC.json @@ -1984,7 +1984,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2079,7 +2079,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2154,7 +2154,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552QE.json b/data/chips/STM32L552QE.json index 6844408..ad2c749 100644 --- a/data/chips/STM32L552QE.json +++ b/data/chips/STM32L552QE.json @@ -1992,7 +1992,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2087,7 +2087,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2162,7 +2162,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552RC.json b/data/chips/STM32L552RC.json index 4229ebe..42341ad 100644 --- a/data/chips/STM32L552RC.json +++ b/data/chips/STM32L552RC.json @@ -1507,7 +1507,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1582,7 +1582,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1642,7 +1642,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552RE.json b/data/chips/STM32L552RE.json index 7b9a19b..01d4d08 100644 --- a/data/chips/STM32L552RE.json +++ b/data/chips/STM32L552RE.json @@ -1515,7 +1515,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1590,7 +1590,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1650,7 +1650,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552VC.json b/data/chips/STM32L552VC.json index 5a073e7..93840e1 100644 --- a/data/chips/STM32L552VC.json +++ b/data/chips/STM32L552VC.json @@ -1809,7 +1809,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1884,7 +1884,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1959,7 +1959,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552VE.json b/data/chips/STM32L552VE.json index 215f9b4..ea9d8be 100644 --- a/data/chips/STM32L552VE.json +++ b/data/chips/STM32L552VE.json @@ -1813,7 +1813,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1888,7 +1888,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1963,7 +1963,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552ZC.json b/data/chips/STM32L552ZC.json index 1bb35e9..3a851a6 100644 --- a/data/chips/STM32L552ZC.json +++ b/data/chips/STM32L552ZC.json @@ -1984,7 +1984,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2079,7 +2079,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2154,7 +2154,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552ZE.json b/data/chips/STM32L552ZE.json index d325df9..e881675 100644 --- a/data/chips/STM32L552ZE.json +++ b/data/chips/STM32L552ZE.json @@ -1988,7 +1988,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2083,7 +2083,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2158,7 +2158,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index 48f8a4a..b639923 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -1492,7 +1492,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1547,7 +1547,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1597,7 +1597,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index b3fe12a..3a33eb9 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -1553,7 +1553,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1648,7 +1648,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1708,7 +1708,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index 65fbbb0..6c8bf6e 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -2031,7 +2031,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2126,7 +2126,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2201,7 +2201,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index 6f8f7b6..7a10cd7 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -1554,7 +1554,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1629,7 +1629,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1689,7 +1689,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index 3c7d829..eac6480 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -1852,7 +1852,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1927,7 +1927,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2002,7 +2002,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index c9cdfb2..d4b29d0 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -2027,7 +2027,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2122,7 +2122,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -2197,7 +2197,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031C6.json b/data/chips/STM32U031C6.json index 590d02d..4219f7e 100644 --- a/data/chips/STM32U031C6.json +++ b/data/chips/STM32U031C6.json @@ -762,7 +762,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -877,7 +877,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031C8.json b/data/chips/STM32U031C8.json index e3e122f..abb7c61 100644 --- a/data/chips/STM32U031C8.json +++ b/data/chips/STM32U031C8.json @@ -762,7 +762,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -877,7 +877,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031F4.json b/data/chips/STM32U031F4.json index 117db70..9b5fa60 100644 --- a/data/chips/STM32U031F4.json +++ b/data/chips/STM32U031F4.json @@ -719,7 +719,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -819,7 +819,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031F6.json b/data/chips/STM32U031F6.json index 27768d4..73d0554 100644 --- a/data/chips/STM32U031F6.json +++ b/data/chips/STM32U031F6.json @@ -719,7 +719,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -819,7 +819,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031F8.json b/data/chips/STM32U031F8.json index 95cc607..9b9173a 100644 --- a/data/chips/STM32U031F8.json +++ b/data/chips/STM32U031F8.json @@ -719,7 +719,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -819,7 +819,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031G6.json b/data/chips/STM32U031G6.json index 1843d8a..792b1b9 100644 --- a/data/chips/STM32U031G6.json +++ b/data/chips/STM32U031G6.json @@ -689,7 +689,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -774,7 +774,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031G8.json b/data/chips/STM32U031G8.json index 01dd54d..ebc1386 100644 --- a/data/chips/STM32U031G8.json +++ b/data/chips/STM32U031G8.json @@ -689,7 +689,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -774,7 +774,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031K4.json b/data/chips/STM32U031K4.json index 594b714..6534306 100644 --- a/data/chips/STM32U031K4.json +++ b/data/chips/STM32U031K4.json @@ -709,7 +709,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -804,7 +804,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031K6.json b/data/chips/STM32U031K6.json index 3e9f997..4d31e6a 100644 --- a/data/chips/STM32U031K6.json +++ b/data/chips/STM32U031K6.json @@ -709,7 +709,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -804,7 +804,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031K8.json b/data/chips/STM32U031K8.json index 1173b29..a84f18a 100644 --- a/data/chips/STM32U031K8.json +++ b/data/chips/STM32U031K8.json @@ -709,7 +709,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -804,7 +804,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031R6.json b/data/chips/STM32U031R6.json index a206148..ba828cf 100644 --- a/data/chips/STM32U031R6.json +++ b/data/chips/STM32U031R6.json @@ -808,7 +808,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -943,7 +943,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U031R8.json b/data/chips/STM32U031R8.json index 4f7f5f5..b022c60 100644 --- a/data/chips/STM32U031R8.json +++ b/data/chips/STM32U031R8.json @@ -808,7 +808,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -943,7 +943,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073C8.json b/data/chips/STM32U073C8.json index 0beee34..8ab8836 100644 --- a/data/chips/STM32U073C8.json +++ b/data/chips/STM32U073C8.json @@ -1158,7 +1158,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1273,7 +1273,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1348,7 +1348,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073CB.json b/data/chips/STM32U073CB.json index 1609657..44e7d4b 100644 --- a/data/chips/STM32U073CB.json +++ b/data/chips/STM32U073CB.json @@ -1158,7 +1158,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1273,7 +1273,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1348,7 +1348,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073CC.json b/data/chips/STM32U073CC.json index 1e3d8a1..80852e2 100644 --- a/data/chips/STM32U073CC.json +++ b/data/chips/STM32U073CC.json @@ -1158,7 +1158,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1273,7 +1273,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1348,7 +1348,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073H8.json b/data/chips/STM32U073H8.json index 2b8e23c..7e3852e 100644 --- a/data/chips/STM32U073H8.json +++ b/data/chips/STM32U073H8.json @@ -1089,7 +1089,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1199,7 +1199,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1274,7 +1274,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073HB.json b/data/chips/STM32U073HB.json index e0f5ae2..2518831 100644 --- a/data/chips/STM32U073HB.json +++ b/data/chips/STM32U073HB.json @@ -1089,7 +1089,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1199,7 +1199,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1274,7 +1274,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073HC.json b/data/chips/STM32U073HC.json index e996fd2..def1c83 100644 --- a/data/chips/STM32U073HC.json +++ b/data/chips/STM32U073HC.json @@ -1089,7 +1089,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1199,7 +1199,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1274,7 +1274,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073K8.json b/data/chips/STM32U073K8.json index cf03d77..e01b62e 100644 --- a/data/chips/STM32U073K8.json +++ b/data/chips/STM32U073K8.json @@ -1050,7 +1050,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1145,7 +1145,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1220,7 +1220,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073KB.json b/data/chips/STM32U073KB.json index f83bf2d..56afcaf 100644 --- a/data/chips/STM32U073KB.json +++ b/data/chips/STM32U073KB.json @@ -1050,7 +1050,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1145,7 +1145,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1220,7 +1220,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073KC.json b/data/chips/STM32U073KC.json index 94c96ce..29f4e46 100644 --- a/data/chips/STM32U073KC.json +++ b/data/chips/STM32U073KC.json @@ -1050,7 +1050,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1145,7 +1145,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1220,7 +1220,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073M8.json b/data/chips/STM32U073M8.json index 6ce7c9c..04e9777 100644 --- a/data/chips/STM32U073M8.json +++ b/data/chips/STM32U073M8.json @@ -1423,7 +1423,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1573,7 +1573,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1683,7 +1683,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073MB.json b/data/chips/STM32U073MB.json index 6a14049..b5afed4 100644 --- a/data/chips/STM32U073MB.json +++ b/data/chips/STM32U073MB.json @@ -1423,7 +1423,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1573,7 +1573,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1683,7 +1683,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073MC.json b/data/chips/STM32U073MC.json index f4560e5..864ca37 100644 --- a/data/chips/STM32U073MC.json +++ b/data/chips/STM32U073MC.json @@ -1423,7 +1423,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1573,7 +1573,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1683,7 +1683,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073R8.json b/data/chips/STM32U073R8.json index 958d797..2c7a41a 100644 --- a/data/chips/STM32U073R8.json +++ b/data/chips/STM32U073R8.json @@ -1334,7 +1334,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1469,7 +1469,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1559,7 +1559,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073RB.json b/data/chips/STM32U073RB.json index 51d51ba..c3119d8 100644 --- a/data/chips/STM32U073RB.json +++ b/data/chips/STM32U073RB.json @@ -1334,7 +1334,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1469,7 +1469,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1559,7 +1559,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U073RC.json b/data/chips/STM32U073RC.json index 5b6a8de..79ac006 100644 --- a/data/chips/STM32U073RC.json +++ b/data/chips/STM32U073RC.json @@ -1334,7 +1334,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1469,7 +1469,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1559,7 +1559,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U083CC.json b/data/chips/STM32U083CC.json index e711825..3b0e765 100644 --- a/data/chips/STM32U083CC.json +++ b/data/chips/STM32U083CC.json @@ -1186,7 +1186,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1301,7 +1301,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1376,7 +1376,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U083HC.json b/data/chips/STM32U083HC.json index 74bdd0a..866504a 100644 --- a/data/chips/STM32U083HC.json +++ b/data/chips/STM32U083HC.json @@ -1117,7 +1117,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1227,7 +1227,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1302,7 +1302,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U083KC.json b/data/chips/STM32U083KC.json index 6233ca4..6a929be 100644 --- a/data/chips/STM32U083KC.json +++ b/data/chips/STM32U083KC.json @@ -1078,7 +1078,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1173,7 +1173,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1248,7 +1248,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U083MC.json b/data/chips/STM32U083MC.json index 39c078a..fd5b239 100644 --- a/data/chips/STM32U083MC.json +++ b/data/chips/STM32U083MC.json @@ -1451,7 +1451,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1601,7 +1601,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1711,7 +1711,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U083RC.json b/data/chips/STM32U083RC.json index d6f2e54..df90016 100644 --- a/data/chips/STM32U083RC.json +++ b/data/chips/STM32U083RC.json @@ -1362,7 +1362,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1497,7 +1497,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { @@ -1587,7 +1587,7 @@ "address": 1073778688, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index e5cf669..2eaa874 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -1334,7 +1334,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1424,7 +1424,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1509,7 +1509,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1581,7 +1581,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index 7be787d..d3f4ef9 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -1334,7 +1334,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1424,7 +1424,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1509,7 +1509,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1581,7 +1581,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index 0bb9aca..7ae84fe 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -1334,7 +1334,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1424,7 +1424,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1509,7 +1509,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1581,7 +1581,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index a58bb64..f93826a 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -1350,7 +1350,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1470,7 +1470,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1555,7 +1555,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1627,7 +1627,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index 73d7008..36b3306 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -1307,7 +1307,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1397,7 +1397,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1482,7 +1482,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1549,7 +1549,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index 104e8b2..91393cd 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -1307,7 +1307,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1397,7 +1397,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1482,7 +1482,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1549,7 +1549,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index 1f79016..c0a3b71 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -1410,7 +1410,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1520,7 +1520,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1620,7 +1620,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1717,7 +1717,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index 4ccff52..a4aeff1 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -1410,7 +1410,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1520,7 +1520,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1620,7 +1620,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1717,7 +1717,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index a40e182..fd9c5ce 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -1410,7 +1410,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1520,7 +1520,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1620,7 +1620,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1717,7 +1717,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index f132ab3..7ab2308 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -1643,7 +1643,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1753,7 +1753,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1878,7 +1878,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1995,7 +1995,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index 9512ed8..f4621df 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -1643,7 +1643,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1753,7 +1753,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1878,7 +1878,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1995,7 +1995,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index 7d2d446..6d6d26b 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -1373,7 +1373,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1463,7 +1463,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1548,7 +1548,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1620,7 +1620,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index c415279..31fdf31 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -1389,7 +1389,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1509,7 +1509,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1594,7 +1594,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1666,7 +1666,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 017f858..32addf5 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -1346,7 +1346,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1436,7 +1436,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1521,7 +1521,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1588,7 +1588,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index 17f4386..bf2b708 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -1449,7 +1449,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1559,7 +1559,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1659,7 +1659,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1756,7 +1756,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index 4745609..1516be3 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -1682,7 +1682,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1792,7 +1792,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1917,7 +1917,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2034,7 +2034,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575AG.json b/data/chips/STM32U575AG.json index 2ed2cf2..44d9a5b 100644 --- a/data/chips/STM32U575AG.json +++ b/data/chips/STM32U575AG.json @@ -2738,7 +2738,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2873,7 +2873,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2998,7 +2998,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3135,7 +3135,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575AI.json b/data/chips/STM32U575AI.json index 1addbe8..697c88b 100644 --- a/data/chips/STM32U575AI.json +++ b/data/chips/STM32U575AI.json @@ -2738,7 +2738,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2873,7 +2873,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2998,7 +2998,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3135,7 +3135,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575CG.json b/data/chips/STM32U575CG.json index 4e311c2..a67e01e 100644 --- a/data/chips/STM32U575CG.json +++ b/data/chips/STM32U575CG.json @@ -1809,7 +1809,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1899,7 +1899,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1984,7 +1984,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2056,7 +2056,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575CI.json b/data/chips/STM32U575CI.json index 012003f..41b4964 100644 --- a/data/chips/STM32U575CI.json +++ b/data/chips/STM32U575CI.json @@ -1809,7 +1809,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1899,7 +1899,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1984,7 +1984,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2056,7 +2056,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575OG.json b/data/chips/STM32U575OG.json index 6cb5d29..5eaf2da 100644 --- a/data/chips/STM32U575OG.json +++ b/data/chips/STM32U575OG.json @@ -2194,7 +2194,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2324,7 +2324,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2424,7 +2424,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2531,7 +2531,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575OI.json b/data/chips/STM32U575OI.json index 8d05541..9b93e5d 100644 --- a/data/chips/STM32U575OI.json +++ b/data/chips/STM32U575OI.json @@ -2194,7 +2194,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2324,7 +2324,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2424,7 +2424,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2531,7 +2531,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575QG.json b/data/chips/STM32U575QG.json index 2a0dddd..a811b91 100644 --- a/data/chips/STM32U575QG.json +++ b/data/chips/STM32U575QG.json @@ -2588,7 +2588,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2723,7 +2723,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2848,7 +2848,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2985,7 +2985,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575QI.json b/data/chips/STM32U575QI.json index 5ce9f1c..ea31d91 100644 --- a/data/chips/STM32U575QI.json +++ b/data/chips/STM32U575QI.json @@ -2588,7 +2588,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2723,7 +2723,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2848,7 +2848,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2985,7 +2985,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575RG.json b/data/chips/STM32U575RG.json index ad3b08b..05c5b28 100644 --- a/data/chips/STM32U575RG.json +++ b/data/chips/STM32U575RG.json @@ -2008,7 +2008,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2118,7 +2118,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2218,7 +2218,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2315,7 +2315,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575RI.json b/data/chips/STM32U575RI.json index 74192d0..eb38a9a 100644 --- a/data/chips/STM32U575RI.json +++ b/data/chips/STM32U575RI.json @@ -2008,7 +2008,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2118,7 +2118,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2218,7 +2218,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2315,7 +2315,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575VG.json b/data/chips/STM32U575VG.json index a9b43f5..2f22eee 100644 --- a/data/chips/STM32U575VG.json +++ b/data/chips/STM32U575VG.json @@ -2387,7 +2387,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2497,7 +2497,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2622,7 +2622,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2739,7 +2739,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575VI.json b/data/chips/STM32U575VI.json index 262967d..38de410 100644 --- a/data/chips/STM32U575VI.json +++ b/data/chips/STM32U575VI.json @@ -2387,7 +2387,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2497,7 +2497,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2622,7 +2622,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2739,7 +2739,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575ZG.json b/data/chips/STM32U575ZG.json index e72115d..1fba183 100644 --- a/data/chips/STM32U575ZG.json +++ b/data/chips/STM32U575ZG.json @@ -2608,7 +2608,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2743,7 +2743,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2868,7 +2868,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3005,7 +3005,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U575ZI.json b/data/chips/STM32U575ZI.json index a169785..24f95dc 100644 --- a/data/chips/STM32U575ZI.json +++ b/data/chips/STM32U575ZI.json @@ -2608,7 +2608,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2743,7 +2743,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2868,7 +2868,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3005,7 +3005,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index b156dfe..18b4628 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -2783,7 +2783,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2918,7 +2918,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3043,7 +3043,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3180,7 +3180,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index 0f0cf65..04171f3 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -1854,7 +1854,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1944,7 +1944,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2029,7 +2029,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2101,7 +2101,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index 8220a91..09f62f4 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -2239,7 +2239,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2369,7 +2369,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2469,7 +2469,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2576,7 +2576,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index cc86ee6..dc9532e 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -2633,7 +2633,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2768,7 +2768,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2893,7 +2893,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3030,7 +3030,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index 1731366..6972853 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -2053,7 +2053,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2163,7 +2163,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2263,7 +2263,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2360,7 +2360,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index b2d1f8b..e0da1a9 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -2432,7 +2432,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2542,7 +2542,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2667,7 +2667,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2784,7 +2784,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index 2307499..8777ccd 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -2653,7 +2653,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2788,7 +2788,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2913,7 +2913,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3050,7 +3050,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index af34027..68b0785 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -2645,7 +2645,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2780,7 +2780,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2905,7 +2905,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3042,7 +3042,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index ac3a00c..f3ca162 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -2645,7 +2645,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2780,7 +2780,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2905,7 +2905,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3042,7 +3042,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index 9d4fd65..35ed89d 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -2480,7 +2480,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2615,7 +2615,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2740,7 +2740,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2877,7 +2877,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index 5655ef5..934c07c 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -2480,7 +2480,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2615,7 +2615,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2740,7 +2740,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2877,7 +2877,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index 0f943ee..8964687 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -1763,7 +1763,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1873,7 +1873,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1973,7 +1973,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2070,7 +2070,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index e635bcd..510aa70 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -1763,7 +1763,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1873,7 +1873,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1973,7 +1973,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2070,7 +2070,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index 8394320..1ecbd80 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -2259,7 +2259,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2369,7 +2369,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2494,7 +2494,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2611,7 +2611,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index d56baf2..bbc961c 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -2259,7 +2259,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2369,7 +2369,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2494,7 +2494,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2611,7 +2611,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index da6c5f9..1d1183f 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -2504,7 +2504,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2639,7 +2639,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2764,7 +2764,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2901,7 +2901,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index 7c3f3cb..f0dd5c6 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -2504,7 +2504,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2639,7 +2639,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2764,7 +2764,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2901,7 +2901,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index 51b1dd1..ff4640f 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -2850,7 +2850,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2985,7 +2985,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3110,7 +3110,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3247,7 +3247,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index 8b587fb..b5607af 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -2875,7 +2875,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3010,7 +3010,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3135,7 +3135,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3272,7 +3272,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index 0f2e3ec..f9f7387 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -2875,7 +2875,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3010,7 +3010,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3135,7 +3135,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3272,7 +3272,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index ad10f81..a6d13f3 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -2270,7 +2270,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2380,7 +2380,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2505,7 +2505,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2622,7 +2622,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index 856e5c5..ed0f949 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -2331,7 +2331,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2441,7 +2441,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2566,7 +2566,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2683,7 +2683,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index 3663853..0ead86c 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -2572,7 +2572,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2702,7 +2702,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2827,7 +2827,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2964,7 +2964,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index 071d677..232892b 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -2572,7 +2572,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2702,7 +2702,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2827,7 +2827,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2964,7 +2964,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index 03a8f27..cc846ba 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -2684,7 +2684,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2819,7 +2819,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2944,7 +2944,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3081,7 +3081,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A5QI.json b/data/chips/STM32U5A5QI.json index b7e0884..a04159a 100644 --- a/data/chips/STM32U5A5QI.json +++ b/data/chips/STM32U5A5QI.json @@ -2485,7 +2485,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2605,7 +2605,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2730,7 +2730,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2867,7 +2867,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index 4cc793b..0f7117e 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -2519,7 +2519,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2654,7 +2654,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2779,7 +2779,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2916,7 +2916,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index 9ba5a88..7f84e44 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -1802,7 +1802,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -1912,7 +1912,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2012,7 +2012,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2109,7 +2109,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index 6369a95..62f2bb0 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -2298,7 +2298,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2408,7 +2408,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2533,7 +2533,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2650,7 +2650,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 841a0d6..64355e6 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -2543,7 +2543,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2678,7 +2678,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2803,7 +2803,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2940,7 +2940,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 5aa67dd..9b64fb5 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -2889,7 +2889,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3024,7 +3024,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3149,7 +3149,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3286,7 +3286,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index 63644c3..2595a0d 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -2914,7 +2914,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3049,7 +3049,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3174,7 +3174,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3311,7 +3311,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 5618ad8..e26ba79 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -2309,7 +2309,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2419,7 +2419,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2544,7 +2544,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2661,7 +2661,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index f60161d..62ffdab 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -2611,7 +2611,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2741,7 +2741,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -2866,7 +2866,7 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -3003,7 +3003,7 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_BASIC" }, "rcc": { diff --git a/data/chips/STM32WB10CC.json b/data/chips/STM32WB10CC.json index 36d15c2..c7be49b 100644 --- a/data/chips/STM32WB10CC.json +++ b/data/chips/STM32WB10CC.json @@ -1114,7 +1114,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1172,7 +1172,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB15CC.json b/data/chips/STM32WB15CC.json index ad1cbe9..3bb9c33 100644 --- a/data/chips/STM32WB15CC.json +++ b/data/chips/STM32WB15CC.json @@ -1180,7 +1180,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1238,7 +1238,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB30CE.json b/data/chips/STM32WB30CE.json index b32ae3e..fa48b4f 100644 --- a/data/chips/STM32WB30CE.json +++ b/data/chips/STM32WB30CE.json @@ -950,7 +950,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1008,7 +1008,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB35CC.json b/data/chips/STM32WB35CC.json index c97e52a..bbc88c6 100644 --- a/data/chips/STM32WB35CC.json +++ b/data/chips/STM32WB35CC.json @@ -1249,7 +1249,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1307,7 +1307,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB35CE.json b/data/chips/STM32WB35CE.json index 59e0202..fbee787 100644 --- a/data/chips/STM32WB35CE.json +++ b/data/chips/STM32WB35CE.json @@ -1249,7 +1249,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1307,7 +1307,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB50CG.json b/data/chips/STM32WB50CG.json index 85fe212..07e223c 100644 --- a/data/chips/STM32WB50CG.json +++ b/data/chips/STM32WB50CG.json @@ -950,7 +950,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1008,7 +1008,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55CC.json b/data/chips/STM32WB55CC.json index 0627fcf..441a713 100644 --- a/data/chips/STM32WB55CC.json +++ b/data/chips/STM32WB55CC.json @@ -1399,7 +1399,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1457,7 +1457,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55CE.json b/data/chips/STM32WB55CE.json index 5ee4735..bc87e61 100644 --- a/data/chips/STM32WB55CE.json +++ b/data/chips/STM32WB55CE.json @@ -1399,7 +1399,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1457,7 +1457,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55CG.json b/data/chips/STM32WB55CG.json index bfc7032..52afcec 100644 --- a/data/chips/STM32WB55CG.json +++ b/data/chips/STM32WB55CG.json @@ -1399,7 +1399,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1457,7 +1457,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55RC.json b/data/chips/STM32WB55RC.json index e9dec3f..1293283 100644 --- a/data/chips/STM32WB55RC.json +++ b/data/chips/STM32WB55RC.json @@ -1586,7 +1586,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1664,7 +1664,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55RE.json b/data/chips/STM32WB55RE.json index 59e2a8c..48dd531 100644 --- a/data/chips/STM32WB55RE.json +++ b/data/chips/STM32WB55RE.json @@ -1586,7 +1586,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1664,7 +1664,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55RG.json b/data/chips/STM32WB55RG.json index a891b01..6391759 100644 --- a/data/chips/STM32WB55RG.json +++ b/data/chips/STM32WB55RG.json @@ -1586,7 +1586,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1664,7 +1664,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55VC.json b/data/chips/STM32WB55VC.json index abb5fce..b7f6606 100644 --- a/data/chips/STM32WB55VC.json +++ b/data/chips/STM32WB55VC.json @@ -1680,7 +1680,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1758,7 +1758,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55VE.json b/data/chips/STM32WB55VE.json index 5b13cd0..d88fcc2 100644 --- a/data/chips/STM32WB55VE.json +++ b/data/chips/STM32WB55VE.json @@ -1680,7 +1680,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1758,7 +1758,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55VG.json b/data/chips/STM32WB55VG.json index f8cf8a6..54f4ca7 100644 --- a/data/chips/STM32WB55VG.json +++ b/data/chips/STM32WB55VG.json @@ -1680,7 +1680,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1758,7 +1758,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WB55VY.json b/data/chips/STM32WB55VY.json index a41eef4..37c573b 100644 --- a/data/chips/STM32WB55VY.json +++ b/data/chips/STM32WB55VY.json @@ -1658,7 +1658,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { @@ -1736,7 +1736,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v1b", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WBA52CE.json b/data/chips/STM32WBA52CE.json index 4e301e7..3fa3c65 100644 --- a/data/chips/STM32WBA52CE.json +++ b/data/chips/STM32WBA52CE.json @@ -663,7 +663,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -748,7 +748,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32WBA52CG.json b/data/chips/STM32WBA52CG.json index fa4492f..522fe02 100644 --- a/data/chips/STM32WBA52CG.json +++ b/data/chips/STM32WBA52CG.json @@ -663,7 +663,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -748,7 +748,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32WBA52KE.json b/data/chips/STM32WBA52KE.json index e8b8f9d..92cd9c0 100644 --- a/data/chips/STM32WBA52KE.json +++ b/data/chips/STM32WBA52KE.json @@ -639,7 +639,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -714,7 +714,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32WBA52KG.json b/data/chips/STM32WBA52KG.json index a8ee756..7b75526 100644 --- a/data/chips/STM32WBA52KG.json +++ b/data/chips/STM32WBA52KG.json @@ -639,7 +639,7 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { @@ -714,7 +714,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2b", + "version": "v2a", "block": "LPTIM_ADV" }, "rcc": { diff --git a/data/chips/STM32WL54CC.json b/data/chips/STM32WL54CC.json index ca1c3e1..829394a 100644 --- a/data/chips/STM32WL54CC.json +++ b/data/chips/STM32WL54CC.json @@ -1133,7 +1133,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1193,7 +1193,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1238,7 +1238,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3706,7 +3706,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3766,7 +3766,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3811,7 +3811,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WL54JC.json b/data/chips/STM32WL54JC.json index b96aca6..e628b5a 100644 --- a/data/chips/STM32WL54JC.json +++ b/data/chips/STM32WL54JC.json @@ -1199,7 +1199,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1279,7 +1279,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1339,7 +1339,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4023,7 +4023,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4103,7 +4103,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4163,7 +4163,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WL55CC.json b/data/chips/STM32WL55CC.json index 80bc21c..19d9ec6 100644 --- a/data/chips/STM32WL55CC.json +++ b/data/chips/STM32WL55CC.json @@ -1139,7 +1139,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1199,7 +1199,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1244,7 +1244,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3712,7 +3712,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3772,7 +3772,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -3817,7 +3817,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WL55JC.json b/data/chips/STM32WL55JC.json index 4c69486..deafbfa 100644 --- a/data/chips/STM32WL55JC.json +++ b/data/chips/STM32WL55JC.json @@ -1205,7 +1205,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1285,7 +1285,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1345,7 +1345,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4029,7 +4029,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4109,7 +4109,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -4169,7 +4169,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4C8.json b/data/chips/STM32WLE4C8.json index df8c152..cb32b51 100644 --- a/data/chips/STM32WLE4C8.json +++ b/data/chips/STM32WLE4C8.json @@ -921,7 +921,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -981,7 +981,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1026,7 +1026,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4CB.json b/data/chips/STM32WLE4CB.json index 7db9768..c84b9d9 100644 --- a/data/chips/STM32WLE4CB.json +++ b/data/chips/STM32WLE4CB.json @@ -921,7 +921,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -981,7 +981,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1026,7 +1026,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4CC.json b/data/chips/STM32WLE4CC.json index 7ab9146..fddf424 100644 --- a/data/chips/STM32WLE4CC.json +++ b/data/chips/STM32WLE4CC.json @@ -1096,7 +1096,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1156,7 +1156,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1201,7 +1201,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4J8.json b/data/chips/STM32WLE4J8.json index a170f62..d2b7aef 100644 --- a/data/chips/STM32WLE4J8.json +++ b/data/chips/STM32WLE4J8.json @@ -987,7 +987,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1067,7 +1067,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1127,7 +1127,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4JB.json b/data/chips/STM32WLE4JB.json index 9a1fac0..573845c 100644 --- a/data/chips/STM32WLE4JB.json +++ b/data/chips/STM32WLE4JB.json @@ -987,7 +987,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1067,7 +1067,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1127,7 +1127,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4JC.json b/data/chips/STM32WLE4JC.json index 768f83f..786e38d 100644 --- a/data/chips/STM32WLE4JC.json +++ b/data/chips/STM32WLE4JC.json @@ -1162,7 +1162,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1242,7 +1242,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1302,7 +1302,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5C8.json b/data/chips/STM32WLE5C8.json index e342b6a..2a690e5 100644 --- a/data/chips/STM32WLE5C8.json +++ b/data/chips/STM32WLE5C8.json @@ -1096,7 +1096,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1156,7 +1156,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1201,7 +1201,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5CB.json b/data/chips/STM32WLE5CB.json index c3144f9..2334c83 100644 --- a/data/chips/STM32WLE5CB.json +++ b/data/chips/STM32WLE5CB.json @@ -1096,7 +1096,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1156,7 +1156,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1201,7 +1201,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5CC.json b/data/chips/STM32WLE5CC.json index 09c3ce1..143c18d 100644 --- a/data/chips/STM32WLE5CC.json +++ b/data/chips/STM32WLE5CC.json @@ -1096,7 +1096,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1156,7 +1156,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1201,7 +1201,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5J8.json b/data/chips/STM32WLE5J8.json index 4a9bc89..15dbd17 100644 --- a/data/chips/STM32WLE5J8.json +++ b/data/chips/STM32WLE5J8.json @@ -1162,7 +1162,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1242,7 +1242,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1302,7 +1302,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5JB.json b/data/chips/STM32WLE5JB.json index ab18672..a2f55d0 100644 --- a/data/chips/STM32WLE5JB.json +++ b/data/chips/STM32WLE5JB.json @@ -1162,7 +1162,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1242,7 +1242,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1302,7 +1302,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5JC.json b/data/chips/STM32WLE5JC.json index 44d1587..658cc3c 100644 --- a/data/chips/STM32WLE5JC.json +++ b/data/chips/STM32WLE5JC.json @@ -1162,7 +1162,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1242,7 +1242,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { @@ -1302,7 +1302,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v2a", + "version": "v1c", "block": "LPTIM" }, "rcc": { diff --git a/data/registers/lptim_v1.json b/data/registers/lptim_v1.json index d9b536a..ccf6e66 100644 --- a/data/registers/lptim_v1.json +++ b/data/registers/lptim_v1.json @@ -1,338 +1,500 @@ { "block/LPTIM": { - "description": "Low power timer", + "description": "Low power timer with Output Compare", "items": [ { "name": "ISR", - "description": "Interrupt and Status Register", + "description": "LPTIM interrupt and status register.", "byte_offset": 0, - "access": "Read", "fieldset": "ISR" }, { "name": "ICR", - "description": "Interrupt Clear Register", + "description": "LPTIM interrupt clear register.", "byte_offset": 4, - "access": "Write", "fieldset": "ICR" }, { "name": "IER", - "description": "Interrupt Enable Register", + "description": "LPTIM interrupt enable register.", "byte_offset": 8, "fieldset": "IER" }, { "name": "CFGR", - "description": "Configuration Register", + "description": "LPTIM configuration register.", "byte_offset": 12, "fieldset": "CFGR" }, { "name": "CR", - "description": "Control Register", + "description": "LPTIM control register.", "byte_offset": 16, "fieldset": "CR" }, { "name": "CMP", - "description": "Compare Register", + "description": "LPTIM compare register 1.", "byte_offset": 20, "fieldset": "CMP" }, { "name": "ARR", - "description": "Autoreload Register", + "description": "LPTIM autoreload register.", "byte_offset": 24, "fieldset": "ARR" }, { "name": "CNT", - "description": "Counter Register", + "description": "LPTIM counter register.", "byte_offset": 28, - "access": "Read", "fieldset": "CNT" } ] }, "fieldset/ARR": { - "description": "Autoreload Register", + "description": "LPTIM autoreload register.", "fields": [ { "name": "ARR", - "description": "Auto reload value", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", "bit_offset": 0, "bit_size": 16 } ] }, "fieldset/CFGR": { - "description": "Configuration Register", + "description": "LPTIM configuration register.", "fields": [ { "name": "CKSEL", - "description": "Clock selector", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 1, + "enum": "ClockSource" }, { "name": "CKPOL", - "description": "Clock Polarity", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", "bit_offset": 1, - "bit_size": 2 + "bit_size": 2, + "enum": "CKPOL" }, { "name": "CKFLT", - "description": "Configurable digital filter for external clock", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", "bit_offset": 3, - "bit_size": 2 + "bit_size": 2, + "enum": "Filter" }, { "name": "TRGFLT", - "description": "Configurable digital filter for trigger", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", "bit_offset": 6, - "bit_size": 2 + "bit_size": 2, + "enum": "Filter" }, { "name": "PRESC", - "description": "Clock prescaler", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", "bit_offset": 9, - "bit_size": 3 + "bit_size": 3, + "enum": "PRESC" }, { "name": "TRIGSEL", - "description": "Trigger selector", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", "bit_offset": 13, "bit_size": 3 }, { "name": "TRIGEN", - "description": "Trigger enable and polarity", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", "bit_offset": 17, - "bit_size": 2 + "bit_size": 2, + "enum": "TRIGEN" }, { "name": "TIMOUT", - "description": "Timeout enable", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", "bit_offset": 19, "bit_size": 1 }, { "name": "WAVE", - "description": "Waveform shape", + "description": "Waveform shape The WAVE bit controls the output shape.", "bit_offset": 20, "bit_size": 1 }, { "name": "WAVPOL", - "description": "Waveform shape polarity", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", "bit_offset": 21, - "bit_size": 1 + "bit_size": 1, + "enum": "WAVPOL" }, { "name": "PRELOAD", - "description": "Registers update mode", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", "bit_offset": 22, "bit_size": 1 }, { "name": "COUNTMODE", - "description": "counter mode enabled", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", "bit_offset": 23, - "bit_size": 1 + "bit_size": 1, + "enum": "ClockSource" }, { "name": "ENC", - "description": "Encoder mode enable", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 24, "bit_size": 1 } ] }, "fieldset/CMP": { - "description": "Compare Register", + "description": "LPTIM compare register 1.", "fields": [ { "name": "CMP", - "description": "Compare value", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", "bit_offset": 0, "bit_size": 16 } ] }, "fieldset/CNT": { - "description": "Counter Register", + "description": "LPTIM counter register.", "fields": [ { "name": "CNT", - "description": "Counter value", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", "bit_offset": 0, "bit_size": 16 } ] }, "fieldset/CR": { - "description": "Control Register", + "description": "LPTIM control register.", "fields": [ { "name": "ENABLE", - "description": "LPTIM Enable", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", "bit_offset": 0, "bit_size": 1 }, { "name": "SNGSTRT", - "description": "LPTIM start in single mode", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", "bit_offset": 1, "bit_size": 1 }, { "name": "CNTSTRT", - "description": "Timer start in continuous mode", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", "bit_offset": 2, "bit_size": 1 } ] }, "fieldset/ICR": { - "description": "Interrupt Clear Register", + "description": "LPTIM interrupt clear register.", "fields": [ { - "name": "CMPMCF", - "description": "compare match Clear Flag", + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } }, { "name": "ARRMCF", - "description": "Autoreload match Clear Flag", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", "bit_offset": 1, "bit_size": 1 }, { "name": "EXTTRIGCF", - "description": "External trigger valid edge Clear Flag", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", "bit_offset": 2, "bit_size": 1 }, { "name": "CMPOKCF", - "description": "Compare register update OK Clear Flag", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", "bit_offset": 3, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } }, { "name": "ARROKCF", - "description": "Autoreload register update OK Clear Flag", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", "bit_offset": 4, "bit_size": 1 }, { "name": "UPCF", - "description": "Direction change to UP Clear Flag", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 5, "bit_size": 1 }, { "name": "DOWNCF", - "description": "Direction change to down Clear Flag", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 6, "bit_size": 1 } ] }, "fieldset/IER": { - "description": "Interrupt Enable Register", + "description": "LPTIM interrupt enable register.", "fields": [ { - "name": "CMPMIE", - "description": "Compare match Interrupt Enable", + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } }, { "name": "ARRMIE", - "description": "Autoreload match Interrupt Enable", + "description": "Autoreload match Interrupt Enable.", "bit_offset": 1, "bit_size": 1 }, { "name": "EXTTRIGIE", - "description": "External trigger valid edge Interrupt Enable", + "description": "External trigger valid edge Interrupt Enable.", "bit_offset": 2, "bit_size": 1 }, { "name": "CMPOKIE", - "description": "Compare register update OK Interrupt Enable", + "description": "Compare register 1 update OK interrupt enable.", "bit_offset": 3, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } }, { "name": "ARROKIE", - "description": "Autoreload register update OK Interrupt Enable", + "description": "Autoreload register update OK Interrupt Enable.", "bit_offset": 4, "bit_size": 1 }, { "name": "UPIE", - "description": "Direction change to UP Interrupt Enable", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 5, "bit_size": 1 }, { "name": "DOWNIE", - "description": "Direction change to down Interrupt Enable", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 6, "bit_size": 1 } ] }, "fieldset/ISR": { - "description": "Interrupt and Status Register", + "description": "LPTIM interrupt and status register.", "fields": [ { - "name": "CMPM", - "description": "Compare match", + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } }, { "name": "ARRM", - "description": "Autoreload match", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", "bit_offset": 1, "bit_size": 1 }, { "name": "EXTTRIG", - "description": "External trigger edge event", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", "bit_offset": 2, "bit_size": 1 }, { "name": "CMPOK", - "description": "Compare register update OK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", "bit_offset": 3, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } }, { "name": "ARROK", - "description": "Autoreload register update OK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", "bit_offset": 4, "bit_size": 1 }, { "name": "UP", - "description": "Counter direction change down to up", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 5, "bit_size": 1 }, { "name": "DOWN", - "description": "Counter direction change up to down", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 6, "bit_size": 1 } ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] } } \ No newline at end of file diff --git a/data/registers/lptim_v1a.json b/data/registers/lptim_v1a.json new file mode 100644 index 0000000..5a7d7ff --- /dev/null +++ b/data/registers/lptim_v1a.json @@ -0,0 +1,505 @@ +{ + "block/LPTIM": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CMP", + "description": "LPTIM compare register 1.", + "byte_offset": 20, + "fieldset": "CMP" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "OR", + "description": "LPTIM option register.", + "byte_offset": 32 + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": 13, + "bit_size": 3 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1, + "enum": "WAVPOL" + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CMP": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CMP", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/lptim_v1b.json b/data/registers/lptim_v1b.json new file mode 100644 index 0000000..8f8ec12 --- /dev/null +++ b/data/registers/lptim_v1b.json @@ -0,0 +1,517 @@ +{ + "block/LPTIM": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CMP", + "description": "LPTIM compare register 1.", + "byte_offset": 20, + "fieldset": "CMP" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "OR", + "description": "LPTIM option register.", + "byte_offset": 32 + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": 13, + "bit_size": 3 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1, + "enum": "WAVPOL" + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CMP": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CMP", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "COUNTRST", + "description": "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "RSTARE", + "description": "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/lptim_v1b_g4.json b/data/registers/lptim_v1b_g4.json new file mode 100644 index 0000000..f52a658 --- /dev/null +++ b/data/registers/lptim_v1b_g4.json @@ -0,0 +1,526 @@ +{ + "block/LPTIM": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CMP", + "description": "LPTIM compare register 1.", + "byte_offset": 20, + "fieldset": "CMP" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "OR", + "description": "LPTIM option register.", + "byte_offset": 32 + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": [ + { + "start": 13, + "end": 15 + }, + { + "start": 29, + "end": 29 + } + ], + "bit_size": 4 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1, + "enum": "WAVPOL" + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CMP": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CMP", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "COUNTRST", + "description": "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "RSTARE", + "description": "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/lptim_v1b_h7.json b/data/registers/lptim_v1b_h7.json new file mode 100644 index 0000000..a154b4b --- /dev/null +++ b/data/registers/lptim_v1b_h7.json @@ -0,0 +1,533 @@ +{ + "block/LPTIM": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CMP", + "description": "LPTIM compare register 1.", + "byte_offset": 20, + "fieldset": "CMP" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "CFGR2", + "description": "LPTIM configuration register 2.", + "byte_offset": 36, + "fieldset": "CFGR2" + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": 13, + "bit_size": 3 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1, + "enum": "WAVPOL" + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR2": { + "description": "LPTIM configuration register 2.", + "fields": [ + { + "name": "INSEL", + "description": "LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to.", + "bit_offset": 0, + "bit_size": 2, + "array": { + "len": 2, + "stride": 4 + } + } + ] + }, + "fieldset/CMP": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CMP", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "COUNTRST", + "description": "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "RSTARE", + "description": "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/lptim_v1c.json b/data/registers/lptim_v1c.json new file mode 100644 index 0000000..5fe21f2 --- /dev/null +++ b/data/registers/lptim_v1c.json @@ -0,0 +1,570 @@ +{ + "block/LPTIM": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CMP", + "description": "LPTIM compare register 1.", + "byte_offset": 20, + "fieldset": "CMP" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "OR", + "description": "LPTIM option register.", + "byte_offset": 32 + }, + { + "name": "RCR", + "description": "LPTIM repetition register.", + "byte_offset": 40, + "fieldset": "RCR" + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": 13, + "bit_size": 3 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1, + "enum": "WAVPOL" + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1, + "enum": "ClockSource" + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CMP": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CMP", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "COUNTRST", + "description": "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "RSTARE", + "description": "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UECF", + "description": "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKCF", + "description": "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UEIE", + "description": "Update event interrupt enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKIE", + "description": "Repetition register update OK interrupt Enable.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UE", + "description": "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOK", + "description": "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/RCR": { + "description": "LPTIM repetition register.", + "fields": [ + { + "name": "REP", + "description": "Repetition register value REP is the repetition value for the LPTIM.", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/ClockSource": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/lptim_v2a.json b/data/registers/lptim_v2a.json index 32d58c6..b94eaee 100644 --- a/data/registers/lptim_v2a.json +++ b/data/registers/lptim_v2a.json @@ -1,62 +1,104 @@ { - "block/LPTIM": { - "description": "Low power timer.", + "block/LPTIM_ADV": { + "extends": "LPTIM_BASIC", + "description": "Low power timer with Output Compare", "items": [ { "name": "ISR", - "description": "Interrupt and Status Register.", + "description": "LPTIM interrupt and status register.", "byte_offset": 0, - "access": "Read", - "fieldset": "ISR" + "fieldset": "ISR_ADV" }, { "name": "ICR", - "description": "Interrupt Clear Register.", + "description": "LPTIM interrupt clear register.", "byte_offset": 4, - "access": "Write", - "fieldset": "ICR" + "fieldset": "ICR_ADV" }, { - "name": "IER", - "description": "Interrupt Enable Register.", + "name": "DIER", + "description": "LPTIM interrupt enable register.", "byte_offset": 8, - "fieldset": "IER" + "fieldset": "DIER_ADV" + }, + { + "name": "CCR", + "description": "LPTIM compare register 1.", + "array": { + "len": 2, + "stride": 32 + }, + "byte_offset": 20, + "fieldset": "CCR" + }, + { + "name": "CCMR", + "description": "LPTIM capture/compare mode register 1.", + "byte_offset": 44, + "fieldset": "CCMR" + } + ] + }, + "block/LPTIM_BASIC": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR_BASIC" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR_BASIC" + }, + { + "name": "DIER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "DIER_BASIC" }, { "name": "CFGR", - "description": "Configuration Register.", + "description": "LPTIM configuration register.", "byte_offset": 12, "fieldset": "CFGR" }, { "name": "CR", - "description": "Control Register.", + "description": "LPTIM control register.", "byte_offset": 16, "fieldset": "CR" }, { - "name": "CMP", - "description": "Compare Register.", + "name": "CCR", + "description": "LPTIM compare register 1.", + "array": { + "len": 1, + "stride": 32 + }, "byte_offset": 20, - "fieldset": "CMP" + "fieldset": "CCR" }, { "name": "ARR", - "description": "Autoreload Register.", + "description": "LPTIM autoreload register.", "byte_offset": 24, "fieldset": "ARR" }, { "name": "CNT", - "description": "Counter Register.", + "description": "LPTIM counter register.", "byte_offset": 28, - "access": "Read", "fieldset": "CNT" }, { - "name": "OR", - "description": "LPTIM option register.", - "byte_offset": 32 + "name": "CFGR2", + "description": "LPTIM configuration register 2.", + "byte_offset": 36, + "fieldset": "CFGR2" }, { "name": "RCR", @@ -67,335 +109,587 @@ ] }, "fieldset/ARR": { - "description": "Autoreload Register.", + "description": "LPTIM autoreload register.", "fields": [ { "name": "ARR", - "description": "Auto reload value.", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CCMR": { + "description": "LPTIM capture/compare mode register 1.", + "fields": [ + { + "name": "CCSEL", + "description": "Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "CCSEL" + }, + { + "name": "CCE", + "description": "Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not.", + "bit_offset": 1, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + }, + { + "name": "CCP_Input", + "description": "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.", + "bit_offset": 2, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "CCP_Input" + }, + { + "name": "CCP_Output", + "description": "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.", + "bit_offset": 2, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "CCP_Output" + }, + { + "name": "ICPSC", + "description": "Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).", + "bit_offset": 8, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "Filter" + }, + { + "name": "ICF", + "description": "Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 12, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "Filter" + } + ] + }, + "fieldset/CCR": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CCR", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", "bit_offset": 0, "bit_size": 16 } ] }, "fieldset/CFGR": { - "description": "Configuration Register.", + "description": "LPTIM configuration register.", "fields": [ { "name": "CKSEL", - "description": "Clock selector.", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", "bit_offset": 0, "bit_size": 1, - "enum": "CKSEL" + "enum": "ClockSource" }, { "name": "CKPOL", - "description": "Clock Polarity.", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", "bit_offset": 1, "bit_size": 2, "enum": "CKPOL" }, { "name": "CKFLT", - "description": "Configurable digital filter for external clock.", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", "bit_offset": 3, "bit_size": 2, "enum": "Filter" }, { "name": "TRGFLT", - "description": "Configurable digital filter for trigger.", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", "bit_offset": 6, "bit_size": 2, "enum": "Filter" }, { "name": "PRESC", - "description": "Clock prescaler.", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", "bit_offset": 9, "bit_size": 3, "enum": "PRESC" }, { "name": "TRIGSEL", - "description": "Trigger selector.", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", "bit_offset": 13, "bit_size": 3 }, { "name": "TRIGEN", - "description": "Trigger enable and polarity.", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", "bit_offset": 17, - "bit_size": 2 + "bit_size": 2, + "enum": "TRIGEN" }, { "name": "TIMOUT", - "description": "Timeout enable.", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", "bit_offset": 19, "bit_size": 1 }, { "name": "WAVE", - "description": "Waveform shape.", + "description": "Waveform shape The WAVE bit controls the output shape.", "bit_offset": 20, "bit_size": 1 }, { "name": "WAVPOL", - "description": "Waveform shape polarity.", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", "bit_offset": 21, - "bit_size": 1 + "bit_size": 1, + "enum": "WAVPOL" }, { "name": "PRELOAD", - "description": "Registers update mode.", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", "bit_offset": 22, "bit_size": 1 }, { "name": "COUNTMODE", - "description": "counter mode enabled.", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", "bit_offset": 23, - "bit_size": 1 + "bit_size": 1, + "enum": "ClockSource" }, { "name": "ENC", - "description": "Encoder mode enable.", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 24, "bit_size": 1 } ] }, - "fieldset/CMP": { - "description": "Compare Register.", + "fieldset/CFGR2": { + "description": "LPTIM configuration register 2.", "fields": [ { - "name": "CMP", - "description": "Compare value.", + "name": "INSEL", + "description": "LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to.", "bit_offset": 0, - "bit_size": 16 + "bit_size": 2, + "array": { + "len": 2, + "stride": 4 + } + }, + { + "name": "ICSEL", + "description": "LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to.", + "bit_offset": 16, + "bit_size": 2, + "array": { + "len": 2, + "stride": 4 + } } ] }, "fieldset/CNT": { - "description": "Counter Register.", + "description": "LPTIM counter register.", "fields": [ { "name": "CNT", - "description": "Counter value.", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", "bit_offset": 0, "bit_size": 16 } ] }, "fieldset/CR": { - "description": "Control Register.", + "description": "LPTIM control register.", "fields": [ { "name": "ENABLE", - "description": "LPTIM Enable.", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", "bit_offset": 0, "bit_size": 1 }, { "name": "SNGSTRT", - "description": "LPTIM start in single mode.", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", "bit_offset": 1, "bit_size": 1 }, { "name": "CNTSTRT", - "description": "Timer start in continuous mode.", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", "bit_offset": 2, "bit_size": 1 }, { - "name": "RSTARE", - "description": "Reset after read enable.", + "name": "COUNTRST", + "description": "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.", "bit_offset": 3, "bit_size": 1 }, { - "name": "COUNTRST", - "description": "Counter reset.", + "name": "RSTARE", + "description": "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.", "bit_offset": 4, "bit_size": 1 } ] }, - "fieldset/ICR": { - "description": "Interrupt Clear Register.", + "fieldset/DIER_ADV": { + "extends": "DIER_BASIC", + "description": "LPTIM interrupt enable register.", "fields": [ { - "name": "CMPMCF", - "description": "compare match Clear Flag.", + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } }, { - "name": "ARRMCF", - "description": "Autoreload match Clear Flag.", + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + }, + { + "name": "CCOIE", + "description": "Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 12, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, + { + "name": "CCDE", + "description": "Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 16, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + } + ] + }, + "fieldset/DIER_BASIC": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", "bit_offset": 1, "bit_size": 1 }, { - "name": "EXTTRIGCF", - "description": "External trigger valid edge Clear Flag.", + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", "bit_offset": 2, "bit_size": 1 }, { - "name": "CMPOKCF", - "description": "Compare register update OK Clear Flag.", + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", "bit_offset": 3, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } }, { - "name": "ARROKCF", - "description": "Autoreload register update OK Clear Flag.", + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", "bit_offset": 4, "bit_size": 1 }, { - "name": "UPCF", - "description": "Direction change to UP Clear Flag.", + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 5, "bit_size": 1 }, { - "name": "DOWNCF", - "description": "Direction change to down Clear Flag.", + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 6, "bit_size": 1 }, { - "name": "UECF", - "description": "Update event clear flag.", + "name": "UEIE", + "description": "Update event interrupt enable.", "bit_offset": 7, "bit_size": 1 }, { - "name": "REPOKCF", - "description": "Repetition register update OK clear flag.", + "name": "REPOKIE", + "description": "Repetition register update OK interrupt Enable.", "bit_offset": 8, "bit_size": 1 } ] }, - "fieldset/IER": { - "description": "Interrupt Enable Register.", + "fieldset/ICR_ADV": { + "extends": "ICR_BASIC", + "description": "LPTIM interrupt clear register.", "fields": [ { - "name": "CMPMIE", - "description": "Compare match Interrupt Enable.", + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } }, { - "name": "ARRMIE", - "description": "Autoreload match Interrupt Enable.", + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + }, + { + "name": "CCOCF", + "description": "Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 12, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + } + ] + }, + "fieldset/ICR_BASIC": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", "bit_offset": 1, "bit_size": 1 }, { - "name": "EXTTRIGIE", - "description": "External trigger valid edge Interrupt Enable.", + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", "bit_offset": 2, "bit_size": 1 }, { - "name": "CMPOKIE", - "description": "Compare register update OK Interrupt Enable.", + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", "bit_offset": 3, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } }, { - "name": "ARROKIE", - "description": "Autoreload register update OK Interrupt Enable.", + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", "bit_offset": 4, "bit_size": 1 }, { - "name": "UPIE", - "description": "Direction change to UP Interrupt Enable.", + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 5, "bit_size": 1 }, { - "name": "DOWNIE", - "description": "Direction change to down Interrupt Enable.", + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 6, "bit_size": 1 }, { - "name": "UEIE", - "description": "Update event interrupt enable.", + "name": "UECF", + "description": "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.", "bit_offset": 7, "bit_size": 1 }, { - "name": "REPOKIE", - "description": "REPOKIE.", + "name": "REPOKCF", + "description": "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.", "bit_offset": 8, "bit_size": 1 + }, + { + "name": "DIEROKCF", + "description": "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.", + "bit_offset": 24, + "bit_size": 1 } ] }, - "fieldset/ISR": { - "description": "Interrupt and Status Register.", + "fieldset/ISR_ADV": { + "extends": "ISR_BASIC", + "description": "LPTIM interrupt and status register.", "fields": [ { - "name": "CMPM", - "description": "Compare match.", + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + }, + { + "name": "CCOF", + "description": "Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 12, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + } + ] + }, + "fieldset/ISR_BASIC": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } }, { "name": "ARRM", - "description": "Autoreload match.", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", "bit_offset": 1, "bit_size": 1 }, { "name": "EXTTRIG", - "description": "External trigger edge event.", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", "bit_offset": 2, "bit_size": 1 }, { "name": "CMPOK", - "description": "Compare register update OK.", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", "bit_offset": 3, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } }, { "name": "ARROK", - "description": "Autoreload register update OK.", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", "bit_offset": 4, "bit_size": 1 }, { "name": "UP", - "description": "Counter direction change down to up.", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 5, "bit_size": 1 }, { "name": "DOWN", - "description": "Counter direction change up to down.", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", "bit_offset": 6, "bit_size": 1 }, { "name": "UE", - "description": "LPTIM update event occurred.", + "description": "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.", "bit_offset": 7, "bit_size": 1 }, { "name": "REPOK", - "description": "Repetition register update Ok.", + "description": "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.", "bit_offset": 8, "bit_size": 1 + }, + { + "name": "DIEROK", + "description": "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.", + "bit_offset": 24, + "bit_size": 1 } ] }, @@ -404,12 +698,57 @@ "fields": [ { "name": "REP", - "description": "Repetition register value.", + "description": "Repetition register value REP is the repetition value for the LPTIM.", "bit_offset": 0, "bit_size": 8 } ] }, + "enum/CCP_Input": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "value": 0 + }, + { + "name": "Falling", + "value": 1 + }, + { + "name": "Both", + "value": 3 + } + ] + }, + "enum/CCP_Output": { + "bit_size": 2, + "variants": [ + { + "name": "ActiveHigh", + "value": 0 + }, + { + "name": "ActiveLow", + "value": 1 + } + ] + }, + "enum/CCSEL": { + "bit_size": 1, + "variants": [ + { + "name": "OutputCompare", + "description": "channel is configured in output PWM mode", + "value": 0 + }, + { + "name": "InputCapture", + "description": "channel is configured in input capture mode", + "value": 1 + } + ] + }, "enum/CKPOL": { "bit_size": 2, "variants": [ @@ -430,17 +769,17 @@ } ] }, - "enum/CKSEL": { + "enum/ClockSource": { "bit_size": 1, "variants": [ { "name": "Internal", - "description": "LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", "value": 0 }, { "name": "External", - "description": "LPTIM is clocked by an external clock source through the LPTIM external Input1", + "description": "clocked by an external clock source through the LPTIM external Input1", "value": 1 } ] @@ -502,5 +841,45 @@ "value": 7 } ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + }, + "enum/WAVPOL": { + "bit_size": 1, + "variants": [ + { + "name": "Positive", + "description": "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 0 + }, + { + "name": "Negative", + "description": "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers.", + "value": 1 + } + ] } } \ No newline at end of file diff --git a/data/registers/lptim_v2b.json b/data/registers/lptim_v2b.json index db4fe37..e18663e 100644 --- a/data/registers/lptim_v2b.json +++ b/data/registers/lptim_v2b.json @@ -1,64 +1,24 @@ { - "block/LPTIM_ADV": { - "extends": "LPTIM_BASIC", + "block/LPTIM": { "description": "Low power timer with Output Compare", "items": [ { "name": "ISR", "description": "LPTIM interrupt and status register.", "byte_offset": 0, - "fieldset": "ISR_ADV" + "fieldset": "ISR" }, { "name": "ICR", "description": "LPTIM interrupt clear register.", "byte_offset": 4, - "fieldset": "ICR_ADV" + "fieldset": "ICR" }, { "name": "DIER", "description": "LPTIM interrupt enable register.", "byte_offset": 8, - "fieldset": "DIER_ADV" - }, - { - "name": "CCR", - "description": "LPTIM compare register 1.", - "array": { - "len": 2, - "stride": 32 - }, - "byte_offset": 20, - "fieldset": "CCR" - }, - { - "name": "CCMR", - "description": "LPTIM capture/compare mode register 1.", - "byte_offset": 44, - "fieldset": "CCMR" - } - ] - }, - "block/LPTIM_BASIC": { - "description": "Low power timer with Output Compare", - "items": [ - { - "name": "ISR", - "description": "LPTIM interrupt and status register.", - "byte_offset": 0, - "fieldset": "ISR_BASIC" - }, - { - "name": "ICR", - "description": "LPTIM interrupt clear register.", - "byte_offset": 4, - "fieldset": "ICR_BASIC" - }, - { - "name": "DIER", - "description": "LPTIM interrupt enable register.", - "byte_offset": 8, - "fieldset": "DIER_BASIC" + "fieldset": "DIER" }, { "name": "CFGR", @@ -76,8 +36,12 @@ "name": "CCR", "description": "LPTIM compare register 1.", "array": { - "len": 1, - "stride": 32 + "offsets": [ + 0, + 32, + 36, + 40 + ] }, "byte_offset": 20, "fieldset": "CCR" @@ -105,6 +69,16 @@ "description": "LPTIM repetition register.", "byte_offset": 40, "fieldset": "RCR" + }, + { + "name": "CCMR", + "description": "LPTIM capture/compare mode register 1.", + "array": { + "len": 2, + "stride": 1 + }, + "byte_offset": 44, + "fieldset": "CCMR" } ] }, @@ -208,7 +182,7 @@ "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", "bit_offset": 0, "bit_size": 1, - "enum": "CKSEL" + "enum": "ClockSource" }, { "name": "CKPOL", @@ -263,12 +237,6 @@ "bit_offset": 20, "bit_size": 1 }, - { - "name": "WAVPOL", - "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", - "bit_offset": 21, - "bit_size": 1 - }, { "name": "PRELOAD", "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", @@ -279,7 +247,8 @@ "name": "COUNTMODE", "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", "bit_offset": 23, - "bit_size": 1 + "bit_size": 1, + "enum": "ClockSource" }, { "name": "ENC", @@ -360,8 +329,7 @@ } ] }, - "fieldset/DIER_ADV": { - "extends": "DIER_BASIC", + "fieldset/DIER": { "description": "LPTIM interrupt enable register.", "fields": [ { @@ -370,53 +338,12 @@ "bit_offset": 0, "bit_size": 1, "array": { - "len": 2, - "stride": 9 - } - }, - { - "name": "CMPOKIE", - "description": "Compare register 1 update OK interrupt enable.", - "bit_offset": 3, - "bit_size": 1, - "array": { - "len": 2, - "stride": 16 - } - }, - { - "name": "CCOIE", - "description": "Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", - "bit_offset": 12, - "bit_size": 1, - "array": { - "len": 2, - "stride": 1 - } - }, - { - "name": "CCDE", - "description": "Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", - "bit_offset": 16, - "bit_size": 1, - "array": { - "len": 2, - "stride": 9 - } - } - ] - }, - "fieldset/DIER_BASIC": { - "description": "LPTIM interrupt enable register.", - "fields": [ - { - "name": "CCIE", - "description": "Capture/compare 1 interrupt enable.", - "bit_offset": 0, - "bit_size": 1, - "array": { - "len": 1, - "stride": 9 + "offsets": [ + 0, + 9, + 10, + 11 + ] } }, { @@ -437,8 +364,12 @@ "bit_offset": 3, "bit_size": 1, "array": { - "len": 1, - "stride": 16 + "offsets": [ + 0, + 16, + 17, + 18 + ] } }, { @@ -470,46 +401,34 @@ "description": "Repetition register update OK interrupt Enable.", "bit_offset": 8, "bit_size": 1 - } - ] - }, - "fieldset/ICR_ADV": { - "extends": "ICR_BASIC", - "description": "LPTIM interrupt clear register.", - "fields": [ - { - "name": "CCCF", - "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", - "bit_offset": 0, - "bit_size": 1, - "array": { - "len": 2, - "stride": 9 - } }, { - "name": "CMPOKCF", - "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", - "bit_offset": 3, + "name": "CCOIE", + "description": "Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 12, "bit_size": 1, "array": { - "len": 2, - "stride": 16 + "len": 4, + "stride": 1 } }, { - "name": "CCOCF", - "description": "Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", - "bit_offset": 12, + "name": "CCDE", + "description": "Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 16, "bit_size": 1, "array": { - "len": 2, - "stride": 1 + "offsets": [ + 0, + 9, + 10, + 11 + ] } } ] }, - "fieldset/ICR_BASIC": { + "fieldset/ICR": { "description": "LPTIM interrupt clear register.", "fields": [ { @@ -518,8 +437,12 @@ "bit_offset": 0, "bit_size": 1, "array": { - "len": 1, - "stride": 9 + "offsets": [ + 0, + 9, + 10, + 11 + ] } }, { @@ -540,8 +463,12 @@ "bit_offset": 3, "bit_size": 1, "array": { - "len": 1, - "stride": 16 + "offsets": [ + 0, + 16, + 17, + 18 + ] } }, { @@ -575,50 +502,24 @@ "bit_size": 1 }, { - "name": "DIEROKCF", - "description": "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.", - "bit_offset": 24, - "bit_size": 1 - } - ] - }, - "fieldset/ISR_ADV": { - "extends": "ISR_BASIC", - "description": "LPTIM interrupt and status register.", - "fields": [ - { - "name": "CCIF", - "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", - "bit_offset": 0, - "bit_size": 1, - "array": { - "len": 2, - "stride": 9 - } - }, - { - "name": "CMPOK", - "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", - "bit_offset": 3, - "bit_size": 1, - "array": { - "len": 2, - "stride": 16 - } - }, - { - "name": "CCOF", - "description": "Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "name": "CCOCF", + "description": "Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", "bit_offset": 12, "bit_size": 1, "array": { - "len": 2, + "len": 4, "stride": 1 } + }, + { + "name": "DIEROKCF", + "description": "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.", + "bit_offset": 24, + "bit_size": 1 } ] }, - "fieldset/ISR_BASIC": { + "fieldset/ISR": { "description": "LPTIM interrupt and status register.", "fields": [ { @@ -627,8 +528,12 @@ "bit_offset": 0, "bit_size": 1, "array": { - "len": 1, - "stride": 9 + "offsets": [ + 0, + 9, + 10, + 11 + ] } }, { @@ -649,8 +554,12 @@ "bit_offset": 3, "bit_size": 1, "array": { - "len": 1, - "stride": 16 + "offsets": [ + 0, + 16, + 17, + 18 + ] } }, { @@ -683,6 +592,16 @@ "bit_offset": 8, "bit_size": 1 }, + { + "name": "CCOF", + "description": "Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 12, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } + }, { "name": "DIEROK", "description": "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.", @@ -767,17 +686,17 @@ } ] }, - "enum/CKSEL": { + "enum/ClockSource": { "bit_size": 1, "variants": [ { "name": "Internal", - "description": "LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)", + "description": "clocked by internal clock source (APB clock or any of the embedded oscillators)", "value": 0 }, { "name": "External", - "description": "LPTIM is clocked by an external clock source through the LPTIM external Input1", + "description": "clocked by an external clock source through the LPTIM external Input1", "value": 1 } ]