diff --git a/data/chips/STM32F102C4.json b/data/chips/STM32F102C4.json index d728ecf..37796e3 100644 --- a/data/chips/STM32F102C4.json +++ b/data/chips/STM32F102C4.json @@ -1236,7 +1236,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F102C6.json b/data/chips/STM32F102C6.json index ac74fbf..c0883bb 100644 --- a/data/chips/STM32F102C6.json +++ b/data/chips/STM32F102C6.json @@ -1236,7 +1236,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F102C8.json b/data/chips/STM32F102C8.json index b85b634..61239ea 100644 --- a/data/chips/STM32F102C8.json +++ b/data/chips/STM32F102C8.json @@ -1484,7 +1484,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F102CB.json b/data/chips/STM32F102CB.json index 28cf9f8..0e9eec0 100644 --- a/data/chips/STM32F102CB.json +++ b/data/chips/STM32F102CB.json @@ -1484,7 +1484,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F102R4.json b/data/chips/STM32F102R4.json index be1a3d1..03e8619 100644 --- a/data/chips/STM32F102R4.json +++ b/data/chips/STM32F102R4.json @@ -1280,7 +1280,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F102R6.json b/data/chips/STM32F102R6.json index 4a11af2..38847ae 100644 --- a/data/chips/STM32F102R6.json +++ b/data/chips/STM32F102R6.json @@ -1280,7 +1280,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F102R8.json b/data/chips/STM32F102R8.json index b3bf853..c38dbd3 100644 --- a/data/chips/STM32F102R8.json +++ b/data/chips/STM32F102R8.json @@ -1540,7 +1540,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F102RB.json b/data/chips/STM32F102RB.json index afdb79a..9e5e2e0 100644 --- a/data/chips/STM32F102RB.json +++ b/data/chips/STM32F102RB.json @@ -1540,7 +1540,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103C4.json b/data/chips/STM32F103C4.json index 2c1efae..4a9f2ed 100644 --- a/data/chips/STM32F103C4.json +++ b/data/chips/STM32F103C4.json @@ -1489,7 +1489,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103C6.json b/data/chips/STM32F103C6.json index 3484763..e639c56 100644 --- a/data/chips/STM32F103C6.json +++ b/data/chips/STM32F103C6.json @@ -1499,7 +1499,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103C8.json b/data/chips/STM32F103C8.json index f72d6c0..d66c04b 100644 --- a/data/chips/STM32F103C8.json +++ b/data/chips/STM32F103C8.json @@ -1764,7 +1764,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103CB.json b/data/chips/STM32F103CB.json index 588c0ba..108208a 100644 --- a/data/chips/STM32F103CB.json +++ b/data/chips/STM32F103CB.json @@ -1762,7 +1762,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103R4.json b/data/chips/STM32F103R4.json index e6a55c0..8f8736c 100644 --- a/data/chips/STM32F103R4.json +++ b/data/chips/STM32F103R4.json @@ -1561,7 +1561,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103R6.json b/data/chips/STM32F103R6.json index 7f3cb73..ef1a36f 100644 --- a/data/chips/STM32F103R6.json +++ b/data/chips/STM32F103R6.json @@ -1567,7 +1567,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103R8.json b/data/chips/STM32F103R8.json index f7f3304..7066d76 100644 --- a/data/chips/STM32F103R8.json +++ b/data/chips/STM32F103R8.json @@ -1848,7 +1848,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103RB.json b/data/chips/STM32F103RB.json index aa19fda..ff64aed 100644 --- a/data/chips/STM32F103RB.json +++ b/data/chips/STM32F103RB.json @@ -1848,7 +1848,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103RC.json b/data/chips/STM32F103RC.json index e040deb..cad61cd 100644 --- a/data/chips/STM32F103RC.json +++ b/data/chips/STM32F103RC.json @@ -2575,7 +2575,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103RD.json b/data/chips/STM32F103RD.json index 3f66e6f..facdc30 100644 --- a/data/chips/STM32F103RD.json +++ b/data/chips/STM32F103RD.json @@ -2575,7 +2575,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103RE.json b/data/chips/STM32F103RE.json index 88382a0..b17ce0c 100644 --- a/data/chips/STM32F103RE.json +++ b/data/chips/STM32F103RE.json @@ -2575,7 +2575,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103RF.json b/data/chips/STM32F103RF.json index 20301b8..a3ed026 100644 --- a/data/chips/STM32F103RF.json +++ b/data/chips/STM32F103RF.json @@ -2878,7 +2878,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103RG.json b/data/chips/STM32F103RG.json index 308ef2a..9d6eeee 100644 --- a/data/chips/STM32F103RG.json +++ b/data/chips/STM32F103RG.json @@ -2878,7 +2878,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103T4.json b/data/chips/STM32F103T4.json index 5e8ef3c..79eb364 100644 --- a/data/chips/STM32F103T4.json +++ b/data/chips/STM32F103T4.json @@ -1431,7 +1431,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103T6.json b/data/chips/STM32F103T6.json index e0b68a5..35d6ef9 100644 --- a/data/chips/STM32F103T6.json +++ b/data/chips/STM32F103T6.json @@ -1431,7 +1431,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103T8.json b/data/chips/STM32F103T8.json index 914a878..2abd5f9 100644 --- a/data/chips/STM32F103T8.json +++ b/data/chips/STM32F103T8.json @@ -1523,7 +1523,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103TB.json b/data/chips/STM32F103TB.json index a5e1f0a..5154f0e 100644 --- a/data/chips/STM32F103TB.json +++ b/data/chips/STM32F103TB.json @@ -1517,7 +1517,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103V8.json b/data/chips/STM32F103V8.json index 1b7efdb..08fe150 100644 --- a/data/chips/STM32F103V8.json +++ b/data/chips/STM32F103V8.json @@ -1944,7 +1944,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103VB.json b/data/chips/STM32F103VB.json index 57b8a0c..bbe573e 100644 --- a/data/chips/STM32F103VB.json +++ b/data/chips/STM32F103VB.json @@ -1948,7 +1948,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103VC.json b/data/chips/STM32F103VC.json index ad84ac4..611f7ac 100644 --- a/data/chips/STM32F103VC.json +++ b/data/chips/STM32F103VC.json @@ -2900,7 +2900,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103VD.json b/data/chips/STM32F103VD.json index d3e219e..939a80c 100644 --- a/data/chips/STM32F103VD.json +++ b/data/chips/STM32F103VD.json @@ -2900,7 +2900,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103VE.json b/data/chips/STM32F103VE.json index 4f89f64..0af53ab 100644 --- a/data/chips/STM32F103VE.json +++ b/data/chips/STM32F103VE.json @@ -2900,7 +2900,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103VF.json b/data/chips/STM32F103VF.json index 4e4f4f9..a44ebde 100644 --- a/data/chips/STM32F103VF.json +++ b/data/chips/STM32F103VF.json @@ -3211,7 +3211,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103VG.json b/data/chips/STM32F103VG.json index 3454d52..3480ef6 100644 --- a/data/chips/STM32F103VG.json +++ b/data/chips/STM32F103VG.json @@ -3211,7 +3211,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103ZC.json b/data/chips/STM32F103ZC.json index d410dd6..cc47b97 100644 --- a/data/chips/STM32F103ZC.json +++ b/data/chips/STM32F103ZC.json @@ -3048,7 +3048,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103ZD.json b/data/chips/STM32F103ZD.json index 13cc86f..03f56db 100644 --- a/data/chips/STM32F103ZD.json +++ b/data/chips/STM32F103ZD.json @@ -3048,7 +3048,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103ZE.json b/data/chips/STM32F103ZE.json index ecc13d3..9afb9f0 100644 --- a/data/chips/STM32F103ZE.json +++ b/data/chips/STM32F103ZE.json @@ -3048,7 +3048,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103ZF.json b/data/chips/STM32F103ZF.json index ddd184c..172e576 100644 --- a/data/chips/STM32F103ZF.json +++ b/data/chips/STM32F103ZF.json @@ -3379,7 +3379,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F103ZG.json b/data/chips/STM32F103ZG.json index d15a053..25e81e6 100644 --- a/data/chips/STM32F103ZG.json +++ b/data/chips/STM32F103ZG.json @@ -3379,7 +3379,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F105R8.json b/data/chips/STM32F105R8.json index 843d112..897c0f8 100644 --- a/data/chips/STM32F105R8.json +++ b/data/chips/STM32F105R8.json @@ -2359,7 +2359,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "USB", "enable": { "register": "AHBENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F105RB.json b/data/chips/STM32F105RB.json index 84cf8cb..9542efb 100644 --- a/data/chips/STM32F105RB.json +++ b/data/chips/STM32F105RB.json @@ -2359,7 +2359,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "USB", "enable": { "register": "AHBENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F105RC.json b/data/chips/STM32F105RC.json index e60b673..9b6c727 100644 --- a/data/chips/STM32F105RC.json +++ b/data/chips/STM32F105RC.json @@ -2359,7 +2359,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "USB", "enable": { "register": "AHBENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F105V8.json b/data/chips/STM32F105V8.json index 4b471af..7549bc8 100644 --- a/data/chips/STM32F105V8.json +++ b/data/chips/STM32F105V8.json @@ -2459,7 +2459,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "USB", "enable": { "register": "AHBENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F105VB.json b/data/chips/STM32F105VB.json index 26523b5..66315cf 100644 --- a/data/chips/STM32F105VB.json +++ b/data/chips/STM32F105VB.json @@ -2459,7 +2459,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "USB", "enable": { "register": "AHBENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F105VC.json b/data/chips/STM32F105VC.json index 1da1b7b..d627732 100644 --- a/data/chips/STM32F105VC.json +++ b/data/chips/STM32F105VC.json @@ -2455,7 +2455,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "USB", "enable": { "register": "AHBENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F107RB.json b/data/chips/STM32F107RB.json index bf33e4e..68c395a 100644 --- a/data/chips/STM32F107RB.json +++ b/data/chips/STM32F107RB.json @@ -2417,7 +2417,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "USB", "enable": { "register": "AHBENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F107RC.json b/data/chips/STM32F107RC.json index e1455c3..bda9991 100644 --- a/data/chips/STM32F107RC.json +++ b/data/chips/STM32F107RC.json @@ -2417,7 +2417,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "USB", "enable": { "register": "AHBENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F107VB.json b/data/chips/STM32F107VB.json index 1d2d7fb..dee41b7 100644 --- a/data/chips/STM32F107VB.json +++ b/data/chips/STM32F107VB.json @@ -2537,7 +2537,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "USB", "enable": { "register": "AHBENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F107VC.json b/data/chips/STM32F107VC.json index 8ed3e8b..1254009 100644 --- a/data/chips/STM32F107VC.json +++ b/data/chips/STM32F107VC.json @@ -2541,7 +2541,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "USB", "enable": { "register": "AHBENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F205RB.json b/data/chips/STM32F205RB.json index 8bcb8d1..990c2c9 100644 --- a/data/chips/STM32F205RB.json +++ b/data/chips/STM32F205RB.json @@ -3633,7 +3633,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -3698,7 +3698,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205RC.json b/data/chips/STM32F205RC.json index b513d86..3707332 100644 --- a/data/chips/STM32F205RC.json +++ b/data/chips/STM32F205RC.json @@ -3644,7 +3644,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -3709,7 +3709,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205RE.json b/data/chips/STM32F205RE.json index fc10fcb..094397d 100644 --- a/data/chips/STM32F205RE.json +++ b/data/chips/STM32F205RE.json @@ -3648,7 +3648,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -3713,7 +3713,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205RF.json b/data/chips/STM32F205RF.json index 207785d..0177afb 100644 --- a/data/chips/STM32F205RF.json +++ b/data/chips/STM32F205RF.json @@ -3644,7 +3644,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -3709,7 +3709,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205RG.json b/data/chips/STM32F205RG.json index 4e7a347..b4e2af7 100644 --- a/data/chips/STM32F205RG.json +++ b/data/chips/STM32F205RG.json @@ -3652,7 +3652,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -3717,7 +3717,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205VB.json b/data/chips/STM32F205VB.json index 1590208..5b75c21 100644 --- a/data/chips/STM32F205VB.json +++ b/data/chips/STM32F205VB.json @@ -4057,7 +4057,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4122,7 +4122,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205VC.json b/data/chips/STM32F205VC.json index 868e01a..3f3bba6 100644 --- a/data/chips/STM32F205VC.json +++ b/data/chips/STM32F205VC.json @@ -4068,7 +4068,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4133,7 +4133,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205VE.json b/data/chips/STM32F205VE.json index 2ea0098..fc9a114 100644 --- a/data/chips/STM32F205VE.json +++ b/data/chips/STM32F205VE.json @@ -4068,7 +4068,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4133,7 +4133,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205VF.json b/data/chips/STM32F205VF.json index 727ab9f..67fb381 100644 --- a/data/chips/STM32F205VF.json +++ b/data/chips/STM32F205VF.json @@ -4068,7 +4068,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4133,7 +4133,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205VG.json b/data/chips/STM32F205VG.json index 56d24bb..af58115 100644 --- a/data/chips/STM32F205VG.json +++ b/data/chips/STM32F205VG.json @@ -4068,7 +4068,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4133,7 +4133,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205ZC.json b/data/chips/STM32F205ZC.json index e088522..eda83da 100644 --- a/data/chips/STM32F205ZC.json +++ b/data/chips/STM32F205ZC.json @@ -4325,7 +4325,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4390,7 +4390,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205ZE.json b/data/chips/STM32F205ZE.json index 78e5324..0ac34a7 100644 --- a/data/chips/STM32F205ZE.json +++ b/data/chips/STM32F205ZE.json @@ -4325,7 +4325,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4390,7 +4390,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205ZF.json b/data/chips/STM32F205ZF.json index 9b7c245..ac11c78 100644 --- a/data/chips/STM32F205ZF.json +++ b/data/chips/STM32F205ZF.json @@ -4325,7 +4325,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4390,7 +4390,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F205ZG.json b/data/chips/STM32F205ZG.json index 2f68918..a5273ab 100644 --- a/data/chips/STM32F205ZG.json +++ b/data/chips/STM32F205ZG.json @@ -4325,7 +4325,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4390,7 +4390,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207IC.json b/data/chips/STM32F207IC.json index 60b10bf..8d8accc 100644 --- a/data/chips/STM32F207IC.json +++ b/data/chips/STM32F207IC.json @@ -4903,7 +4903,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4968,7 +4968,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207IE.json b/data/chips/STM32F207IE.json index d0a885c..4b520e1 100644 --- a/data/chips/STM32F207IE.json +++ b/data/chips/STM32F207IE.json @@ -4903,7 +4903,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4968,7 +4968,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207IF.json b/data/chips/STM32F207IF.json index 7e081e0..df6f161 100644 --- a/data/chips/STM32F207IF.json +++ b/data/chips/STM32F207IF.json @@ -4903,7 +4903,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4968,7 +4968,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207IG.json b/data/chips/STM32F207IG.json index b3e700e..ed37211 100644 --- a/data/chips/STM32F207IG.json +++ b/data/chips/STM32F207IG.json @@ -4903,7 +4903,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4968,7 +4968,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207VC.json b/data/chips/STM32F207VC.json index 2b3a0ff..8587ecc 100644 --- a/data/chips/STM32F207VC.json +++ b/data/chips/STM32F207VC.json @@ -4357,7 +4357,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4422,7 +4422,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207VE.json b/data/chips/STM32F207VE.json index 3e8ca31..3e7a9c9 100644 --- a/data/chips/STM32F207VE.json +++ b/data/chips/STM32F207VE.json @@ -4357,7 +4357,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4422,7 +4422,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207VF.json b/data/chips/STM32F207VF.json index 4262c1f..c07b268 100644 --- a/data/chips/STM32F207VF.json +++ b/data/chips/STM32F207VF.json @@ -4357,7 +4357,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4422,7 +4422,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207VG.json b/data/chips/STM32F207VG.json index 10c8607..1420b41 100644 --- a/data/chips/STM32F207VG.json +++ b/data/chips/STM32F207VG.json @@ -4357,7 +4357,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4422,7 +4422,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207ZC.json b/data/chips/STM32F207ZC.json index 6261239..3bf1e16 100644 --- a/data/chips/STM32F207ZC.json +++ b/data/chips/STM32F207ZC.json @@ -4644,7 +4644,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4709,7 +4709,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207ZE.json b/data/chips/STM32F207ZE.json index 5019993..d339691 100644 --- a/data/chips/STM32F207ZE.json +++ b/data/chips/STM32F207ZE.json @@ -4644,7 +4644,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4709,7 +4709,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207ZF.json b/data/chips/STM32F207ZF.json index cd0b8d9..f738719 100644 --- a/data/chips/STM32F207ZF.json +++ b/data/chips/STM32F207ZF.json @@ -4644,7 +4644,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4709,7 +4709,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F207ZG.json b/data/chips/STM32F207ZG.json index 7387b8a..5dcc9af 100644 --- a/data/chips/STM32F207ZG.json +++ b/data/chips/STM32F207ZG.json @@ -4644,7 +4644,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4709,7 +4709,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F215RE.json b/data/chips/STM32F215RE.json index 4e5faf8..4e733d1 100644 --- a/data/chips/STM32F215RE.json +++ b/data/chips/STM32F215RE.json @@ -3713,7 +3713,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -3778,7 +3778,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F215RG.json b/data/chips/STM32F215RG.json index e97d688..5cf7a13 100644 --- a/data/chips/STM32F215RG.json +++ b/data/chips/STM32F215RG.json @@ -3713,7 +3713,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -3778,7 +3778,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F215VE.json b/data/chips/STM32F215VE.json index 8e5c9f9..ae41cb7 100644 --- a/data/chips/STM32F215VE.json +++ b/data/chips/STM32F215VE.json @@ -4137,7 +4137,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4202,7 +4202,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F215VG.json b/data/chips/STM32F215VG.json index 652b04e..42f0fe5 100644 --- a/data/chips/STM32F215VG.json +++ b/data/chips/STM32F215VG.json @@ -4137,7 +4137,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4202,7 +4202,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F215ZE.json b/data/chips/STM32F215ZE.json index 08bd6f3..170ca6a 100644 --- a/data/chips/STM32F215ZE.json +++ b/data/chips/STM32F215ZE.json @@ -4394,7 +4394,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4459,7 +4459,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F215ZG.json b/data/chips/STM32F215ZG.json index 47c1d9e..ca9fd99 100644 --- a/data/chips/STM32F215ZG.json +++ b/data/chips/STM32F215ZG.json @@ -4394,7 +4394,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4459,7 +4459,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F217IE.json b/data/chips/STM32F217IE.json index 5e17769..720e209 100644 --- a/data/chips/STM32F217IE.json +++ b/data/chips/STM32F217IE.json @@ -4972,7 +4972,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5037,7 +5037,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F217IG.json b/data/chips/STM32F217IG.json index eb4122b..1499207 100644 --- a/data/chips/STM32F217IG.json +++ b/data/chips/STM32F217IG.json @@ -4972,7 +4972,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5037,7 +5037,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F217VE.json b/data/chips/STM32F217VE.json index e61c12f..1686191 100644 --- a/data/chips/STM32F217VE.json +++ b/data/chips/STM32F217VE.json @@ -4426,7 +4426,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4491,7 +4491,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F217VG.json b/data/chips/STM32F217VG.json index 6524b41..cbbbfa3 100644 --- a/data/chips/STM32F217VG.json +++ b/data/chips/STM32F217VG.json @@ -4426,7 +4426,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4491,7 +4491,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F217ZE.json b/data/chips/STM32F217ZE.json index 504eccb..02ffbd0 100644 --- a/data/chips/STM32F217ZE.json +++ b/data/chips/STM32F217ZE.json @@ -4713,7 +4713,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4778,7 +4778,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F217ZG.json b/data/chips/STM32F217ZG.json index 3c7c4b5..5962dd4 100644 --- a/data/chips/STM32F217ZG.json +++ b/data/chips/STM32F217ZG.json @@ -4713,7 +4713,7 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4778,7 +4778,7 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": "PLL1_Q", "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F302C6.json b/data/chips/STM32F302C6.json index accce5f..799410d 100644 --- a/data/chips/STM32F302C6.json +++ b/data/chips/STM32F302C6.json @@ -2623,7 +2623,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302C8.json b/data/chips/STM32F302C8.json index 803d9e9..158c440 100644 --- a/data/chips/STM32F302C8.json +++ b/data/chips/STM32F302C8.json @@ -2627,7 +2627,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302CB.json b/data/chips/STM32F302CB.json index c01962b..06e55c1 100644 --- a/data/chips/STM32F302CB.json +++ b/data/chips/STM32F302CB.json @@ -3065,7 +3065,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302CC.json b/data/chips/STM32F302CC.json index 8c8ac3e..6770caf 100644 --- a/data/chips/STM32F302CC.json +++ b/data/chips/STM32F302CC.json @@ -3065,7 +3065,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302K6.json b/data/chips/STM32F302K6.json index 5926491..c4d311a 100644 --- a/data/chips/STM32F302K6.json +++ b/data/chips/STM32F302K6.json @@ -2269,7 +2269,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302K8.json b/data/chips/STM32F302K8.json index 06e85a5..6a3ca06 100644 --- a/data/chips/STM32F302K8.json +++ b/data/chips/STM32F302K8.json @@ -2269,7 +2269,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302R6.json b/data/chips/STM32F302R6.json index 0bb634f..b57e549 100644 --- a/data/chips/STM32F302R6.json +++ b/data/chips/STM32F302R6.json @@ -2762,7 +2762,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302R8.json b/data/chips/STM32F302R8.json index ae767ed..4e239b9 100644 --- a/data/chips/STM32F302R8.json +++ b/data/chips/STM32F302R8.json @@ -2762,7 +2762,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302RB.json b/data/chips/STM32F302RB.json index 49fe5bf..5312941 100644 --- a/data/chips/STM32F302RB.json +++ b/data/chips/STM32F302RB.json @@ -3329,7 +3329,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302RC.json b/data/chips/STM32F302RC.json index cd1a3df..da9435f 100644 --- a/data/chips/STM32F302RC.json +++ b/data/chips/STM32F302RC.json @@ -3329,7 +3329,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302RD.json b/data/chips/STM32F302RD.json index a0330b2..c0ce7ca 100644 --- a/data/chips/STM32F302RD.json +++ b/data/chips/STM32F302RD.json @@ -3506,7 +3506,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302RE.json b/data/chips/STM32F302RE.json index c659bad..de8f1ec 100644 --- a/data/chips/STM32F302RE.json +++ b/data/chips/STM32F302RE.json @@ -3506,7 +3506,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302VB.json b/data/chips/STM32F302VB.json index 223d7a7..64fb3ee 100644 --- a/data/chips/STM32F302VB.json +++ b/data/chips/STM32F302VB.json @@ -3665,7 +3665,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302VC.json b/data/chips/STM32F302VC.json index fb2a8e3..9618d6a 100644 --- a/data/chips/STM32F302VC.json +++ b/data/chips/STM32F302VC.json @@ -3669,7 +3669,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302VD.json b/data/chips/STM32F302VD.json index 1d33da6..8387b7d 100644 --- a/data/chips/STM32F302VD.json +++ b/data/chips/STM32F302VD.json @@ -4203,7 +4203,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302VE.json b/data/chips/STM32F302VE.json index 2f27c7f..7f6c4ec 100644 --- a/data/chips/STM32F302VE.json +++ b/data/chips/STM32F302VE.json @@ -4203,7 +4203,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302ZD.json b/data/chips/STM32F302ZD.json index 378700d..e7b5097 100644 --- a/data/chips/STM32F302ZD.json +++ b/data/chips/STM32F302ZD.json @@ -4343,7 +4343,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F302ZE.json b/data/chips/STM32F302ZE.json index bc4aaed..4b6c0d4 100644 --- a/data/chips/STM32F302ZE.json +++ b/data/chips/STM32F302ZE.json @@ -4343,7 +4343,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303CB.json b/data/chips/STM32F303CB.json index 92c3ad9..107c5f7 100644 --- a/data/chips/STM32F303CB.json +++ b/data/chips/STM32F303CB.json @@ -3647,7 +3647,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303CC.json b/data/chips/STM32F303CC.json index 67a7c10..1b9b324 100644 --- a/data/chips/STM32F303CC.json +++ b/data/chips/STM32F303CC.json @@ -3647,7 +3647,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303RB.json b/data/chips/STM32F303RB.json index 3580837..2f29b53 100644 --- a/data/chips/STM32F303RB.json +++ b/data/chips/STM32F303RB.json @@ -3979,7 +3979,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303RC.json b/data/chips/STM32F303RC.json index 7e7f5a7..bd61ecd 100644 --- a/data/chips/STM32F303RC.json +++ b/data/chips/STM32F303RC.json @@ -3985,7 +3985,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303RD.json b/data/chips/STM32F303RD.json index 74bf991..0776793 100644 --- a/data/chips/STM32F303RD.json +++ b/data/chips/STM32F303RD.json @@ -4152,7 +4152,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303RE.json b/data/chips/STM32F303RE.json index e28ce84..fdae142 100644 --- a/data/chips/STM32F303RE.json +++ b/data/chips/STM32F303RE.json @@ -4152,7 +4152,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303VB.json b/data/chips/STM32F303VB.json index c90e350..52e7032 100644 --- a/data/chips/STM32F303VB.json +++ b/data/chips/STM32F303VB.json @@ -4445,7 +4445,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303VC.json b/data/chips/STM32F303VC.json index d5f986d..2497081 100644 --- a/data/chips/STM32F303VC.json +++ b/data/chips/STM32F303VC.json @@ -4449,7 +4449,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303VD.json b/data/chips/STM32F303VD.json index a87950b..fd6aec0 100644 --- a/data/chips/STM32F303VD.json +++ b/data/chips/STM32F303VD.json @@ -5099,7 +5099,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303VE.json b/data/chips/STM32F303VE.json index cc20e74..3d26101 100644 --- a/data/chips/STM32F303VE.json +++ b/data/chips/STM32F303VE.json @@ -5103,7 +5103,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303ZD.json b/data/chips/STM32F303ZD.json index a99e965..376a457 100644 --- a/data/chips/STM32F303ZD.json +++ b/data/chips/STM32F303ZD.json @@ -5329,7 +5329,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F303ZE.json b/data/chips/STM32F303ZE.json index 2c323fd..123c92f 100644 --- a/data/chips/STM32F303ZE.json +++ b/data/chips/STM32F303ZE.json @@ -5329,7 +5329,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F373C8.json b/data/chips/STM32F373C8.json index 30cb154..72ad5d9 100644 --- a/data/chips/STM32F373C8.json +++ b/data/chips/STM32F373C8.json @@ -3527,7 +3527,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F373CB.json b/data/chips/STM32F373CB.json index 78f15e6..8fd9834 100644 --- a/data/chips/STM32F373CB.json +++ b/data/chips/STM32F373CB.json @@ -3527,7 +3527,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F373CC.json b/data/chips/STM32F373CC.json index 9273aca..02f61d8 100644 --- a/data/chips/STM32F373CC.json +++ b/data/chips/STM32F373CC.json @@ -3527,7 +3527,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F373R8.json b/data/chips/STM32F373R8.json index db462f1..ee37722 100644 --- a/data/chips/STM32F373R8.json +++ b/data/chips/STM32F373R8.json @@ -3785,7 +3785,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F373RB.json b/data/chips/STM32F373RB.json index 6491eb5..646a5ee 100644 --- a/data/chips/STM32F373RB.json +++ b/data/chips/STM32F373RB.json @@ -3785,7 +3785,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F373RC.json b/data/chips/STM32F373RC.json index 661a68b..a847e62 100644 --- a/data/chips/STM32F373RC.json +++ b/data/chips/STM32F373RC.json @@ -3785,7 +3785,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F373V8.json b/data/chips/STM32F373V8.json index c1a193a..25701ef 100644 --- a/data/chips/STM32F373V8.json +++ b/data/chips/STM32F373V8.json @@ -4126,7 +4126,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F373VB.json b/data/chips/STM32F373VB.json index b2e681c..71bde00 100644 --- a/data/chips/STM32F373VB.json +++ b/data/chips/STM32F373VB.json @@ -4126,7 +4126,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F373VC.json b/data/chips/STM32F373VC.json index 3609756..1592884 100644 --- a/data/chips/STM32F373VC.json +++ b/data/chips/STM32F373VC.json @@ -4126,7 +4126,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "USB", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32F401CB.json b/data/chips/STM32F401CB.json index 2901b71..3c4d28c 100644 --- a/data/chips/STM32F401CB.json +++ b/data/chips/STM32F401CB.json @@ -2408,7 +2408,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F401CC.json b/data/chips/STM32F401CC.json index 2517ec7..1390213 100644 --- a/data/chips/STM32F401CC.json +++ b/data/chips/STM32F401CC.json @@ -2423,7 +2423,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F401CD.json b/data/chips/STM32F401CD.json index 5b400ee..3b9fa99 100644 --- a/data/chips/STM32F401CD.json +++ b/data/chips/STM32F401CD.json @@ -2419,7 +2419,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F401CE.json b/data/chips/STM32F401CE.json index 6261aaa..81e7ab8 100644 --- a/data/chips/STM32F401CE.json +++ b/data/chips/STM32F401CE.json @@ -2419,7 +2419,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F401RB.json b/data/chips/STM32F401RB.json index a9d5adb..c3bcfe1 100644 --- a/data/chips/STM32F401RB.json +++ b/data/chips/STM32F401RB.json @@ -2652,7 +2652,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F401RC.json b/data/chips/STM32F401RC.json index afdf43f..390ab12 100644 --- a/data/chips/STM32F401RC.json +++ b/data/chips/STM32F401RC.json @@ -2663,7 +2663,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F401RD.json b/data/chips/STM32F401RD.json index e3d2695..0bd36ab 100644 --- a/data/chips/STM32F401RD.json +++ b/data/chips/STM32F401RD.json @@ -2663,7 +2663,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F401RE.json b/data/chips/STM32F401RE.json index 43660e1..e4d484b 100644 --- a/data/chips/STM32F401RE.json +++ b/data/chips/STM32F401RE.json @@ -2663,7 +2663,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F401VB.json b/data/chips/STM32F401VB.json index 4bd254b..3cc65d7 100644 --- a/data/chips/STM32F401VB.json +++ b/data/chips/STM32F401VB.json @@ -2882,7 +2882,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F401VC.json b/data/chips/STM32F401VC.json index 72bda95..1e4c0c0 100644 --- a/data/chips/STM32F401VC.json +++ b/data/chips/STM32F401VC.json @@ -2893,7 +2893,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F401VD.json b/data/chips/STM32F401VD.json index e8540a0..1f7a7b8 100644 --- a/data/chips/STM32F401VD.json +++ b/data/chips/STM32F401VD.json @@ -2893,7 +2893,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F401VE.json b/data/chips/STM32F401VE.json index 3da1811..8cae935 100644 --- a/data/chips/STM32F401VE.json +++ b/data/chips/STM32F401VE.json @@ -2893,7 +2893,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F405OE.json b/data/chips/STM32F405OE.json index 04eb7cc..0150308 100644 --- a/data/chips/STM32F405OE.json +++ b/data/chips/STM32F405OE.json @@ -4057,7 +4057,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4122,7 +4125,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F405OG.json b/data/chips/STM32F405OG.json index 02e6d0a..04ba1fc 100644 --- a/data/chips/STM32F405OG.json +++ b/data/chips/STM32F405OG.json @@ -4057,7 +4057,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4122,7 +4125,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F405RG.json b/data/chips/STM32F405RG.json index a68718f..b14ac8d 100644 --- a/data/chips/STM32F405RG.json +++ b/data/chips/STM32F405RG.json @@ -3706,7 +3706,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -3771,7 +3774,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F405VG.json b/data/chips/STM32F405VG.json index 155b7bd..1f7a674 100644 --- a/data/chips/STM32F405VG.json +++ b/data/chips/STM32F405VG.json @@ -4130,7 +4130,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4195,7 +4198,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F405ZG.json b/data/chips/STM32F405ZG.json index 98a78b7..cea20b2 100644 --- a/data/chips/STM32F405ZG.json +++ b/data/chips/STM32F405ZG.json @@ -4387,7 +4387,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4452,7 +4455,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F407IE.json b/data/chips/STM32F407IE.json index 3c2a4c7..32f8551 100644 --- a/data/chips/STM32F407IE.json +++ b/data/chips/STM32F407IE.json @@ -4982,7 +4982,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5047,7 +5050,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F407IG.json b/data/chips/STM32F407IG.json index 0ece159..946e025 100644 --- a/data/chips/STM32F407IG.json +++ b/data/chips/STM32F407IG.json @@ -4982,7 +4982,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5047,7 +5050,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F407VE.json b/data/chips/STM32F407VE.json index f4f7d30..e61ce4d 100644 --- a/data/chips/STM32F407VE.json +++ b/data/chips/STM32F407VE.json @@ -4431,7 +4431,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4496,7 +4499,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F407VG.json b/data/chips/STM32F407VG.json index e143271..cd9d1b4 100644 --- a/data/chips/STM32F407VG.json +++ b/data/chips/STM32F407VG.json @@ -4431,7 +4431,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4496,7 +4499,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F407ZE.json b/data/chips/STM32F407ZE.json index 4649750..b7d8ba0 100644 --- a/data/chips/STM32F407ZE.json +++ b/data/chips/STM32F407ZE.json @@ -4718,7 +4718,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4783,7 +4786,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F407ZG.json b/data/chips/STM32F407ZG.json index 3d4d143..3f267d1 100644 --- a/data/chips/STM32F407ZG.json +++ b/data/chips/STM32F407ZG.json @@ -4718,7 +4718,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4783,7 +4786,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F411CC.json b/data/chips/STM32F411CC.json index 02a906a..3c61eed 100644 --- a/data/chips/STM32F411CC.json +++ b/data/chips/STM32F411CC.json @@ -2814,7 +2814,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F411CE.json b/data/chips/STM32F411CE.json index f5cb861..ac76cae 100644 --- a/data/chips/STM32F411CE.json +++ b/data/chips/STM32F411CE.json @@ -2820,7 +2820,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F411RC.json b/data/chips/STM32F411RC.json index 1df642e..909d128 100644 --- a/data/chips/STM32F411RC.json +++ b/data/chips/STM32F411RC.json @@ -2994,7 +2994,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F411RE.json b/data/chips/STM32F411RE.json index f50a498..404efb8 100644 --- a/data/chips/STM32F411RE.json +++ b/data/chips/STM32F411RE.json @@ -3000,7 +3000,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F411VC.json b/data/chips/STM32F411VC.json index 607d641..fd1b5b3 100644 --- a/data/chips/STM32F411VC.json +++ b/data/chips/STM32F411VC.json @@ -3273,7 +3273,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F411VE.json b/data/chips/STM32F411VE.json index a4644f2..e937ca8 100644 --- a/data/chips/STM32F411VE.json +++ b/data/chips/STM32F411VE.json @@ -3279,7 +3279,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F412CE.json b/data/chips/STM32F412CE.json index 977dac5..33cd66c 100644 --- a/data/chips/STM32F412CE.json +++ b/data/chips/STM32F412CE.json @@ -3544,7 +3544,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F412CG.json b/data/chips/STM32F412CG.json index 3df0b64..3603924 100644 --- a/data/chips/STM32F412CG.json +++ b/data/chips/STM32F412CG.json @@ -3544,7 +3544,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F412RE.json b/data/chips/STM32F412RE.json index c1b335a..df356e4 100644 --- a/data/chips/STM32F412RE.json +++ b/data/chips/STM32F412RE.json @@ -4071,7 +4071,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F412RG.json b/data/chips/STM32F412RG.json index f008d69..a2dcc6d 100644 --- a/data/chips/STM32F412RG.json +++ b/data/chips/STM32F412RG.json @@ -4071,7 +4071,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F412VE.json b/data/chips/STM32F412VE.json index 8e26005..b3a1f10 100644 --- a/data/chips/STM32F412VE.json +++ b/data/chips/STM32F412VE.json @@ -4763,7 +4763,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F412VG.json b/data/chips/STM32F412VG.json index 3bb3853..26bdc3d 100644 --- a/data/chips/STM32F412VG.json +++ b/data/chips/STM32F412VG.json @@ -4763,7 +4763,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F412ZE.json b/data/chips/STM32F412ZE.json index 73cf919..182f94e 100644 --- a/data/chips/STM32F412ZE.json +++ b/data/chips/STM32F412ZE.json @@ -5085,7 +5085,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F412ZG.json b/data/chips/STM32F412ZG.json index 7f04f8c..1085360 100644 --- a/data/chips/STM32F412ZG.json +++ b/data/chips/STM32F412ZG.json @@ -5085,7 +5085,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F413CG.json b/data/chips/STM32F413CG.json index bad5ffa..95b306d 100644 --- a/data/chips/STM32F413CG.json +++ b/data/chips/STM32F413CG.json @@ -4200,7 +4200,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F413CH.json b/data/chips/STM32F413CH.json index 4c0d404..b6ae5a7 100644 --- a/data/chips/STM32F413CH.json +++ b/data/chips/STM32F413CH.json @@ -4200,7 +4200,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F413MG.json b/data/chips/STM32F413MG.json index d12ab79..c945f95 100644 --- a/data/chips/STM32F413MG.json +++ b/data/chips/STM32F413MG.json @@ -5164,7 +5164,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F413MH.json b/data/chips/STM32F413MH.json index e3f9512..67a5bdc 100644 --- a/data/chips/STM32F413MH.json +++ b/data/chips/STM32F413MH.json @@ -5164,7 +5164,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F413RG.json b/data/chips/STM32F413RG.json index 432e8cc..7555cb7 100644 --- a/data/chips/STM32F413RG.json +++ b/data/chips/STM32F413RG.json @@ -4874,7 +4874,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F413RH.json b/data/chips/STM32F413RH.json index e5a12d1..1f72cd9 100644 --- a/data/chips/STM32F413RH.json +++ b/data/chips/STM32F413RH.json @@ -4874,7 +4874,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F413VG.json b/data/chips/STM32F413VG.json index cc9c386..d451852 100644 --- a/data/chips/STM32F413VG.json +++ b/data/chips/STM32F413VG.json @@ -5841,7 +5841,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F413VH.json b/data/chips/STM32F413VH.json index 329d5ed..39d4065 100644 --- a/data/chips/STM32F413VH.json +++ b/data/chips/STM32F413VH.json @@ -5841,7 +5841,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F413ZG.json b/data/chips/STM32F413ZG.json index c94f57a..643f204 100644 --- a/data/chips/STM32F413ZG.json +++ b/data/chips/STM32F413ZG.json @@ -6181,7 +6181,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F413ZH.json b/data/chips/STM32F413ZH.json index 0dcce1e..a184189 100644 --- a/data/chips/STM32F413ZH.json +++ b/data/chips/STM32F413ZH.json @@ -6181,7 +6181,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F415OG.json b/data/chips/STM32F415OG.json index f440488..3e28c25 100644 --- a/data/chips/STM32F415OG.json +++ b/data/chips/STM32F415OG.json @@ -4126,7 +4126,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4191,7 +4194,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F415RG.json b/data/chips/STM32F415RG.json index 32a744a..249bea0 100644 --- a/data/chips/STM32F415RG.json +++ b/data/chips/STM32F415RG.json @@ -3775,7 +3775,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -3840,7 +3843,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F415VG.json b/data/chips/STM32F415VG.json index 7901f14..7fd3eae 100644 --- a/data/chips/STM32F415VG.json +++ b/data/chips/STM32F415VG.json @@ -4199,7 +4199,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4264,7 +4267,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F415ZG.json b/data/chips/STM32F415ZG.json index 99ebc1e..ec0d56a 100644 --- a/data/chips/STM32F415ZG.json +++ b/data/chips/STM32F415ZG.json @@ -4456,7 +4456,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4521,7 +4524,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F417IE.json b/data/chips/STM32F417IE.json index 2e11235..2ceb946 100644 --- a/data/chips/STM32F417IE.json +++ b/data/chips/STM32F417IE.json @@ -5051,7 +5051,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5116,7 +5119,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F417IG.json b/data/chips/STM32F417IG.json index 4213a9e..e65969a 100644 --- a/data/chips/STM32F417IG.json +++ b/data/chips/STM32F417IG.json @@ -5051,7 +5051,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5116,7 +5119,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F417VE.json b/data/chips/STM32F417VE.json index 61ff90e..0401b48 100644 --- a/data/chips/STM32F417VE.json +++ b/data/chips/STM32F417VE.json @@ -4500,7 +4500,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4565,7 +4568,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F417VG.json b/data/chips/STM32F417VG.json index 8c5a86d..344285e 100644 --- a/data/chips/STM32F417VG.json +++ b/data/chips/STM32F417VG.json @@ -4500,7 +4500,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4565,7 +4568,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F417ZE.json b/data/chips/STM32F417ZE.json index f72a5fa..acb41f7 100644 --- a/data/chips/STM32F417ZE.json +++ b/data/chips/STM32F417ZE.json @@ -4787,7 +4787,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4852,7 +4855,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F417ZG.json b/data/chips/STM32F417ZG.json index 869f10d..f25cc9d 100644 --- a/data/chips/STM32F417ZG.json +++ b/data/chips/STM32F417ZG.json @@ -4787,7 +4787,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4852,7 +4855,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F423CH.json b/data/chips/STM32F423CH.json index 9d65cb2..4854749 100644 --- a/data/chips/STM32F423CH.json +++ b/data/chips/STM32F423CH.json @@ -4227,7 +4227,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F423MH.json b/data/chips/STM32F423MH.json index 7faf49d..903e1d2 100644 --- a/data/chips/STM32F423MH.json +++ b/data/chips/STM32F423MH.json @@ -5191,7 +5191,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F423RH.json b/data/chips/STM32F423RH.json index bf967fe..23ba7e9 100644 --- a/data/chips/STM32F423RH.json +++ b/data/chips/STM32F423RH.json @@ -4901,7 +4901,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F423VH.json b/data/chips/STM32F423VH.json index 2adf354..b02b4ff 100644 --- a/data/chips/STM32F423VH.json +++ b/data/chips/STM32F423VH.json @@ -5868,7 +5868,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F423ZH.json b/data/chips/STM32F423ZH.json index 208c044..490de3c 100644 --- a/data/chips/STM32F423ZH.json +++ b/data/chips/STM32F423ZH.json @@ -6208,7 +6208,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32F427AG.json b/data/chips/STM32F427AG.json index 5558e2a..aae209a 100644 --- a/data/chips/STM32F427AG.json +++ b/data/chips/STM32F427AG.json @@ -5480,7 +5480,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5545,7 +5548,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F427AI.json b/data/chips/STM32F427AI.json index 7811547..0a98338 100644 --- a/data/chips/STM32F427AI.json +++ b/data/chips/STM32F427AI.json @@ -5513,7 +5513,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5578,7 +5581,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F427IG.json b/data/chips/STM32F427IG.json index aad0e1c..1c86167 100644 --- a/data/chips/STM32F427IG.json +++ b/data/chips/STM32F427IG.json @@ -5742,7 +5742,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5807,7 +5810,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F427II.json b/data/chips/STM32F427II.json index 88e6173..700dcfb 100644 --- a/data/chips/STM32F427II.json +++ b/data/chips/STM32F427II.json @@ -5775,7 +5775,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5840,7 +5843,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F427VG.json b/data/chips/STM32F427VG.json index b09d618..33930b7 100644 --- a/data/chips/STM32F427VG.json +++ b/data/chips/STM32F427VG.json @@ -4830,7 +4830,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4895,7 +4898,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F427VI.json b/data/chips/STM32F427VI.json index e493664..529007a 100644 --- a/data/chips/STM32F427VI.json +++ b/data/chips/STM32F427VI.json @@ -4863,7 +4863,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4928,7 +4931,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F427ZG.json b/data/chips/STM32F427ZG.json index 800bfd7..5c56b59 100644 --- a/data/chips/STM32F427ZG.json +++ b/data/chips/STM32F427ZG.json @@ -5339,7 +5339,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5404,7 +5407,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F427ZI.json b/data/chips/STM32F427ZI.json index fa780b5..91f8eab 100644 --- a/data/chips/STM32F427ZI.json +++ b/data/chips/STM32F427ZI.json @@ -5372,7 +5372,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5437,7 +5440,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429AG.json b/data/chips/STM32F429AG.json index e7fbcd7..9c9d609 100644 --- a/data/chips/STM32F429AG.json +++ b/data/chips/STM32F429AG.json @@ -5785,7 +5785,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5850,7 +5853,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429AI.json b/data/chips/STM32F429AI.json index b6d5e6c..304747f 100644 --- a/data/chips/STM32F429AI.json +++ b/data/chips/STM32F429AI.json @@ -5818,7 +5818,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5883,7 +5886,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429BE.json b/data/chips/STM32F429BE.json index 25de419..9322594 100644 --- a/data/chips/STM32F429BE.json +++ b/data/chips/STM32F429BE.json @@ -6171,7 +6171,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6236,7 +6239,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429BG.json b/data/chips/STM32F429BG.json index 63af3f0..b8a0b3f 100644 --- a/data/chips/STM32F429BG.json +++ b/data/chips/STM32F429BG.json @@ -6177,7 +6177,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6242,7 +6245,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429BI.json b/data/chips/STM32F429BI.json index 31aeaa8..d385617 100644 --- a/data/chips/STM32F429BI.json +++ b/data/chips/STM32F429BI.json @@ -6210,7 +6210,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6275,7 +6278,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429IE.json b/data/chips/STM32F429IE.json index 36bc08e..33cfb24 100644 --- a/data/chips/STM32F429IE.json +++ b/data/chips/STM32F429IE.json @@ -6035,7 +6035,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6100,7 +6103,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429IG.json b/data/chips/STM32F429IG.json index 9fb4c56..673757a 100644 --- a/data/chips/STM32F429IG.json +++ b/data/chips/STM32F429IG.json @@ -6047,7 +6047,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6112,7 +6115,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429II.json b/data/chips/STM32F429II.json index 93396b3..b4bf559 100644 --- a/data/chips/STM32F429II.json +++ b/data/chips/STM32F429II.json @@ -6080,7 +6080,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6145,7 +6148,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429NE.json b/data/chips/STM32F429NE.json index 69ee819..54ef6cf 100644 --- a/data/chips/STM32F429NE.json +++ b/data/chips/STM32F429NE.json @@ -6171,7 +6171,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6236,7 +6239,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429NG.json b/data/chips/STM32F429NG.json index 33231d2..40f3629 100644 --- a/data/chips/STM32F429NG.json +++ b/data/chips/STM32F429NG.json @@ -6177,7 +6177,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6242,7 +6245,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429NI.json b/data/chips/STM32F429NI.json index 9846dad..0d64a73 100644 --- a/data/chips/STM32F429NI.json +++ b/data/chips/STM32F429NI.json @@ -6210,7 +6210,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6275,7 +6278,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429VE.json b/data/chips/STM32F429VE.json index 1e683b8..6ddbe92 100644 --- a/data/chips/STM32F429VE.json +++ b/data/chips/STM32F429VE.json @@ -4963,7 +4963,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5028,7 +5031,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429VG.json b/data/chips/STM32F429VG.json index 6905cdd..34adae3 100644 --- a/data/chips/STM32F429VG.json +++ b/data/chips/STM32F429VG.json @@ -4969,7 +4969,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5034,7 +5037,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429VI.json b/data/chips/STM32F429VI.json index 31c7b30..7dbb7bc 100644 --- a/data/chips/STM32F429VI.json +++ b/data/chips/STM32F429VI.json @@ -5002,7 +5002,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5067,7 +5070,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429ZE.json b/data/chips/STM32F429ZE.json index f45ff39..322eaee 100644 --- a/data/chips/STM32F429ZE.json +++ b/data/chips/STM32F429ZE.json @@ -5537,7 +5537,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5602,7 +5605,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429ZG.json b/data/chips/STM32F429ZG.json index 72ba410..3ada3e8 100644 --- a/data/chips/STM32F429ZG.json +++ b/data/chips/STM32F429ZG.json @@ -5547,7 +5547,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5612,7 +5615,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F429ZI.json b/data/chips/STM32F429ZI.json index f34e5c9..6981fa8 100644 --- a/data/chips/STM32F429ZI.json +++ b/data/chips/STM32F429ZI.json @@ -5580,7 +5580,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5645,7 +5648,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F437AI.json b/data/chips/STM32F437AI.json index 0f886ca..0a98ba7 100644 --- a/data/chips/STM32F437AI.json +++ b/data/chips/STM32F437AI.json @@ -5582,7 +5582,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5647,7 +5650,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F437IG.json b/data/chips/STM32F437IG.json index a196561..f6c5839 100644 --- a/data/chips/STM32F437IG.json +++ b/data/chips/STM32F437IG.json @@ -5811,7 +5811,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5876,7 +5879,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F437II.json b/data/chips/STM32F437II.json index a8d1cc1..ce41e6c 100644 --- a/data/chips/STM32F437II.json +++ b/data/chips/STM32F437II.json @@ -5844,7 +5844,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5909,7 +5912,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F437VG.json b/data/chips/STM32F437VG.json index 82379c5..2a13b0d 100644 --- a/data/chips/STM32F437VG.json +++ b/data/chips/STM32F437VG.json @@ -4899,7 +4899,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4964,7 +4967,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F437VI.json b/data/chips/STM32F437VI.json index 53fe65b..2438bbc 100644 --- a/data/chips/STM32F437VI.json +++ b/data/chips/STM32F437VI.json @@ -4932,7 +4932,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4997,7 +5000,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F437ZG.json b/data/chips/STM32F437ZG.json index cc5291e..612682e 100644 --- a/data/chips/STM32F437ZG.json +++ b/data/chips/STM32F437ZG.json @@ -5408,7 +5408,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5473,7 +5476,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F437ZI.json b/data/chips/STM32F437ZI.json index 4c53f4a..b0b3fb4 100644 --- a/data/chips/STM32F437ZI.json +++ b/data/chips/STM32F437ZI.json @@ -5441,7 +5441,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5506,7 +5509,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F439AI.json b/data/chips/STM32F439AI.json index f443f52..76bee47 100644 --- a/data/chips/STM32F439AI.json +++ b/data/chips/STM32F439AI.json @@ -5887,7 +5887,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5952,7 +5955,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F439BG.json b/data/chips/STM32F439BG.json index c1d9eea..20e05eb 100644 --- a/data/chips/STM32F439BG.json +++ b/data/chips/STM32F439BG.json @@ -6246,7 +6246,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6311,7 +6314,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F439BI.json b/data/chips/STM32F439BI.json index 1f96a3b..a8f384a 100644 --- a/data/chips/STM32F439BI.json +++ b/data/chips/STM32F439BI.json @@ -6279,7 +6279,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6344,7 +6347,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F439IG.json b/data/chips/STM32F439IG.json index fae2b1a..ce006c1 100644 --- a/data/chips/STM32F439IG.json +++ b/data/chips/STM32F439IG.json @@ -6116,7 +6116,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6181,7 +6184,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F439II.json b/data/chips/STM32F439II.json index 0070f71..0bd111f 100644 --- a/data/chips/STM32F439II.json +++ b/data/chips/STM32F439II.json @@ -6149,7 +6149,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6214,7 +6217,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F439NG.json b/data/chips/STM32F439NG.json index 0c8f4ff..1819c2d 100644 --- a/data/chips/STM32F439NG.json +++ b/data/chips/STM32F439NG.json @@ -6246,7 +6246,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6311,7 +6314,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F439NI.json b/data/chips/STM32F439NI.json index e040ad6..7ad294d 100644 --- a/data/chips/STM32F439NI.json +++ b/data/chips/STM32F439NI.json @@ -6279,7 +6279,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6344,7 +6347,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F439VG.json b/data/chips/STM32F439VG.json index a7a425b..4a09b9a 100644 --- a/data/chips/STM32F439VG.json +++ b/data/chips/STM32F439VG.json @@ -5038,7 +5038,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5103,7 +5106,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F439VI.json b/data/chips/STM32F439VI.json index 9748be5..c1f7103 100644 --- a/data/chips/STM32F439VI.json +++ b/data/chips/STM32F439VI.json @@ -5071,7 +5071,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5136,7 +5139,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F439ZG.json b/data/chips/STM32F439ZG.json index 31721d9..cc32afc 100644 --- a/data/chips/STM32F439ZG.json +++ b/data/chips/STM32F439ZG.json @@ -5616,7 +5616,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5681,7 +5684,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F439ZI.json b/data/chips/STM32F439ZI.json index 06aa4a0..d49fc2c 100644 --- a/data/chips/STM32F439ZI.json +++ b/data/chips/STM32F439ZI.json @@ -5649,7 +5649,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5714,7 +5717,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F446MC.json b/data/chips/STM32F446MC.json index f134cca..62d8cc9 100644 --- a/data/chips/STM32F446MC.json +++ b/data/chips/STM32F446MC.json @@ -4487,7 +4487,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4552,7 +4555,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F446ME.json b/data/chips/STM32F446ME.json index 1c92911..372e13b 100644 --- a/data/chips/STM32F446ME.json +++ b/data/chips/STM32F446ME.json @@ -4487,7 +4487,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4552,7 +4555,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F446RC.json b/data/chips/STM32F446RC.json index eea4326..c6c65d1 100644 --- a/data/chips/STM32F446RC.json +++ b/data/chips/STM32F446RC.json @@ -4205,7 +4205,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4270,7 +4273,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F446RE.json b/data/chips/STM32F446RE.json index 2020fe9..df65943 100644 --- a/data/chips/STM32F446RE.json +++ b/data/chips/STM32F446RE.json @@ -4205,7 +4205,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4270,7 +4273,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F446VC.json b/data/chips/STM32F446VC.json index faf7cae..af7b2a4 100644 --- a/data/chips/STM32F446VC.json +++ b/data/chips/STM32F446VC.json @@ -5051,7 +5051,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5116,7 +5119,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F446VE.json b/data/chips/STM32F446VE.json index 4e8266c..d6b7827 100644 --- a/data/chips/STM32F446VE.json +++ b/data/chips/STM32F446VE.json @@ -5051,7 +5051,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5116,7 +5119,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F446ZC.json b/data/chips/STM32F446ZC.json index 7d62dc5..ab48f4c 100644 --- a/data/chips/STM32F446ZC.json +++ b/data/chips/STM32F446ZC.json @@ -5494,7 +5494,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5559,7 +5562,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F446ZE.json b/data/chips/STM32F446ZE.json index 823360b..de6b3d9 100644 --- a/data/chips/STM32F446ZE.json +++ b/data/chips/STM32F446ZE.json @@ -5494,7 +5494,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5559,7 +5562,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469AE.json b/data/chips/STM32F469AE.json index 8888781..3f747e0 100644 --- a/data/chips/STM32F469AE.json +++ b/data/chips/STM32F469AE.json @@ -5762,7 +5762,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5827,7 +5830,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469AG.json b/data/chips/STM32F469AG.json index e63a085..3f5852d 100644 --- a/data/chips/STM32F469AG.json +++ b/data/chips/STM32F469AG.json @@ -5762,7 +5762,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5827,7 +5830,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469AI.json b/data/chips/STM32F469AI.json index 62ffa5d..0f57a7d 100644 --- a/data/chips/STM32F469AI.json +++ b/data/chips/STM32F469AI.json @@ -5795,7 +5795,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5860,7 +5863,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469BE.json b/data/chips/STM32F469BE.json index e53447f..ac17619 100644 --- a/data/chips/STM32F469BE.json +++ b/data/chips/STM32F469BE.json @@ -6381,7 +6381,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6446,7 +6449,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469BG.json b/data/chips/STM32F469BG.json index 21ec8c3..924463b 100644 --- a/data/chips/STM32F469BG.json +++ b/data/chips/STM32F469BG.json @@ -6381,7 +6381,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6446,7 +6449,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469BI.json b/data/chips/STM32F469BI.json index b3a4c99..034d34e 100644 --- a/data/chips/STM32F469BI.json +++ b/data/chips/STM32F469BI.json @@ -6414,7 +6414,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6479,7 +6482,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469IE.json b/data/chips/STM32F469IE.json index bb287a5..fe1d85e 100644 --- a/data/chips/STM32F469IE.json +++ b/data/chips/STM32F469IE.json @@ -6075,7 +6075,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6140,7 +6143,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469IG.json b/data/chips/STM32F469IG.json index 9be67ae..a4e876f 100644 --- a/data/chips/STM32F469IG.json +++ b/data/chips/STM32F469IG.json @@ -6075,7 +6075,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6140,7 +6143,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469II.json b/data/chips/STM32F469II.json index 28a1b61..ff37da6 100644 --- a/data/chips/STM32F469II.json +++ b/data/chips/STM32F469II.json @@ -6108,7 +6108,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6173,7 +6176,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469NE.json b/data/chips/STM32F469NE.json index 021900b..b1475dc 100644 --- a/data/chips/STM32F469NE.json +++ b/data/chips/STM32F469NE.json @@ -6381,7 +6381,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6446,7 +6449,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469NG.json b/data/chips/STM32F469NG.json index 75d82f3..be9257d 100644 --- a/data/chips/STM32F469NG.json +++ b/data/chips/STM32F469NG.json @@ -6381,7 +6381,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6446,7 +6449,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469NI.json b/data/chips/STM32F469NI.json index 1d2416c..9669c86 100644 --- a/data/chips/STM32F469NI.json +++ b/data/chips/STM32F469NI.json @@ -6414,7 +6414,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6479,7 +6482,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469VE.json b/data/chips/STM32F469VE.json index 257d880..a87d7e6 100644 --- a/data/chips/STM32F469VE.json +++ b/data/chips/STM32F469VE.json @@ -4778,7 +4778,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4843,7 +4846,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469VG.json b/data/chips/STM32F469VG.json index cd29a8f..e3e96c7 100644 --- a/data/chips/STM32F469VG.json +++ b/data/chips/STM32F469VG.json @@ -4778,7 +4778,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4843,7 +4846,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469VI.json b/data/chips/STM32F469VI.json index 64be651..006fd7d 100644 --- a/data/chips/STM32F469VI.json +++ b/data/chips/STM32F469VI.json @@ -4811,7 +4811,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4876,7 +4879,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469ZE.json b/data/chips/STM32F469ZE.json index 3844b5e..414c344 100644 --- a/data/chips/STM32F469ZE.json +++ b/data/chips/STM32F469ZE.json @@ -5296,7 +5296,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5361,7 +5364,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469ZG.json b/data/chips/STM32F469ZG.json index 0b28acd..8da3f02 100644 --- a/data/chips/STM32F469ZG.json +++ b/data/chips/STM32F469ZG.json @@ -5296,7 +5296,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5361,7 +5364,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F469ZI.json b/data/chips/STM32F469ZI.json index af51568..6a66d72 100644 --- a/data/chips/STM32F469ZI.json +++ b/data/chips/STM32F469ZI.json @@ -5329,7 +5329,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5394,7 +5397,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479AG.json b/data/chips/STM32F479AG.json index 7f74a3b..8f9942f 100644 --- a/data/chips/STM32F479AG.json +++ b/data/chips/STM32F479AG.json @@ -5826,7 +5826,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5891,7 +5894,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479AI.json b/data/chips/STM32F479AI.json index 719831c..abeb2ef 100644 --- a/data/chips/STM32F479AI.json +++ b/data/chips/STM32F479AI.json @@ -5859,7 +5859,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5924,7 +5927,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479BG.json b/data/chips/STM32F479BG.json index ebb9fdb..ba56724 100644 --- a/data/chips/STM32F479BG.json +++ b/data/chips/STM32F479BG.json @@ -6445,7 +6445,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6510,7 +6513,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479BI.json b/data/chips/STM32F479BI.json index 12b977d..5781663 100644 --- a/data/chips/STM32F479BI.json +++ b/data/chips/STM32F479BI.json @@ -6478,7 +6478,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6543,7 +6546,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479IG.json b/data/chips/STM32F479IG.json index 2bfd095..a3b0c95 100644 --- a/data/chips/STM32F479IG.json +++ b/data/chips/STM32F479IG.json @@ -6139,7 +6139,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6204,7 +6207,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479II.json b/data/chips/STM32F479II.json index 471d886..f43b27c 100644 --- a/data/chips/STM32F479II.json +++ b/data/chips/STM32F479II.json @@ -6172,7 +6172,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6237,7 +6240,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479NG.json b/data/chips/STM32F479NG.json index 5eb990f..11719e3 100644 --- a/data/chips/STM32F479NG.json +++ b/data/chips/STM32F479NG.json @@ -6445,7 +6445,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6510,7 +6513,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479NI.json b/data/chips/STM32F479NI.json index dce269f..a67bbc0 100644 --- a/data/chips/STM32F479NI.json +++ b/data/chips/STM32F479NI.json @@ -6478,7 +6478,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6543,7 +6546,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479VG.json b/data/chips/STM32F479VG.json index b30684c..43bce61 100644 --- a/data/chips/STM32F479VG.json +++ b/data/chips/STM32F479VG.json @@ -4842,7 +4842,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4907,7 +4910,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479VI.json b/data/chips/STM32F479VI.json index f06ca32..a481c53 100644 --- a/data/chips/STM32F479VI.json +++ b/data/chips/STM32F479VI.json @@ -4875,7 +4875,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4940,7 +4943,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479ZG.json b/data/chips/STM32F479ZG.json index c47dbca..f35a3ed 100644 --- a/data/chips/STM32F479ZG.json +++ b/data/chips/STM32F479ZG.json @@ -5360,7 +5360,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5425,7 +5428,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F479ZI.json b/data/chips/STM32F479ZI.json index 4be4844..a0af52e 100644 --- a/data/chips/STM32F479ZI.json +++ b/data/chips/STM32F479ZI.json @@ -5393,7 +5393,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5458,7 +5461,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F722IC.json b/data/chips/STM32F722IC.json index c269a4d..658a56c 100644 --- a/data/chips/STM32F722IC.json +++ b/data/chips/STM32F722IC.json @@ -5816,7 +5816,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5881,7 +5884,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F722IE.json b/data/chips/STM32F722IE.json index 6fe01bd..e045d22 100644 --- a/data/chips/STM32F722IE.json +++ b/data/chips/STM32F722IE.json @@ -5816,7 +5816,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5881,7 +5884,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F722RC.json b/data/chips/STM32F722RC.json index 587b4fa..9f0baab 100644 --- a/data/chips/STM32F722RC.json +++ b/data/chips/STM32F722RC.json @@ -3983,7 +3983,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4048,7 +4051,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F722RE.json b/data/chips/STM32F722RE.json index 9266225..3eebbde 100644 --- a/data/chips/STM32F722RE.json +++ b/data/chips/STM32F722RE.json @@ -3983,7 +3983,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4048,7 +4051,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F722VC.json b/data/chips/STM32F722VC.json index 1a3785a..82ff51a 100644 --- a/data/chips/STM32F722VC.json +++ b/data/chips/STM32F722VC.json @@ -4996,7 +4996,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5061,7 +5064,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F722VE.json b/data/chips/STM32F722VE.json index 2d04e56..5c799dc 100644 --- a/data/chips/STM32F722VE.json +++ b/data/chips/STM32F722VE.json @@ -4996,7 +4996,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5061,7 +5064,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F722ZC.json b/data/chips/STM32F722ZC.json index 3965912..44a8e35 100644 --- a/data/chips/STM32F722ZC.json +++ b/data/chips/STM32F722ZC.json @@ -5454,7 +5454,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5519,7 +5522,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F722ZE.json b/data/chips/STM32F722ZE.json index 8e6d8b1..ea243c1 100644 --- a/data/chips/STM32F722ZE.json +++ b/data/chips/STM32F722ZE.json @@ -5454,7 +5454,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5519,7 +5522,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F723IC.json b/data/chips/STM32F723IC.json index 319a2c9..7595ea0 100644 --- a/data/chips/STM32F723IC.json +++ b/data/chips/STM32F723IC.json @@ -5736,7 +5736,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5801,7 +5804,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F723IE.json b/data/chips/STM32F723IE.json index db26155..2ce0ca8 100644 --- a/data/chips/STM32F723IE.json +++ b/data/chips/STM32F723IE.json @@ -5736,7 +5736,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5801,7 +5804,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F723VC.json b/data/chips/STM32F723VC.json index 573e016..c8eccac 100644 --- a/data/chips/STM32F723VC.json +++ b/data/chips/STM32F723VC.json @@ -4736,7 +4736,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4801,7 +4804,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F723VE.json b/data/chips/STM32F723VE.json index fa64951..1a5e205 100644 --- a/data/chips/STM32F723VE.json +++ b/data/chips/STM32F723VE.json @@ -4736,7 +4736,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4801,7 +4804,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F723ZC.json b/data/chips/STM32F723ZC.json index bcb4c49..f4a5092 100644 --- a/data/chips/STM32F723ZC.json +++ b/data/chips/STM32F723ZC.json @@ -5333,7 +5333,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5398,7 +5401,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F723ZE.json b/data/chips/STM32F723ZE.json index 77a8609..946ee06 100644 --- a/data/chips/STM32F723ZE.json +++ b/data/chips/STM32F723ZE.json @@ -5333,7 +5333,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5398,7 +5401,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F730I8.json b/data/chips/STM32F730I8.json index d970df5..c54afd4 100644 --- a/data/chips/STM32F730I8.json +++ b/data/chips/STM32F730I8.json @@ -5737,7 +5737,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5802,7 +5805,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F730R8.json b/data/chips/STM32F730R8.json index ce4210c..b2a1cd4 100644 --- a/data/chips/STM32F730R8.json +++ b/data/chips/STM32F730R8.json @@ -3988,7 +3988,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4053,7 +4056,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F730V8.json b/data/chips/STM32F730V8.json index c946ccc..c8319a9 100644 --- a/data/chips/STM32F730V8.json +++ b/data/chips/STM32F730V8.json @@ -5001,7 +5001,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5066,7 +5069,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F730Z8.json b/data/chips/STM32F730Z8.json index 76e2800..6cf326b 100644 --- a/data/chips/STM32F730Z8.json +++ b/data/chips/STM32F730Z8.json @@ -5334,7 +5334,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5399,7 +5402,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F732IE.json b/data/chips/STM32F732IE.json index 8735d43..5f5fa85 100644 --- a/data/chips/STM32F732IE.json +++ b/data/chips/STM32F732IE.json @@ -5855,7 +5855,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5920,7 +5923,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F732RE.json b/data/chips/STM32F732RE.json index e2b273b..bb1c860 100644 --- a/data/chips/STM32F732RE.json +++ b/data/chips/STM32F732RE.json @@ -4022,7 +4022,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4087,7 +4090,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F732VE.json b/data/chips/STM32F732VE.json index 7937e5c..3521518 100644 --- a/data/chips/STM32F732VE.json +++ b/data/chips/STM32F732VE.json @@ -5035,7 +5035,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5100,7 +5103,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F732ZE.json b/data/chips/STM32F732ZE.json index 25f696c..19c18bf 100644 --- a/data/chips/STM32F732ZE.json +++ b/data/chips/STM32F732ZE.json @@ -5493,7 +5493,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5558,7 +5561,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F733IE.json b/data/chips/STM32F733IE.json index 677907e..0b32e29 100644 --- a/data/chips/STM32F733IE.json +++ b/data/chips/STM32F733IE.json @@ -5775,7 +5775,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5840,7 +5843,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F733VE.json b/data/chips/STM32F733VE.json index 4772566..855a815 100644 --- a/data/chips/STM32F733VE.json +++ b/data/chips/STM32F733VE.json @@ -4775,7 +4775,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -4840,7 +4843,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F733ZE.json b/data/chips/STM32F733ZE.json index e72d438..5d74651 100644 --- a/data/chips/STM32F733ZE.json +++ b/data/chips/STM32F733ZE.json @@ -5372,7 +5372,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5437,7 +5440,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F745IE.json b/data/chips/STM32F745IE.json index 770d558..c669ad5 100644 --- a/data/chips/STM32F745IE.json +++ b/data/chips/STM32F745IE.json @@ -6574,7 +6574,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6639,7 +6642,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F745IG.json b/data/chips/STM32F745IG.json index 198b003..2b91fac 100644 --- a/data/chips/STM32F745IG.json +++ b/data/chips/STM32F745IG.json @@ -6574,7 +6574,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6639,7 +6642,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F745VE.json b/data/chips/STM32F745VE.json index b78bdf1..f3802fc 100644 --- a/data/chips/STM32F745VE.json +++ b/data/chips/STM32F745VE.json @@ -5517,7 +5517,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5582,7 +5585,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F745VG.json b/data/chips/STM32F745VG.json index 050ecb9..aa3b233 100644 --- a/data/chips/STM32F745VG.json +++ b/data/chips/STM32F745VG.json @@ -5517,7 +5517,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5582,7 +5585,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F745ZE.json b/data/chips/STM32F745ZE.json index c73e354..5a08892 100644 --- a/data/chips/STM32F745ZE.json +++ b/data/chips/STM32F745ZE.json @@ -6107,7 +6107,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6172,7 +6175,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F745ZG.json b/data/chips/STM32F745ZG.json index a85fdb5..aec2e06 100644 --- a/data/chips/STM32F745ZG.json +++ b/data/chips/STM32F745ZG.json @@ -6107,7 +6107,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6172,7 +6175,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F746BE.json b/data/chips/STM32F746BE.json index 38ff111..5a26a5a 100644 --- a/data/chips/STM32F746BE.json +++ b/data/chips/STM32F746BE.json @@ -7039,7 +7039,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7104,7 +7107,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F746BG.json b/data/chips/STM32F746BG.json index 23926ba..e6b0850 100644 --- a/data/chips/STM32F746BG.json +++ b/data/chips/STM32F746BG.json @@ -7039,7 +7039,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7104,7 +7107,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F746IE.json b/data/chips/STM32F746IE.json index a5b404d..e1fa458 100644 --- a/data/chips/STM32F746IE.json +++ b/data/chips/STM32F746IE.json @@ -6903,7 +6903,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6968,7 +6971,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F746IG.json b/data/chips/STM32F746IG.json index b8a3a3e..56a51f7 100644 --- a/data/chips/STM32F746IG.json +++ b/data/chips/STM32F746IG.json @@ -6903,7 +6903,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6968,7 +6971,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F746NE.json b/data/chips/STM32F746NE.json index 0731761..c772699 100644 --- a/data/chips/STM32F746NE.json +++ b/data/chips/STM32F746NE.json @@ -7039,7 +7039,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7104,7 +7107,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F746NG.json b/data/chips/STM32F746NG.json index 335245a..56dab61 100644 --- a/data/chips/STM32F746NG.json +++ b/data/chips/STM32F746NG.json @@ -7039,7 +7039,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7104,7 +7107,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F746VE.json b/data/chips/STM32F746VE.json index c1e7057..b73b15f 100644 --- a/data/chips/STM32F746VE.json +++ b/data/chips/STM32F746VE.json @@ -5701,7 +5701,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5766,7 +5769,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F746VG.json b/data/chips/STM32F746VG.json index 7a2ff16..c90057b 100644 --- a/data/chips/STM32F746VG.json +++ b/data/chips/STM32F746VG.json @@ -5701,7 +5701,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5766,7 +5769,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F746ZE.json b/data/chips/STM32F746ZE.json index 1a12209..1a086f5 100644 --- a/data/chips/STM32F746ZE.json +++ b/data/chips/STM32F746ZE.json @@ -6345,7 +6345,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6410,7 +6413,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F746ZG.json b/data/chips/STM32F746ZG.json index bce8f2d..5c02699 100644 --- a/data/chips/STM32F746ZG.json +++ b/data/chips/STM32F746ZG.json @@ -6345,7 +6345,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6410,7 +6413,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F750N8.json b/data/chips/STM32F750N8.json index 3d88b82..48f1b0d 100644 --- a/data/chips/STM32F750N8.json +++ b/data/chips/STM32F750N8.json @@ -7062,7 +7062,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7127,7 +7130,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F750V8.json b/data/chips/STM32F750V8.json index 879de04..56db08a 100644 --- a/data/chips/STM32F750V8.json +++ b/data/chips/STM32F750V8.json @@ -5720,7 +5720,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5785,7 +5788,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F750Z8.json b/data/chips/STM32F750Z8.json index 38d5226..d6d9f70 100644 --- a/data/chips/STM32F750Z8.json +++ b/data/chips/STM32F750Z8.json @@ -6364,7 +6364,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6429,7 +6432,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F756BG.json b/data/chips/STM32F756BG.json index 1c5f66b..f5b11df 100644 --- a/data/chips/STM32F756BG.json +++ b/data/chips/STM32F756BG.json @@ -7108,7 +7108,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7173,7 +7176,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F756IG.json b/data/chips/STM32F756IG.json index b8d1a11..2452d3c 100644 --- a/data/chips/STM32F756IG.json +++ b/data/chips/STM32F756IG.json @@ -6972,7 +6972,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7037,7 +7040,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F756NG.json b/data/chips/STM32F756NG.json index 5c8f016..ed6c7d0 100644 --- a/data/chips/STM32F756NG.json +++ b/data/chips/STM32F756NG.json @@ -7108,7 +7108,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7173,7 +7176,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F756VG.json b/data/chips/STM32F756VG.json index 84f9977..079941d 100644 --- a/data/chips/STM32F756VG.json +++ b/data/chips/STM32F756VG.json @@ -5770,7 +5770,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -5835,7 +5838,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F756ZG.json b/data/chips/STM32F756ZG.json index de0a393..54f79a4 100644 --- a/data/chips/STM32F756ZG.json +++ b/data/chips/STM32F756ZG.json @@ -6414,7 +6414,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6479,7 +6482,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F765BG.json b/data/chips/STM32F765BG.json index efeff08..0ae2f30 100644 --- a/data/chips/STM32F765BG.json +++ b/data/chips/STM32F765BG.json @@ -7405,7 +7405,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7470,7 +7473,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F765BI.json b/data/chips/STM32F765BI.json index eec2d4c..09e32c5 100644 --- a/data/chips/STM32F765BI.json +++ b/data/chips/STM32F765BI.json @@ -7411,7 +7411,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7476,7 +7479,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F765IG.json b/data/chips/STM32F765IG.json index 7cf0cc7..d733642 100644 --- a/data/chips/STM32F765IG.json +++ b/data/chips/STM32F765IG.json @@ -7415,7 +7415,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7480,7 +7483,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F765II.json b/data/chips/STM32F765II.json index ac7ece3..0ef245b 100644 --- a/data/chips/STM32F765II.json +++ b/data/chips/STM32F765II.json @@ -7415,7 +7415,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7480,7 +7483,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F765NG.json b/data/chips/STM32F765NG.json index d898fe2..23e6001 100644 --- a/data/chips/STM32F765NG.json +++ b/data/chips/STM32F765NG.json @@ -7411,7 +7411,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7476,7 +7479,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F765NI.json b/data/chips/STM32F765NI.json index d01d174..1a99a9e 100644 --- a/data/chips/STM32F765NI.json +++ b/data/chips/STM32F765NI.json @@ -7411,7 +7411,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7476,7 +7479,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F765VG.json b/data/chips/STM32F765VG.json index 2aaeea9..3c9e36a 100644 --- a/data/chips/STM32F765VG.json +++ b/data/chips/STM32F765VG.json @@ -6309,7 +6309,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6374,7 +6377,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F765VI.json b/data/chips/STM32F765VI.json index 084539d..9dcf65f 100644 --- a/data/chips/STM32F765VI.json +++ b/data/chips/STM32F765VI.json @@ -6309,7 +6309,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6374,7 +6377,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F765ZG.json b/data/chips/STM32F765ZG.json index ef0e84a..aa002ca 100644 --- a/data/chips/STM32F765ZG.json +++ b/data/chips/STM32F765ZG.json @@ -6928,7 +6928,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6993,7 +6996,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F765ZI.json b/data/chips/STM32F765ZI.json index 53a7a39..caab9e0 100644 --- a/data/chips/STM32F765ZI.json +++ b/data/chips/STM32F765ZI.json @@ -6928,7 +6928,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6993,7 +6996,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F767BG.json b/data/chips/STM32F767BG.json index 59f9034..73df9e1 100644 --- a/data/chips/STM32F767BG.json +++ b/data/chips/STM32F767BG.json @@ -8020,7 +8020,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8085,7 +8088,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F767BI.json b/data/chips/STM32F767BI.json index 76708a2..6057d5a 100644 --- a/data/chips/STM32F767BI.json +++ b/data/chips/STM32F767BI.json @@ -8020,7 +8020,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8085,7 +8088,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F767IG.json b/data/chips/STM32F767IG.json index e2da54b..81bee86 100644 --- a/data/chips/STM32F767IG.json +++ b/data/chips/STM32F767IG.json @@ -7864,7 +7864,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7929,7 +7932,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F767II.json b/data/chips/STM32F767II.json index 42e3209..43921a9 100644 --- a/data/chips/STM32F767II.json +++ b/data/chips/STM32F767II.json @@ -7864,7 +7864,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7929,7 +7932,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F767NG.json b/data/chips/STM32F767NG.json index 6d6e096..2b539f5 100644 --- a/data/chips/STM32F767NG.json +++ b/data/chips/STM32F767NG.json @@ -8020,7 +8020,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8085,7 +8088,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F767NI.json b/data/chips/STM32F767NI.json index bb374fc..137b005 100644 --- a/data/chips/STM32F767NI.json +++ b/data/chips/STM32F767NI.json @@ -8020,7 +8020,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8085,7 +8088,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F767VG.json b/data/chips/STM32F767VG.json index 718883e..4102c00 100644 --- a/data/chips/STM32F767VG.json +++ b/data/chips/STM32F767VG.json @@ -6593,7 +6593,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6658,7 +6661,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F767VI.json b/data/chips/STM32F767VI.json index 260316a..872d104 100644 --- a/data/chips/STM32F767VI.json +++ b/data/chips/STM32F767VI.json @@ -6593,7 +6593,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6658,7 +6661,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F767ZG.json b/data/chips/STM32F767ZG.json index 5616338..c5891be 100644 --- a/data/chips/STM32F767ZG.json +++ b/data/chips/STM32F767ZG.json @@ -7267,7 +7267,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7332,7 +7335,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F767ZI.json b/data/chips/STM32F767ZI.json index 838aabe..a57c745 100644 --- a/data/chips/STM32F767ZI.json +++ b/data/chips/STM32F767ZI.json @@ -7267,7 +7267,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7332,7 +7335,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F768AI.json b/data/chips/STM32F768AI.json index 760a85d..3142f28 100644 --- a/data/chips/STM32F768AI.json +++ b/data/chips/STM32F768AI.json @@ -7015,7 +7015,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7080,7 +7083,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F769AG.json b/data/chips/STM32F769AG.json index 2b3b75b..1a7565c 100644 --- a/data/chips/STM32F769AG.json +++ b/data/chips/STM32F769AG.json @@ -7015,7 +7015,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7080,7 +7083,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F769AI.json b/data/chips/STM32F769AI.json index b97df00..6afad5b 100644 --- a/data/chips/STM32F769AI.json +++ b/data/chips/STM32F769AI.json @@ -7304,7 +7304,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7369,7 +7372,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F769BG.json b/data/chips/STM32F769BG.json index 7b6487f..6958fd7 100644 --- a/data/chips/STM32F769BG.json +++ b/data/chips/STM32F769BG.json @@ -7987,7 +7987,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8052,7 +8055,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F769BI.json b/data/chips/STM32F769BI.json index 5e067a1..02657a3 100644 --- a/data/chips/STM32F769BI.json +++ b/data/chips/STM32F769BI.json @@ -7987,7 +7987,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8052,7 +8055,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F769IG.json b/data/chips/STM32F769IG.json index 32e6c3b..4e920d4 100644 --- a/data/chips/STM32F769IG.json +++ b/data/chips/STM32F769IG.json @@ -7652,7 +7652,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7717,7 +7720,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F769II.json b/data/chips/STM32F769II.json index 86a0b6c..35d5f9e 100644 --- a/data/chips/STM32F769II.json +++ b/data/chips/STM32F769II.json @@ -7652,7 +7652,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7717,7 +7720,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F769NG.json b/data/chips/STM32F769NG.json index e34af1b..22f019f 100644 --- a/data/chips/STM32F769NG.json +++ b/data/chips/STM32F769NG.json @@ -7987,7 +7987,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8052,7 +8055,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F769NI.json b/data/chips/STM32F769NI.json index fe12472..c1d7857 100644 --- a/data/chips/STM32F769NI.json +++ b/data/chips/STM32F769NI.json @@ -7987,7 +7987,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8052,7 +8055,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F777BI.json b/data/chips/STM32F777BI.json index a6e853f..b2de4bd 100644 --- a/data/chips/STM32F777BI.json +++ b/data/chips/STM32F777BI.json @@ -8095,7 +8095,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8160,7 +8163,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F777II.json b/data/chips/STM32F777II.json index 8df1ab5..3da8bf2 100644 --- a/data/chips/STM32F777II.json +++ b/data/chips/STM32F777II.json @@ -7939,7 +7939,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8004,7 +8007,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F777NI.json b/data/chips/STM32F777NI.json index 497cf55..3c5dc35 100644 --- a/data/chips/STM32F777NI.json +++ b/data/chips/STM32F777NI.json @@ -8095,7 +8095,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8160,7 +8163,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F777VI.json b/data/chips/STM32F777VI.json index bc89cda..b44bf5c 100644 --- a/data/chips/STM32F777VI.json +++ b/data/chips/STM32F777VI.json @@ -6668,7 +6668,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -6733,7 +6736,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F777ZI.json b/data/chips/STM32F777ZI.json index b82df3b..84f181b 100644 --- a/data/chips/STM32F777ZI.json +++ b/data/chips/STM32F777ZI.json @@ -7342,7 +7342,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7407,7 +7410,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F778AI.json b/data/chips/STM32F778AI.json index 94e53b4..2afec14 100644 --- a/data/chips/STM32F778AI.json +++ b/data/chips/STM32F778AI.json @@ -7367,7 +7367,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7432,7 +7435,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F779AI.json b/data/chips/STM32F779AI.json index d5291b0..6594371 100644 --- a/data/chips/STM32F779AI.json +++ b/data/chips/STM32F779AI.json @@ -7373,7 +7373,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7438,7 +7441,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F779BI.json b/data/chips/STM32F779BI.json index 053576f..3c65eca 100644 --- a/data/chips/STM32F779BI.json +++ b/data/chips/STM32F779BI.json @@ -8056,7 +8056,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8121,7 +8124,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F779II.json b/data/chips/STM32F779II.json index cd858c7..67b236a 100644 --- a/data/chips/STM32F779II.json +++ b/data/chips/STM32F779II.json @@ -7721,7 +7721,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -7786,7 +7789,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32F779NI.json b/data/chips/STM32F779NI.json index b0a1583..40c28af 100644 --- a/data/chips/STM32F779NI.json +++ b/data/chips/STM32F779NI.json @@ -8056,7 +8056,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" @@ -8121,7 +8124,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "DCKCFGR2", + "field": "CLK48SEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32G431C6.json b/data/chips/STM32G431C6.json index c906dea..3dacd0b 100644 --- a/data/chips/STM32G431C6.json +++ b/data/chips/STM32G431C6.json @@ -4073,7 +4073,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431C8.json b/data/chips/STM32G431C8.json index 147f42f..c6b9c92 100644 --- a/data/chips/STM32G431C8.json +++ b/data/chips/STM32G431C8.json @@ -4073,7 +4073,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431CB.json b/data/chips/STM32G431CB.json index 261a177..566b149 100644 --- a/data/chips/STM32G431CB.json +++ b/data/chips/STM32G431CB.json @@ -4077,7 +4077,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431K6.json b/data/chips/STM32G431K6.json index 6c38236..f048d7b 100644 --- a/data/chips/STM32G431K6.json +++ b/data/chips/STM32G431K6.json @@ -3563,7 +3563,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431K8.json b/data/chips/STM32G431K8.json index ae18ce4..348a7e5 100644 --- a/data/chips/STM32G431K8.json +++ b/data/chips/STM32G431K8.json @@ -3563,7 +3563,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431KB.json b/data/chips/STM32G431KB.json index 685c2bf..5559f18 100644 --- a/data/chips/STM32G431KB.json +++ b/data/chips/STM32G431KB.json @@ -3563,7 +3563,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431M6.json b/data/chips/STM32G431M6.json index 22c9ad6..f3d96c4 100644 --- a/data/chips/STM32G431M6.json +++ b/data/chips/STM32G431M6.json @@ -4516,7 +4516,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431M8.json b/data/chips/STM32G431M8.json index 8f4f1c6..3954997 100644 --- a/data/chips/STM32G431M8.json +++ b/data/chips/STM32G431M8.json @@ -4516,7 +4516,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431MB.json b/data/chips/STM32G431MB.json index 1f701e9..b55c859 100644 --- a/data/chips/STM32G431MB.json +++ b/data/chips/STM32G431MB.json @@ -4516,7 +4516,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431R6.json b/data/chips/STM32G431R6.json index 02456c6..438a0df 100644 --- a/data/chips/STM32G431R6.json +++ b/data/chips/STM32G431R6.json @@ -4392,7 +4392,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431R8.json b/data/chips/STM32G431R8.json index 1835b82..e413c6c 100644 --- a/data/chips/STM32G431R8.json +++ b/data/chips/STM32G431R8.json @@ -4392,7 +4392,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431RB.json b/data/chips/STM32G431RB.json index 1fbd1ff..7a4e960 100644 --- a/data/chips/STM32G431RB.json +++ b/data/chips/STM32G431RB.json @@ -4392,7 +4392,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431V6.json b/data/chips/STM32G431V6.json index 3cbda48..705160d 100644 --- a/data/chips/STM32G431V6.json +++ b/data/chips/STM32G431V6.json @@ -4768,7 +4768,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431V8.json b/data/chips/STM32G431V8.json index b7881f4..364a463 100644 --- a/data/chips/STM32G431V8.json +++ b/data/chips/STM32G431V8.json @@ -4768,7 +4768,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G431VB.json b/data/chips/STM32G431VB.json index 28cc23f..d50defa 100644 --- a/data/chips/STM32G431VB.json +++ b/data/chips/STM32G431VB.json @@ -4768,7 +4768,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G441CB.json b/data/chips/STM32G441CB.json index 8b00835..c10b451 100644 --- a/data/chips/STM32G441CB.json +++ b/data/chips/STM32G441CB.json @@ -4110,7 +4110,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G441KB.json b/data/chips/STM32G441KB.json index 69278d8..e0203a9 100644 --- a/data/chips/STM32G441KB.json +++ b/data/chips/STM32G441KB.json @@ -3596,7 +3596,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G441MB.json b/data/chips/STM32G441MB.json index 371d3eb..903c4de 100644 --- a/data/chips/STM32G441MB.json +++ b/data/chips/STM32G441MB.json @@ -4549,7 +4549,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G441RB.json b/data/chips/STM32G441RB.json index 8e748bd..9e45a02 100644 --- a/data/chips/STM32G441RB.json +++ b/data/chips/STM32G441RB.json @@ -4425,7 +4425,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G441VB.json b/data/chips/STM32G441VB.json index 8982da9..3d505e3 100644 --- a/data/chips/STM32G441VB.json +++ b/data/chips/STM32G441VB.json @@ -4801,7 +4801,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G471CC.json b/data/chips/STM32G471CC.json index 064b0b9..9eb791a 100644 --- a/data/chips/STM32G471CC.json +++ b/data/chips/STM32G471CC.json @@ -4297,7 +4297,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G471CE.json b/data/chips/STM32G471CE.json index 741cb98..d5b24a7 100644 --- a/data/chips/STM32G471CE.json +++ b/data/chips/STM32G471CE.json @@ -4297,7 +4297,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G471MC.json b/data/chips/STM32G471MC.json index be3067c..b595e90 100644 --- a/data/chips/STM32G471MC.json +++ b/data/chips/STM32G471MC.json @@ -4912,7 +4912,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G471ME.json b/data/chips/STM32G471ME.json index c3e114d..34c7e61 100644 --- a/data/chips/STM32G471ME.json +++ b/data/chips/STM32G471ME.json @@ -4916,7 +4916,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G471QC.json b/data/chips/STM32G471QC.json index d6afd7c..c6bf810 100644 --- a/data/chips/STM32G471QC.json +++ b/data/chips/STM32G471QC.json @@ -5541,7 +5541,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G471QE.json b/data/chips/STM32G471QE.json index 16f3675..399dd40 100644 --- a/data/chips/STM32G471QE.json +++ b/data/chips/STM32G471QE.json @@ -5541,7 +5541,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G471RC.json b/data/chips/STM32G471RC.json index 5736e83..0fed239 100644 --- a/data/chips/STM32G471RC.json +++ b/data/chips/STM32G471RC.json @@ -4642,7 +4642,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G471RE.json b/data/chips/STM32G471RE.json index d6dce89..605bf44 100644 --- a/data/chips/STM32G471RE.json +++ b/data/chips/STM32G471RE.json @@ -4642,7 +4642,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G471VC.json b/data/chips/STM32G471VC.json index 96139b9..db2c80b 100644 --- a/data/chips/STM32G471VC.json +++ b/data/chips/STM32G471VC.json @@ -5289,7 +5289,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G471VE.json b/data/chips/STM32G471VE.json index 88c00c2..f5b6997 100644 --- a/data/chips/STM32G471VE.json +++ b/data/chips/STM32G471VE.json @@ -5289,7 +5289,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473CB.json b/data/chips/STM32G473CB.json index efccbeb..63f6469 100644 --- a/data/chips/STM32G473CB.json +++ b/data/chips/STM32G473CB.json @@ -5121,7 +5121,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473CC.json b/data/chips/STM32G473CC.json index bc147f4..2a53026 100644 --- a/data/chips/STM32G473CC.json +++ b/data/chips/STM32G473CC.json @@ -5121,7 +5121,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473CE.json b/data/chips/STM32G473CE.json index 4d2dfb2..35b4f46 100644 --- a/data/chips/STM32G473CE.json +++ b/data/chips/STM32G473CE.json @@ -5121,7 +5121,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473MB.json b/data/chips/STM32G473MB.json index cc8f26e..fff2f5b 100644 --- a/data/chips/STM32G473MB.json +++ b/data/chips/STM32G473MB.json @@ -5882,7 +5882,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473MC.json b/data/chips/STM32G473MC.json index 86a518d..74816a6 100644 --- a/data/chips/STM32G473MC.json +++ b/data/chips/STM32G473MC.json @@ -5882,7 +5882,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473ME.json b/data/chips/STM32G473ME.json index f11b3a3..76d7753 100644 --- a/data/chips/STM32G473ME.json +++ b/data/chips/STM32G473ME.json @@ -5886,7 +5886,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473PB.json b/data/chips/STM32G473PB.json index 2ff37c0..ad7f76e 100644 --- a/data/chips/STM32G473PB.json +++ b/data/chips/STM32G473PB.json @@ -6865,7 +6865,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473PC.json b/data/chips/STM32G473PC.json index 9e6aa38..d862623 100644 --- a/data/chips/STM32G473PC.json +++ b/data/chips/STM32G473PC.json @@ -6865,7 +6865,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473PE.json b/data/chips/STM32G473PE.json index 3fe4a79..553f40b 100644 --- a/data/chips/STM32G473PE.json +++ b/data/chips/STM32G473PE.json @@ -6865,7 +6865,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473QB.json b/data/chips/STM32G473QB.json index 7d4cecf..d572352 100644 --- a/data/chips/STM32G473QB.json +++ b/data/chips/STM32G473QB.json @@ -6981,7 +6981,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473QC.json b/data/chips/STM32G473QC.json index 4425601..8e58e6d 100644 --- a/data/chips/STM32G473QC.json +++ b/data/chips/STM32G473QC.json @@ -6981,7 +6981,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473QE.json b/data/chips/STM32G473QE.json index 5698751..bf10b33 100644 --- a/data/chips/STM32G473QE.json +++ b/data/chips/STM32G473QE.json @@ -6981,7 +6981,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473RB.json b/data/chips/STM32G473RB.json index ff6abbc..3a0b9c2 100644 --- a/data/chips/STM32G473RB.json +++ b/data/chips/STM32G473RB.json @@ -5489,7 +5489,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473RC.json b/data/chips/STM32G473RC.json index bc1ab90..bb7980c 100644 --- a/data/chips/STM32G473RC.json +++ b/data/chips/STM32G473RC.json @@ -5489,7 +5489,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473RE.json b/data/chips/STM32G473RE.json index b71e425..f3637c0 100644 --- a/data/chips/STM32G473RE.json +++ b/data/chips/STM32G473RE.json @@ -5489,7 +5489,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473VB.json b/data/chips/STM32G473VB.json index 6efe182..0010229 100644 --- a/data/chips/STM32G473VB.json +++ b/data/chips/STM32G473VB.json @@ -6600,7 +6600,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473VC.json b/data/chips/STM32G473VC.json index 6436252..f0012c2 100644 --- a/data/chips/STM32G473VC.json +++ b/data/chips/STM32G473VC.json @@ -6600,7 +6600,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G473VE.json b/data/chips/STM32G473VE.json index 4a35028..e309988 100644 --- a/data/chips/STM32G473VE.json +++ b/data/chips/STM32G473VE.json @@ -6600,7 +6600,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474CB.json b/data/chips/STM32G474CB.json index c9ca00c..29dbaf5 100644 --- a/data/chips/STM32G474CB.json +++ b/data/chips/STM32G474CB.json @@ -5367,7 +5367,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474CC.json b/data/chips/STM32G474CC.json index b3faf18..9a82b73 100644 --- a/data/chips/STM32G474CC.json +++ b/data/chips/STM32G474CC.json @@ -5367,7 +5367,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474CE.json b/data/chips/STM32G474CE.json index a21ba75..6797cc6 100644 --- a/data/chips/STM32G474CE.json +++ b/data/chips/STM32G474CE.json @@ -5367,7 +5367,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474MB.json b/data/chips/STM32G474MB.json index caf0769..ce39b13 100644 --- a/data/chips/STM32G474MB.json +++ b/data/chips/STM32G474MB.json @@ -6158,7 +6158,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474MC.json b/data/chips/STM32G474MC.json index a02d9be..d2a074e 100644 --- a/data/chips/STM32G474MC.json +++ b/data/chips/STM32G474MC.json @@ -6158,7 +6158,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474ME.json b/data/chips/STM32G474ME.json index 8635b95..f25b552 100644 --- a/data/chips/STM32G474ME.json +++ b/data/chips/STM32G474ME.json @@ -6162,7 +6162,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474PB.json b/data/chips/STM32G474PB.json index 19b1fed..dd74ce2 100644 --- a/data/chips/STM32G474PB.json +++ b/data/chips/STM32G474PB.json @@ -7129,7 +7129,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474PC.json b/data/chips/STM32G474PC.json index dd595ba..307c93e 100644 --- a/data/chips/STM32G474PC.json +++ b/data/chips/STM32G474PC.json @@ -7129,7 +7129,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474PE.json b/data/chips/STM32G474PE.json index 988193a..a0177a3 100644 --- a/data/chips/STM32G474PE.json +++ b/data/chips/STM32G474PE.json @@ -7129,7 +7129,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474QB.json b/data/chips/STM32G474QB.json index b4f4917..efef65c 100644 --- a/data/chips/STM32G474QB.json +++ b/data/chips/STM32G474QB.json @@ -7257,7 +7257,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474QC.json b/data/chips/STM32G474QC.json index 22dd9d3..7b44b83 100644 --- a/data/chips/STM32G474QC.json +++ b/data/chips/STM32G474QC.json @@ -7257,7 +7257,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474QE.json b/data/chips/STM32G474QE.json index 0507f45..252132a 100644 --- a/data/chips/STM32G474QE.json +++ b/data/chips/STM32G474QE.json @@ -7257,7 +7257,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474RB.json b/data/chips/STM32G474RB.json index 3169699..3ba6dfb 100644 --- a/data/chips/STM32G474RB.json +++ b/data/chips/STM32G474RB.json @@ -5765,7 +5765,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474RC.json b/data/chips/STM32G474RC.json index 9d35ade..aed4928 100644 --- a/data/chips/STM32G474RC.json +++ b/data/chips/STM32G474RC.json @@ -5765,7 +5765,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474RE.json b/data/chips/STM32G474RE.json index db62679..a1983e2 100644 --- a/data/chips/STM32G474RE.json +++ b/data/chips/STM32G474RE.json @@ -5765,7 +5765,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474VB.json b/data/chips/STM32G474VB.json index af9db76..e89cc37 100644 --- a/data/chips/STM32G474VB.json +++ b/data/chips/STM32G474VB.json @@ -6876,7 +6876,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474VC.json b/data/chips/STM32G474VC.json index f55cbd3..096eec7 100644 --- a/data/chips/STM32G474VC.json +++ b/data/chips/STM32G474VC.json @@ -6876,7 +6876,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G474VE.json b/data/chips/STM32G474VE.json index 1b16019..f5b700c 100644 --- a/data/chips/STM32G474VE.json +++ b/data/chips/STM32G474VE.json @@ -6876,7 +6876,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G483CE.json b/data/chips/STM32G483CE.json index 35debc6..03dcedb 100644 --- a/data/chips/STM32G483CE.json +++ b/data/chips/STM32G483CE.json @@ -5160,7 +5160,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G483ME.json b/data/chips/STM32G483ME.json index c1773de..619452e 100644 --- a/data/chips/STM32G483ME.json +++ b/data/chips/STM32G483ME.json @@ -5925,7 +5925,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G483PE.json b/data/chips/STM32G483PE.json index 883d246..9a687a8 100644 --- a/data/chips/STM32G483PE.json +++ b/data/chips/STM32G483PE.json @@ -6904,7 +6904,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G483QE.json b/data/chips/STM32G483QE.json index 801bf0c..f1149ec 100644 --- a/data/chips/STM32G483QE.json +++ b/data/chips/STM32G483QE.json @@ -7020,7 +7020,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G483RE.json b/data/chips/STM32G483RE.json index a8b7922..7693300 100644 --- a/data/chips/STM32G483RE.json +++ b/data/chips/STM32G483RE.json @@ -5528,7 +5528,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G483VE.json b/data/chips/STM32G483VE.json index 82d344e..db4c165 100644 --- a/data/chips/STM32G483VE.json +++ b/data/chips/STM32G483VE.json @@ -6639,7 +6639,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G484CE.json b/data/chips/STM32G484CE.json index e5d0195..c9c73b5 100644 --- a/data/chips/STM32G484CE.json +++ b/data/chips/STM32G484CE.json @@ -5400,7 +5400,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G484ME.json b/data/chips/STM32G484ME.json index a7e054d..00178a1 100644 --- a/data/chips/STM32G484ME.json +++ b/data/chips/STM32G484ME.json @@ -6195,7 +6195,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G484PE.json b/data/chips/STM32G484PE.json index 98eaff9..9d8cd23 100644 --- a/data/chips/STM32G484PE.json +++ b/data/chips/STM32G484PE.json @@ -7168,7 +7168,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G484QE.json b/data/chips/STM32G484QE.json index f775ad5..9aed428 100644 --- a/data/chips/STM32G484QE.json +++ b/data/chips/STM32G484QE.json @@ -7290,7 +7290,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G484RE.json b/data/chips/STM32G484RE.json index 3dde6ea..9662e7e 100644 --- a/data/chips/STM32G484RE.json +++ b/data/chips/STM32G484RE.json @@ -5798,7 +5798,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G484VE.json b/data/chips/STM32G484VE.json index 03ccf39..40df967 100644 --- a/data/chips/STM32G484VE.json +++ b/data/chips/STM32G484VE.json @@ -6909,7 +6909,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G491CC.json b/data/chips/STM32G491CC.json index ff66d55..300954d 100644 --- a/data/chips/STM32G491CC.json +++ b/data/chips/STM32G491CC.json @@ -4431,7 +4431,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G491CE.json b/data/chips/STM32G491CE.json index a0b481d..3fec61a 100644 --- a/data/chips/STM32G491CE.json +++ b/data/chips/STM32G491CE.json @@ -4431,7 +4431,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G491KC.json b/data/chips/STM32G491KC.json index 9bc7654..e9ea28e 100644 --- a/data/chips/STM32G491KC.json +++ b/data/chips/STM32G491KC.json @@ -3837,7 +3837,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G491KE.json b/data/chips/STM32G491KE.json index 0807b9b..86f4d65 100644 --- a/data/chips/STM32G491KE.json +++ b/data/chips/STM32G491KE.json @@ -3837,7 +3837,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G491MC.json b/data/chips/STM32G491MC.json index 48f50a3..7463558 100644 --- a/data/chips/STM32G491MC.json +++ b/data/chips/STM32G491MC.json @@ -5039,7 +5039,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G491ME.json b/data/chips/STM32G491ME.json index 2f75bc7..efb3186 100644 --- a/data/chips/STM32G491ME.json +++ b/data/chips/STM32G491ME.json @@ -5039,7 +5039,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G491RC.json b/data/chips/STM32G491RC.json index 1c73c11..7f028b1 100644 --- a/data/chips/STM32G491RC.json +++ b/data/chips/STM32G491RC.json @@ -4841,7 +4841,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G491RE.json b/data/chips/STM32G491RE.json index fccac73..73497d6 100644 --- a/data/chips/STM32G491RE.json +++ b/data/chips/STM32G491RE.json @@ -4845,7 +4845,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G491VC.json b/data/chips/STM32G491VC.json index cbcc082..c98e7a4 100644 --- a/data/chips/STM32G491VC.json +++ b/data/chips/STM32G491VC.json @@ -5393,7 +5393,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G491VE.json b/data/chips/STM32G491VE.json index 779d717..2b261f5 100644 --- a/data/chips/STM32G491VE.json +++ b/data/chips/STM32G491VE.json @@ -5393,7 +5393,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G4A1CE.json b/data/chips/STM32G4A1CE.json index 5eab502..14f3b6c 100644 --- a/data/chips/STM32G4A1CE.json +++ b/data/chips/STM32G4A1CE.json @@ -4470,7 +4470,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G4A1KE.json b/data/chips/STM32G4A1KE.json index d102dd8..34fd87a 100644 --- a/data/chips/STM32G4A1KE.json +++ b/data/chips/STM32G4A1KE.json @@ -3876,7 +3876,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G4A1ME.json b/data/chips/STM32G4A1ME.json index fea3b34..e45061b 100644 --- a/data/chips/STM32G4A1ME.json +++ b/data/chips/STM32G4A1ME.json @@ -5078,7 +5078,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G4A1RE.json b/data/chips/STM32G4A1RE.json index 82183c2..2374957 100644 --- a/data/chips/STM32G4A1RE.json +++ b/data/chips/STM32G4A1RE.json @@ -4884,7 +4884,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32G4A1VE.json b/data/chips/STM32G4A1VE.json index cabc5d1..613d800 100644 --- a/data/chips/STM32G4A1VE.json +++ b/data/chips/STM32G4A1VE.json @@ -5432,7 +5432,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32H723VE.json b/data/chips/STM32H723VE.json index fd3f053..9990e0b 100644 --- a/data/chips/STM32H723VE.json +++ b/data/chips/STM32H723VE.json @@ -8225,7 +8225,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H723VG.json b/data/chips/STM32H723VG.json index d79d3fa..3c8d011 100644 --- a/data/chips/STM32H723VG.json +++ b/data/chips/STM32H723VG.json @@ -8225,7 +8225,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H723ZE.json b/data/chips/STM32H723ZE.json index 2063290..c1b4496 100644 --- a/data/chips/STM32H723ZE.json +++ b/data/chips/STM32H723ZE.json @@ -9402,7 +9402,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H723ZG.json b/data/chips/STM32H723ZG.json index 42e63e4..5b28d6a 100644 --- a/data/chips/STM32H723ZG.json +++ b/data/chips/STM32H723ZG.json @@ -9402,7 +9402,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H725AE.json b/data/chips/STM32H725AE.json index 831bdf5..49ce264 100644 --- a/data/chips/STM32H725AE.json +++ b/data/chips/STM32H725AE.json @@ -9633,7 +9633,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H725AG.json b/data/chips/STM32H725AG.json index 4677042..f96d84c 100644 --- a/data/chips/STM32H725AG.json +++ b/data/chips/STM32H725AG.json @@ -9639,7 +9639,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H725IE.json b/data/chips/STM32H725IE.json index 5db567e..8150671 100644 --- a/data/chips/STM32H725IE.json +++ b/data/chips/STM32H725IE.json @@ -9993,7 +9993,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H725IG.json b/data/chips/STM32H725IG.json index 48c4d56..e3d2c75 100644 --- a/data/chips/STM32H725IG.json +++ b/data/chips/STM32H725IG.json @@ -9999,7 +9999,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H725RE.json b/data/chips/STM32H725RE.json index c48f5e1..6681eda 100644 --- a/data/chips/STM32H725RE.json +++ b/data/chips/STM32H725RE.json @@ -6075,7 +6075,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H725RG.json b/data/chips/STM32H725RG.json index d60b27c..e1825fb 100644 --- a/data/chips/STM32H725RG.json +++ b/data/chips/STM32H725RG.json @@ -6081,7 +6081,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H725VE.json b/data/chips/STM32H725VE.json index 261e4ce..c036516 100644 --- a/data/chips/STM32H725VE.json +++ b/data/chips/STM32H725VE.json @@ -8030,7 +8030,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H725VG.json b/data/chips/STM32H725VG.json index db272f8..65f5577 100644 --- a/data/chips/STM32H725VG.json +++ b/data/chips/STM32H725VG.json @@ -8040,7 +8040,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H725ZE.json b/data/chips/STM32H725ZE.json index b01f663..83d5da0 100644 --- a/data/chips/STM32H725ZE.json +++ b/data/chips/STM32H725ZE.json @@ -9020,7 +9020,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H725ZG.json b/data/chips/STM32H725ZG.json index f467cb6..2aea6dd 100644 --- a/data/chips/STM32H725ZG.json +++ b/data/chips/STM32H725ZG.json @@ -9026,7 +9026,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index f6677a2..6286fe4 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -9754,7 +9754,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index be16c2b..0e1a30b 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -10114,7 +10114,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index 971668e..c81b1bf 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -8340,7 +8340,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index e09ad54..6d6a096 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -9517,7 +9517,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index bdb4153..5a8ae58 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -8340,7 +8340,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index 4798b0b..61d5bcd 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -9517,7 +9517,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index 601017b..1395858 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -9754,7 +9754,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index a799727..d70bdfe 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -10114,7 +10114,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H735RG.json b/data/chips/STM32H735RG.json index fd2e49f..c453516 100644 --- a/data/chips/STM32H735RG.json +++ b/data/chips/STM32H735RG.json @@ -6105,7 +6105,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index 2a0b9c6..509e292 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -8155,7 +8155,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index 3c6f88d..5ba6dfc 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -9141,7 +9141,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742AG.json b/data/chips/STM32H742AG.json index 4483e8b..0557834 100644 --- a/data/chips/STM32H742AG.json +++ b/data/chips/STM32H742AG.json @@ -8335,7 +8335,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8400,7 +8403,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742AI.json b/data/chips/STM32H742AI.json index efa4a08..f6d588b 100644 --- a/data/chips/STM32H742AI.json +++ b/data/chips/STM32H742AI.json @@ -8346,7 +8346,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8411,7 +8414,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742BG.json b/data/chips/STM32H742BG.json index 898cd34..2ecbaff 100644 --- a/data/chips/STM32H742BG.json +++ b/data/chips/STM32H742BG.json @@ -8703,7 +8703,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8768,7 +8771,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742BI.json b/data/chips/STM32H742BI.json index 37ba9e9..c51108f 100644 --- a/data/chips/STM32H742BI.json +++ b/data/chips/STM32H742BI.json @@ -8714,7 +8714,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8779,7 +8782,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742IG.json b/data/chips/STM32H742IG.json index 3fbdea5..8a8915d 100644 --- a/data/chips/STM32H742IG.json +++ b/data/chips/STM32H742IG.json @@ -8577,7 +8577,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8642,7 +8645,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742II.json b/data/chips/STM32H742II.json index d8f09b3..0e900ae 100644 --- a/data/chips/STM32H742II.json +++ b/data/chips/STM32H742II.json @@ -8588,7 +8588,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8653,7 +8656,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742VG.json b/data/chips/STM32H742VG.json index 67acfc9..a573bb9 100644 --- a/data/chips/STM32H742VG.json +++ b/data/chips/STM32H742VG.json @@ -7246,7 +7246,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -7311,7 +7314,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742VI.json b/data/chips/STM32H742VI.json index 936e150..071c931 100644 --- a/data/chips/STM32H742VI.json +++ b/data/chips/STM32H742VI.json @@ -7257,7 +7257,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -7322,7 +7325,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742XG.json b/data/chips/STM32H742XG.json index 6a3da7b..2e47c4f 100644 --- a/data/chips/STM32H742XG.json +++ b/data/chips/STM32H742XG.json @@ -8767,7 +8767,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8832,7 +8835,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742XI.json b/data/chips/STM32H742XI.json index bcb950f..f77d6a7 100644 --- a/data/chips/STM32H742XI.json +++ b/data/chips/STM32H742XI.json @@ -8778,7 +8778,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8843,7 +8846,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742ZG.json b/data/chips/STM32H742ZG.json index 8089829..72db5b0 100644 --- a/data/chips/STM32H742ZG.json +++ b/data/chips/STM32H742ZG.json @@ -8028,7 +8028,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8093,7 +8096,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H742ZI.json b/data/chips/STM32H742ZI.json index 6c6d533..14f611b 100644 --- a/data/chips/STM32H742ZI.json +++ b/data/chips/STM32H742ZI.json @@ -8039,7 +8039,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8104,7 +8107,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743AG.json b/data/chips/STM32H743AG.json index ffd550c..910e8b8 100644 --- a/data/chips/STM32H743AG.json +++ b/data/chips/STM32H743AG.json @@ -8760,7 +8760,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8825,7 +8828,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743AI.json b/data/chips/STM32H743AI.json index d05e89a..a2b8ed6 100644 --- a/data/chips/STM32H743AI.json +++ b/data/chips/STM32H743AI.json @@ -8771,7 +8771,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8836,7 +8839,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743BG.json b/data/chips/STM32H743BG.json index 23a9698..2091984 100644 --- a/data/chips/STM32H743BG.json +++ b/data/chips/STM32H743BG.json @@ -9308,7 +9308,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9373,7 +9376,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743BI.json b/data/chips/STM32H743BI.json index e0d5179..5135442 100644 --- a/data/chips/STM32H743BI.json +++ b/data/chips/STM32H743BI.json @@ -9319,7 +9319,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9384,7 +9387,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743IG.json b/data/chips/STM32H743IG.json index 236fef9..72e4b9a 100644 --- a/data/chips/STM32H743IG.json +++ b/data/chips/STM32H743IG.json @@ -9022,7 +9022,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9087,7 +9090,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743II.json b/data/chips/STM32H743II.json index 2561c00..61e5670 100644 --- a/data/chips/STM32H743II.json +++ b/data/chips/STM32H743II.json @@ -9033,7 +9033,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9098,7 +9101,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743VG.json b/data/chips/STM32H743VG.json index 7904bbd..b9f215a 100644 --- a/data/chips/STM32H743VG.json +++ b/data/chips/STM32H743VG.json @@ -7526,7 +7526,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -7591,7 +7594,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743VI.json b/data/chips/STM32H743VI.json index 3d22f9f..35bb5f9 100644 --- a/data/chips/STM32H743VI.json +++ b/data/chips/STM32H743VI.json @@ -7537,7 +7537,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -7602,7 +7605,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743XG.json b/data/chips/STM32H743XG.json index cad2f40..c665b34 100644 --- a/data/chips/STM32H743XG.json +++ b/data/chips/STM32H743XG.json @@ -9372,7 +9372,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9437,7 +9440,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743XI.json b/data/chips/STM32H743XI.json index ac3540a..4c6ed72 100644 --- a/data/chips/STM32H743XI.json +++ b/data/chips/STM32H743XI.json @@ -9383,7 +9383,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9448,7 +9451,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743ZG.json b/data/chips/STM32H743ZG.json index f0e244f..e154897 100644 --- a/data/chips/STM32H743ZG.json +++ b/data/chips/STM32H743ZG.json @@ -8363,7 +8363,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8428,7 +8431,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H743ZI.json b/data/chips/STM32H743ZI.json index dcc1c4c..05fae8b 100644 --- a/data/chips/STM32H743ZI.json +++ b/data/chips/STM32H743ZI.json @@ -8374,7 +8374,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8439,7 +8442,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H745BG.json b/data/chips/STM32H745BG.json index 3f23aac..b0bfe99 100644 --- a/data/chips/STM32H745BG.json +++ b/data/chips/STM32H745BG.json @@ -9194,7 +9194,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9259,7 +9262,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -19022,7 +19028,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -19087,7 +19096,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H745BI.json b/data/chips/STM32H745BI.json index 5b178b9..5b21e9d 100644 --- a/data/chips/STM32H745BI.json +++ b/data/chips/STM32H745BI.json @@ -9205,7 +9205,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9270,7 +9273,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -19033,7 +19039,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -19098,7 +19107,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H745IG.json b/data/chips/STM32H745IG.json index 57104bf..8c90de2 100644 --- a/data/chips/STM32H745IG.json +++ b/data/chips/STM32H745IG.json @@ -8945,7 +8945,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9010,7 +9013,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -18515,7 +18521,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -18580,7 +18589,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H745II.json b/data/chips/STM32H745II.json index 003e406..4231119 100644 --- a/data/chips/STM32H745II.json +++ b/data/chips/STM32H745II.json @@ -8956,7 +8956,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9021,7 +9024,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -18526,7 +18532,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -18591,7 +18600,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H745XG.json b/data/chips/STM32H745XG.json index 1fa0d41..1f3a436 100644 --- a/data/chips/STM32H745XG.json +++ b/data/chips/STM32H745XG.json @@ -9363,7 +9363,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9428,7 +9431,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -19360,7 +19366,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -19425,7 +19434,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H745XI.json b/data/chips/STM32H745XI.json index 3af3bf5..902c9fd 100644 --- a/data/chips/STM32H745XI.json +++ b/data/chips/STM32H745XI.json @@ -9374,7 +9374,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9439,7 +9442,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -19371,7 +19377,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -19436,7 +19445,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H745ZG.json b/data/chips/STM32H745ZG.json index 21bd395..8ccc479 100644 --- a/data/chips/STM32H745ZG.json +++ b/data/chips/STM32H745ZG.json @@ -8139,7 +8139,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8204,7 +8207,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -16902,7 +16908,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -16967,7 +16976,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H745ZI.json b/data/chips/STM32H745ZI.json index 63d8ebf..ed168c2 100644 --- a/data/chips/STM32H745ZI.json +++ b/data/chips/STM32H745ZI.json @@ -8150,7 +8150,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8215,7 +8218,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -16913,7 +16919,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -16978,7 +16987,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index 20f6421..5254f3d 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -8360,7 +8360,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8425,7 +8428,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -17342,7 +17348,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -17407,7 +17416,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index 8069493..6ca0658 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -8371,7 +8371,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8436,7 +8439,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -17353,7 +17359,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -17418,7 +17427,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index d0e11c3..f7e0642 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -9025,7 +9025,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9090,7 +9093,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -18682,7 +18688,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -18747,7 +18756,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index 58066e7..f26aa44 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -9036,7 +9036,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9101,7 +9104,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -18693,7 +18699,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -18758,7 +18767,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index df71dec..39a5dc9 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -8360,7 +8360,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8425,7 +8428,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -17342,7 +17348,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -17407,7 +17416,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index 883deb4..9a74727 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -8371,7 +8371,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8436,7 +8439,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -17353,7 +17359,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -17418,7 +17427,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index 4c843ba..d19dfba 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -9369,7 +9369,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9434,7 +9437,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -19370,7 +19376,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -19435,7 +19444,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index 0dc7685..a9e9bf0 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -9380,7 +9380,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9445,7 +9448,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -19381,7 +19387,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -19446,7 +19455,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index af74cc2..aa49231 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -7828,7 +7828,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -7893,7 +7896,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -16267,7 +16273,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -16332,7 +16341,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H750IB.json b/data/chips/STM32H750IB.json index e3ef62f..6bdc8a7 100644 --- a/data/chips/STM32H750IB.json +++ b/data/chips/STM32H750IB.json @@ -9083,7 +9083,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9148,7 +9151,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H750VB.json b/data/chips/STM32H750VB.json index 345981c..72a6d19 100644 --- a/data/chips/STM32H750VB.json +++ b/data/chips/STM32H750VB.json @@ -7583,7 +7583,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -7648,7 +7651,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H750XB.json b/data/chips/STM32H750XB.json index 05d8b37..7e76413 100644 --- a/data/chips/STM32H750XB.json +++ b/data/chips/STM32H750XB.json @@ -9433,7 +9433,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9498,7 +9501,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H750ZB.json b/data/chips/STM32H750ZB.json index e4c076e..c6007bb 100644 --- a/data/chips/STM32H750ZB.json +++ b/data/chips/STM32H750ZB.json @@ -8412,7 +8412,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8477,7 +8480,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H753AI.json b/data/chips/STM32H753AI.json index ab3f357..77cfa70 100644 --- a/data/chips/STM32H753AI.json +++ b/data/chips/STM32H753AI.json @@ -8850,7 +8850,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8915,7 +8918,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H753BI.json b/data/chips/STM32H753BI.json index e9aed57..d306951 100644 --- a/data/chips/STM32H753BI.json +++ b/data/chips/STM32H753BI.json @@ -9398,7 +9398,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9463,7 +9466,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H753II.json b/data/chips/STM32H753II.json index f007bae..50efed9 100644 --- a/data/chips/STM32H753II.json +++ b/data/chips/STM32H753II.json @@ -9112,7 +9112,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9177,7 +9180,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H753VI.json b/data/chips/STM32H753VI.json index b99b8ca..21e2479 100644 --- a/data/chips/STM32H753VI.json +++ b/data/chips/STM32H753VI.json @@ -7616,7 +7616,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -7681,7 +7684,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H753XI.json b/data/chips/STM32H753XI.json index 32db8cc..ad469f3 100644 --- a/data/chips/STM32H753XI.json +++ b/data/chips/STM32H753XI.json @@ -9462,7 +9462,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9527,7 +9530,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H753ZI.json b/data/chips/STM32H753ZI.json index 619cdf6..a23f3a7 100644 --- a/data/chips/STM32H753ZI.json +++ b/data/chips/STM32H753ZI.json @@ -8453,7 +8453,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8518,7 +8521,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index 4b662b0..a84daf6 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -9284,7 +9284,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9349,7 +9352,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -19189,7 +19195,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -19254,7 +19263,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index e107e78..43ff3c4 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -9035,7 +9035,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9100,7 +9103,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -18682,7 +18688,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -18747,7 +18756,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index 755a47a..0f33a53 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -9453,7 +9453,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9518,7 +9521,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -19527,7 +19533,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -19592,7 +19601,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index b7c8cf9..6db1ed1 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -8229,7 +8229,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8294,7 +8297,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -17069,7 +17075,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -17134,7 +17143,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index 312a680..c62cf7c 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -8450,7 +8450,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8515,7 +8518,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -17509,7 +17515,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -17574,7 +17583,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index 8e540f3..4127494 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -9115,7 +9115,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9180,7 +9183,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -18849,7 +18855,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -18914,7 +18923,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 9e9f811..274b756 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -8450,7 +8450,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -8515,7 +8518,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -17509,7 +17515,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -17574,7 +17583,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 727a896..f58e838 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -9459,7 +9459,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -9524,7 +9527,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -19537,7 +19543,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -19602,7 +19611,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index 936b6ff..ff4c48d 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -7907,7 +7907,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -7972,7 +7975,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" @@ -16423,7 +16429,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_FSEN" @@ -16488,7 +16497,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index 2299fcd..ce88c9a 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -8856,7 +8856,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index aa50fca..0ed0e56 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -8867,7 +8867,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index b39a88e..db7869c 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -9549,7 +9549,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index 4273988..83d5510 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -9560,7 +9560,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index d1cb995..70296c4 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -9726,7 +9726,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index 9fbb6c3..72aaf38 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -9743,7 +9743,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index 1683e85..7b002a8 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -9688,7 +9688,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index edfb890..6498b12 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -9699,7 +9699,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index 497fe87..5d1de09 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -7958,7 +7958,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3RG.json b/data/chips/STM32H7A3RG.json index 77f189b..6394ae3 100644 --- a/data/chips/STM32H7A3RG.json +++ b/data/chips/STM32H7A3RG.json @@ -6018,7 +6018,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3RI.json b/data/chips/STM32H7A3RI.json index 6a2e929..a78ec39 100644 --- a/data/chips/STM32H7A3RI.json +++ b/data/chips/STM32H7A3RI.json @@ -6029,7 +6029,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index 95ae86a..fc76022 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -7694,7 +7694,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index 3c7dc45..54093c4 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -7705,7 +7705,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index 66fe46c..c78c45d 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -8621,7 +8621,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index b0726ce..eceec1f 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -8632,7 +8632,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index efda45d..0c6a485 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -8965,7 +8965,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index b2722be..ccb353b 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -9495,7 +9495,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index aa4ac9d..ba3fbdf 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -6112,7 +6112,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index fe4b934..25cc71c 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -7776,7 +7776,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index c04a12e..3e7cd62 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -8726,7 +8726,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index 2cf4926..bb8f10b 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -8982,7 +8982,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index a294e46..42ff363 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -9675,7 +9675,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index 6cfd83b..4a970a4 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -9858,7 +9858,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index b55f2e1..76a7336 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -9814,7 +9814,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index d6ed809..952c2be 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -8058,7 +8058,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 525efef..ee94eed 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -6129,7 +6129,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index b011ccb..89cb784 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -7805,7 +7805,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index 0ef896b..7a24766 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -8747,7 +8747,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "HCLK1", + "kernel_clock": { + "register": "D2CCIP2R", + "field": "USBSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32L052C6.json b/data/chips/STM32L052C6.json index 1d41708..38cc3dc 100644 --- a/data/chips/STM32L052C6.json +++ b/data/chips/STM32L052C6.json @@ -2250,7 +2250,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L052C8.json b/data/chips/STM32L052C8.json index 8b132aa..cb37c22 100644 --- a/data/chips/STM32L052C8.json +++ b/data/chips/STM32L052C8.json @@ -2250,7 +2250,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L052K6.json b/data/chips/STM32L052K6.json index e170346..f341679 100644 --- a/data/chips/STM32L052K6.json +++ b/data/chips/STM32L052K6.json @@ -1880,7 +1880,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L052K8.json b/data/chips/STM32L052K8.json index fed4584..d00456a 100644 --- a/data/chips/STM32L052K8.json +++ b/data/chips/STM32L052K8.json @@ -1880,7 +1880,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L052R6.json b/data/chips/STM32L052R6.json index fb7aee4..d670ca6 100644 --- a/data/chips/STM32L052R6.json +++ b/data/chips/STM32L052R6.json @@ -2409,7 +2409,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L052R8.json b/data/chips/STM32L052R8.json index 0de3057..2564da3 100644 --- a/data/chips/STM32L052R8.json +++ b/data/chips/STM32L052R8.json @@ -2409,7 +2409,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L052T6.json b/data/chips/STM32L052T6.json index 7ab52c8..c8af93f 100644 --- a/data/chips/STM32L052T6.json +++ b/data/chips/STM32L052T6.json @@ -2031,7 +2031,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L052T8.json b/data/chips/STM32L052T8.json index 37b4153..c09b13a 100644 --- a/data/chips/STM32L052T8.json +++ b/data/chips/STM32L052T8.json @@ -2035,7 +2035,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L053C6.json b/data/chips/STM32L053C6.json index ced37c8..1d8a0ef 100644 --- a/data/chips/STM32L053C6.json +++ b/data/chips/STM32L053C6.json @@ -2389,7 +2389,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L053C8.json b/data/chips/STM32L053C8.json index f8f6b78..a3becda 100644 --- a/data/chips/STM32L053C8.json +++ b/data/chips/STM32L053C8.json @@ -2389,7 +2389,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L053R6.json b/data/chips/STM32L053R6.json index 2eae97c..e0ccd40 100644 --- a/data/chips/STM32L053R6.json +++ b/data/chips/STM32L053R6.json @@ -2638,7 +2638,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L053R8.json b/data/chips/STM32L053R8.json index d84b331..910d0b9 100644 --- a/data/chips/STM32L053R8.json +++ b/data/chips/STM32L053R8.json @@ -2638,7 +2638,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L062C8.json b/data/chips/STM32L062C8.json index 05342fa..e5ed87e 100644 --- a/data/chips/STM32L062C8.json +++ b/data/chips/STM32L062C8.json @@ -2271,7 +2271,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L062K8.json b/data/chips/STM32L062K8.json index 484fd28..4c23bf5 100644 --- a/data/chips/STM32L062K8.json +++ b/data/chips/STM32L062K8.json @@ -1917,7 +1917,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L063C8.json b/data/chips/STM32L063C8.json index 64e9db8..6169cd9 100644 --- a/data/chips/STM32L063C8.json +++ b/data/chips/STM32L063C8.json @@ -2426,7 +2426,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L063R8.json b/data/chips/STM32L063R8.json index ef31590..5e2a1bb 100644 --- a/data/chips/STM32L063R8.json +++ b/data/chips/STM32L063R8.json @@ -2671,7 +2671,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L072CB.json b/data/chips/STM32L072CB.json index e09b9d2..71d4a39 100644 --- a/data/chips/STM32L072CB.json +++ b/data/chips/STM32L072CB.json @@ -2797,7 +2797,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L072CZ.json b/data/chips/STM32L072CZ.json index 4c62506..14cef6e 100644 --- a/data/chips/STM32L072CZ.json +++ b/data/chips/STM32L072CZ.json @@ -2801,7 +2801,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L072KB.json b/data/chips/STM32L072KB.json index e9ef4a8..12a54ab 100644 --- a/data/chips/STM32L072KB.json +++ b/data/chips/STM32L072KB.json @@ -2381,7 +2381,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L072KZ.json b/data/chips/STM32L072KZ.json index cddd7fd..2b0242d 100644 --- a/data/chips/STM32L072KZ.json +++ b/data/chips/STM32L072KZ.json @@ -2381,7 +2381,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L072RB.json b/data/chips/STM32L072RB.json index 233fa93..d7508ed 100644 --- a/data/chips/STM32L072RB.json +++ b/data/chips/STM32L072RB.json @@ -2959,7 +2959,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L072RZ.json b/data/chips/STM32L072RZ.json index 55233b1..f4360d0 100644 --- a/data/chips/STM32L072RZ.json +++ b/data/chips/STM32L072RZ.json @@ -2959,7 +2959,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L072V8.json b/data/chips/STM32L072V8.json index ceaf10c..3b37d95 100644 --- a/data/chips/STM32L072V8.json +++ b/data/chips/STM32L072V8.json @@ -3194,7 +3194,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L072VB.json b/data/chips/STM32L072VB.json index 04e9c18..8ec59f0 100644 --- a/data/chips/STM32L072VB.json +++ b/data/chips/STM32L072VB.json @@ -3194,7 +3194,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L072VZ.json b/data/chips/STM32L072VZ.json index 40d01c8..99f7a1e 100644 --- a/data/chips/STM32L072VZ.json +++ b/data/chips/STM32L072VZ.json @@ -3194,7 +3194,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L073CB.json b/data/chips/STM32L073CB.json index 7e122df..de734f4 100644 --- a/data/chips/STM32L073CB.json +++ b/data/chips/STM32L073CB.json @@ -2947,7 +2947,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L073CZ.json b/data/chips/STM32L073CZ.json index 6e41032..105945a 100644 --- a/data/chips/STM32L073CZ.json +++ b/data/chips/STM32L073CZ.json @@ -2951,7 +2951,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L073RB.json b/data/chips/STM32L073RB.json index 1815eb4..c4484c4 100644 --- a/data/chips/STM32L073RB.json +++ b/data/chips/STM32L073RB.json @@ -3184,7 +3184,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L073RZ.json b/data/chips/STM32L073RZ.json index afd9be7..e23de2c 100644 --- a/data/chips/STM32L073RZ.json +++ b/data/chips/STM32L073RZ.json @@ -3188,7 +3188,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L073V8.json b/data/chips/STM32L073V8.json index d9ab84f..7501394 100644 --- a/data/chips/STM32L073V8.json +++ b/data/chips/STM32L073V8.json @@ -3551,7 +3551,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L073VB.json b/data/chips/STM32L073VB.json index af6b784..677a05f 100644 --- a/data/chips/STM32L073VB.json +++ b/data/chips/STM32L073VB.json @@ -3551,7 +3551,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L073VZ.json b/data/chips/STM32L073VZ.json index f06bc88..9a28aae 100644 --- a/data/chips/STM32L073VZ.json +++ b/data/chips/STM32L073VZ.json @@ -3551,7 +3551,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L082CZ.json b/data/chips/STM32L082CZ.json index 18bf8fa..60ddb73 100644 --- a/data/chips/STM32L082CZ.json +++ b/data/chips/STM32L082CZ.json @@ -2830,7 +2830,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L082KB.json b/data/chips/STM32L082KB.json index 4f2984c..bea935d 100644 --- a/data/chips/STM32L082KB.json +++ b/data/chips/STM32L082KB.json @@ -2418,7 +2418,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L082KZ.json b/data/chips/STM32L082KZ.json index 4bed7f7..e2d3d4a 100644 --- a/data/chips/STM32L082KZ.json +++ b/data/chips/STM32L082KZ.json @@ -2418,7 +2418,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L083CB.json b/data/chips/STM32L083CB.json index 75435ce..e10273e 100644 --- a/data/chips/STM32L083CB.json +++ b/data/chips/STM32L083CB.json @@ -2893,7 +2893,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L083CZ.json b/data/chips/STM32L083CZ.json index 415680d..dea3be0 100644 --- a/data/chips/STM32L083CZ.json +++ b/data/chips/STM32L083CZ.json @@ -2897,7 +2897,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L083RB.json b/data/chips/STM32L083RB.json index bfce2cc..3fc5628 100644 --- a/data/chips/STM32L083RB.json +++ b/data/chips/STM32L083RB.json @@ -3221,7 +3221,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L083RZ.json b/data/chips/STM32L083RZ.json index a205508..063ef0e 100644 --- a/data/chips/STM32L083RZ.json +++ b/data/chips/STM32L083RZ.json @@ -3221,7 +3221,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L083V8.json b/data/chips/STM32L083V8.json index 86db942..7e2ace7 100644 --- a/data/chips/STM32L083V8.json +++ b/data/chips/STM32L083V8.json @@ -3588,7 +3588,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L083VB.json b/data/chips/STM32L083VB.json index 6fe4b0e..1acbebf 100644 --- a/data/chips/STM32L083VB.json +++ b/data/chips/STM32L083VB.json @@ -3588,7 +3588,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L083VZ.json b/data/chips/STM32L083VZ.json index d8abc9b..3bd6a93 100644 --- a/data/chips/STM32L083VZ.json +++ b/data/chips/STM32L083VZ.json @@ -3588,7 +3588,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L100C6-A.json b/data/chips/STM32L100C6-A.json index b97107f..5db9797 100644 --- a/data/chips/STM32L100C6-A.json +++ b/data/chips/STM32L100C6-A.json @@ -2204,7 +2204,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L100C6.json b/data/chips/STM32L100C6.json index 51d4196..ab506ce 100644 --- a/data/chips/STM32L100C6.json +++ b/data/chips/STM32L100C6.json @@ -2190,7 +2190,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L100R8-A.json b/data/chips/STM32L100R8-A.json index 8063f03..1999400 100644 --- a/data/chips/STM32L100R8-A.json +++ b/data/chips/STM32L100R8-A.json @@ -2382,7 +2382,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L100R8.json b/data/chips/STM32L100R8.json index 61a4251..0471fe0 100644 --- a/data/chips/STM32L100R8.json +++ b/data/chips/STM32L100R8.json @@ -2368,7 +2368,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L100RB-A.json b/data/chips/STM32L100RB-A.json index fa1f80e..e9ba938 100644 --- a/data/chips/STM32L100RB-A.json +++ b/data/chips/STM32L100RB-A.json @@ -2382,7 +2382,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L100RB.json b/data/chips/STM32L100RB.json index afbe62f..33635c7 100644 --- a/data/chips/STM32L100RB.json +++ b/data/chips/STM32L100RB.json @@ -2368,7 +2368,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L100RC.json b/data/chips/STM32L100RC.json index b89eabe..51e4ea5 100644 --- a/data/chips/STM32L100RC.json +++ b/data/chips/STM32L100RC.json @@ -2585,7 +2585,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151C6-A.json b/data/chips/STM32L151C6-A.json index 779dde0..f31c9a1 100644 --- a/data/chips/STM32L151C6-A.json +++ b/data/chips/STM32L151C6-A.json @@ -2090,7 +2090,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151C6.json b/data/chips/STM32L151C6.json index 59339bf..6801f54 100644 --- a/data/chips/STM32L151C6.json +++ b/data/chips/STM32L151C6.json @@ -2082,7 +2082,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151C8-A.json b/data/chips/STM32L151C8-A.json index cf996fd..dd797bc 100644 --- a/data/chips/STM32L151C8-A.json +++ b/data/chips/STM32L151C8-A.json @@ -2090,7 +2090,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151C8.json b/data/chips/STM32L151C8.json index ff44d85..546339b 100644 --- a/data/chips/STM32L151C8.json +++ b/data/chips/STM32L151C8.json @@ -2082,7 +2082,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151CB-A.json b/data/chips/STM32L151CB-A.json index 267147a..332d979 100644 --- a/data/chips/STM32L151CB-A.json +++ b/data/chips/STM32L151CB-A.json @@ -2090,7 +2090,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151CB.json b/data/chips/STM32L151CB.json index 091964d..a02607f 100644 --- a/data/chips/STM32L151CB.json +++ b/data/chips/STM32L151CB.json @@ -2082,7 +2082,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151CC.json b/data/chips/STM32L151CC.json index 88d09f1..bb09ae1 100644 --- a/data/chips/STM32L151CC.json +++ b/data/chips/STM32L151CC.json @@ -2381,7 +2381,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151QC.json b/data/chips/STM32L151QC.json index 380b115..2a25c51 100644 --- a/data/chips/STM32L151QC.json +++ b/data/chips/STM32L151QC.json @@ -2884,7 +2884,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151QD.json b/data/chips/STM32L151QD.json index e63504d..7c860d5 100644 --- a/data/chips/STM32L151QD.json +++ b/data/chips/STM32L151QD.json @@ -3403,7 +3403,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151QE.json b/data/chips/STM32L151QE.json index f38ce1d..f9154f2 100644 --- a/data/chips/STM32L151QE.json +++ b/data/chips/STM32L151QE.json @@ -2967,7 +2967,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151R6-A.json b/data/chips/STM32L151R6-A.json index 2e81339..7d84b0d 100644 --- a/data/chips/STM32L151R6-A.json +++ b/data/chips/STM32L151R6-A.json @@ -2178,7 +2178,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151R6.json b/data/chips/STM32L151R6.json index 7f5f7c0..b07d1c2 100644 --- a/data/chips/STM32L151R6.json +++ b/data/chips/STM32L151R6.json @@ -2170,7 +2170,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151R8-A.json b/data/chips/STM32L151R8-A.json index 4c6ee29..d6336ed 100644 --- a/data/chips/STM32L151R8-A.json +++ b/data/chips/STM32L151R8-A.json @@ -2178,7 +2178,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151R8.json b/data/chips/STM32L151R8.json index 769ded5..5028e6d 100644 --- a/data/chips/STM32L151R8.json +++ b/data/chips/STM32L151R8.json @@ -2170,7 +2170,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151RB-A.json b/data/chips/STM32L151RB-A.json index 2674b41..919a752 100644 --- a/data/chips/STM32L151RB-A.json +++ b/data/chips/STM32L151RB-A.json @@ -2178,7 +2178,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151RB.json b/data/chips/STM32L151RB.json index c0c2146..31c2590 100644 --- a/data/chips/STM32L151RB.json +++ b/data/chips/STM32L151RB.json @@ -2170,7 +2170,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151RC-A.json b/data/chips/STM32L151RC-A.json index 846083e..301686e 100644 --- a/data/chips/STM32L151RC-A.json +++ b/data/chips/STM32L151RC-A.json @@ -2547,7 +2547,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151RC.json b/data/chips/STM32L151RC.json index 2771e30..ddefd1f 100644 --- a/data/chips/STM32L151RC.json +++ b/data/chips/STM32L151RC.json @@ -2510,7 +2510,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151RD.json b/data/chips/STM32L151RD.json index 05fd688..af5fbf6 100644 --- a/data/chips/STM32L151RD.json +++ b/data/chips/STM32L151RD.json @@ -2718,7 +2718,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151RE.json b/data/chips/STM32L151RE.json index 705f92d..4c36d62 100644 --- a/data/chips/STM32L151RE.json +++ b/data/chips/STM32L151RE.json @@ -2640,7 +2640,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151UC.json b/data/chips/STM32L151UC.json index f80021b..6452c18 100644 --- a/data/chips/STM32L151UC.json +++ b/data/chips/STM32L151UC.json @@ -2500,7 +2500,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151V8-A.json b/data/chips/STM32L151V8-A.json index 091a8d0..29332cf 100644 --- a/data/chips/STM32L151V8-A.json +++ b/data/chips/STM32L151V8-A.json @@ -2399,7 +2399,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151V8.json b/data/chips/STM32L151V8.json index 1044bfe..6f2c789 100644 --- a/data/chips/STM32L151V8.json +++ b/data/chips/STM32L151V8.json @@ -2386,7 +2386,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151VB-A.json b/data/chips/STM32L151VB-A.json index 0aa02d0..505f211 100644 --- a/data/chips/STM32L151VB-A.json +++ b/data/chips/STM32L151VB-A.json @@ -2399,7 +2399,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151VB.json b/data/chips/STM32L151VB.json index 3f80ee9..e26c807 100644 --- a/data/chips/STM32L151VB.json +++ b/data/chips/STM32L151VB.json @@ -2386,7 +2386,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151VC-A.json b/data/chips/STM32L151VC-A.json index cf9ac78..2757aed 100644 --- a/data/chips/STM32L151VC-A.json +++ b/data/chips/STM32L151VC-A.json @@ -2783,7 +2783,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151VC.json b/data/chips/STM32L151VC.json index cada82f..5b0bfdd 100644 --- a/data/chips/STM32L151VC.json +++ b/data/chips/STM32L151VC.json @@ -2745,7 +2745,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151VD-X.json b/data/chips/STM32L151VD-X.json index 4c42d44..86753c2 100644 --- a/data/chips/STM32L151VD-X.json +++ b/data/chips/STM32L151VD-X.json @@ -2884,7 +2884,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151VD.json b/data/chips/STM32L151VD.json index 3ed328d..bb686b2 100644 --- a/data/chips/STM32L151VD.json +++ b/data/chips/STM32L151VD.json @@ -3213,7 +3213,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151VE.json b/data/chips/STM32L151VE.json index 80a3097..9ea6a24 100644 --- a/data/chips/STM32L151VE.json +++ b/data/chips/STM32L151VE.json @@ -2884,7 +2884,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151ZC.json b/data/chips/STM32L151ZC.json index 325e893..5978a44 100644 --- a/data/chips/STM32L151ZC.json +++ b/data/chips/STM32L151ZC.json @@ -2900,7 +2900,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151ZD.json b/data/chips/STM32L151ZD.json index e9eb179..b193a8e 100644 --- a/data/chips/STM32L151ZD.json +++ b/data/chips/STM32L151ZD.json @@ -3423,7 +3423,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L151ZE.json b/data/chips/STM32L151ZE.json index a3ad970..4bc2cd6 100644 --- a/data/chips/STM32L151ZE.json +++ b/data/chips/STM32L151ZE.json @@ -2984,7 +2984,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152C6-A.json b/data/chips/STM32L152C6-A.json index f9f0115..63042da 100644 --- a/data/chips/STM32L152C6-A.json +++ b/data/chips/STM32L152C6-A.json @@ -2229,7 +2229,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152C6.json b/data/chips/STM32L152C6.json index 63eeb4a..b07a923 100644 --- a/data/chips/STM32L152C6.json +++ b/data/chips/STM32L152C6.json @@ -2221,7 +2221,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152C8-A.json b/data/chips/STM32L152C8-A.json index 6f52c59..82efa26 100644 --- a/data/chips/STM32L152C8-A.json +++ b/data/chips/STM32L152C8-A.json @@ -2229,7 +2229,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152C8.json b/data/chips/STM32L152C8.json index 64720bd..a8f52f7 100644 --- a/data/chips/STM32L152C8.json +++ b/data/chips/STM32L152C8.json @@ -2221,7 +2221,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152CB-A.json b/data/chips/STM32L152CB-A.json index 51ad527..38ea178 100644 --- a/data/chips/STM32L152CB-A.json +++ b/data/chips/STM32L152CB-A.json @@ -2229,7 +2229,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152CB.json b/data/chips/STM32L152CB.json index c848ff5..cb118f4 100644 --- a/data/chips/STM32L152CB.json +++ b/data/chips/STM32L152CB.json @@ -2221,7 +2221,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152CC.json b/data/chips/STM32L152CC.json index a42292e..01f906d 100644 --- a/data/chips/STM32L152CC.json +++ b/data/chips/STM32L152CC.json @@ -2520,7 +2520,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152QC.json b/data/chips/STM32L152QC.json index aff3ce3..c256013 100644 --- a/data/chips/STM32L152QC.json +++ b/data/chips/STM32L152QC.json @@ -3193,7 +3193,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152QD.json b/data/chips/STM32L152QD.json index 6d17319..9c4347f 100644 --- a/data/chips/STM32L152QD.json +++ b/data/chips/STM32L152QD.json @@ -3712,7 +3712,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152QE.json b/data/chips/STM32L152QE.json index 3cbb318..31d7d29 100644 --- a/data/chips/STM32L152QE.json +++ b/data/chips/STM32L152QE.json @@ -3276,7 +3276,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152R6-A.json b/data/chips/STM32L152R6-A.json index 450666e..f3430f7 100644 --- a/data/chips/STM32L152R6-A.json +++ b/data/chips/STM32L152R6-A.json @@ -2427,7 +2427,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152R6.json b/data/chips/STM32L152R6.json index c9b77db..b5bdf72 100644 --- a/data/chips/STM32L152R6.json +++ b/data/chips/STM32L152R6.json @@ -2399,7 +2399,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152R8-A.json b/data/chips/STM32L152R8-A.json index 7c111eb..e5d25a7 100644 --- a/data/chips/STM32L152R8-A.json +++ b/data/chips/STM32L152R8-A.json @@ -2427,7 +2427,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152R8.json b/data/chips/STM32L152R8.json index b816342..0e4a072 100644 --- a/data/chips/STM32L152R8.json +++ b/data/chips/STM32L152R8.json @@ -2399,7 +2399,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152RB-A.json b/data/chips/STM32L152RB-A.json index 2f9fd96..4eb25c1 100644 --- a/data/chips/STM32L152RB-A.json +++ b/data/chips/STM32L152RB-A.json @@ -2427,7 +2427,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152RB.json b/data/chips/STM32L152RB.json index db7a678..d16fe7d 100644 --- a/data/chips/STM32L152RB.json +++ b/data/chips/STM32L152RB.json @@ -2399,7 +2399,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152RC-A.json b/data/chips/STM32L152RC-A.json index 814f615..144f5fa 100644 --- a/data/chips/STM32L152RC-A.json +++ b/data/chips/STM32L152RC-A.json @@ -2796,7 +2796,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152RC.json b/data/chips/STM32L152RC.json index 3db0309..b35eb69 100644 --- a/data/chips/STM32L152RC.json +++ b/data/chips/STM32L152RC.json @@ -2735,7 +2735,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152RD.json b/data/chips/STM32L152RD.json index 66bda2c..2258377 100644 --- a/data/chips/STM32L152RD.json +++ b/data/chips/STM32L152RD.json @@ -2967,7 +2967,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152RE.json b/data/chips/STM32L152RE.json index 347b08c..88fc8e9 100644 --- a/data/chips/STM32L152RE.json +++ b/data/chips/STM32L152RE.json @@ -2889,7 +2889,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152UC.json b/data/chips/STM32L152UC.json index 0085908..34fa267 100644 --- a/data/chips/STM32L152UC.json +++ b/data/chips/STM32L152UC.json @@ -2729,7 +2729,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152V8-A.json b/data/chips/STM32L152V8-A.json index f0f9ecd..dd51100 100644 --- a/data/chips/STM32L152V8-A.json +++ b/data/chips/STM32L152V8-A.json @@ -2708,7 +2708,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152V8.json b/data/chips/STM32L152V8.json index 79e477b..5104a9e 100644 --- a/data/chips/STM32L152V8.json +++ b/data/chips/STM32L152V8.json @@ -2695,7 +2695,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152VB-A.json b/data/chips/STM32L152VB-A.json index 92bd803..d359ba9 100644 --- a/data/chips/STM32L152VB-A.json +++ b/data/chips/STM32L152VB-A.json @@ -2708,7 +2708,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152VB.json b/data/chips/STM32L152VB.json index e6b1904..b04497e 100644 --- a/data/chips/STM32L152VB.json +++ b/data/chips/STM32L152VB.json @@ -2695,7 +2695,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152VC-A.json b/data/chips/STM32L152VC-A.json index 268d499..df82883 100644 --- a/data/chips/STM32L152VC-A.json +++ b/data/chips/STM32L152VC-A.json @@ -3092,7 +3092,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152VC.json b/data/chips/STM32L152VC.json index ff22298..58370ef 100644 --- a/data/chips/STM32L152VC.json +++ b/data/chips/STM32L152VC.json @@ -3060,7 +3060,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152VD-X.json b/data/chips/STM32L152VD-X.json index 5f88751..35367ca 100644 --- a/data/chips/STM32L152VD-X.json +++ b/data/chips/STM32L152VD-X.json @@ -3189,7 +3189,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152VD.json b/data/chips/STM32L152VD.json index a0ecfff..d6800e7 100644 --- a/data/chips/STM32L152VD.json +++ b/data/chips/STM32L152VD.json @@ -3522,7 +3522,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152VE.json b/data/chips/STM32L152VE.json index 78f73e2..0b4831d 100644 --- a/data/chips/STM32L152VE.json +++ b/data/chips/STM32L152VE.json @@ -3193,7 +3193,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152ZC.json b/data/chips/STM32L152ZC.json index 547bafd..c2d6da6 100644 --- a/data/chips/STM32L152ZC.json +++ b/data/chips/STM32L152ZC.json @@ -3209,7 +3209,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152ZD.json b/data/chips/STM32L152ZD.json index a8ed19e..3edc5e5 100644 --- a/data/chips/STM32L152ZD.json +++ b/data/chips/STM32L152ZD.json @@ -3732,7 +3732,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L152ZE.json b/data/chips/STM32L152ZE.json index 4c1355f..8f5d75e 100644 --- a/data/chips/STM32L152ZE.json +++ b/data/chips/STM32L152ZE.json @@ -3293,7 +3293,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162QC.json b/data/chips/STM32L162QC.json index 1058ee1..b9c689f 100644 --- a/data/chips/STM32L162QC.json +++ b/data/chips/STM32L162QC.json @@ -3212,7 +3212,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162QD.json b/data/chips/STM32L162QD.json index 3ead0a0..96fa6a8 100644 --- a/data/chips/STM32L162QD.json +++ b/data/chips/STM32L162QD.json @@ -3737,7 +3737,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162RC-A.json b/data/chips/STM32L162RC-A.json index e9d5bff..6c656d8 100644 --- a/data/chips/STM32L162RC-A.json +++ b/data/chips/STM32L162RC-A.json @@ -2821,7 +2821,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162RC.json b/data/chips/STM32L162RC.json index 716f0ce..094bfca 100644 --- a/data/chips/STM32L162RC.json +++ b/data/chips/STM32L162RC.json @@ -2754,7 +2754,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162RD.json b/data/chips/STM32L162RD.json index 69f1bf6..932935f 100644 --- a/data/chips/STM32L162RD.json +++ b/data/chips/STM32L162RD.json @@ -2986,7 +2986,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162RE.json b/data/chips/STM32L162RE.json index fb4d090..c84ac1e 100644 --- a/data/chips/STM32L162RE.json +++ b/data/chips/STM32L162RE.json @@ -2914,7 +2914,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162VC-A.json b/data/chips/STM32L162VC-A.json index df6f469..0e9b262 100644 --- a/data/chips/STM32L162VC-A.json +++ b/data/chips/STM32L162VC-A.json @@ -3117,7 +3117,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162VC.json b/data/chips/STM32L162VC.json index c0e2277..44381c7 100644 --- a/data/chips/STM32L162VC.json +++ b/data/chips/STM32L162VC.json @@ -3079,7 +3079,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162VD-X.json b/data/chips/STM32L162VD-X.json index 8315992..8a9de8f 100644 --- a/data/chips/STM32L162VD-X.json +++ b/data/chips/STM32L162VD-X.json @@ -3214,7 +3214,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162VD.json b/data/chips/STM32L162VD.json index 320429c..8be2909 100644 --- a/data/chips/STM32L162VD.json +++ b/data/chips/STM32L162VD.json @@ -3547,7 +3547,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162VE.json b/data/chips/STM32L162VE.json index 3a2f4d6..233e196 100644 --- a/data/chips/STM32L162VE.json +++ b/data/chips/STM32L162VE.json @@ -3218,7 +3218,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162ZC.json b/data/chips/STM32L162ZC.json index 85e53cd..93ec8a4 100644 --- a/data/chips/STM32L162ZC.json +++ b/data/chips/STM32L162ZC.json @@ -3228,7 +3228,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162ZD.json b/data/chips/STM32L162ZD.json index 4aff806..30b7ce4 100644 --- a/data/chips/STM32L162ZD.json +++ b/data/chips/STM32L162ZD.json @@ -3757,7 +3757,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L162ZE.json b/data/chips/STM32L162ZE.json index 183622a..240589a 100644 --- a/data/chips/STM32L162ZE.json +++ b/data/chips/STM32L162ZE.json @@ -3318,7 +3318,7 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": "PLL1_VCO_DIV_2", "enable": { "register": "APB1ENR", "field": "USBEN" diff --git a/data/chips/STM32L412C8.json b/data/chips/STM32L412C8.json index 5cd4fd7..6a42a0f 100644 --- a/data/chips/STM32L412C8.json +++ b/data/chips/STM32L412C8.json @@ -2853,7 +2853,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L412CB.json b/data/chips/STM32L412CB.json index 4956568..8bf9759 100644 --- a/data/chips/STM32L412CB.json +++ b/data/chips/STM32L412CB.json @@ -2861,7 +2861,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L412K8.json b/data/chips/STM32L412K8.json index 407166d..158c791 100644 --- a/data/chips/STM32L412K8.json +++ b/data/chips/STM32L412K8.json @@ -2426,7 +2426,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L412KB.json b/data/chips/STM32L412KB.json index 0112cc9..5317dad 100644 --- a/data/chips/STM32L412KB.json +++ b/data/chips/STM32L412KB.json @@ -2426,7 +2426,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L412R8.json b/data/chips/STM32L412R8.json index 7615092..1653182 100644 --- a/data/chips/STM32L412R8.json +++ b/data/chips/STM32L412R8.json @@ -3049,7 +3049,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L412RB.json b/data/chips/STM32L412RB.json index 31e3529..a92e224 100644 --- a/data/chips/STM32L412RB.json +++ b/data/chips/STM32L412RB.json @@ -3063,7 +3063,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L412T8.json b/data/chips/STM32L412T8.json index 03d901b..5e954ea 100644 --- a/data/chips/STM32L412T8.json +++ b/data/chips/STM32L412T8.json @@ -2486,7 +2486,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L412TB.json b/data/chips/STM32L412TB.json index 9cd175c..9d6758c 100644 --- a/data/chips/STM32L412TB.json +++ b/data/chips/STM32L412TB.json @@ -2490,7 +2490,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L422CB.json b/data/chips/STM32L422CB.json index 37b6b79..72ff366 100644 --- a/data/chips/STM32L422CB.json +++ b/data/chips/STM32L422CB.json @@ -2902,7 +2902,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L422KB.json b/data/chips/STM32L422KB.json index 42cb3da..f593adb 100644 --- a/data/chips/STM32L422KB.json +++ b/data/chips/STM32L422KB.json @@ -2475,7 +2475,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L422RB.json b/data/chips/STM32L422RB.json index 7a36ce3..00ee931 100644 --- a/data/chips/STM32L422RB.json +++ b/data/chips/STM32L422RB.json @@ -3104,7 +3104,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L422TB.json b/data/chips/STM32L422TB.json index d95ac85..4f4f9b2 100644 --- a/data/chips/STM32L422TB.json +++ b/data/chips/STM32L422TB.json @@ -2535,7 +2535,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L432KB.json b/data/chips/STM32L432KB.json index ceb67c9..86d6772 100644 --- a/data/chips/STM32L432KB.json +++ b/data/chips/STM32L432KB.json @@ -2786,7 +2786,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L432KC.json b/data/chips/STM32L432KC.json index 4aedea3..ef16a9e 100644 --- a/data/chips/STM32L432KC.json +++ b/data/chips/STM32L432KC.json @@ -2786,7 +2786,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L433CB.json b/data/chips/STM32L433CB.json index d86836d..8658970 100644 --- a/data/chips/STM32L433CB.json +++ b/data/chips/STM32L433CB.json @@ -3522,7 +3522,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L433CC.json b/data/chips/STM32L433CC.json index 450e0dc..1f33c3e 100644 --- a/data/chips/STM32L433CC.json +++ b/data/chips/STM32L433CC.json @@ -3522,7 +3522,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L433RB.json b/data/chips/STM32L433RB.json index 1cd2c69..8598dae 100644 --- a/data/chips/STM32L433RB.json +++ b/data/chips/STM32L433RB.json @@ -3906,7 +3906,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L433RC.json b/data/chips/STM32L433RC.json index 3cba00b..768583c 100644 --- a/data/chips/STM32L433RC.json +++ b/data/chips/STM32L433RC.json @@ -3916,7 +3916,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L433VC.json b/data/chips/STM32L433VC.json index 4494af7..1125c08 100644 --- a/data/chips/STM32L433VC.json +++ b/data/chips/STM32L433VC.json @@ -4321,7 +4321,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L442KC.json b/data/chips/STM32L442KC.json index 089ea83..e35a374 100644 --- a/data/chips/STM32L442KC.json +++ b/data/chips/STM32L442KC.json @@ -2835,7 +2835,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L443CC.json b/data/chips/STM32L443CC.json index e7a8f95..8f80d3d 100644 --- a/data/chips/STM32L443CC.json +++ b/data/chips/STM32L443CC.json @@ -3575,7 +3575,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L443RC.json b/data/chips/STM32L443RC.json index 46c3e6e..467427d 100644 --- a/data/chips/STM32L443RC.json +++ b/data/chips/STM32L443RC.json @@ -3955,7 +3955,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L443VC.json b/data/chips/STM32L443VC.json index 15d48a7..d9ff415 100644 --- a/data/chips/STM32L443VC.json +++ b/data/chips/STM32L443VC.json @@ -4370,7 +4370,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L452CC.json b/data/chips/STM32L452CC.json index f9e1301..d72f572 100644 --- a/data/chips/STM32L452CC.json +++ b/data/chips/STM32L452CC.json @@ -3573,7 +3573,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L452CE.json b/data/chips/STM32L452CE.json index facab27..62dbd75 100644 --- a/data/chips/STM32L452CE.json +++ b/data/chips/STM32L452CE.json @@ -3581,7 +3581,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L452RC.json b/data/chips/STM32L452RC.json index 590627d..58944f0 100644 --- a/data/chips/STM32L452RC.json +++ b/data/chips/STM32L452RC.json @@ -3944,7 +3944,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L452RE.json b/data/chips/STM32L452RE.json index 1bc9bec..5682714 100644 --- a/data/chips/STM32L452RE.json +++ b/data/chips/STM32L452RE.json @@ -3958,7 +3958,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L452VC.json b/data/chips/STM32L452VC.json index 8dc51de..233d6ef 100644 --- a/data/chips/STM32L452VC.json +++ b/data/chips/STM32L452VC.json @@ -4384,7 +4384,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L452VE.json b/data/chips/STM32L452VE.json index 1cbf0ff..1e5b586 100644 --- a/data/chips/STM32L452VE.json +++ b/data/chips/STM32L452VE.json @@ -4384,7 +4384,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L462CE.json b/data/chips/STM32L462CE.json index 0ae017c..ecaae09 100644 --- a/data/chips/STM32L462CE.json +++ b/data/chips/STM32L462CE.json @@ -3632,7 +3632,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L462RE.json b/data/chips/STM32L462RE.json index e206f6a..416752c 100644 --- a/data/chips/STM32L462RE.json +++ b/data/chips/STM32L462RE.json @@ -3993,7 +3993,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L462VE.json b/data/chips/STM32L462VE.json index 88493f1..4b5c28d 100644 --- a/data/chips/STM32L462VE.json +++ b/data/chips/STM32L462VE.json @@ -4433,7 +4433,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32L475RC.json b/data/chips/STM32L475RC.json index 92d5147..e4e3567 100644 --- a/data/chips/STM32L475RC.json +++ b/data/chips/STM32L475RC.json @@ -4592,7 +4592,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L475RE.json b/data/chips/STM32L475RE.json index 17e8946..24bb7b9 100644 --- a/data/chips/STM32L475RE.json +++ b/data/chips/STM32L475RE.json @@ -4592,7 +4592,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L475RG.json b/data/chips/STM32L475RG.json index 8019198..a14f747 100644 --- a/data/chips/STM32L475RG.json +++ b/data/chips/STM32L475RG.json @@ -4603,7 +4603,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L475VC.json b/data/chips/STM32L475VC.json index 291c626..50f84ce 100644 --- a/data/chips/STM32L475VC.json +++ b/data/chips/STM32L475VC.json @@ -5348,7 +5348,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L475VE.json b/data/chips/STM32L475VE.json index dcf37ac..ff9b251 100644 --- a/data/chips/STM32L475VE.json +++ b/data/chips/STM32L475VE.json @@ -5348,7 +5348,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L475VG.json b/data/chips/STM32L475VG.json index bdd38dd..d7b90e5 100644 --- a/data/chips/STM32L475VG.json +++ b/data/chips/STM32L475VG.json @@ -5359,7 +5359,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476JE.json b/data/chips/STM32L476JE.json index d999790..285a45e 100644 --- a/data/chips/STM32L476JE.json +++ b/data/chips/STM32L476JE.json @@ -4980,7 +4980,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476JG.json b/data/chips/STM32L476JG.json index c5d7a6b..97d091c 100644 --- a/data/chips/STM32L476JG.json +++ b/data/chips/STM32L476JG.json @@ -5001,7 +5001,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476ME.json b/data/chips/STM32L476ME.json index 67d28a3..9a9305f 100644 --- a/data/chips/STM32L476ME.json +++ b/data/chips/STM32L476ME.json @@ -5085,7 +5085,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476MG.json b/data/chips/STM32L476MG.json index 4c8ca52..af65818 100644 --- a/data/chips/STM32L476MG.json +++ b/data/chips/STM32L476MG.json @@ -5096,7 +5096,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476QE.json b/data/chips/STM32L476QE.json index f5856d6..e5bbf7c 100644 --- a/data/chips/STM32L476QE.json +++ b/data/chips/STM32L476QE.json @@ -6064,7 +6064,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476QG.json b/data/chips/STM32L476QG.json index 762ebab..b69526b 100644 --- a/data/chips/STM32L476QG.json +++ b/data/chips/STM32L476QG.json @@ -6079,7 +6079,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476RC.json b/data/chips/STM32L476RC.json index a8168b7..5f034ec 100644 --- a/data/chips/STM32L476RC.json +++ b/data/chips/STM32L476RC.json @@ -4870,7 +4870,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476RE.json b/data/chips/STM32L476RE.json index 337be40..68ad40a 100644 --- a/data/chips/STM32L476RE.json +++ b/data/chips/STM32L476RE.json @@ -4870,7 +4870,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476RG.json b/data/chips/STM32L476RG.json index a1647a4..31c2bd8 100644 --- a/data/chips/STM32L476RG.json +++ b/data/chips/STM32L476RG.json @@ -4881,7 +4881,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476VC.json b/data/chips/STM32L476VC.json index b494da2..84b26a3 100644 --- a/data/chips/STM32L476VC.json +++ b/data/chips/STM32L476VC.json @@ -5892,7 +5892,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476VE.json b/data/chips/STM32L476VE.json index 404ebf5..b991b7b 100644 --- a/data/chips/STM32L476VE.json +++ b/data/chips/STM32L476VE.json @@ -5892,7 +5892,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476VG.json b/data/chips/STM32L476VG.json index 660e623..a97415d 100644 --- a/data/chips/STM32L476VG.json +++ b/data/chips/STM32L476VG.json @@ -5907,7 +5907,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476ZE.json b/data/chips/STM32L476ZE.json index 60ddcd5..bf68517 100644 --- a/data/chips/STM32L476ZE.json +++ b/data/chips/STM32L476ZE.json @@ -6139,7 +6139,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L476ZG.json b/data/chips/STM32L476ZG.json index 43d855a..d5d8047 100644 --- a/data/chips/STM32L476ZG.json +++ b/data/chips/STM32L476ZG.json @@ -6164,7 +6164,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L486JG.json b/data/chips/STM32L486JG.json index f040732..559a1cd 100644 --- a/data/chips/STM32L486JG.json +++ b/data/chips/STM32L486JG.json @@ -5040,7 +5040,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L486QG.json b/data/chips/STM32L486QG.json index f0165cd..be366a4 100644 --- a/data/chips/STM32L486QG.json +++ b/data/chips/STM32L486QG.json @@ -6124,7 +6124,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L486RG.json b/data/chips/STM32L486RG.json index a82c98a..f81630f 100644 --- a/data/chips/STM32L486RG.json +++ b/data/chips/STM32L486RG.json @@ -4930,7 +4930,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L486VG.json b/data/chips/STM32L486VG.json index a150820..f30393b 100644 --- a/data/chips/STM32L486VG.json +++ b/data/chips/STM32L486VG.json @@ -5752,7 +5752,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L486ZG.json b/data/chips/STM32L486ZG.json index fa44384..195301a 100644 --- a/data/chips/STM32L486ZG.json +++ b/data/chips/STM32L486ZG.json @@ -6199,7 +6199,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L496AE.json b/data/chips/STM32L496AE.json index 9508977..3c2add7 100644 --- a/data/chips/STM32L496AE.json +++ b/data/chips/STM32L496AE.json @@ -6970,7 +6970,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L496AG.json b/data/chips/STM32L496AG.json index 522c4f3..b8701ab 100644 --- a/data/chips/STM32L496AG.json +++ b/data/chips/STM32L496AG.json @@ -6991,7 +6991,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L496QE.json b/data/chips/STM32L496QE.json index 8a3f628..6a93537 100644 --- a/data/chips/STM32L496QE.json +++ b/data/chips/STM32L496QE.json @@ -6726,7 +6726,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L496QG.json b/data/chips/STM32L496QG.json index ecc4bb5..15b2340 100644 --- a/data/chips/STM32L496QG.json +++ b/data/chips/STM32L496QG.json @@ -6745,7 +6745,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L496RE.json b/data/chips/STM32L496RE.json index 1e3847f..66d8786 100644 --- a/data/chips/STM32L496RE.json +++ b/data/chips/STM32L496RE.json @@ -5421,7 +5421,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L496RG.json b/data/chips/STM32L496RG.json index 71b42f6..d0e2841 100644 --- a/data/chips/STM32L496RG.json +++ b/data/chips/STM32L496RG.json @@ -5436,7 +5436,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L496VE.json b/data/chips/STM32L496VE.json index 91ca287..d21bfde 100644 --- a/data/chips/STM32L496VE.json +++ b/data/chips/STM32L496VE.json @@ -6432,7 +6432,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L496VG.json b/data/chips/STM32L496VG.json index 425a1a8..2786050 100644 --- a/data/chips/STM32L496VG.json +++ b/data/chips/STM32L496VG.json @@ -6461,7 +6461,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L496WG.json b/data/chips/STM32L496WG.json index 037980a..7bc88a9 100644 --- a/data/chips/STM32L496WG.json +++ b/data/chips/STM32L496WG.json @@ -6572,7 +6572,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L496ZE.json b/data/chips/STM32L496ZE.json index 1d7eb2d..2e929bf 100644 --- a/data/chips/STM32L496ZE.json +++ b/data/chips/STM32L496ZE.json @@ -6839,7 +6839,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L496ZG.json b/data/chips/STM32L496ZG.json index 62a0db0..2be44e9 100644 --- a/data/chips/STM32L496ZG.json +++ b/data/chips/STM32L496ZG.json @@ -6860,7 +6860,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4A6AG.json b/data/chips/STM32L4A6AG.json index 3cd195d..af33421 100644 --- a/data/chips/STM32L4A6AG.json +++ b/data/chips/STM32L4A6AG.json @@ -7068,7 +7068,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4A6QG.json b/data/chips/STM32L4A6QG.json index 878d85a..38639e3 100644 --- a/data/chips/STM32L4A6QG.json +++ b/data/chips/STM32L4A6QG.json @@ -6824,7 +6824,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4A6RG.json b/data/chips/STM32L4A6RG.json index e511377..fd93c49 100644 --- a/data/chips/STM32L4A6RG.json +++ b/data/chips/STM32L4A6RG.json @@ -5519,7 +5519,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4A6VG.json b/data/chips/STM32L4A6VG.json index 7318474..5bbcf8a 100644 --- a/data/chips/STM32L4A6VG.json +++ b/data/chips/STM32L4A6VG.json @@ -6538,7 +6538,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4A6ZG.json b/data/chips/STM32L4A6ZG.json index d4dafde..4fb0b14 100644 --- a/data/chips/STM32L4A6ZG.json +++ b/data/chips/STM32L4A6ZG.json @@ -6937,7 +6937,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5AE.json b/data/chips/STM32L4P5AE.json index 631a584..099ce1f 100644 --- a/data/chips/STM32L4P5AE.json +++ b/data/chips/STM32L4P5AE.json @@ -7408,7 +7408,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5AG.json b/data/chips/STM32L4P5AG.json index 2921eb2..b783489 100644 --- a/data/chips/STM32L4P5AG.json +++ b/data/chips/STM32L4P5AG.json @@ -7412,7 +7412,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5CE.json b/data/chips/STM32L4P5CE.json index 21cc33b..d169250 100644 --- a/data/chips/STM32L4P5CE.json +++ b/data/chips/STM32L4P5CE.json @@ -4476,7 +4476,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5CG.json b/data/chips/STM32L4P5CG.json index ec89be5..194c330 100644 --- a/data/chips/STM32L4P5CG.json +++ b/data/chips/STM32L4P5CG.json @@ -4484,7 +4484,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5QE.json b/data/chips/STM32L4P5QE.json index 7d11d57..0c10e0c 100644 --- a/data/chips/STM32L4P5QE.json +++ b/data/chips/STM32L4P5QE.json @@ -6953,7 +6953,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5QG.json b/data/chips/STM32L4P5QG.json index 9a50c44..9b24b82 100644 --- a/data/chips/STM32L4P5QG.json +++ b/data/chips/STM32L4P5QG.json @@ -6961,7 +6961,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5RE.json b/data/chips/STM32L4P5RE.json index 11342f0..93fb8d7 100644 --- a/data/chips/STM32L4P5RE.json +++ b/data/chips/STM32L4P5RE.json @@ -5258,7 +5258,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5RG.json b/data/chips/STM32L4P5RG.json index 4f0b9e0..cbfbd9d 100644 --- a/data/chips/STM32L4P5RG.json +++ b/data/chips/STM32L4P5RG.json @@ -5262,7 +5262,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5VE.json b/data/chips/STM32L4P5VE.json index 61690a2..3e160e4 100644 --- a/data/chips/STM32L4P5VE.json +++ b/data/chips/STM32L4P5VE.json @@ -6547,7 +6547,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5VG.json b/data/chips/STM32L4P5VG.json index 574bdc8..b7c71ca 100644 --- a/data/chips/STM32L4P5VG.json +++ b/data/chips/STM32L4P5VG.json @@ -6555,7 +6555,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5ZE.json b/data/chips/STM32L4P5ZE.json index 1262ead..5936387 100644 --- a/data/chips/STM32L4P5ZE.json +++ b/data/chips/STM32L4P5ZE.json @@ -7058,7 +7058,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4P5ZG.json b/data/chips/STM32L4P5ZG.json index 7ffb9f8..f82bdb0 100644 --- a/data/chips/STM32L4P5ZG.json +++ b/data/chips/STM32L4P5ZG.json @@ -7062,7 +7062,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4Q5AG.json b/data/chips/STM32L4Q5AG.json index ca81fc0..1de6ed7 100644 --- a/data/chips/STM32L4Q5AG.json +++ b/data/chips/STM32L4Q5AG.json @@ -7478,7 +7478,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4Q5CG.json b/data/chips/STM32L4Q5CG.json index 3dba30e..edee987 100644 --- a/data/chips/STM32L4Q5CG.json +++ b/data/chips/STM32L4Q5CG.json @@ -4550,7 +4550,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4Q5QG.json b/data/chips/STM32L4Q5QG.json index e5ec3b0..4752cda 100644 --- a/data/chips/STM32L4Q5QG.json +++ b/data/chips/STM32L4Q5QG.json @@ -7023,7 +7023,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4Q5RG.json b/data/chips/STM32L4Q5RG.json index 5706082..507212b 100644 --- a/data/chips/STM32L4Q5RG.json +++ b/data/chips/STM32L4Q5RG.json @@ -5328,7 +5328,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4Q5VG.json b/data/chips/STM32L4Q5VG.json index 4071c25..766b218 100644 --- a/data/chips/STM32L4Q5VG.json +++ b/data/chips/STM32L4Q5VG.json @@ -6621,7 +6621,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4Q5ZG.json b/data/chips/STM32L4Q5ZG.json index 4923c15..08fd13d 100644 --- a/data/chips/STM32L4Q5ZG.json +++ b/data/chips/STM32L4Q5ZG.json @@ -7128,7 +7128,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R5AG.json b/data/chips/STM32L4R5AG.json index 18cfdb6..ea748d4 100644 --- a/data/chips/STM32L4R5AG.json +++ b/data/chips/STM32L4R5AG.json @@ -6551,7 +6551,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R5AI.json b/data/chips/STM32L4R5AI.json index 841d7a0..817dfb3 100644 --- a/data/chips/STM32L4R5AI.json +++ b/data/chips/STM32L4R5AI.json @@ -6555,7 +6555,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R5QG.json b/data/chips/STM32L4R5QG.json index 19cdd40..74d9322 100644 --- a/data/chips/STM32L4R5QG.json +++ b/data/chips/STM32L4R5QG.json @@ -6230,7 +6230,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R5QI.json b/data/chips/STM32L4R5QI.json index 656235b..53ac029 100644 --- a/data/chips/STM32L4R5QI.json +++ b/data/chips/STM32L4R5QI.json @@ -6230,7 +6230,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R5VG.json b/data/chips/STM32L4R5VG.json index 9394687..cdced4c 100644 --- a/data/chips/STM32L4R5VG.json +++ b/data/chips/STM32L4R5VG.json @@ -5746,7 +5746,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R5VI.json b/data/chips/STM32L4R5VI.json index d404fe7..250d4ae 100644 --- a/data/chips/STM32L4R5VI.json +++ b/data/chips/STM32L4R5VI.json @@ -5746,7 +5746,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R5ZG.json b/data/chips/STM32L4R5ZG.json index b19182e..6506766 100644 --- a/data/chips/STM32L4R5ZG.json +++ b/data/chips/STM32L4R5ZG.json @@ -6325,7 +6325,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R5ZI.json b/data/chips/STM32L4R5ZI.json index 6a5d912..e0f2e89 100644 --- a/data/chips/STM32L4R5ZI.json +++ b/data/chips/STM32L4R5ZI.json @@ -6335,7 +6335,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R7AI.json b/data/chips/STM32L4R7AI.json index c72581e..b0c822b 100644 --- a/data/chips/STM32L4R7AI.json +++ b/data/chips/STM32L4R7AI.json @@ -6806,7 +6806,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R7VI.json b/data/chips/STM32L4R7VI.json index 843e098..401aadb 100644 --- a/data/chips/STM32L4R7VI.json +++ b/data/chips/STM32L4R7VI.json @@ -5961,7 +5961,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R7ZI.json b/data/chips/STM32L4R7ZI.json index 67aa896..0ccef8a 100644 --- a/data/chips/STM32L4R7ZI.json +++ b/data/chips/STM32L4R7ZI.json @@ -6576,7 +6576,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R9AG.json b/data/chips/STM32L4R9AG.json index 701b7d7..29421f2 100644 --- a/data/chips/STM32L4R9AG.json +++ b/data/chips/STM32L4R9AG.json @@ -6744,7 +6744,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R9AI.json b/data/chips/STM32L4R9AI.json index 5555e08..b662830 100644 --- a/data/chips/STM32L4R9AI.json +++ b/data/chips/STM32L4R9AI.json @@ -6744,7 +6744,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R9VG.json b/data/chips/STM32L4R9VG.json index fde1caf..983d603 100644 --- a/data/chips/STM32L4R9VG.json +++ b/data/chips/STM32L4R9VG.json @@ -5781,7 +5781,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R9VI.json b/data/chips/STM32L4R9VI.json index 8196f39..4d97aaf 100644 --- a/data/chips/STM32L4R9VI.json +++ b/data/chips/STM32L4R9VI.json @@ -5781,7 +5781,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R9ZG.json b/data/chips/STM32L4R9ZG.json index 2206fc3..3d8bca0 100644 --- a/data/chips/STM32L4R9ZG.json +++ b/data/chips/STM32L4R9ZG.json @@ -6575,7 +6575,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4R9ZI.json b/data/chips/STM32L4R9ZI.json index 86cc8ce..4db09b0 100644 --- a/data/chips/STM32L4R9ZI.json +++ b/data/chips/STM32L4R9ZI.json @@ -6585,7 +6585,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4S5AI.json b/data/chips/STM32L4S5AI.json index 241c58d..c129563 100644 --- a/data/chips/STM32L4S5AI.json +++ b/data/chips/STM32L4S5AI.json @@ -6632,7 +6632,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4S5QI.json b/data/chips/STM32L4S5QI.json index 828b9f6..16fa03d 100644 --- a/data/chips/STM32L4S5QI.json +++ b/data/chips/STM32L4S5QI.json @@ -6307,7 +6307,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4S5VI.json b/data/chips/STM32L4S5VI.json index 7a5a26f..e9f0ecf 100644 --- a/data/chips/STM32L4S5VI.json +++ b/data/chips/STM32L4S5VI.json @@ -5827,7 +5827,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4S5ZI.json b/data/chips/STM32L4S5ZI.json index 5930467..eb4f535 100644 --- a/data/chips/STM32L4S5ZI.json +++ b/data/chips/STM32L4S5ZI.json @@ -6406,7 +6406,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4S7AI.json b/data/chips/STM32L4S7AI.json index 66215f5..ab5c1c7 100644 --- a/data/chips/STM32L4S7AI.json +++ b/data/chips/STM32L4S7AI.json @@ -6887,7 +6887,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4S7VI.json b/data/chips/STM32L4S7VI.json index 9d2fcb4..a56cb4a 100644 --- a/data/chips/STM32L4S7VI.json +++ b/data/chips/STM32L4S7VI.json @@ -6042,7 +6042,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4S7ZI.json b/data/chips/STM32L4S7ZI.json index 31c4c1c..0541bdc 100644 --- a/data/chips/STM32L4S7ZI.json +++ b/data/chips/STM32L4S7ZI.json @@ -6657,7 +6657,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4S9AI.json b/data/chips/STM32L4S9AI.json index 1890052..3f0cbd5 100644 --- a/data/chips/STM32L4S9AI.json +++ b/data/chips/STM32L4S9AI.json @@ -6825,7 +6825,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4S9VI.json b/data/chips/STM32L4S9VI.json index 5933aa2..7d24e5c 100644 --- a/data/chips/STM32L4S9VI.json +++ b/data/chips/STM32L4S9VI.json @@ -5862,7 +5862,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L4S9ZI.json b/data/chips/STM32L4S9ZI.json index 3599ea5..1d98c31 100644 --- a/data/chips/STM32L4S9ZI.json +++ b/data/chips/STM32L4S9ZI.json @@ -6656,7 +6656,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "AHB2ENR", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32L552CC.json b/data/chips/STM32L552CC.json index e3d8218..e88c234 100644 --- a/data/chips/STM32L552CC.json +++ b/data/chips/STM32L552CC.json @@ -4131,7 +4131,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L552CE.json b/data/chips/STM32L552CE.json index 87df37f..4d5cc7f 100644 --- a/data/chips/STM32L552CE.json +++ b/data/chips/STM32L552CE.json @@ -4139,7 +4139,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L552ME.json b/data/chips/STM32L552ME.json index 4449f8d..bf2330a 100644 --- a/data/chips/STM32L552ME.json +++ b/data/chips/STM32L552ME.json @@ -4840,7 +4840,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L552QC.json b/data/chips/STM32L552QC.json index 7aa1604..d5e877d 100644 --- a/data/chips/STM32L552QC.json +++ b/data/chips/STM32L552QC.json @@ -5879,7 +5879,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L552QE.json b/data/chips/STM32L552QE.json index 0f416da..a92ac6b 100644 --- a/data/chips/STM32L552QE.json +++ b/data/chips/STM32L552QE.json @@ -5887,7 +5887,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L552RC.json b/data/chips/STM32L552RC.json index 76fd8e9..62b8667 100644 --- a/data/chips/STM32L552RC.json +++ b/data/chips/STM32L552RC.json @@ -4685,7 +4685,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L552RE.json b/data/chips/STM32L552RE.json index 81a018a..af26239 100644 --- a/data/chips/STM32L552RE.json +++ b/data/chips/STM32L552RE.json @@ -4693,7 +4693,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L552VC.json b/data/chips/STM32L552VC.json index 5dcc5ae..a4dd8d3 100644 --- a/data/chips/STM32L552VC.json +++ b/data/chips/STM32L552VC.json @@ -5459,7 +5459,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L552VE.json b/data/chips/STM32L552VE.json index fc2d6fc..a9279b8 100644 --- a/data/chips/STM32L552VE.json +++ b/data/chips/STM32L552VE.json @@ -5463,7 +5463,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L552ZC.json b/data/chips/STM32L552ZC.json index a5b93aa..73d2ef3 100644 --- a/data/chips/STM32L552ZC.json +++ b/data/chips/STM32L552ZC.json @@ -5988,7 +5988,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L552ZE.json b/data/chips/STM32L552ZE.json index 98b4d80..7db0ccb 100644 --- a/data/chips/STM32L552ZE.json +++ b/data/chips/STM32L552ZE.json @@ -5992,7 +5992,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index 59bcb0a..e6a0c9e 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -4232,7 +4232,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index b3b7d1a..e3c6eb4 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -4933,7 +4933,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index 302917f..b858433 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -5980,7 +5980,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index 770d307..252b833 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -4786,7 +4786,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index 05a4dfa..b499466 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -5556,7 +5556,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index 638085e..97b3f39 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -6085,7 +6085,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR2", "field": "USBEN" diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index 1b67849..ca5d0bf 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -4088,7 +4088,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index 4e759eb..b34a1a1 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -4088,7 +4088,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index 0c4e270..0a13e48 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -4088,7 +4088,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index bbb39fa..d9904c6 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -4313,7 +4313,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index 750baea..f5aefeb 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -4168,7 +4168,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index df2c268..2037ef6 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -4168,7 +4168,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index 68f11cd..748fe2d 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -4674,7 +4674,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index 130cd3b..614a0f6 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -4674,7 +4674,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index 88a7c01..623a8b1 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -4674,7 +4674,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index c27784e..7ad507c 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -5641,7 +5641,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index bcf6168..7eec627 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -5641,7 +5641,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index c81f11b..24f1fba 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -4223,7 +4223,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index a3d648e..14c3e55 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -4448,7 +4448,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 500b5e0..1a45f3f 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -4303,7 +4303,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index becf437..322c6f7 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -4809,7 +4809,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index d0726a4..5f481a8 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -5776,7 +5776,10 @@ }, "rcc": { "bus_clock": "PCLK2", - "kernel_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "APB2ENR", "field": "USBEN" diff --git a/data/chips/STM32U575AG.json b/data/chips/STM32U575AG.json index 4dd82b3..4bbe459 100644 --- a/data/chips/STM32U575AG.json +++ b/data/chips/STM32U575AG.json @@ -8070,7 +8070,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575AI.json b/data/chips/STM32U575AI.json index 76d3bcf..e8a62cf 100644 --- a/data/chips/STM32U575AI.json +++ b/data/chips/STM32U575AI.json @@ -8070,7 +8070,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575CG.json b/data/chips/STM32U575CG.json index 0c5dc45..553a01d 100644 --- a/data/chips/STM32U575CG.json +++ b/data/chips/STM32U575CG.json @@ -4827,7 +4827,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575CI.json b/data/chips/STM32U575CI.json index fd44b2e..0d8ae41 100644 --- a/data/chips/STM32U575CI.json +++ b/data/chips/STM32U575CI.json @@ -4827,7 +4827,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575OG.json b/data/chips/STM32U575OG.json index a0b7856..a98bd87 100644 --- a/data/chips/STM32U575OG.json +++ b/data/chips/STM32U575OG.json @@ -6308,7 +6308,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575OI.json b/data/chips/STM32U575OI.json index d1ae860..8e64e1b 100644 --- a/data/chips/STM32U575OI.json +++ b/data/chips/STM32U575OI.json @@ -6308,7 +6308,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575QG.json b/data/chips/STM32U575QG.json index 776077d..3d93029 100644 --- a/data/chips/STM32U575QG.json +++ b/data/chips/STM32U575QG.json @@ -7525,7 +7525,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575QI.json b/data/chips/STM32U575QI.json index 4444703..7dc1ea8 100644 --- a/data/chips/STM32U575QI.json +++ b/data/chips/STM32U575QI.json @@ -7525,7 +7525,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575RG.json b/data/chips/STM32U575RG.json index 4f21a38..6c36ce2 100644 --- a/data/chips/STM32U575RG.json +++ b/data/chips/STM32U575RG.json @@ -5765,7 +5765,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575RI.json b/data/chips/STM32U575RI.json index c2f163b..9a3939d 100644 --- a/data/chips/STM32U575RI.json +++ b/data/chips/STM32U575RI.json @@ -5765,7 +5765,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575VG.json b/data/chips/STM32U575VG.json index 79cc6d5..4a17b11 100644 --- a/data/chips/STM32U575VG.json +++ b/data/chips/STM32U575VG.json @@ -6955,7 +6955,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575VI.json b/data/chips/STM32U575VI.json index 5a7aa6a..9d60d5e 100644 --- a/data/chips/STM32U575VI.json +++ b/data/chips/STM32U575VI.json @@ -6955,7 +6955,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575ZG.json b/data/chips/STM32U575ZG.json index b7be1cb..b40246e 100644 --- a/data/chips/STM32U575ZG.json +++ b/data/chips/STM32U575ZG.json @@ -7665,7 +7665,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U575ZI.json b/data/chips/STM32U575ZI.json index 0daed7b..3c3ea42 100644 --- a/data/chips/STM32U575ZI.json +++ b/data/chips/STM32U575ZI.json @@ -7665,7 +7665,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index 7c49eb0..e6c47f5 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -8238,7 +8238,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index 8c40404..ad6fbb9 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -4995,7 +4995,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index db6707c..316b689 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -6476,7 +6476,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index 0510515..97354b3 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -7693,7 +7693,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index dd8ea02..de2bfae 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -5933,7 +5933,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index 3df7592..ada36cd 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -7123,7 +7123,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index 8ea655b..2d426e7 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -7833,7 +7833,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_FSEN" diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index f8209e5..22e1c82 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -8135,7 +8135,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index 46fbec3..0f5c2a1 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -8135,7 +8135,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index 51077a3..85c37b9 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -7575,7 +7575,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index d28b63d..84cc5ae 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -7575,7 +7575,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index 5216351..7775e7b 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -5573,7 +5573,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index ea5b542..531df44 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -5573,7 +5573,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index 95b2fb9..e94c4e0 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -6930,7 +6930,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index 15615e9..734ce00 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -6930,7 +6930,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index 2132c67..731a0e1 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -7719,7 +7719,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index 8556a05..25264b1 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -7719,7 +7719,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index 372aa5d..88d495d 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -8576,7 +8576,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index 60f952e..cbb50e9 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -8631,7 +8631,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index 779b435..e4eb455 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -8631,7 +8631,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index e135f19..4bdb205 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -7025,7 +7025,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index 1107e09..3e34aa4 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -7198,7 +7198,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index faed05a..de8dc73 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -7993,7 +7993,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index ad0fd3d..fb4711c 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -7993,7 +7993,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index 958f6f5..56993ec 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -8297,7 +8297,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index 82c3202..6b3d9a4 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -7737,7 +7737,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index 1952075..4a42edb 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -5735,7 +5735,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index d60a78b..300675a 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -7092,7 +7092,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index d9422ba..bebc33d 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -7881,7 +7881,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index fc18f2a..824ec33 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -8738,7 +8738,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index fd3307f..c6e7702 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -8793,7 +8793,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 981c90b..6d3d4c4 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -7187,7 +7187,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index 81bcd65..df9c309 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -8155,7 +8155,10 @@ }, "rcc": { "bus_clock": "HCLK2", - "kernel_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ICLKSEL" + }, "enable": { "register": "AHB2ENR1", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32WB35CC.json b/data/chips/STM32WB35CC.json index 0ef46fd..c97e52a 100644 --- a/data/chips/STM32WB35CC.json +++ b/data/chips/STM32WB35CC.json @@ -2480,7 +2480,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32WB35CE.json b/data/chips/STM32WB35CE.json index 9cfa3e9..59e0202 100644 --- a/data/chips/STM32WB35CE.json +++ b/data/chips/STM32WB35CE.json @@ -2480,7 +2480,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32WB55CC.json b/data/chips/STM32WB55CC.json index baea681..f9fb718 100644 --- a/data/chips/STM32WB55CC.json +++ b/data/chips/STM32WB55CC.json @@ -2631,7 +2631,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32WB55CE.json b/data/chips/STM32WB55CE.json index 318f124..ef58a8f 100644 --- a/data/chips/STM32WB55CE.json +++ b/data/chips/STM32WB55CE.json @@ -2631,7 +2631,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32WB55CG.json b/data/chips/STM32WB55CG.json index 4c30629..105179e 100644 --- a/data/chips/STM32WB55CG.json +++ b/data/chips/STM32WB55CG.json @@ -2631,7 +2631,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32WB55RC.json b/data/chips/STM32WB55RC.json index d46d8ab..6f2e2d8 100644 --- a/data/chips/STM32WB55RC.json +++ b/data/chips/STM32WB55RC.json @@ -3184,7 +3184,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32WB55RE.json b/data/chips/STM32WB55RE.json index ffcdcc8..6c2c0a1 100644 --- a/data/chips/STM32WB55RE.json +++ b/data/chips/STM32WB55RE.json @@ -3184,7 +3184,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32WB55RG.json b/data/chips/STM32WB55RG.json index 4ea5b5c..b7cadc5 100644 --- a/data/chips/STM32WB55RG.json +++ b/data/chips/STM32WB55RG.json @@ -3184,7 +3184,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32WB55VC.json b/data/chips/STM32WB55VC.json index bb71eb5..7f3493a 100644 --- a/data/chips/STM32WB55VC.json +++ b/data/chips/STM32WB55VC.json @@ -3483,7 +3483,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32WB55VE.json b/data/chips/STM32WB55VE.json index 959f9f2..2a5d0a5 100644 --- a/data/chips/STM32WB55VE.json +++ b/data/chips/STM32WB55VE.json @@ -3483,7 +3483,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32WB55VG.json b/data/chips/STM32WB55VG.json index 87e97a9..18adc90 100644 --- a/data/chips/STM32WB55VG.json +++ b/data/chips/STM32WB55VG.json @@ -3483,7 +3483,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/chips/STM32WB55VY.json b/data/chips/STM32WB55VY.json index 06ff664..c24fa37 100644 --- a/data/chips/STM32WB55VY.json +++ b/data/chips/STM32WB55VY.json @@ -3461,7 +3461,10 @@ }, "rcc": { "bus_clock": "PCLK1", - "kernel_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR", + "field": "CLK48SEL" + }, "enable": { "register": "APB1ENR1", "field": "USBEN" diff --git a/data/registers/rcc_h5.json b/data/registers/rcc_h5.json index 3d8a24b..70f36a3 100644 --- a/data/registers/rcc_h5.json +++ b/data/registers/rcc_h5.json @@ -2429,11 +2429,11 @@ "enum": "SAISEL" }, { - "name": "CKPERSEL", + "name": "PERSEL", "description": "per_ck clock source selection", "bit_offset": 30, "bit_size": 2, - "enum": "CKPERSEL" + "enum": "PERSEL" } ] }, @@ -3142,7 +3142,7 @@ "bit_size": 1 }, { - "name": "CKPERSELSEC", + "name": "PERSELSEC", "description": "per_ck selection security\r Set and reset by software.", "bit_offset": 13, "bit_size": 1 @@ -3204,26 +3204,6 @@ } ] }, - "enum/CKPERSEL": { - "bit_size": 2, - "variants": [ - { - "name": "HSI", - "description": "hsi_ker_ck selected as kernel clock (default after reset)", - "value": 0 - }, - { - "name": "CSI", - "description": "csi_ker_ck selected as kernel clock", - "value": 1 - }, - { - "name": "HSE", - "description": "hse_ck selected as kernel clock", - "value": 2 - } - ] - }, "enum/DACHOLDSEL": { "bit_size": 1, "variants": [ @@ -3739,6 +3719,26 @@ } ] }, + "enum/PERSEL": { + "bit_size": 2, + "variants": [ + { + "name": "HSI", + "description": "hsi_ker_ck selected as kernel clock (default after reset)", + "value": 0 + }, + { + "name": "CSI", + "description": "csi_ker_ck selected as kernel clock", + "value": 1 + }, + { + "name": "HSE", + "description": "hse_ck selected as kernel clock", + "value": 2 + } + ] + }, "enum/PLLDIV": { "bit_size": 7, "variants": [ diff --git a/data/registers/rcc_h50.json b/data/registers/rcc_h50.json index 34dd30a..6e09f1d 100644 --- a/data/registers/rcc_h50.json +++ b/data/registers/rcc_h50.json @@ -1365,11 +1365,11 @@ "enum": "FDCANSEL" }, { - "name": "CKPERSEL", + "name": "PERSEL", "description": "per_ck clock source selection", "bit_offset": 30, "bit_size": 2, - "enum": "CKPERSEL" + "enum": "PERSEL" } ] }, @@ -2026,26 +2026,6 @@ } ] }, - "enum/CKPERSEL": { - "bit_size": 2, - "variants": [ - { - "name": "HSI", - "description": "hsi_ker_ck selected as kernel clock (default after reset)", - "value": 0 - }, - { - "name": "CSI", - "description": "csi_ker_ck selected as kernel clock", - "value": 1 - }, - { - "name": "HSE", - "description": "hse_ck selected as kernel clock", - "value": 2 - } - ] - }, "enum/DACHOLDSEL": { "bit_size": 1, "variants": [ @@ -2511,6 +2491,26 @@ } ] }, + "enum/PERSEL": { + "bit_size": 2, + "variants": [ + { + "name": "HSI", + "description": "hsi_ker_ck selected as kernel clock (default after reset)", + "value": 0 + }, + { + "name": "CSI", + "description": "csi_ker_ck selected as kernel clock", + "value": 1 + }, + { + "name": "HSE", + "description": "hse_ck selected as kernel clock", + "value": 2 + } + ] + }, "enum/PLLDIV": { "bit_size": 7, "variants": [ diff --git a/data/registers/rcc_h7.json b/data/registers/rcc_h7.json index 0e1bb74..f61e894 100644 --- a/data/registers/rcc_h7.json +++ b/data/registers/rcc_h7.json @@ -4638,11 +4638,11 @@ "enum": "SDMMCSEL" }, { - "name": "CKPERSEL", + "name": "PERSEL", "description": "per_ck clock source selection", "bit_offset": 28, "bit_size": 2, - "enum": "CKPERSEL" + "enum": "PERSEL" } ] }, @@ -5318,26 +5318,6 @@ } ] }, - "enum/CKPERSEL": { - "bit_size": 2, - "variants": [ - { - "name": "HSI", - "description": "HSI selected as peripheral clock", - "value": 0 - }, - { - "name": "CSI", - "description": "CSI selected as peripheral clock", - "value": 1 - }, - { - "name": "HSE", - "description": "HSE selected as peripheral clock", - "value": 2 - } - ] - }, "enum/DFSDMSEL": { "bit_size": 1, "variants": [ @@ -5813,6 +5793,26 @@ } ] }, + "enum/PERSEL": { + "bit_size": 2, + "variants": [ + { + "name": "HSI", + "description": "HSI selected as peripheral clock", + "value": 0 + }, + { + "name": "CSI", + "description": "CSI selected as peripheral clock", + "value": 1 + }, + { + "name": "HSE", + "description": "HSE selected as peripheral clock", + "value": 2 + } + ] + }, "enum/PLLDIV": { "bit_size": 7, "variants": [ diff --git a/data/registers/rcc_h7ab.json b/data/registers/rcc_h7ab.json index af714a9..782658c 100644 --- a/data/registers/rcc_h7ab.json +++ b/data/registers/rcc_h7ab.json @@ -3048,11 +3048,11 @@ "enum": "SDMMCSEL" }, { - "name": "CKPERSEL", + "name": "PERSEL", "description": "per_ck clock source selection", "bit_offset": 28, "bit_size": 2, - "enum": "CKPERSEL" + "enum": "PERSEL" } ] }, @@ -3680,26 +3680,6 @@ } ] }, - "enum/CKPERSEL": { - "bit_size": 2, - "variants": [ - { - "name": "HSI", - "description": "HSI selected as peripheral clock", - "value": 0 - }, - { - "name": "CSI", - "description": "CSI selected as peripheral clock", - "value": 1 - }, - { - "name": "HSE", - "description": "HSE selected as peripheral clock", - "value": 2 - } - ] - }, "enum/DFSDMSEL": { "bit_size": 1, "variants": [ @@ -4175,6 +4155,26 @@ } ] }, + "enum/PERSEL": { + "bit_size": 2, + "variants": [ + { + "name": "HSI", + "description": "HSI selected as peripheral clock", + "value": 0 + }, + { + "name": "CSI", + "description": "CSI selected as peripheral clock", + "value": 1 + }, + { + "name": "HSE", + "description": "HSE selected as peripheral clock", + "value": 2 + } + ] + }, "enum/PLLDIV": { "bit_size": 7, "variants": [ diff --git a/data/registers/rcc_h7rm0433.json b/data/registers/rcc_h7rm0433.json index 231c173..f093f01 100644 --- a/data/registers/rcc_h7rm0433.json +++ b/data/registers/rcc_h7rm0433.json @@ -4613,11 +4613,11 @@ "enum": "SDMMCSEL" }, { - "name": "CKPERSEL", + "name": "PERSEL", "description": "per_ck clock source selection", "bit_offset": 28, "bit_size": 2, - "enum": "CKPERSEL" + "enum": "PERSEL" } ] }, @@ -5293,26 +5293,6 @@ } ] }, - "enum/CKPERSEL": { - "bit_size": 2, - "variants": [ - { - "name": "HSI", - "description": "HSI selected as peripheral clock", - "value": 0 - }, - { - "name": "CSI", - "description": "CSI selected as peripheral clock", - "value": 1 - }, - { - "name": "HSE", - "description": "HSE selected as peripheral clock", - "value": 2 - } - ] - }, "enum/DFSDMSEL": { "bit_size": 1, "variants": [ @@ -5788,6 +5768,26 @@ } ] }, + "enum/PERSEL": { + "bit_size": 2, + "variants": [ + { + "name": "HSI", + "description": "HSI selected as peripheral clock", + "value": 0 + }, + { + "name": "CSI", + "description": "CSI selected as peripheral clock", + "value": 1 + }, + { + "name": "HSE", + "description": "HSE selected as peripheral clock", + "value": 2 + } + ] + }, "enum/PLLDIV": { "bit_size": 7, "variants": [