diff --git a/data/chips/STM32F070CB.json b/data/chips/STM32F070CB.json index a51a56c..ffc51e0 100644 --- a/data/chips/STM32F070CB.json +++ b/data/chips/STM32F070CB.json @@ -1009,11 +1009,13 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false } ] }, @@ -1345,11 +1347,13 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false } ] }, @@ -2220,11 +2224,13 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false } ] }, @@ -2312,11 +2318,13 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F070RB.json b/data/chips/STM32F070RB.json index 883fb47..4ee5cb9 100644 --- a/data/chips/STM32F070RB.json +++ b/data/chips/STM32F070RB.json @@ -1129,11 +1129,13 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false } ] }, @@ -1475,11 +1477,13 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false } ] }, @@ -2375,11 +2379,13 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false } ] }, @@ -2502,11 +2508,13 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F071C8.json b/data/chips/STM32F071C8.json index 3ebe2e1..29732c2 100644 --- a/data/chips/STM32F071C8.json +++ b/data/chips/STM32F071C8.json @@ -1510,19 +1510,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -1928,19 +1932,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3136,19 +3144,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3236,19 +3248,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F071CB.json b/data/chips/STM32F071CB.json index e8cd869..5cdb4a3 100644 --- a/data/chips/STM32F071CB.json +++ b/data/chips/STM32F071CB.json @@ -1822,19 +1822,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2240,19 +2244,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3448,19 +3456,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3548,19 +3560,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F071RB.json b/data/chips/STM32F071RB.json index 44a6c02..1f30dde 100644 --- a/data/chips/STM32F071RB.json +++ b/data/chips/STM32F071RB.json @@ -1348,19 +1348,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -1786,19 +1790,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3024,19 +3032,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3159,19 +3171,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F071V8.json b/data/chips/STM32F071V8.json index 8dc405d..8a1dd35 100644 --- a/data/chips/STM32F071V8.json +++ b/data/chips/STM32F071V8.json @@ -2169,19 +2169,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2691,19 +2695,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -4089,19 +4097,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -4254,19 +4266,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F071VB.json b/data/chips/STM32F071VB.json index 9037fcb..3071545 100644 --- a/data/chips/STM32F071VB.json +++ b/data/chips/STM32F071VB.json @@ -2175,19 +2175,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2697,19 +2701,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -4095,19 +4103,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -4260,19 +4272,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F072C8.json b/data/chips/STM32F072C8.json index 5022f4e..ce037eb 100644 --- a/data/chips/STM32F072C8.json +++ b/data/chips/STM32F072C8.json @@ -1595,19 +1595,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2013,19 +2017,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3221,19 +3229,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3321,19 +3333,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F072CB.json b/data/chips/STM32F072CB.json index 1b27449..59106b9 100644 --- a/data/chips/STM32F072CB.json +++ b/data/chips/STM32F072CB.json @@ -1895,19 +1895,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2313,19 +2317,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3521,19 +3529,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3621,19 +3633,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F072R8.json b/data/chips/STM32F072R8.json index c4d2e69..ad918a6 100644 --- a/data/chips/STM32F072R8.json +++ b/data/chips/STM32F072R8.json @@ -1421,19 +1421,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -1859,19 +1863,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3097,19 +3105,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3232,19 +3244,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F072RB.json b/data/chips/STM32F072RB.json index fc5fa2b..439fd3b 100644 --- a/data/chips/STM32F072RB.json +++ b/data/chips/STM32F072RB.json @@ -2201,19 +2201,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2639,19 +2643,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3877,19 +3885,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -4012,19 +4024,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F072V8.json b/data/chips/STM32F072V8.json index 0c67878..4c7bff7 100644 --- a/data/chips/STM32F072V8.json +++ b/data/chips/STM32F072V8.json @@ -2258,19 +2258,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2780,19 +2784,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -4178,19 +4186,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -4343,19 +4355,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F072VB.json b/data/chips/STM32F072VB.json index 32d330c..38f61d1 100644 --- a/data/chips/STM32F072VB.json +++ b/data/chips/STM32F072VB.json @@ -2258,19 +2258,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2780,19 +2784,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -4178,19 +4186,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -4343,19 +4355,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F078CB.json b/data/chips/STM32F078CB.json index afc1af5..d619148 100644 --- a/data/chips/STM32F078CB.json +++ b/data/chips/STM32F078CB.json @@ -1834,19 +1834,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2252,19 +2256,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3455,19 +3463,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3555,19 +3567,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F078RB.json b/data/chips/STM32F078RB.json index 2bd4f1a..053b5b7 100644 --- a/data/chips/STM32F078RB.json +++ b/data/chips/STM32F078RB.json @@ -1750,19 +1750,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2188,19 +2192,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3421,19 +3429,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -3556,19 +3568,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F078VB.json b/data/chips/STM32F078VB.json index 942ae0e..aced7cf 100644 --- a/data/chips/STM32F078VB.json +++ b/data/chips/STM32F078VB.json @@ -2187,19 +2187,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2709,19 +2713,23 @@ "dma_channels": [ { "signal": "RX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -4102,19 +4110,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH4" + "channel": "DMA1_CH4", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH5" + "channel": "DMA1_CH5", + "syscfg_cfgr1_remap_bit": false }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": true }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -4267,19 +4279,23 @@ "dma_channels": [ { "signal": "TX", - "channel": "DMA1_CH2" + "channel": "DMA1_CH2", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH3" + "channel": "DMA1_CH3", + "syscfg_cfgr1_remap_bit": true }, { "signal": "RX", - "channel": "DMA1_CH6" + "channel": "DMA1_CH6", + "syscfg_cfgr1_remap_bit": false }, { "signal": "TX", - "channel": "DMA1_CH7" + "channel": "DMA1_CH7", + "syscfg_cfgr1_remap_bit": false } ] }, diff --git a/data/chips/STM32F302CB.json b/data/chips/STM32F302CB.json index cabcdb2..5c7e7aa 100644 --- a/data/chips/STM32F302CB.json +++ b/data/chips/STM32F302CB.json @@ -706,11 +706,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F302CC.json b/data/chips/STM32F302CC.json index b8cbf46..9dae715 100644 --- a/data/chips/STM32F302CC.json +++ b/data/chips/STM32F302CC.json @@ -706,11 +706,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F302RB.json b/data/chips/STM32F302RB.json index 3249126..fe38d80 100644 --- a/data/chips/STM32F302RB.json +++ b/data/chips/STM32F302RB.json @@ -846,11 +846,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F302RC.json b/data/chips/STM32F302RC.json index 179d1b4..a405d6f 100644 --- a/data/chips/STM32F302RC.json +++ b/data/chips/STM32F302RC.json @@ -846,11 +846,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F302RD.json b/data/chips/STM32F302RD.json index 672b178..55fbaa1 100644 --- a/data/chips/STM32F302RD.json +++ b/data/chips/STM32F302RD.json @@ -844,11 +844,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F302RE.json b/data/chips/STM32F302RE.json index cee71bd..a953ac7 100644 --- a/data/chips/STM32F302RE.json +++ b/data/chips/STM32F302RE.json @@ -844,11 +844,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F302VB.json b/data/chips/STM32F302VB.json index 3ed509a..57526e8 100644 --- a/data/chips/STM32F302VB.json +++ b/data/chips/STM32F302VB.json @@ -1070,11 +1070,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F302VC.json b/data/chips/STM32F302VC.json index d944a33..36a3c17 100644 --- a/data/chips/STM32F302VC.json +++ b/data/chips/STM32F302VC.json @@ -1676,11 +1676,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F302VD.json b/data/chips/STM32F302VD.json index 3ea2f7e..f0f2854 100644 --- a/data/chips/STM32F302VD.json +++ b/data/chips/STM32F302VD.json @@ -1674,11 +1674,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F302VE.json b/data/chips/STM32F302VE.json index 3f12304..8bda27b 100644 --- a/data/chips/STM32F302VE.json +++ b/data/chips/STM32F302VE.json @@ -1674,11 +1674,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F302ZD.json b/data/chips/STM32F302ZD.json index 6da6543..532e716 100644 --- a/data/chips/STM32F302ZD.json +++ b/data/chips/STM32F302ZD.json @@ -1336,11 +1336,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F302ZE.json b/data/chips/STM32F302ZE.json index e7224cd..61fccab 100644 --- a/data/chips/STM32F302ZE.json +++ b/data/chips/STM32F302ZE.json @@ -1336,11 +1336,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303CB.json b/data/chips/STM32F303CB.json index e88e24a..ece8225 100644 --- a/data/chips/STM32F303CB.json +++ b/data/chips/STM32F303CB.json @@ -730,11 +730,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -837,11 +839,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303CC.json b/data/chips/STM32F303CC.json index 6fa5079..e34fd89 100644 --- a/data/chips/STM32F303CC.json +++ b/data/chips/STM32F303CC.json @@ -730,11 +730,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -837,11 +839,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303RB.json b/data/chips/STM32F303RB.json index cf86cde..903297a 100644 --- a/data/chips/STM32F303RB.json +++ b/data/chips/STM32F303RB.json @@ -870,11 +870,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -977,11 +979,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303RC.json b/data/chips/STM32F303RC.json index b8ca3f9..8abbbe6 100644 --- a/data/chips/STM32F303RC.json +++ b/data/chips/STM32F303RC.json @@ -876,11 +876,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -983,11 +985,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303RD.json b/data/chips/STM32F303RD.json index 107761f..3bc2ff0 100644 --- a/data/chips/STM32F303RD.json +++ b/data/chips/STM32F303RD.json @@ -868,11 +868,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -975,11 +977,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303RE.json b/data/chips/STM32F303RE.json index ae43e92..868ade5 100644 --- a/data/chips/STM32F303RE.json +++ b/data/chips/STM32F303RE.json @@ -868,11 +868,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -975,11 +977,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303VB.json b/data/chips/STM32F303VB.json index 3d6f438..dc4d6c0 100644 --- a/data/chips/STM32F303VB.json +++ b/data/chips/STM32F303VB.json @@ -1094,11 +1094,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -1289,11 +1291,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303VC.json b/data/chips/STM32F303VC.json index 1892a1c..3f8a7f7 100644 --- a/data/chips/STM32F303VC.json +++ b/data/chips/STM32F303VC.json @@ -1700,11 +1700,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -1895,11 +1897,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303VD.json b/data/chips/STM32F303VD.json index 5296be7..26a6e41 100644 --- a/data/chips/STM32F303VD.json +++ b/data/chips/STM32F303VD.json @@ -1698,11 +1698,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -1893,11 +1895,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303VE.json b/data/chips/STM32F303VE.json index b925b31..58aa9c1 100644 --- a/data/chips/STM32F303VE.json +++ b/data/chips/STM32F303VE.json @@ -2304,11 +2304,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -2499,11 +2501,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303ZD.json b/data/chips/STM32F303ZD.json index 56ac48c..ae83629 100644 --- a/data/chips/STM32F303ZD.json +++ b/data/chips/STM32F303ZD.json @@ -1360,11 +1360,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -1555,11 +1557,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F303ZE.json b/data/chips/STM32F303ZE.json index 77b2928..579a107 100644 --- a/data/chips/STM32F303ZE.json +++ b/data/chips/STM32F303ZE.json @@ -1360,11 +1360,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -1555,11 +1557,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F358CC.json b/data/chips/STM32F358CC.json index ceb7fab..5ce966a 100644 --- a/data/chips/STM32F358CC.json +++ b/data/chips/STM32F358CC.json @@ -690,11 +690,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -797,11 +799,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F358RC.json b/data/chips/STM32F358RC.json index 2634e7b..e0b277d 100644 --- a/data/chips/STM32F358RC.json +++ b/data/chips/STM32F358RC.json @@ -830,11 +830,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -937,11 +939,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F358VC.json b/data/chips/STM32F358VC.json index 30891eb..b9f5b4d 100644 --- a/data/chips/STM32F358VC.json +++ b/data/chips/STM32F358VC.json @@ -1054,11 +1054,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -1249,11 +1251,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] }, diff --git a/data/chips/STM32F398VE.json b/data/chips/STM32F398VE.json index 4ebfeed..8932893 100644 --- a/data/chips/STM32F398VE.json +++ b/data/chips/STM32F398VE.json @@ -1058,11 +1058,13 @@ "dma_channels": [ { "signal": "ADC2", - "channel": "DMA2_CH1" + "channel": "DMA2_CH1", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC2", - "channel": "DMA2_CH3" + "channel": "DMA2_CH3", + "syscfg_cfgr1_remap_bit": true } ] }, @@ -1253,11 +1255,13 @@ "dma_channels": [ { "signal": "ADC4", - "channel": "DMA2_CH2" + "channel": "DMA2_CH2", + "syscfg_cfgr1_remap_bit": false }, { "signal": "ADC4", - "channel": "DMA2_CH4" + "channel": "DMA2_CH4", + "syscfg_cfgr1_remap_bit": true } ] },