diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 0bf4b80..80bf4e3 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -4082,6 +4082,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1a", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index 8906394..20a1e27 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -4105,6 +4105,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1a", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index 5b70db4..c974e50 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -2939,6 +2939,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1a", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index daaafa0..685c94f 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -2814,6 +2814,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1a", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index f33c5eb..3543848 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -3343,6 +3343,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1a", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index 1a9d6fc..d620e41 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -3857,6 +3857,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1a", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index 47a6b2e..7189671 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -1903,6 +1903,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index 45f4c0f..5b87bca 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -2089,6 +2089,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index d249767..f52a85d 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -2677,6 +2677,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index 70b024b..b074848 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -2050,6 +2050,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index bde9507..7e67220 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -2423,6 +2423,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index d074e2e..0e1541e 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -2698,6 +2698,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index 9c2fb25..25bbc95 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -1979,6 +1979,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index 759f151..93d9352 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -2080,6 +2080,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 3dee2cc..b680c68 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -1942,6 +1942,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index 40b54db..4f22290 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -2167,6 +2167,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index af45e04..4682708 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -2555,6 +2555,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index a2323ef..1100deb 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -4151,6 +4151,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index c023cae..6e90268 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -2600,6 +2600,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index 49b999d..b45fb09 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -3202,6 +3202,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index b6d389d..e3320da 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -3881,6 +3881,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index 453389a..908bec8 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -2931,6 +2931,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index e4b7ca7..1a17a9b 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -3505,6 +3505,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index 75b0995..d5ec005 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -3936,6 +3936,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index db2f4bf..44ed1f2 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -4058,6 +4058,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index c9b35b0..3d88200 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -3773,6 +3773,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index 9997ab1..c98a37e 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -2671,6 +2671,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index ed5cb14..0ba7c0c 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -3362,6 +3362,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 6db0dbd..f26a3ea 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -3832,6 +3832,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 8b47aa0..bab6643 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -4499,6 +4499,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index 41b5f6a..b13cb52 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -4524,6 +4524,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 9e6503d..8943bd8 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -3539,6 +3539,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index 2967d3b..059eae1 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -4126,6 +4126,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1b", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32WB10CC.json b/data/chips/STM32WB10CC.json index c91d6d6..36d15c2 100644 --- a/data/chips/STM32WB10CC.json +++ b/data/chips/STM32WB10CC.json @@ -1223,6 +1223,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB15CC.json b/data/chips/STM32WB15CC.json index e938465..ad1cbe9 100644 --- a/data/chips/STM32WB15CC.json +++ b/data/chips/STM32WB15CC.json @@ -1369,6 +1369,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB30CE.json b/data/chips/STM32WB30CE.json index 18d42da..b32ae3e 100644 --- a/data/chips/STM32WB30CE.json +++ b/data/chips/STM32WB30CE.json @@ -1059,6 +1059,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB35CC.json b/data/chips/STM32WB35CC.json index f5264d3..0ef46fd 100644 --- a/data/chips/STM32WB35CC.json +++ b/data/chips/STM32WB35CC.json @@ -1438,6 +1438,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB35CE.json b/data/chips/STM32WB35CE.json index 321f3f3..9cfa3e9 100644 --- a/data/chips/STM32WB35CE.json +++ b/data/chips/STM32WB35CE.json @@ -1438,6 +1438,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB50CG.json b/data/chips/STM32WB50CG.json index 8208160..85fe212 100644 --- a/data/chips/STM32WB50CG.json +++ b/data/chips/STM32WB50CG.json @@ -1059,6 +1059,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55CC.json b/data/chips/STM32WB55CC.json index 3f3df22..baea681 100644 --- a/data/chips/STM32WB55CC.json +++ b/data/chips/STM32WB55CC.json @@ -1583,6 +1583,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55CE.json b/data/chips/STM32WB55CE.json index 6579520..318f124 100644 --- a/data/chips/STM32WB55CE.json +++ b/data/chips/STM32WB55CE.json @@ -1583,6 +1583,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55CG.json b/data/chips/STM32WB55CG.json index 91fcc3a..4c30629 100644 --- a/data/chips/STM32WB55CG.json +++ b/data/chips/STM32WB55CG.json @@ -1583,6 +1583,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55RC.json b/data/chips/STM32WB55RC.json index 941b96f..d46d8ab 100644 --- a/data/chips/STM32WB55RC.json +++ b/data/chips/STM32WB55RC.json @@ -1835,6 +1835,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55RE.json b/data/chips/STM32WB55RE.json index e78fc3a..ffcdcc8 100644 --- a/data/chips/STM32WB55RE.json +++ b/data/chips/STM32WB55RE.json @@ -1835,6 +1835,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55RG.json b/data/chips/STM32WB55RG.json index ae4a604..4ea5b5c 100644 --- a/data/chips/STM32WB55RG.json +++ b/data/chips/STM32WB55RG.json @@ -1835,6 +1835,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VC.json b/data/chips/STM32WB55VC.json index ab5b557..bb71eb5 100644 --- a/data/chips/STM32WB55VC.json +++ b/data/chips/STM32WB55VC.json @@ -1944,6 +1944,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VE.json b/data/chips/STM32WB55VE.json index 5bdf338..959f9f2 100644 --- a/data/chips/STM32WB55VE.json +++ b/data/chips/STM32WB55VE.json @@ -1944,6 +1944,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VG.json b/data/chips/STM32WB55VG.json index 24f0cd6..87e97a9 100644 --- a/data/chips/STM32WB55VG.json +++ b/data/chips/STM32WB55VG.json @@ -1944,6 +1944,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VY.json b/data/chips/STM32WB55VY.json index a0cc8cc..06ff664 100644 --- a/data/chips/STM32WB55VY.json +++ b/data/chips/STM32WB55VY.json @@ -1922,6 +1922,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WBA52CE.json b/data/chips/STM32WBA52CE.json index 6ba48f0..255d0b2 100644 --- a/data/chips/STM32WBA52CE.json +++ b/data/chips/STM32WBA52CE.json @@ -932,6 +932,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1a", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32WBA52CG.json b/data/chips/STM32WBA52CG.json index bef060b..4c5e6a8 100644 --- a/data/chips/STM32WBA52CG.json +++ b/data/chips/STM32WBA52CG.json @@ -932,6 +932,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1a", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32WBA52KE.json b/data/chips/STM32WBA52KE.json index f200e97..7e4303a 100644 --- a/data/chips/STM32WBA52KE.json +++ b/data/chips/STM32WBA52KE.json @@ -863,6 +863,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1a", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32WBA52KG.json b/data/chips/STM32WBA52KG.json index ed46b7b..5cf1672 100644 --- a/data/chips/STM32WBA52KG.json +++ b/data/chips/STM32WBA52KG.json @@ -863,6 +863,11 @@ { "name": "PKA", "address": 1108090880, + "registers": { + "kind": "pka", + "version": "v1a", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32WL54CC.json b/data/chips/STM32WL54CC.json index 8a91c6e..ee32326 100644 --- a/data/chips/STM32WL54CC.json +++ b/data/chips/STM32WL54CC.json @@ -1343,6 +1343,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -3906,6 +3911,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WL54JC.json b/data/chips/STM32WL54JC.json index 5493483..f9f992b 100644 --- a/data/chips/STM32WL54JC.json +++ b/data/chips/STM32WL54JC.json @@ -1479,6 +1479,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -4293,6 +4298,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WL55CC.json b/data/chips/STM32WL55CC.json index b1b32be..0b1bb45 100644 --- a/data/chips/STM32WL55CC.json +++ b/data/chips/STM32WL55CC.json @@ -1349,6 +1349,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -3912,6 +3917,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WL55JC.json b/data/chips/STM32WL55JC.json index 954c4fe..4a51103 100644 --- a/data/chips/STM32WL55JC.json +++ b/data/chips/STM32WL55JC.json @@ -1485,6 +1485,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -4299,6 +4304,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4C8.json b/data/chips/STM32WLE4C8.json index bb33429..ff39e34 100644 --- a/data/chips/STM32WLE4C8.json +++ b/data/chips/STM32WLE4C8.json @@ -1131,6 +1131,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4CB.json b/data/chips/STM32WLE4CB.json index 2217747..81d2aaa 100644 --- a/data/chips/STM32WLE4CB.json +++ b/data/chips/STM32WLE4CB.json @@ -1131,6 +1131,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4CC.json b/data/chips/STM32WLE4CC.json index 1fed47f..9348975 100644 --- a/data/chips/STM32WLE4CC.json +++ b/data/chips/STM32WLE4CC.json @@ -1306,6 +1306,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4J8.json b/data/chips/STM32WLE4J8.json index 3f61448..8e58638 100644 --- a/data/chips/STM32WLE4J8.json +++ b/data/chips/STM32WLE4J8.json @@ -1267,6 +1267,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4JB.json b/data/chips/STM32WLE4JB.json index 1eebe36..fc4d02e 100644 --- a/data/chips/STM32WLE4JB.json +++ b/data/chips/STM32WLE4JB.json @@ -1267,6 +1267,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4JC.json b/data/chips/STM32WLE4JC.json index b79c22d..2c05737 100644 --- a/data/chips/STM32WLE4JC.json +++ b/data/chips/STM32WLE4JC.json @@ -1442,6 +1442,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5C8.json b/data/chips/STM32WLE5C8.json index c3e172a..ca4457e 100644 --- a/data/chips/STM32WLE5C8.json +++ b/data/chips/STM32WLE5C8.json @@ -1306,6 +1306,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5CB.json b/data/chips/STM32WLE5CB.json index 4a3073c..ea4330d 100644 --- a/data/chips/STM32WLE5CB.json +++ b/data/chips/STM32WLE5CB.json @@ -1306,6 +1306,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5CC.json b/data/chips/STM32WLE5CC.json index fc42705..75b9924 100644 --- a/data/chips/STM32WLE5CC.json +++ b/data/chips/STM32WLE5CC.json @@ -1306,6 +1306,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5J8.json b/data/chips/STM32WLE5J8.json index 46584a8..14afe21 100644 --- a/data/chips/STM32WLE5J8.json +++ b/data/chips/STM32WLE5J8.json @@ -1442,6 +1442,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5JB.json b/data/chips/STM32WLE5JB.json index ae114a7..d061aa8 100644 --- a/data/chips/STM32WLE5JB.json +++ b/data/chips/STM32WLE5JB.json @@ -1442,6 +1442,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5JC.json b/data/chips/STM32WLE5JC.json index bd87ac6..5601efc 100644 --- a/data/chips/STM32WLE5JC.json +++ b/data/chips/STM32WLE5JC.json @@ -1442,6 +1442,11 @@ { "name": "PKA", "address": 1476403200, + "registers": { + "kind": "pka", + "version": "v1c", + "block": "PKA" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/registers/pka_v1a.json b/data/registers/pka_v1a.json new file mode 100644 index 0000000..210103b --- /dev/null +++ b/data/registers/pka_v1a.json @@ -0,0 +1,164 @@ +{ + "block/PKA": { + "description": "Private key accelerator.", + "items": [ + { + "name": "CR", + "description": "PKA control register.", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "SR", + "description": "PKA status register.", + "byte_offset": 4, + "fieldset": "SR" + }, + { + "name": "CLRFR", + "description": "PKA clear flag register.", + "byte_offset": 8, + "fieldset": "CLRFR" + } + ] + }, + "fieldset/CLRFR": { + "description": "PKA clear flag register.", + "fields": [ + { + "name": "PROCENDFC", + "description": "Clear PKA End of Operation flag.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "RAMERRFC", + "description": "Clear PKA RAM error flag.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ADDRERRFC", + "description": "Clear address error flag.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "OPERRFC", + "description": "Clear operation error flag.", + "bit_offset": 21, + "bit_size": 1 + } + ] + }, + "fieldset/CR": { + "description": "PKA control register.", + "fields": [ + { + "name": "EN", + "description": "PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "START", + "description": "start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MODE", + "description": "PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored.", + "bit_offset": 8, + "bit_size": 6 + }, + { + "name": "PROCENDIE", + "description": "End of operation interrupt enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "RAMERRIE", + "description": "RAM error interrupt enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ADDRERRIE", + "description": "Address error interrupt enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "OPERRIE", + "description": "Operation error interrupt enable.", + "bit_offset": 21, + "bit_size": 1 + } + ] + }, + "fieldset/SR": { + "description": "PKA status register.", + "fields": [ + { + "name": "INITOK", + "description": "PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "LMF", + "description": "Limited mode flag This bit is updated when EN bit in PKA_CR is set.", + "bit_offset": 1, + "bit_size": 1, + "enum": "LMF" + }, + { + "name": "BUSY", + "description": "PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PROCENDF", + "description": "PKA End of Operation flag.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "RAMERRF", + "description": "PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ADDRERRF", + "description": "Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "OPERRF", + "description": "Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR.", + "bit_offset": 21, + "bit_size": 1 + } + ] + }, + "enum/LMF": { + "bit_size": 1, + "variants": [ + { + "name": "All", + "description": "All values documented in MODE bitfield can be used.", + "value": 0 + }, + { + "name": "Limited", + "description": "Only ECDSA verification (MODE = 0x26) is supported by the PKA.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/pka_v1b.json b/data/registers/pka_v1b.json new file mode 100644 index 0000000..6a7745c --- /dev/null +++ b/data/registers/pka_v1b.json @@ -0,0 +1,142 @@ +{ + "block/PKA": { + "description": "Private key accelerator.", + "items": [ + { + "name": "CR", + "description": "PKA control register.", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "SR", + "description": "PKA status register.", + "byte_offset": 4, + "fieldset": "SR" + }, + { + "name": "CLRFR", + "description": "PKA clear flag register.", + "byte_offset": 8, + "fieldset": "CLRFR" + } + ] + }, + "fieldset/CLRFR": { + "description": "PKA clear flag register.", + "fields": [ + { + "name": "PROCENDFC", + "description": "Clear PKA End of Operation flag.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "RAMERRFC", + "description": "Clear PKA RAM error flag.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ADDRERRFC", + "description": "Clear address error flag.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "OPERRFC", + "description": "Clear operation error flag.", + "bit_offset": 21, + "bit_size": 1 + } + ] + }, + "fieldset/CR": { + "description": "PKA control register.", + "fields": [ + { + "name": "EN", + "description": "PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "START", + "description": "start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MODE", + "description": "PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored.", + "bit_offset": 8, + "bit_size": 6 + }, + { + "name": "PROCENDIE", + "description": "End of operation interrupt enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "RAMERRIE", + "description": "RAM error interrupt enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ADDRERRIE", + "description": "Address error interrupt enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "OPERRIE", + "description": "Operation error interrupt enable.", + "bit_offset": 21, + "bit_size": 1 + } + ] + }, + "fieldset/SR": { + "description": "PKA status register.", + "fields": [ + { + "name": "INITOK", + "description": "PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BUSY", + "description": "PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PROCENDF", + "description": "PKA End of Operation flag.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "RAMERRF", + "description": "PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ADDRERRF", + "description": "Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "OPERRF", + "description": "Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR.", + "bit_offset": 21, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/pka_v1c.json b/data/registers/pka_v1c.json new file mode 100644 index 0000000..c545ec0 --- /dev/null +++ b/data/registers/pka_v1c.json @@ -0,0 +1,118 @@ +{ + "block/PKA": { + "description": "Private key accelerator.", + "items": [ + { + "name": "CR", + "description": "PKA control register.", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "SR", + "description": "PKA status register.", + "byte_offset": 4, + "fieldset": "SR" + }, + { + "name": "CLRFR", + "description": "PKA clear flag register.", + "byte_offset": 8, + "fieldset": "CLRFR" + } + ] + }, + "fieldset/CLRFR": { + "description": "PKA clear flag register.", + "fields": [ + { + "name": "PROCENDFC", + "description": "Clear PKA End of Operation flag.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "RAMERRFC", + "description": "Clear PKA RAM error flag.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ADDRERRFC", + "description": "Clear address error flag.", + "bit_offset": 20, + "bit_size": 1 + } + ] + }, + "fieldset/CR": { + "description": "PKA control register.", + "fields": [ + { + "name": "EN", + "description": "PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "START", + "description": "start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MODE", + "description": "PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored.", + "bit_offset": 8, + "bit_size": 6 + }, + { + "name": "PROCENDIE", + "description": "End of operation interrupt enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "RAMERRIE", + "description": "RAM error interrupt enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ADDRERRIE", + "description": "Address error interrupt enable.", + "bit_offset": 20, + "bit_size": 1 + } + ] + }, + "fieldset/SR": { + "description": "PKA status register.", + "fields": [ + { + "name": "BUSY", + "description": "PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PROCENDF", + "description": "PKA End of Operation flag.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "RAMERRF", + "description": "PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ADDRERRF", + "description": "Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR.", + "bit_offset": 20, + "bit_size": 1 + } + ] + } +} \ No newline at end of file