diff --git a/data/chips/STM32H7R3A8.json b/data/chips/STM32H7R3A8.json index 5145fc7..d42b2d0 100644 --- a/data/chips/STM32H7R3A8.json +++ b/data/chips/STM32H7R3A8.json @@ -8295,7 +8295,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7R3I8.json b/data/chips/STM32H7R3I8.json index f41721a..7159f60 100644 --- a/data/chips/STM32H7R3I8.json +++ b/data/chips/STM32H7R3I8.json @@ -9726,7 +9726,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7R3L8.json b/data/chips/STM32H7R3L8.json index 3f02053..d22d8cb 100644 --- a/data/chips/STM32H7R3L8.json +++ b/data/chips/STM32H7R3L8.json @@ -10686,7 +10686,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7R3V8.json b/data/chips/STM32H7R3V8.json index c835133..9475070 100644 --- a/data/chips/STM32H7R3V8.json +++ b/data/chips/STM32H7R3V8.json @@ -6675,7 +6675,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7R3Z8.json b/data/chips/STM32H7R3Z8.json index 7073e7f..da22252 100644 --- a/data/chips/STM32H7R3Z8.json +++ b/data/chips/STM32H7R3Z8.json @@ -8646,7 +8646,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7R7L8.json b/data/chips/STM32H7R7L8.json index 403a504..fc87950 100644 --- a/data/chips/STM32H7R7L8.json +++ b/data/chips/STM32H7R7L8.json @@ -10974,7 +10974,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7S3A8.json b/data/chips/STM32H7S3A8.json index d42fdbd..592fe24 100644 --- a/data/chips/STM32H7S3A8.json +++ b/data/chips/STM32H7S3A8.json @@ -8420,7 +8420,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7S3I8.json b/data/chips/STM32H7S3I8.json index 1f39c83..c6e0a17 100644 --- a/data/chips/STM32H7S3I8.json +++ b/data/chips/STM32H7S3I8.json @@ -9851,7 +9851,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7S3L8.json b/data/chips/STM32H7S3L8.json index 5cf10c2..e8de5af 100644 --- a/data/chips/STM32H7S3L8.json +++ b/data/chips/STM32H7S3L8.json @@ -10811,7 +10811,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7S3V8.json b/data/chips/STM32H7S3V8.json index f2b6d6a..88b4598 100644 --- a/data/chips/STM32H7S3V8.json +++ b/data/chips/STM32H7S3V8.json @@ -6800,7 +6800,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7S3Z8.json b/data/chips/STM32H7S3Z8.json index 6583478..b2c8852 100644 --- a/data/chips/STM32H7S3Z8.json +++ b/data/chips/STM32H7S3Z8.json @@ -8771,7 +8771,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/chips/STM32H7S7L8.json b/data/chips/STM32H7S7L8.json index 4c8a36f..b2abaf0 100644 --- a/data/chips/STM32H7S7L8.json +++ b/data/chips/STM32H7S7L8.json @@ -11099,7 +11099,10 @@ }, "rcc": { "bus_clock": "HCLK1", - "kernel_clock": "USB", + "kernel_clock": { + "register": "AHBPERCKSELR", + "field": "USBPHYCSEL" + }, "enable": { "register": "AHB1ENR", "field": "USB_OTG_HSEN" diff --git a/data/registers/otg_v1.json b/data/registers/otg_v1.json index 0cfeeb3..3ae6c5f 100644 --- a/data/registers/otg_v1.json +++ b/data/registers/otg_v1.json @@ -101,6 +101,12 @@ "byte_offset": 56, "fieldset": "GCCFG_V2" }, + { + "name": "GCCFG_V3", + "description": "General core configuration register, for core_id 0x0000_5xxx", + "byte_offset": 56, + "fieldset": "GCCFG_V3" + }, { "name": "CID", "description": "Core ID register", @@ -1129,6 +1135,95 @@ } ] }, + "fieldset/GCCFG_V3": { + "description": "OTG general core configuration register.", + "fields": [ + { + "name": "CHGDET", + "description": "Charger detection, result of the current mode (primary or secondary).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "FSVPLUS", + "description": "Single-Ended DP indicator This bit gives the voltage level on DP (also result of the comparison with V<sub>LGC</sub> threshold as defined in BC v1.2 standard).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "FSVMINUS", + "description": "Single-Ended DM indicator This bit gives the voltage level on DM (also result of the comparison with V<sub>LGC</sub> threshold as defined in BC v1.2 standard).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "SESSVLD", + "description": "VBUS session indicator Indicates if VBUS is above VBUS session threshold.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "HCDPEN", + "description": "Host CDP behavior enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "HCDPDETEN", + "description": "Host CDP port voltage detector enable on DP.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "HVDMSRCEN", + "description": "Host CDP port Voltage source enable on DM.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "DCDEN", + "description": "Data Contact Detection enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "PDEN", + "description": "Primary detection enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "VBDEN", + "description": "VBUS detection enable Enables VBUS Sensing Comparators in order to detect VBUS presence and/or perform OTG operation.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SDEN", + "description": "Secondary detection enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "VBVALOVAL", + "description": "Software override value of the VBUS B-session detection.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "VBVALOVEN", + "description": "Enables a software override of the VBUS B-session detection.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "FORCEHOSTPD", + "description": "Force host mode pull-downs If the ID pin functions are enabled, the host mode pull-downs on DP and DM activate automatically. However, whenever that is not the case, yet host mode is required, this bit must be used to force the pull-downs active.", + "bit_offset": 25, + "bit_size": 1 + } + ] + }, "fieldset/GI2CCTL": { "description": "I2C access register", "fields": [