diff --git a/data/chips/STM32L052C6.json b/data/chips/STM32L052C6.json index 38cc3dc..e6f6522 100644 --- a/data/chips/STM32L052C6.json +++ b/data/chips/STM32L052C6.json @@ -1909,6 +1909,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L052C8.json b/data/chips/STM32L052C8.json index cb37c22..bf3ece3 100644 --- a/data/chips/STM32L052C8.json +++ b/data/chips/STM32L052C8.json @@ -1909,6 +1909,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L052K6.json b/data/chips/STM32L052K6.json index f341679..be8913c 100644 --- a/data/chips/STM32L052K6.json +++ b/data/chips/STM32L052K6.json @@ -1564,6 +1564,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L052K8.json b/data/chips/STM32L052K8.json index d00456a..c7df320 100644 --- a/data/chips/STM32L052K8.json +++ b/data/chips/STM32L052K8.json @@ -1564,6 +1564,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L052R6.json b/data/chips/STM32L052R6.json index d670ca6..a9f8f37 100644 --- a/data/chips/STM32L052R6.json +++ b/data/chips/STM32L052R6.json @@ -2023,6 +2023,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L052R8.json b/data/chips/STM32L052R8.json index 2564da3..5aa1679 100644 --- a/data/chips/STM32L052R8.json +++ b/data/chips/STM32L052R8.json @@ -2023,6 +2023,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L052T6.json b/data/chips/STM32L052T6.json index c8af93f..f6a49a8 100644 --- a/data/chips/STM32L052T6.json +++ b/data/chips/STM32L052T6.json @@ -1705,6 +1705,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L052T8.json b/data/chips/STM32L052T8.json index c09b13a..1b0e2ef 100644 --- a/data/chips/STM32L052T8.json +++ b/data/chips/STM32L052T8.json @@ -1709,6 +1709,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L053C6.json b/data/chips/STM32L053C6.json index 93a4847..7cb17fa 100644 --- a/data/chips/STM32L053C6.json +++ b/data/chips/STM32L053C6.json @@ -2048,6 +2048,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L053C8.json b/data/chips/STM32L053C8.json index 6f1b6a4..b2b2b21 100644 --- a/data/chips/STM32L053C8.json +++ b/data/chips/STM32L053C8.json @@ -2048,6 +2048,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L053R6.json b/data/chips/STM32L053R6.json index aa1ab4c..41fd392 100644 --- a/data/chips/STM32L053R6.json +++ b/data/chips/STM32L053R6.json @@ -2252,6 +2252,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L053R8.json b/data/chips/STM32L053R8.json index e3dbd1b..aa55dc3 100644 --- a/data/chips/STM32L053R8.json +++ b/data/chips/STM32L053R8.json @@ -2252,6 +2252,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L062C8.json b/data/chips/STM32L062C8.json index e5ed87e..cdad4cf 100644 --- a/data/chips/STM32L062C8.json +++ b/data/chips/STM32L062C8.json @@ -1930,6 +1930,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L062K8.json b/data/chips/STM32L062K8.json index 4c23bf5..750295a 100644 --- a/data/chips/STM32L062K8.json +++ b/data/chips/STM32L062K8.json @@ -1601,6 +1601,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L063C8.json b/data/chips/STM32L063C8.json index 6ae68b7..c4e4b3e 100644 --- a/data/chips/STM32L063C8.json +++ b/data/chips/STM32L063C8.json @@ -2085,6 +2085,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L063R8.json b/data/chips/STM32L063R8.json index 8035ec2..6171013 100644 --- a/data/chips/STM32L063R8.json +++ b/data/chips/STM32L063R8.json @@ -2285,6 +2285,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L072CB.json b/data/chips/STM32L072CB.json index 71d4a39..2cae5c5 100644 --- a/data/chips/STM32L072CB.json +++ b/data/chips/STM32L072CB.json @@ -2269,6 +2269,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L072CZ.json b/data/chips/STM32L072CZ.json index 14cef6e..7c204fe 100644 --- a/data/chips/STM32L072CZ.json +++ b/data/chips/STM32L072CZ.json @@ -2273,6 +2273,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L072KB.json b/data/chips/STM32L072KB.json index 12a54ab..cb5ac37 100644 --- a/data/chips/STM32L072KB.json +++ b/data/chips/STM32L072KB.json @@ -1903,6 +1903,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L072KZ.json b/data/chips/STM32L072KZ.json index 2b0242d..785031e 100644 --- a/data/chips/STM32L072KZ.json +++ b/data/chips/STM32L072KZ.json @@ -1903,6 +1903,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L072RB.json b/data/chips/STM32L072RB.json index d7508ed..e9cbd6b 100644 --- a/data/chips/STM32L072RB.json +++ b/data/chips/STM32L072RB.json @@ -2376,6 +2376,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L072RZ.json b/data/chips/STM32L072RZ.json index f4360d0..604fbf2 100644 --- a/data/chips/STM32L072RZ.json +++ b/data/chips/STM32L072RZ.json @@ -2376,6 +2376,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L072V8.json b/data/chips/STM32L072V8.json index 3b37d95..32e84a5 100644 --- a/data/chips/STM32L072V8.json +++ b/data/chips/STM32L072V8.json @@ -2546,6 +2546,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L072VB.json b/data/chips/STM32L072VB.json index 8ec59f0..9c541b1 100644 --- a/data/chips/STM32L072VB.json +++ b/data/chips/STM32L072VB.json @@ -2546,6 +2546,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L072VZ.json b/data/chips/STM32L072VZ.json index 99f7a1e..eafdee1 100644 --- a/data/chips/STM32L072VZ.json +++ b/data/chips/STM32L072VZ.json @@ -2546,6 +2546,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L073CB.json b/data/chips/STM32L073CB.json index de734f4..e0aae88 100644 --- a/data/chips/STM32L073CB.json +++ b/data/chips/STM32L073CB.json @@ -2419,6 +2419,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L073CZ.json b/data/chips/STM32L073CZ.json index 105945a..3fcf6db 100644 --- a/data/chips/STM32L073CZ.json +++ b/data/chips/STM32L073CZ.json @@ -2423,6 +2423,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L073RB.json b/data/chips/STM32L073RB.json index c4484c4..0f9770c 100644 --- a/data/chips/STM32L073RB.json +++ b/data/chips/STM32L073RB.json @@ -2601,6 +2601,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L073RZ.json b/data/chips/STM32L073RZ.json index e23de2c..a061d00 100644 --- a/data/chips/STM32L073RZ.json +++ b/data/chips/STM32L073RZ.json @@ -2605,6 +2605,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L073V8.json b/data/chips/STM32L073V8.json index 7501394..b6da3db 100644 --- a/data/chips/STM32L073V8.json +++ b/data/chips/STM32L073V8.json @@ -2903,6 +2903,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L073VB.json b/data/chips/STM32L073VB.json index 677a05f..0ad05e7 100644 --- a/data/chips/STM32L073VB.json +++ b/data/chips/STM32L073VB.json @@ -2903,6 +2903,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L073VZ.json b/data/chips/STM32L073VZ.json index 9a28aae..cbe6d1c 100644 --- a/data/chips/STM32L073VZ.json +++ b/data/chips/STM32L073VZ.json @@ -2903,6 +2903,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L082CZ.json b/data/chips/STM32L082CZ.json index 60ddb73..48d5b9f 100644 --- a/data/chips/STM32L082CZ.json +++ b/data/chips/STM32L082CZ.json @@ -2302,6 +2302,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L082KB.json b/data/chips/STM32L082KB.json index bea935d..98fe542 100644 --- a/data/chips/STM32L082KB.json +++ b/data/chips/STM32L082KB.json @@ -1940,6 +1940,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L082KZ.json b/data/chips/STM32L082KZ.json index e2d3d4a..eba75f5 100644 --- a/data/chips/STM32L082KZ.json +++ b/data/chips/STM32L082KZ.json @@ -1940,6 +1940,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L083CB.json b/data/chips/STM32L083CB.json index e10273e..dffa9c0 100644 --- a/data/chips/STM32L083CB.json +++ b/data/chips/STM32L083CB.json @@ -2380,6 +2380,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L083CZ.json b/data/chips/STM32L083CZ.json index dea3be0..3ae3d3f 100644 --- a/data/chips/STM32L083CZ.json +++ b/data/chips/STM32L083CZ.json @@ -2384,6 +2384,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L083RB.json b/data/chips/STM32L083RB.json index 3fc5628..bca0dba 100644 --- a/data/chips/STM32L083RB.json +++ b/data/chips/STM32L083RB.json @@ -2638,6 +2638,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L083RZ.json b/data/chips/STM32L083RZ.json index 063ef0e..9083d13 100644 --- a/data/chips/STM32L083RZ.json +++ b/data/chips/STM32L083RZ.json @@ -2638,6 +2638,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L083V8.json b/data/chips/STM32L083V8.json index 7e2ace7..108fc9c 100644 --- a/data/chips/STM32L083V8.json +++ b/data/chips/STM32L083V8.json @@ -2940,6 +2940,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L083VB.json b/data/chips/STM32L083VB.json index 1acbebf..20d5edb 100644 --- a/data/chips/STM32L083VB.json +++ b/data/chips/STM32L083VB.json @@ -2940,6 +2940,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/chips/STM32L083VZ.json b/data/chips/STM32L083VZ.json index 3bd6a93..b0d2af7 100644 --- a/data/chips/STM32L083VZ.json +++ b/data/chips/STM32L083VZ.json @@ -2940,6 +2940,18 @@ "version": "v3", "block": "TSC" }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHBENR", + "field": "TSCEN" + }, + "reset": { + "register": "AHBRSTR", + "field": "TSCRST" + } + }, "pins": [ { "pin": "PA0", diff --git a/data/registers/rcc_l0.json b/data/registers/rcc_l0.json index 55ac863..678903c 100644 --- a/data/registers/rcc_l0.json +++ b/data/registers/rcc_l0.json @@ -149,7 +149,7 @@ "bit_size": 1 }, { - "name": "TOUCHEN", + "name": "TSCEN", "description": "Touch Sensing clock enable", "bit_offset": 16, "bit_size": 1 @@ -190,7 +190,7 @@ "bit_size": 1 }, { - "name": "TOUCHRST", + "name": "TSCRST", "description": "Touch Sensing reset", "bit_offset": 16, "bit_size": 1 @@ -237,7 +237,7 @@ "bit_size": 1 }, { - "name": "TOUCHSMEN", + "name": "TSCSMEN", "description": "Touch Sensing clock enable during sleep mode", "bit_offset": 16, "bit_size": 1 diff --git a/data/registers/rcc_l0_v2.json b/data/registers/rcc_l0_v2.json index 76aa086..6c28b32 100644 --- a/data/registers/rcc_l0_v2.json +++ b/data/registers/rcc_l0_v2.json @@ -155,7 +155,7 @@ "bit_size": 1 }, { - "name": "TOUCHEN", + "name": "TSCEN", "description": "Touch Sensing clock enable", "bit_offset": 16, "bit_size": 1 @@ -196,7 +196,7 @@ "bit_size": 1 }, { - "name": "TOUCHRST", + "name": "TSCRST", "description": "Touch Sensing reset", "bit_offset": 16, "bit_size": 1 @@ -243,7 +243,7 @@ "bit_size": 1 }, { - "name": "TOUCHSMEN", + "name": "TSCSMEN", "description": "Touch Sensing clock enable during sleep mode", "bit_offset": 16, "bit_size": 1