diff --git a/data/chips/STM32H745BG.json b/data/chips/STM32H745BG.json index 3c49175..5c84eff 100644 --- a/data/chips/STM32H745BG.json +++ b/data/chips/STM32H745BG.json @@ -3274,6 +3274,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13114,6 +13135,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745BI.json b/data/chips/STM32H745BI.json index aeb45e6..fdd41dc 100644 --- a/data/chips/STM32H745BI.json +++ b/data/chips/STM32H745BI.json @@ -3285,6 +3285,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13125,6 +13146,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745IG.json b/data/chips/STM32H745IG.json index d77ffc8..3e2acc9 100644 --- a/data/chips/STM32H745IG.json +++ b/data/chips/STM32H745IG.json @@ -3242,6 +3242,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12824,6 +12845,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745II.json b/data/chips/STM32H745II.json index 9ef7036..084297b 100644 --- a/data/chips/STM32H745II.json +++ b/data/chips/STM32H745II.json @@ -3253,6 +3253,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12835,6 +12856,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745XG.json b/data/chips/STM32H745XG.json index 2d6b720..84826f8 100644 --- a/data/chips/STM32H745XG.json +++ b/data/chips/STM32H745XG.json @@ -3338,6 +3338,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13347,6 +13368,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745XI.json b/data/chips/STM32H745XI.json index be0f65e..8084939 100644 --- a/data/chips/STM32H745XI.json +++ b/data/chips/STM32H745XI.json @@ -3349,6 +3349,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13358,6 +13379,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745ZG.json b/data/chips/STM32H745ZG.json index b0b0b5b..81e4346 100644 --- a/data/chips/STM32H745ZG.json +++ b/data/chips/STM32H745ZG.json @@ -2879,6 +2879,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -11654,6 +11675,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H745ZI.json b/data/chips/STM32H745ZI.json index ed3c0fe..be4bc95 100644 --- a/data/chips/STM32H745ZI.json +++ b/data/chips/STM32H745ZI.json @@ -2890,6 +2890,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -11665,6 +11686,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index be2029e..175c9bb 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -3012,6 +3012,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12006,6 +12027,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index 38e4252..3998e29 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -3023,6 +3023,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12017,6 +12038,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index 164c5ed..467ff84 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -3280,6 +3280,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12949,6 +12970,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index 0d9129d..7caf30c 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -3291,6 +3291,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12960,6 +12981,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index ab5fef6..a8041dc 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -3012,6 +3012,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12006,6 +12027,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index f608c4c..49eb2de 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -3023,6 +3023,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12017,6 +12038,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index d61ce67..119c8ea 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -3344,6 +3344,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13357,6 +13378,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index 6e274fc..fd5d5f4 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -3355,6 +3355,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13368,6 +13389,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index b76b6f9..1bc5811 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -2871,6 +2871,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -11322,6 +11343,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index ad04ec6..10437dc 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -3364,6 +3364,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13281,6 +13302,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index b7f2cfc..5043561 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -3332,6 +3332,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12991,6 +13012,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index 464da0a..fe5de1d 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -3428,6 +3428,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13514,6 +13535,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index 99aa289..87db591 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -2969,6 +2969,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -11821,6 +11842,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index d3b13b1..4e0cb35 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -3102,6 +3102,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12173,6 +12194,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index a2b291e..7d01f5f 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -3370,6 +3370,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13116,6 +13137,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 9d1e7d3..393c33a 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -3102,6 +3102,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -12173,6 +12194,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 01a7f3d..69858ed 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -3434,6 +3434,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -13524,6 +13545,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index a61017c..ad5deeb 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -2950,6 +2950,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, @@ -11478,6 +11499,27 @@ } ] }, + { + "name": "HSEM", + "address": 1476551680, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "HSEMEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "HSEMRST" + } + } + }, { "name": "I2C1", "address": 1073763328, diff --git a/data/chips/STM32WLE4C8.json b/data/chips/STM32WLE4C8.json index ff39e34..05b21b1 100644 --- a/data/chips/STM32WLE4C8.json +++ b/data/chips/STM32WLE4C8.json @@ -658,6 +658,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4CB.json b/data/chips/STM32WLE4CB.json index 81d2aaa..d35e29d 100644 --- a/data/chips/STM32WLE4CB.json +++ b/data/chips/STM32WLE4CB.json @@ -658,6 +658,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4CC.json b/data/chips/STM32WLE4CC.json index 9348975..7ce689a 100644 --- a/data/chips/STM32WLE4CC.json +++ b/data/chips/STM32WLE4CC.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4J8.json b/data/chips/STM32WLE4J8.json index 8e58638..15f95ce 100644 --- a/data/chips/STM32WLE4J8.json +++ b/data/chips/STM32WLE4J8.json @@ -684,6 +684,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4JB.json b/data/chips/STM32WLE4JB.json index fc4d02e..02ef219 100644 --- a/data/chips/STM32WLE4JB.json +++ b/data/chips/STM32WLE4JB.json @@ -684,6 +684,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4JC.json b/data/chips/STM32WLE4JC.json index 2c05737..190cb65 100644 --- a/data/chips/STM32WLE4JC.json +++ b/data/chips/STM32WLE4JC.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5C8.json b/data/chips/STM32WLE5C8.json index ca4457e..79a0164 100644 --- a/data/chips/STM32WLE5C8.json +++ b/data/chips/STM32WLE5C8.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5CB.json b/data/chips/STM32WLE5CB.json index ea4330d..54d3796 100644 --- a/data/chips/STM32WLE5CB.json +++ b/data/chips/STM32WLE5CB.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5CC.json b/data/chips/STM32WLE5CC.json index 75b9924..5ba55f7 100644 --- a/data/chips/STM32WLE5CC.json +++ b/data/chips/STM32WLE5CC.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5J8.json b/data/chips/STM32WLE5J8.json index 14afe21..8bdf911 100644 --- a/data/chips/STM32WLE5J8.json +++ b/data/chips/STM32WLE5J8.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5JB.json b/data/chips/STM32WLE5JB.json index d061aa8..d488c02 100644 --- a/data/chips/STM32WLE5JB.json +++ b/data/chips/STM32WLE5JB.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5JC.json b/data/chips/STM32WLE5JC.json index 5601efc..f269d4f 100644 --- a/data/chips/STM32WLE5JC.json +++ b/data/chips/STM32WLE5JC.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v8", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/registers/hsem_v1.json b/data/registers/hsem_v1.json new file mode 100644 index 0000000..fc6cd29 --- /dev/null +++ b/data/registers/hsem_v1.json @@ -0,0 +1,226 @@ +{ + "block/HSEM": { + "description": "Hardware semaphore (HSEM).", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "C1IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 256, + "fieldset": "IER" + }, + { + "name": "C1ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 260, + "fieldset": "ICR" + }, + { + "name": "C1ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 264, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "C1MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "C2IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 272, + "fieldset": "IER" + }, + { + "name": "C2ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 276, + "fieldset": "ICR" + }, + { + "name": "C2ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 280, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "C2MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 284, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "COREID of semaphores to be cleared.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "Interrupt semaphore x clear bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "Interrupt semaphore x enable bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "Interrupt semaphore x status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "masked interrupt semaphore x status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v2.json b/data/registers/hsem_v2.json new file mode 100644 index 0000000..1c0fa8f --- /dev/null +++ b/data/registers/hsem_v2.json @@ -0,0 +1,929 @@ +{ + "block/HSEM": { + "description": "HSEM.", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "C1IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 256, + "fieldset": "C1IER" + }, + { + "name": "C1ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 260, + "access": "Read", + "fieldset": "C1ICR" + }, + { + "name": "C1ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 264, + "access": "Read", + "fieldset": "C1ISR" + }, + { + "name": "C1MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "C1MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/C1ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISEM0", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ISEM1", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ISEM2", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ISEM3", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ISEM4", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ISEM5", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "ISEM6", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ISEM7", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "ISEM8", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "ISEM9", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "ISEM10", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "ISEM11", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "ISEM12", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "ISEM13", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "ISEM14", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "ISEM15", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "ISEM16", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ISEM17", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ISEM18", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ISEM19", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ISEM20", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ISEM21", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ISEM22", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ISEM23", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ISEM24", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ISEM25", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "ISEM26", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ISEM27", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ISEM28", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ISEM29", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "ISEM30", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "ISEM31", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/C1IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISEM0", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ISEM1", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ISEM2", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ISEM3", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ISEM4", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ISEM5", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "ISEM6", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ISEM7", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "ISEM8", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "ISEM9", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "ISEM10", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "ISEM11", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "ISEM12", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "ISEM13", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "ISEM14", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "ISEM15", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "ISEM16", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ISEM17", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ISEM18", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ISEM19", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ISEM20", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ISEM21", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ISEM22", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ISEM23", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ISEM24", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ISEM25", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "ISEM26", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ISEM27", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ISEM28", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ISEM29", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "ISEM30", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "ISEM31", + "description": "Interrupt(N) semaphore n enable bit.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/C1ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISEM0", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ISEM1", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ISEM2", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ISEM3", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ISEM4", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ISEM5", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "ISEM6", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ISEM7", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "ISEM8", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "ISEM9", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "ISEM10", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "ISEM11", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "ISEM12", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "ISEM13", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "ISEM14", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "ISEM15", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "ISEM16", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ISEM17", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ISEM18", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ISEM19", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ISEM20", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ISEM21", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ISEM22", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ISEM23", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ISEM24", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ISEM25", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "ISEM26", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ISEM27", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ISEM28", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ISEM29", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "ISEM30", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "ISEM31", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/C1MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "ISEM0", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ISEM1", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ISEM2", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ISEM3", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ISEM4", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ISEM5", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "ISEM6", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ISEM7", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "ISEM8", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "ISEM9", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "ISEM10", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "ISEM11", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "ISEM12", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "ISEM13", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "ISEM14", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "ISEM15", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "ISEM16", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ISEM17", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ISEM18", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ISEM19", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ISEM20", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ISEM21", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ISEM22", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ISEM23", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ISEM24", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ISEM25", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "ISEM26", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ISEM27", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ISEM28", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ISEM29", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "ISEM30", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "ISEM31", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "MasterID of semaphores to be cleared.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "MASTERID", + "description": "Semaphore MasterID.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "MASTERID", + "description": "Semaphore MasterID.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v3.json b/data/registers/hsem_v3.json new file mode 100644 index 0000000..9f434fb --- /dev/null +++ b/data/registers/hsem_v3.json @@ -0,0 +1,929 @@ +{ + "block/HSEM": { + "description": "HSEM.", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 256, + "fieldset": "IER" + }, + { + "name": "ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 260, + "access": "Read", + "fieldset": "ICR" + }, + { + "name": "ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 264, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "MASTERID", + "description": "MasterID of semaphores to be cleared.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISEM0", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ISEM1", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ISEM2", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ISEM3", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ISEM4", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ISEM5", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "ISEM6", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ISEM7", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "ISEM8", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "ISEM9", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "ISEM10", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "ISEM11", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "ISEM12", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "ISEM13", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "ISEM14", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "ISEM15", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "ISEM16", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ISEM17", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ISEM18", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ISEM19", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ISEM20", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ISEM21", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ISEM22", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ISEM23", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ISEM24", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ISEM25", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "ISEM26", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ISEM27", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ISEM28", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ISEM29", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "ISEM30", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "ISEM31", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISEM0", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ISEM1", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ISEM2", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ISEM3", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ISEM4", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ISEM5", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "ISEM6", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ISEM7", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "ISEM8", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "ISEM9", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "ISEM10", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "ISEM11", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "ISEM12", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "ISEM13", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "ISEM14", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "ISEM15", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "ISEM16", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ISEM17", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ISEM18", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ISEM19", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ISEM20", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ISEM21", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ISEM22", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ISEM23", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ISEM24", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ISEM25", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "ISEM26", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ISEM27", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ISEM28", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ISEM29", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "ISEM30", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "ISEM31", + "description": "Interrupt(N) semaphore n enable bit.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISEM0", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ISEM1", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ISEM2", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ISEM3", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ISEM4", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ISEM5", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "ISEM6", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ISEM7", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "ISEM8", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "ISEM9", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "ISEM10", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "ISEM11", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "ISEM12", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "ISEM13", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "ISEM14", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "ISEM15", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "ISEM16", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ISEM17", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ISEM18", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ISEM19", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ISEM20", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ISEM21", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ISEM22", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ISEM23", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ISEM24", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ISEM25", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "ISEM26", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ISEM27", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ISEM28", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ISEM29", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "ISEM30", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "ISEM31", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "ISEM0", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ISEM1", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ISEM2", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ISEM3", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ISEM4", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ISEM5", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "ISEM6", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "ISEM7", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "ISEM8", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "ISEM9", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "ISEM10", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "ISEM11", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "ISEM12", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "ISEM13", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "ISEM14", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "ISEM15", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "ISEM16", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ISEM17", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "ISEM18", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "ISEM19", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "ISEM20", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ISEM21", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "ISEM22", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ISEM23", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ISEM24", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ISEM25", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "ISEM26", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "ISEM27", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ISEM28", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ISEM29", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "ISEM30", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "ISEM31", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "MASTERID", + "description": "Semaphore MasterID.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "MASTERID", + "description": "Semaphore MasterID.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v4.json b/data/registers/hsem_v4.json new file mode 100644 index 0000000..8fe77b0 --- /dev/null +++ b/data/registers/hsem_v4.json @@ -0,0 +1,2196 @@ +{ + "block/HSEM": { + "description": "HSEM.", + "items": [ + { + "name": "HSEM_R0", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 0, + "fieldset": "HSEM_R0" + }, + { + "name": "HSEM_R1", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 4, + "fieldset": "HSEM_R1" + }, + { + "name": "HSEM_R2", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 8, + "fieldset": "HSEM_R2" + }, + { + "name": "HSEM_R3", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 12, + "fieldset": "HSEM_R3" + }, + { + "name": "HSEM_R4", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 16, + "fieldset": "HSEM_R4" + }, + { + "name": "HSEM_R5", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 20, + "fieldset": "HSEM_R5" + }, + { + "name": "HSEM_R6", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 24, + "fieldset": "HSEM_R6" + }, + { + "name": "HSEM_R7", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 28, + "fieldset": "HSEM_R7" + }, + { + "name": "HSEM_R8", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 32, + "fieldset": "HSEM_R8" + }, + { + "name": "HSEM_R9", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 36, + "fieldset": "HSEM_R9" + }, + { + "name": "HSEM_R10", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 40, + "fieldset": "HSEM_R10" + }, + { + "name": "HSEM_R11", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 44, + "fieldset": "HSEM_R11" + }, + { + "name": "HSEM_R12", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 48, + "fieldset": "HSEM_R12" + }, + { + "name": "HSEM_R13", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 52, + "fieldset": "HSEM_R13" + }, + { + "name": "HSEM_R14", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 56, + "fieldset": "HSEM_R14" + }, + { + "name": "HSEM_R15", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 60, + "fieldset": "HSEM_R15" + }, + { + "name": "HSEM_R16", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 64, + "fieldset": "HSEM_R16" + }, + { + "name": "HSEM_R17", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 68, + "fieldset": "HSEM_R17" + }, + { + "name": "HSEM_R18", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 72, + "fieldset": "HSEM_R18" + }, + { + "name": "HSEM_R19", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 76, + "fieldset": "HSEM_R19" + }, + { + "name": "HSEM_R20", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 80, + "fieldset": "HSEM_R20" + }, + { + "name": "HSEM_R21", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 84, + "fieldset": "HSEM_R21" + }, + { + "name": "HSEM_R22", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 88, + "fieldset": "HSEM_R22" + }, + { + "name": "HSEM_R23", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 92, + "fieldset": "HSEM_R23" + }, + { + "name": "HSEM_R24", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 96, + "fieldset": "HSEM_R24" + }, + { + "name": "HSEM_R25", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 100, + "fieldset": "HSEM_R25" + }, + { + "name": "HSEM_R26", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 104, + "fieldset": "HSEM_R26" + }, + { + "name": "HSEM_R27", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 108, + "fieldset": "HSEM_R27" + }, + { + "name": "HSEM_R28", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 112, + "fieldset": "HSEM_R28" + }, + { + "name": "HSEM_R29", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 116, + "fieldset": "HSEM_R29" + }, + { + "name": "HSEM_R30", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 120, + "fieldset": "HSEM_R30" + }, + { + "name": "HSEM_R31", + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 124, + "fieldset": "HSEM_R31" + }, + { + "name": "HSEM_RLR0", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 128, + "access": "Read", + "fieldset": "HSEM_RLR0" + }, + { + "name": "HSEM_RLR1", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 132, + "access": "Read", + "fieldset": "HSEM_RLR1" + }, + { + "name": "HSEM_RLR2", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 136, + "access": "Read", + "fieldset": "HSEM_RLR2" + }, + { + "name": "HSEM_RLR3", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 140, + "access": "Read", + "fieldset": "HSEM_RLR3" + }, + { + "name": "HSEM_RLR4", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 144, + "access": "Read", + "fieldset": "HSEM_RLR4" + }, + { + "name": "HSEM_RLR5", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 148, + "access": "Read", + "fieldset": "HSEM_RLR5" + }, + { + "name": "HSEM_RLR6", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 152, + "access": "Read", + "fieldset": "HSEM_RLR6" + }, + { + "name": "HSEM_RLR7", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 156, + "access": "Read", + "fieldset": "HSEM_RLR7" + }, + { + "name": "HSEM_RLR8", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 160, + "access": "Read", + "fieldset": "HSEM_RLR8" + }, + { + "name": "HSEM_RLR9", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 164, + "access": "Read", + "fieldset": "HSEM_RLR9" + }, + { + "name": "HSEM_RLR10", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 168, + "access": "Read", + "fieldset": "HSEM_RLR10" + }, + { + "name": "HSEM_RLR11", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 172, + "access": "Read", + "fieldset": "HSEM_RLR11" + }, + { + "name": "HSEM_RLR12", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 176, + "access": "Read", + "fieldset": "HSEM_RLR12" + }, + { + "name": "HSEM_RLR13", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 180, + "access": "Read", + "fieldset": "HSEM_RLR13" + }, + { + "name": "HSEM_RLR14", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 184, + "access": "Read", + "fieldset": "HSEM_RLR14" + }, + { + "name": "HSEM_RLR15", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 188, + "access": "Read", + "fieldset": "HSEM_RLR15" + }, + { + "name": "HSEM_RLR16", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 192, + "access": "Read", + "fieldset": "HSEM_RLR16" + }, + { + "name": "HSEM_RLR17", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 196, + "access": "Read", + "fieldset": "HSEM_RLR17" + }, + { + "name": "HSEM_RLR18", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 200, + "access": "Read", + "fieldset": "HSEM_RLR18" + }, + { + "name": "HSEM_RLR19", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 204, + "access": "Read", + "fieldset": "HSEM_RLR19" + }, + { + "name": "HSEM_RLR20", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 208, + "access": "Read", + "fieldset": "HSEM_RLR20" + }, + { + "name": "HSEM_RLR21", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 212, + "access": "Read", + "fieldset": "HSEM_RLR21" + }, + { + "name": "HSEM_RLR22", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 216, + "access": "Read", + "fieldset": "HSEM_RLR22" + }, + { + "name": "HSEM_RLR23", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 220, + "access": "Read", + "fieldset": "HSEM_RLR23" + }, + { + "name": "HSEM_RLR24", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 224, + "access": "Read", + "fieldset": "HSEM_RLR24" + }, + { + "name": "HSEM_RLR25", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 228, + "access": "Read", + "fieldset": "HSEM_RLR25" + }, + { + "name": "HSEM_RLR26", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 232, + "access": "Read", + "fieldset": "HSEM_RLR26" + }, + { + "name": "HSEM_RLR27", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 236, + "access": "Read", + "fieldset": "HSEM_RLR27" + }, + { + "name": "HSEM_RLR28", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 240, + "access": "Read", + "fieldset": "HSEM_RLR28" + }, + { + "name": "HSEM_RLR29", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 244, + "access": "Read", + "fieldset": "HSEM_RLR29" + }, + { + "name": "HSEM_RLR30", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 248, + "access": "Read", + "fieldset": "HSEM_RLR30" + }, + { + "name": "HSEM_RLR31", + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 252, + "access": "Read", + "fieldset": "HSEM_RLR31" + }, + { + "name": "HSEM_C1IER", + "description": "HSEM i1terrupt enable register.", + "byte_offset": 256, + "fieldset": "HSEM_C1IER" + }, + { + "name": "HSEM_C1ICR", + "description": "HSEM i1terrupt clear register.", + "byte_offset": 260, + "fieldset": "HSEM_C1ICR" + }, + { + "name": "HSEM_C1ISR", + "description": "HSEM i1terrupt status register.", + "byte_offset": 264, + "access": "Read", + "fieldset": "HSEM_C1ISR" + }, + { + "name": "HSEM_C1MISR", + "description": "HSEM i1terrupt status register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "HSEM_C1MISR" + }, + { + "name": "HSEM_C2IER", + "description": "HSEM i2terrupt enable register.", + "byte_offset": 272, + "fieldset": "HSEM_C2IER" + }, + { + "name": "HSEM_C2ICR", + "description": "HSEM i2terrupt clear register.", + "byte_offset": 276, + "fieldset": "HSEM_C2ICR" + }, + { + "name": "HSEM_C2ISR", + "description": "HSEM i2terrupt status register.", + "byte_offset": 280, + "access": "Read", + "fieldset": "HSEM_C2ISR" + }, + { + "name": "HSEM_C2MISR", + "description": "HSEM i2terrupt status register.", + "byte_offset": 284, + "access": "Read", + "fieldset": "HSEM_C2MISR" + }, + { + "name": "HSEM_CR", + "description": "Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "byte_offset": 320, + "access": "Write", + "fieldset": "HSEM_CR" + }, + { + "name": "HSEM_KEYR", + "description": "HSEM interrupt clear register.", + "byte_offset": 324, + "fieldset": "HSEM_KEYR" + }, + { + "name": "HSEM_HWCFGR2", + "description": "HSEM hardware configuration register 2.", + "byte_offset": 1004, + "access": "Read", + "fieldset": "HSEM_HWCFGR2" + }, + { + "name": "HSEM_HWCFGR1", + "description": "HSEM hardware configuration register 1.", + "byte_offset": 1008, + "access": "Read", + "fieldset": "HSEM_HWCFGR1" + }, + { + "name": "HSEM_VERR", + "description": "HSEM IP version register.", + "byte_offset": 1012, + "access": "Read", + "fieldset": "HSEM_VERR" + }, + { + "name": "HSEM_IPIDR", + "description": "HSEM IP identification register.", + "byte_offset": 1016, + "access": "Read", + "fieldset": "HSEM_IPIDR" + }, + { + "name": "HSEM_SIDR", + "description": "HSEM size identification register.", + "byte_offset": 1020, + "access": "Read", + "fieldset": "HSEM_SIDR" + } + ] + }, + "fieldset/HSEM_C1ICR": { + "description": "HSEM i1terrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "ISC.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HSEM_C1IER": { + "description": "HSEM i1terrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "ISE.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HSEM_C1ISR": { + "description": "HSEM i1terrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "ISF.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HSEM_C1MISR": { + "description": "HSEM i1terrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "MISF.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HSEM_C2ICR": { + "description": "HSEM i2terrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "ISC.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HSEM_C2IER": { + "description": "HSEM i2terrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "ISE.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HSEM_C2ISR": { + "description": "HSEM i2terrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "ISF.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HSEM_C2MISR": { + "description": "HSEM i2terrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "MISF.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HSEM_CR": { + "description": "Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "KEY.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/HSEM_HWCFGR1": { + "description": "HSEM hardware configuration register 1.", + "fields": [ + { + "name": "NBSEM", + "description": "NBSEM.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "NBINT", + "description": "NBINT.", + "bit_offset": 8, + "bit_size": 4 + } + ] + }, + "fieldset/HSEM_HWCFGR2": { + "description": "HSEM hardware configuration register 2.", + "fields": [ + { + "name": "MASTERID1", + "description": "MASTERID1.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "MASTERID2", + "description": "MASTERID2.", + "bit_offset": 4, + "bit_size": 4 + }, + { + "name": "MASTERID3", + "description": "MASTERID3.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "MASTERID4", + "description": "MASTERID4.", + "bit_offset": 12, + "bit_size": 4 + } + ] + }, + "fieldset/HSEM_IPIDR": { + "description": "HSEM IP identification register.", + "fields": [ + { + "name": "IPID", + "description": "IPID.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HSEM_KEYR": { + "description": "HSEM interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "KEY.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/HSEM_R0": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R1": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R10": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R11": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R12": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R13": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R14": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R15": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R16": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R17": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R18": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R19": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R2": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R20": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R21": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R22": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R23": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R24": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R25": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R26": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R27": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R28": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R29": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R3": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R30": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R31": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R4": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R5": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R6": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R7": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R8": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_R9": { + "description": "The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR0": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR1": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR10": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR11": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR12": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR13": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR14": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR15": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR16": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR17": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR18": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR19": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR2": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR20": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR21": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR22": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR23": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR24": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR25": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR26": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR27": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR28": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR29": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR3": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR30": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR31": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR4": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR5": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR6": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR7": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR8": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR9": { + "description": "Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.", + "fields": [ + { + "name": "PROCID", + "description": "PROCID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "LOCK.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_SIDR": { + "description": "HSEM size identification register.", + "fields": [ + { + "name": "SID", + "description": "SID.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/HSEM_VERR": { + "description": "HSEM IP version register.", + "fields": [ + { + "name": "MINREV", + "description": "MINREV.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "MAJREV", + "description": "MAJREV.", + "bit_offset": 4, + "bit_size": 4 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v5.json b/data/registers/hsem_v5.json new file mode 100644 index 0000000..e32f5b7 --- /dev/null +++ b/data/registers/hsem_v5.json @@ -0,0 +1,374 @@ +{ + "block/HSEM": { + "description": "HSEM.", + "items": [ + { + "name": "R", + "description": "Semaphore %s register.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "Semaphore %s read lock register.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "C1IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 256, + "fieldset": "C1IER" + }, + { + "name": "C1ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 260, + "fieldset": "C1ICR" + }, + { + "name": "C1ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 264, + "access": "Read", + "fieldset": "C1ISR" + }, + { + "name": "C1MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "C1MISR" + }, + { + "name": "C2IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 272, + "fieldset": "C2IER" + }, + { + "name": "C2ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 276, + "fieldset": "C2ICR" + }, + { + "name": "C2ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 280, + "access": "Read", + "fieldset": "C2ISR" + }, + { + "name": "C2MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 284, + "access": "Read", + "fieldset": "C2MISR" + }, + { + "name": "CR", + "description": "Semaphore Clear register.", + "byte_offset": 320, + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + }, + { + "name": "HWCFGR2", + "description": "Semaphore hardware configuration register 2.", + "byte_offset": 1004, + "access": "Read", + "fieldset": "HWCFGR2" + }, + { + "name": "HWCFGR1", + "description": "Semaphore hardware configuration register 1.", + "byte_offset": 1008, + "access": "Read", + "fieldset": "HWCFGR1" + }, + { + "name": "VERR", + "description": "HSEM version register.", + "byte_offset": 1012, + "access": "Read", + "fieldset": "VERR" + }, + { + "name": "IPIDR", + "description": "HSEM indentification register.", + "byte_offset": 1016, + "access": "Read", + "fieldset": "IPIDR" + }, + { + "name": "SIDR", + "description": "HSEM size indentification register.", + "byte_offset": 1020, + "access": "Read", + "fieldset": "SIDR" + } + ] + }, + "fieldset/C1ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISCm", + "description": "CPU(n) semaphore m clear bit.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/C1IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISEm", + "description": "CPU(n) semaphore m enable bit.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/C1ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISFm", + "description": "CPU(n) semaphore m status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/C1MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISFm", + "description": "masked CPU(n) semaphore m status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/C2ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISCm", + "description": "CPU(2) semaphore m clear bit.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/C2IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISEm", + "description": "CPU(2) semaphore m enable bit.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/C2ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISFm", + "description": "CPU(2) semaphore m status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/C2MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISFm", + "description": "masked CPU(2) semaphore m status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/CR": { + "description": "Semaphore Clear register.", + "fields": [ + { + "name": "COREID", + "description": "CoreID of semaphore to be cleared.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/HWCFGR1": { + "description": "Semaphore hardware configuration register 1.", + "fields": [ + { + "name": "NBSEM", + "description": "Hardware Configuration number of semaphores.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "NBINT", + "description": "Hardware Configuration number of interrupts supported number of master IDs.", + "bit_offset": 8, + "bit_size": 4 + } + ] + }, + "fieldset/HWCFGR2": { + "description": "Semaphore hardware configuration register 2.", + "fields": [ + { + "name": "MASTERID1", + "description": "Hardware Configuration valid bus masters ID1.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "MASTERID2", + "description": "Hardware Configuration valid bus masters ID2.", + "bit_offset": 4, + "bit_size": 4 + }, + { + "name": "MASTERID3", + "description": "Hardware Configuration valid bus masters ID3.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "MASTERID4", + "description": "Hardware Configuration valid bus masters ID4.", + "bit_offset": 12, + "bit_size": 4 + } + ] + }, + "fieldset/IPIDR": { + "description": "HSEM indentification register.", + "fields": [ + { + "name": "ID", + "description": "Identification Code.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/KEYR": { + "description": "Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/R": { + "description": "Semaphore %s register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore CoreID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "Semaphore %s read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore CoreID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/SIDR": { + "description": "HSEM size indentification register.", + "fields": [ + { + "name": "SID", + "description": "Size Identification Code.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/VERR": { + "description": "HSEM version register.", + "fields": [ + { + "name": "MINREV", + "description": "Minor Revision.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "MAJREV", + "description": "Major Revision.", + "bit_offset": 4, + "bit_size": 4 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v6.json b/data/registers/hsem_v6.json new file mode 100644 index 0000000..1df12a8 --- /dev/null +++ b/data/registers/hsem_v6.json @@ -0,0 +1,2981 @@ +{ + "block/HSEM": { + "description": "Hardware semaphore.", + "items": [ + { + "name": "HSEM_R1", + "description": "HSEM register semaphore 1.", + "byte_offset": 4, + "fieldset": "HSEM_R1" + }, + { + "name": "HSEM_R2", + "description": "HSEM register semaphore 2.", + "byte_offset": 8, + "fieldset": "HSEM_R2" + }, + { + "name": "HSEM_R3", + "description": "HSEM register semaphore 3.", + "byte_offset": 12, + "fieldset": "HSEM_R3" + }, + { + "name": "HSEM_R4", + "description": "HSEM register semaphore 4.", + "byte_offset": 16, + "fieldset": "HSEM_R4" + }, + { + "name": "HSEM_R5", + "description": "HSEM register semaphore 5.", + "byte_offset": 20, + "fieldset": "HSEM_R5" + }, + { + "name": "HSEM_R6", + "description": "HSEM register semaphore 6.", + "byte_offset": 24, + "fieldset": "HSEM_R6" + }, + { + "name": "HSEM_R7", + "description": "HSEM register semaphore 7.", + "byte_offset": 28, + "fieldset": "HSEM_R7" + }, + { + "name": "HSEM_R8", + "description": "HSEM register semaphore 8.", + "byte_offset": 32, + "fieldset": "HSEM_R8" + }, + { + "name": "HSEM_R9", + "description": "HSEM register semaphore 9.", + "byte_offset": 36, + "fieldset": "HSEM_R9" + }, + { + "name": "HSEM_R10", + "description": "HSEM register semaphore 10.", + "byte_offset": 40, + "fieldset": "HSEM_R10" + }, + { + "name": "HSEM_R11", + "description": "HSEM register semaphore 11.", + "byte_offset": 44, + "fieldset": "HSEM_R11" + }, + { + "name": "HSEM_R12", + "description": "HSEM register semaphore 12.", + "byte_offset": 48, + "fieldset": "HSEM_R12" + }, + { + "name": "HSEM_R13", + "description": "HSEM register semaphore 13.", + "byte_offset": 52, + "fieldset": "HSEM_R13" + }, + { + "name": "HSEM_R14", + "description": "HSEM register semaphore 14.", + "byte_offset": 56, + "fieldset": "HSEM_R14" + }, + { + "name": "HSEM_R15", + "description": "HSEM register semaphore 15.", + "byte_offset": 60, + "fieldset": "HSEM_R15" + }, + { + "name": "HSEM_RLR0", + "description": "HSEM read lock register semaphore 0.", + "byte_offset": 128, + "fieldset": "HSEM_RLR0" + }, + { + "name": "HSEM_RLR1", + "description": "HSEM read lock register semaphore 1.", + "byte_offset": 132, + "fieldset": "HSEM_RLR1" + }, + { + "name": "HSEM_RLR2", + "description": "HSEM read lock register semaphore 2.", + "byte_offset": 136, + "fieldset": "HSEM_RLR2" + }, + { + "name": "HSEM_RLR3", + "description": "HSEM read lock register semaphore 3.", + "byte_offset": 140, + "fieldset": "HSEM_RLR3" + }, + { + "name": "HSEM_RLR4", + "description": "HSEM read lock register semaphore 4.", + "byte_offset": 144, + "fieldset": "HSEM_RLR4" + }, + { + "name": "HSEM_RLR5", + "description": "HSEM read lock register semaphore 5.", + "byte_offset": 148, + "fieldset": "HSEM_RLR5" + }, + { + "name": "HSEM_RLR6", + "description": "HSEM read lock register semaphore 6.", + "byte_offset": 152, + "fieldset": "HSEM_RLR6" + }, + { + "name": "HSEM_RLR7", + "description": "HSEM read lock register semaphore 7.", + "byte_offset": 156, + "fieldset": "HSEM_RLR7" + }, + { + "name": "HSEM_RLR8", + "description": "HSEM read lock register semaphore 8.", + "byte_offset": 160, + "fieldset": "HSEM_RLR8" + }, + { + "name": "HSEM_RLR9", + "description": "HSEM read lock register semaphore 9.", + "byte_offset": 164, + "fieldset": "HSEM_RLR9" + }, + { + "name": "HSEM_RLR10", + "description": "HSEM read lock register semaphore 10.", + "byte_offset": 168, + "fieldset": "HSEM_RLR10" + }, + { + "name": "HSEM_RLR11", + "description": "HSEM read lock register semaphore 11.", + "byte_offset": 172, + "fieldset": "HSEM_RLR11" + }, + { + "name": "HSEM_RLR12", + "description": "HSEM read lock register semaphore 12.", + "byte_offset": 176, + "fieldset": "HSEM_RLR12" + }, + { + "name": "HSEM_RLR13", + "description": "HSEM read lock register semaphore 13.", + "byte_offset": 180, + "fieldset": "HSEM_RLR13" + }, + { + "name": "HSEM_RLR14", + "description": "HSEM read lock register semaphore 14.", + "byte_offset": 184, + "fieldset": "HSEM_RLR14" + }, + { + "name": "HSEM_RLR15", + "description": "HSEM read lock register semaphore 15.", + "byte_offset": 188, + "fieldset": "HSEM_RLR15" + }, + { + "name": "HSEM_IER", + "description": "HSEM non-secure interrupt enable register.", + "byte_offset": 256, + "fieldset": "HSEM_IER" + }, + { + "name": "HSEM_ICR", + "description": "HSEM non-secure interrupt clear register.", + "byte_offset": 260, + "fieldset": "HSEM_ICR" + }, + { + "name": "HSEM_ISR", + "description": "HSEM non-secure interrupt status register.", + "byte_offset": 264, + "fieldset": "HSEM_ISR" + }, + { + "name": "HSEM_MISR", + "description": "HSEM non-secure interrupt status register.", + "byte_offset": 268, + "fieldset": "HSEM_MISR" + }, + { + "name": "HSEM_SIER", + "description": "HSEM secure interrupt enable register.", + "byte_offset": 384, + "fieldset": "HSEM_SIER" + }, + { + "name": "HSEM_SICR", + "description": "HSEM secure interrupt clear register.", + "byte_offset": 388, + "fieldset": "HSEM_SICR" + }, + { + "name": "HSEM_SISR", + "description": "HSEM secure interrupt status register.", + "byte_offset": 392, + "fieldset": "HSEM_SISR" + }, + { + "name": "HSEM_MSISR", + "description": "HSEM secure masked interrupt status register.", + "byte_offset": 396, + "fieldset": "HSEM_MSISR" + }, + { + "name": "HSEM_SECCFGR", + "description": "HSEM security configuration register.", + "byte_offset": 512, + "fieldset": "HSEM_SECCFGR" + }, + { + "name": "HSEM_PRIVCFGR", + "description": "HSEM privilege configuration register.", + "byte_offset": 528, + "fieldset": "HSEM_PRIVCFGR" + }, + { + "name": "HSEM_CR", + "description": "HSEM clear register.", + "byte_offset": 560, + "fieldset": "HSEM_CR" + }, + { + "name": "HSEM_KEYR", + "description": "HSEM interrupt clear register.", + "byte_offset": 564, + "fieldset": "HSEM_KEYR" + }, + { + "name": "HSEM_R0", + "description": "HSEM register semaphore 0.", + "byte_offset": 1108089856, + "fieldset": "HSEM_R0" + } + ] + }, + "fieldset/HSEM_CR": { + "description": "HSEM clear register.", + "fields": [ + { + "name": "LOCKID", + "description": "LOCKID of semaphores to be cleared This field can be written by software and is always read 0. This field indicates the LOCKID for which the semaphores are cleared when writing the HSEM_CR.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "SEC value of semaphores to be cleared. This field can be written by software, is always read 0. Indicates the SEC for which the CID semaphores are cleared when writing the HSEM_CR.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "PRIV", + "description": "PRIV value of semaphores to be cleared. This field can be written by software, is always read 0. Indicates the PRIV for which the CID semaphores are cleared when writing the HSEM_CR.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "KEY", + "description": "Semaphore clear key This field can be written by software and is always read 0. If this key value does not match HSEM_KEYR.KEY, semaphores are not affected. If this key value matches HSEM_KEYR.KEY, all semaphores matching the LOCKID are cleared to the free state.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/HSEM_ICR": { + "description": "HSEM non-secure interrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "Non-secure Interrupt semaphore x clear bit This bit is written by software, and is always read 0. When semaphore x SECx is disabled, bit x can be accessed with secure and non-secure access. When semaphore x SECx is enabled, bit x cannot be accessed, write to this bit is discarded. When semaphore x PRIVx is disabled, bit x can be accessed with privileged and unprivileged access. When semaphore x PRIVx is enabled, bit x can only be accessed with privileged access. Unprivileged write to this bit is discarded.", + "bit_offset": 0, + "bit_size": 16, + "enum": "ISC" + } + ] + }, + "fieldset/HSEM_IER": { + "description": "HSEM non-secure interrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "Non-secure Interrupt semaphore x enable bit This bit is read and written by software. When semaphore x SECx is disabled, bit x can be accessed with secure and non-secure access. When semaphore x SECx is enabled, bit x is forced to 0 and cannot be accessed, write to this bit is discarded and a read returns 0. When semaphore x PRIVx is disabled, bit x can be accessed with privilege and unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with privileged access. Unprivileged write to this bit is discarded, unprivileged read returns 0.", + "bit_offset": 0, + "bit_size": 16, + "enum": "ISE" + } + ] + }, + "fieldset/HSEM_ISR": { + "description": "HSEM non-secure interrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "Interrupt semaphore x status bit before enable (mask) This bit is set by hardware, and reset only by software. This bit is cleared by software writing the corresponding HSEM_ICR bit.", + "bit_offset": 0, + "bit_size": 16, + "enum": "ISF" + } + ] + }, + "fieldset/HSEM_KEYR": { + "description": "HSEM interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore clear key This field can be written and read by software. Key value to match when clearing semaphores.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/HSEM_MISR": { + "description": "HSEM non-secure interrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "Masked non-secure interrupt semaphore x status bit after enable (mask) This bit is set by hardware and read only by software. This bit is cleared by software writing the corresponding HSEM_ICR bit. This bit is read as 0 when semaphore x status is masked in HSEM_IER bit x. When semaphore x SECx is disabled, bit x can be accessed with secure and non-secure access. When semaphore x SECx is enabled, bit x cannot be accessed, read returns 0. When semaphore x PRIVx is disabled, bit x can be accessed with privileged and unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with privileged access. Unprivileged read returns 0.", + "bit_offset": 0, + "bit_size": 16, + "enum": "MISF" + } + ] + }, + "fieldset/HSEM_MSISR": { + "description": "HSEM secure masked interrupt status register.", + "fields": [ + { + "name": "SMISF", + "description": "Secure masked interrupt semaphore x status bit after enable (mask) This bit is set by hardware and read only by software. Bit is cleared by software writing the corresponding HSEM_SCnICR bit x. Bit is read as 0 when semaphore x status is masked in HSEM_SCnIER bit x. When semaphore x PRIVx is disabled, bit x can be accessed with secure privilege and secure unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with secure privilege access. Secure unprivileged read return 0 value.", + "bit_offset": 0, + "bit_size": 16, + "enum": "SMISF" + } + ] + }, + "fieldset/HSEM_PRIVCFGR": { + "description": "HSEM privilege configuration register.", + "fields": [ + { + "name": "PRIV", + "description": "Semaphore x privilege attribute This bit is set and cleared by software. When semaphore x SECx is disabled, bit x can be write accessed with secure privileged and non-secure privileged access. When semaphore x SECx is enabled, bit x can only be write accessed with secure privilege access. Non-secure privileged write access is discarded. Both secure and non-secure read return the register bit x value.", + "bit_offset": 0, + "bit_size": 16, + "enum": "HSEM_PRIVCFGR_PRIV" + } + ] + }, + "fieldset/HSEM_R0": { + "description": "HSEM register semaphore 0.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R0_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R0_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R0_LOCK" + } + ] + }, + "fieldset/HSEM_R1": { + "description": "HSEM register semaphore 1.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R1_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R1_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R1_LOCK" + } + ] + }, + "fieldset/HSEM_R10": { + "description": "HSEM register semaphore 10.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R10_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R10_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R10_LOCK" + } + ] + }, + "fieldset/HSEM_R11": { + "description": "HSEM register semaphore 11.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R11_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R11_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R11_LOCK" + } + ] + }, + "fieldset/HSEM_R12": { + "description": "HSEM register semaphore 12.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R12_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R12_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R12_LOCK" + } + ] + }, + "fieldset/HSEM_R13": { + "description": "HSEM register semaphore 13.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R13_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R13_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R13_LOCK" + } + ] + }, + "fieldset/HSEM_R14": { + "description": "HSEM register semaphore 14.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R14_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R14_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R14_LOCK" + } + ] + }, + "fieldset/HSEM_R15": { + "description": "HSEM register semaphore 15.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R15_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R15_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R15_LOCK" + } + ] + }, + "fieldset/HSEM_R2": { + "description": "HSEM register semaphore 2.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R2_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R2_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R2_LOCK" + } + ] + }, + "fieldset/HSEM_R3": { + "description": "HSEM register semaphore 3.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R3_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R3_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R3_LOCK" + } + ] + }, + "fieldset/HSEM_R4": { + "description": "HSEM register semaphore 4.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R4_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R4_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R4_LOCK" + } + ] + }, + "fieldset/HSEM_R5": { + "description": "HSEM register semaphore 5.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R5_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R5_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R5_LOCK" + } + ] + }, + "fieldset/HSEM_R6": { + "description": "HSEM register semaphore 6.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R6_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R6_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R6_LOCK" + } + ] + }, + "fieldset/HSEM_R7": { + "description": "HSEM register semaphore 7.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R7_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R7_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R7_LOCK" + } + ] + }, + "fieldset/HSEM_R8": { + "description": "HSEM register semaphore 8.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R8_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R8_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R8_LOCK" + } + ] + }, + "fieldset/HSEM_R9": { + "description": "HSEM register semaphore 9.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore PROCID Written by software -When the semaphore is free and the LOCK is written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition, PROCID is set to the written data. - When the semaphore is unlocked, LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the PROCID is cleared to 0. - When the semaphore is unlocked, LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match the AHB bus master definition, the PROCID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PROCID is not affected. - An authorized read returns the stored PROCID value.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1 and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master protection. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master protection, the LOCKID is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 or AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master protection, the LOCKID is not affected. - Write when LOCK bit is already 1 (semaphore locked), the LOCKID is not affected. - An authorized read returns the stored LOCKID value.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the SEC is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the SEC is not affected. - Write when LOCK bit is already 1 (semaphore locked), the SEC is not affected. - An authorized read returns the stored SEC value.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_R9_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege Written by software - When the semaphore is free and the LOCK bit is at the same time written to 1, and the LOCKID matches the AHB bus master ID, SEC and PRIV matches the AHB bus master definition. - When the semaphore is unlocked (LOCK written to 0 and AHB bus master ID matched LOCKID, SEC and PRIV matches the AHB bus master definition, the PRIV is cleared to 0. - When the semaphore is unlocked (LOCK bit written to 0 and AHB bus master ID does not match LOCKID and/or SEC or PRIV do not match AHB bus master definition, the PRIV is not affected. - Write when LOCK bit is already 1 (semaphore locked), the PRIV is not affected. - An authorized read returns the stored PRIV value.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_R9_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit can be written and read by software.", + "bit_offset": 31, + "bit_size": 1, + "enum": "HSEM_R9_LOCK" + } + ] + }, + "fieldset/HSEM_RLR0": { + "description": "HSEM read lock register semaphore 0.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR0_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR0_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR1": { + "description": "HSEM read lock register semaphore 1.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR1_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR1_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR10": { + "description": "HSEM read lock register semaphore 10.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR10_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR10_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR11": { + "description": "HSEM read lock register semaphore 11.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR11_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR11_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR12": { + "description": "HSEM read lock register semaphore 12.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR12_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR12_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR13": { + "description": "HSEM read lock register semaphore 13.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR13_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR13_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR14": { + "description": "HSEM read lock register semaphore 14.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR14_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR14_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR15": { + "description": "HSEM read lock register semaphore 15.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR15_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR15_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR2": { + "description": "HSEM read lock register semaphore 2.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR2_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR2_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR3": { + "description": "HSEM read lock register semaphore 3.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR3_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR3_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR4": { + "description": "HSEM read lock register semaphore 4.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR4_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR4_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR5": { + "description": "HSEM read lock register semaphore 5.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR5_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR5_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR6": { + "description": "HSEM read lock register semaphore 6.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR6_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR6_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR7": { + "description": "HSEM read lock register semaphore 7.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR7_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR7_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR8": { + "description": "HSEM read lock register semaphore 8.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR8_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR8_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_RLR9": { + "description": "HSEM read lock register semaphore 9.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore processor ID This field is read only by software at this address. - On a read when the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PROCID to 0. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PROCID of the AHB bus master that has locked the semaphore.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "LOCKID", + "description": "Semaphore LOCKID This field is read only by software at this address. On a read, when the semaphore is free, the hardware sets the LOCKID to the AHB bus master ID reading the semaphore. The LOCKID of the AHB bus master locking the semaphore is read. On a read when the semaphore is locked, this field returns the LOCKID of the AHB bus master that has locked the semaphore.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SEC", + "description": "Semaphore secure. This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the SEC to the valid AHB bus master security definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the SEC of the AHB bus master that has locked the semaphore.", + "bit_offset": 12, + "bit_size": 1, + "enum": "HSEM_RLR9_SEC" + }, + { + "name": "PRIV", + "description": "Semaphore privilege This field is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and hardware sets the PRIV to the valid AHB bus master privileged definition. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns the PRIV of the AHB bus master that has locked the semaphore.", + "bit_offset": 13, + "bit_size": 1, + "enum": "HSEM_RLR9_PRIV" + }, + { + "name": "LOCK", + "description": "Lock indication This bit is read only by software at this address. - When the semaphore is free: A read with a valid AHB bus master ID and SEC and PRIV locks the semaphore and returns 1. - When the semaphore is locked: A read with a valid AHB bus master ID and SEC and PRIV returns 1 (the LOCKID and SEC and PRIV and PROCID reflect the already locked semaphore information).", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSEM_SECCFGR": { + "description": "HSEM security configuration register.", + "fields": [ + { + "name": "SEC", + "description": "Semaphore x security attribute This bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 16, + "enum": "HSEM_SECCFGR_SEC" + } + ] + }, + "fieldset/HSEM_SICR": { + "description": "HSEM secure interrupt clear register.", + "fields": [ + { + "name": "SISC", + "description": "Secure interrupt semaphore x clear bit This bit is written by software, and is always read 0. When semaphore x PRIVx is disabled, bit x can be accessed with secure privilege and secure unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with secure privilege access. Secure unprivileged write to this bit is discarded.", + "bit_offset": 0, + "bit_size": 16, + "enum": "SISC" + } + ] + }, + "fieldset/HSEM_SIER": { + "description": "HSEM secure interrupt enable register.", + "fields": [ + { + "name": "SISE", + "description": "Secure interrupt semaphore x enable bit This bit is read and written by software. When semaphore x PRIVx is disabled, bit x can be accessed with secure privilege and secure unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with secure privilege access. secure unprivileged write to this bit is discarded, secure unprivileged read return 0 value.", + "bit_offset": 0, + "bit_size": 16, + "enum": "SISE" + } + ] + }, + "fieldset/HSEM_SISR": { + "description": "HSEM secure interrupt status register.", + "fields": [ + { + "name": "SISF", + "description": "Secure interrupt semaphore x status bit before enable (mask) This bit is set by hardware and read only by software. Bit is cleared by software writing the corresponding HSEM_SCnICR bit x. When semaphore x PRIVx is disabled, bit x can be accessed with secure privilege and secure unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with secure privilege access. Secure unprivileged read return 0 value.", + "bit_offset": 0, + "bit_size": 16, + "enum": "SISF" + } + ] + }, + "enum/HSEM_PRIVCFGR_PRIV": { + "bit_size": 16, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore x unprivileged, can be accessed by both privileged and unprivileged processors.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore x privileged, can be accessed only by privileged processors.", + "value": 1 + } + ] + }, + "enum/HSEM_R0_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R0_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R0_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R10_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R10_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R10_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R11_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R11_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R11_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R12_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R12_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R12_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R13_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R13_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R13_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R14_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R14_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R14_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R15_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R15_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R15_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R1_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R1_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R1_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R2_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R2_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R2_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R3_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R3_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R3_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R4_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R4_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R4_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R5_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R5_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R5_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R6_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R6_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R6_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R7_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R7_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R7_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R8_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R8_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R8_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R9_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "On write free semaphore (only when LOCKID and PROCID match), on read semaphore is free.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "On write try to lock semaphore, on read semaphore is locked.", + "value": 1 + } + ] + }, + "enum/HSEM_R9_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privilege compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_R9_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR0_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR0_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR10_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR10_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR11_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR11_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR12_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR12_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR13_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR13_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR14_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR14_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR15_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR15_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR1_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR1_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR2_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR2_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR3_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR3_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR4_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR4_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR5_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR5_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR6_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR6_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR7_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR7_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR8_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR8_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR9_PRIV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by unprivileged compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by privileged compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_RLR9_SEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore free or locked by non-secure compartment.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore locked by secure compartment.", + "value": 1 + } + ] + }, + "enum/HSEM_SECCFGR_SEC": { + "bit_size": 16, + "variants": [ + { + "name": "B_0x0", + "description": "Semaphore x non-security, can be accessed by both secure and non-secure processors. When unlocking semaphore x both a secure and non-secure interrupt can be generated.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Semaphore x security, can be accessed only by secure processors. When unlocking semaphore x only a secure interrupt can be generated.", + "value": 1 + } + ] + }, + "enum/ISC": { + "bit_size": 16, + "variants": [ + { + "name": "B_0x0", + "description": "non-secure Interrupt semaphore x status ISFx and masked status MISFx not affected.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "non-secure Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/ISE": { + "bit_size": 16, + "variants": [ + { + "name": "B_0x0", + "description": "Non-secure Interrupt generation for semaphore x disabled (masked).", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Non-secure Interrupt generation for semaphore x enabled (not masked).", + "value": 1 + } + ] + }, + "enum/ISF": { + "bit_size": 16, + "variants": [ + { + "name": "B_0x0", + "description": "Interrupt semaphore x status, no interrupt pending.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Interrupt semaphore x status, interrupt pending.", + "value": 1 + } + ] + }, + "enum/MISF": { + "bit_size": 16, + "variants": [ + { + "name": "B_0x0", + "description": "non-secure interrupt semaphore x status after masking not pending.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "non-secure interrupt semaphore x status after masking pending.", + "value": 1 + } + ] + }, + "enum/SISC": { + "bit_size": 16, + "variants": [ + { + "name": "B_0x0", + "description": "Secure interrupt semaphore x status ISFx and masked status MISFx not affected.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Secure interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/SISE": { + "bit_size": 16, + "variants": [ + { + "name": "B_0x0", + "description": "Secure interrupt generation for semaphore x is disabled (masked).", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Secure interrupt generation for semaphore x is enabled (not masked).", + "value": 1 + } + ] + }, + "enum/SISF": { + "bit_size": 16, + "variants": [ + { + "name": "B_0x0", + "description": "Secure interrupt semaphore x status, no interrupt pending.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Secure interrupt semaphore x status, interrupt pending.", + "value": 1 + } + ] + }, + "enum/SMISF": { + "bit_size": 16, + "variants": [ + { + "name": "B_0x0", + "description": "Secure interrupt semaphore x status after masking not pending.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Secure interrupt semaphore x status after masking pending.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v7.json b/data/registers/hsem_v7.json new file mode 100644 index 0000000..1df78d4 --- /dev/null +++ b/data/registers/hsem_v7.json @@ -0,0 +1,3055 @@ +{ + "block/HSEM": { + "description": "Hardware semaphore.", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "C1IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 256, + "fieldset": "C1IER" + }, + { + "name": "C1ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 260, + "fieldset": "C1ICR" + }, + { + "name": "C1ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 264, + "access": "Read", + "fieldset": "C1ISR" + }, + { + "name": "C1MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "C1MISR" + }, + { + "name": "C2IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 272, + "fieldset": "C2IER" + }, + { + "name": "C2ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 276, + "fieldset": "C2ICR" + }, + { + "name": "C2ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 280, + "access": "Read", + "fieldset": "C2ISR" + }, + { + "name": "C2MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 284, + "access": "Read", + "fieldset": "C2MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "access": "Write", + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/C1ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC0", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 0, + "bit_size": 1, + "enum": "C1ICR_ISC0" + }, + { + "name": "ISC1", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 1, + "bit_size": 1, + "enum": "C1ICR_ISC1" + }, + { + "name": "ISC2", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 2, + "bit_size": 1, + "enum": "C1ICR_ISC2" + }, + { + "name": "ISC3", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 3, + "bit_size": 1, + "enum": "C1ICR_ISC3" + }, + { + "name": "ISC4", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 4, + "bit_size": 1, + "enum": "C1ICR_ISC4" + }, + { + "name": "ISC5", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 5, + "bit_size": 1, + "enum": "C1ICR_ISC5" + }, + { + "name": "ISC6", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 6, + "bit_size": 1, + "enum": "C1ICR_ISC6" + }, + { + "name": "ISC7", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 7, + "bit_size": 1, + "enum": "C1ICR_ISC7" + }, + { + "name": "ISC8", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 8, + "bit_size": 1, + "enum": "C1ICR_ISC8" + }, + { + "name": "ISC9", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 9, + "bit_size": 1, + "enum": "C1ICR_ISC9" + }, + { + "name": "ISC10", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 10, + "bit_size": 1, + "enum": "C1ICR_ISC10" + }, + { + "name": "ISC11", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 11, + "bit_size": 1, + "enum": "C1ICR_ISC11" + }, + { + "name": "ISC12", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 12, + "bit_size": 1, + "enum": "C1ICR_ISC12" + }, + { + "name": "ISC13", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 13, + "bit_size": 1, + "enum": "C1ICR_ISC13" + }, + { + "name": "ISC14", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 14, + "bit_size": 1, + "enum": "C1ICR_ISC14" + }, + { + "name": "ISC15", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 15, + "bit_size": 1, + "enum": "C1ICR_ISC15" + } + ] + }, + "fieldset/C1IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE0", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 0, + "bit_size": 1, + "enum": "C1IER_ISE0" + }, + { + "name": "ISE1", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 1, + "bit_size": 1, + "enum": "C1IER_ISE1" + }, + { + "name": "ISE2", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 2, + "bit_size": 1, + "enum": "C1IER_ISE2" + }, + { + "name": "ISE3", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 3, + "bit_size": 1, + "enum": "C1IER_ISE3" + }, + { + "name": "ISE4", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 4, + "bit_size": 1, + "enum": "C1IER_ISE4" + }, + { + "name": "ISE5", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 5, + "bit_size": 1, + "enum": "C1IER_ISE5" + }, + { + "name": "ISE6", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 6, + "bit_size": 1, + "enum": "C1IER_ISE6" + }, + { + "name": "ISE7", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 7, + "bit_size": 1, + "enum": "C1IER_ISE7" + }, + { + "name": "ISE8", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 8, + "bit_size": 1, + "enum": "C1IER_ISE8" + }, + { + "name": "ISE9", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 9, + "bit_size": 1, + "enum": "C1IER_ISE9" + }, + { + "name": "ISE10", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 10, + "bit_size": 1, + "enum": "C1IER_ISE10" + }, + { + "name": "ISE11", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 11, + "bit_size": 1, + "enum": "C1IER_ISE11" + }, + { + "name": "ISE12", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 12, + "bit_size": 1, + "enum": "C1IER_ISE12" + }, + { + "name": "ISE13", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 13, + "bit_size": 1, + "enum": "C1IER_ISE13" + }, + { + "name": "ISE14", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 14, + "bit_size": 1, + "enum": "C1IER_ISE14" + }, + { + "name": "ISE15", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 15, + "bit_size": 1, + "enum": "C1IER_ISE15" + } + ] + }, + "fieldset/C1ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF0", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "enum": "C1ISR_ISF0" + }, + { + "name": "ISF1", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 1, + "bit_size": 1, + "enum": "C1ISR_ISF1" + }, + { + "name": "ISF2", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 2, + "bit_size": 1, + "enum": "C1ISR_ISF2" + }, + { + "name": "ISF3", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 3, + "bit_size": 1, + "enum": "C1ISR_ISF3" + }, + { + "name": "ISF4", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 4, + "bit_size": 1, + "enum": "C1ISR_ISF4" + }, + { + "name": "ISF5", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 5, + "bit_size": 1, + "enum": "C1ISR_ISF5" + }, + { + "name": "ISF6", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 6, + "bit_size": 1, + "enum": "C1ISR_ISF6" + }, + { + "name": "ISF7", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 7, + "bit_size": 1, + "enum": "C1ISR_ISF7" + }, + { + "name": "ISF8", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 8, + "bit_size": 1, + "enum": "C1ISR_ISF8" + }, + { + "name": "ISF9", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 9, + "bit_size": 1, + "enum": "C1ISR_ISF9" + }, + { + "name": "ISF10", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 10, + "bit_size": 1, + "enum": "C1ISR_ISF10" + }, + { + "name": "ISF11", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 11, + "bit_size": 1, + "enum": "C1ISR_ISF11" + }, + { + "name": "ISF12", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 12, + "bit_size": 1, + "enum": "C1ISR_ISF12" + }, + { + "name": "ISF13", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 13, + "bit_size": 1, + "enum": "C1ISR_ISF13" + }, + { + "name": "ISF14", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 14, + "bit_size": 1, + "enum": "C1ISR_ISF14" + }, + { + "name": "ISF15", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 15, + "bit_size": 1, + "enum": "C1ISR_ISF15" + } + ] + }, + "fieldset/C1MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF0", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "enum": "C1MISR_MISF0" + }, + { + "name": "MISF1", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 1, + "bit_size": 1, + "enum": "C1MISR_MISF1" + }, + { + "name": "MISF2", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 2, + "bit_size": 1, + "enum": "C1MISR_MISF2" + }, + { + "name": "MISF3", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 3, + "bit_size": 1, + "enum": "C1MISR_MISF3" + }, + { + "name": "MISF4", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 4, + "bit_size": 1, + "enum": "C1MISR_MISF4" + }, + { + "name": "MISF5", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 5, + "bit_size": 1, + "enum": "C1MISR_MISF5" + }, + { + "name": "MISF6", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 6, + "bit_size": 1, + "enum": "C1MISR_MISF6" + }, + { + "name": "MISF7", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 7, + "bit_size": 1, + "enum": "C1MISR_MISF7" + }, + { + "name": "MISF8", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 8, + "bit_size": 1, + "enum": "C1MISR_MISF8" + }, + { + "name": "MISF9", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 9, + "bit_size": 1, + "enum": "C1MISR_MISF9" + }, + { + "name": "MISF10", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 10, + "bit_size": 1, + "enum": "C1MISR_MISF10" + }, + { + "name": "MISF11", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 11, + "bit_size": 1, + "enum": "C1MISR_MISF11" + }, + { + "name": "MISF12", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 12, + "bit_size": 1, + "enum": "C1MISR_MISF12" + }, + { + "name": "MISF13", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 13, + "bit_size": 1, + "enum": "C1MISR_MISF13" + }, + { + "name": "MISF14", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 14, + "bit_size": 1, + "enum": "C1MISR_MISF14" + }, + { + "name": "MISF15", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 15, + "bit_size": 1, + "enum": "C1MISR_MISF15" + } + ] + }, + "fieldset/C2ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC0", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 0, + "bit_size": 1, + "enum": "C2ICR_ISC0" + }, + { + "name": "ISC1", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 1, + "bit_size": 1, + "enum": "C2ICR_ISC1" + }, + { + "name": "ISC2", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 2, + "bit_size": 1, + "enum": "C2ICR_ISC2" + }, + { + "name": "ISC3", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 3, + "bit_size": 1, + "enum": "C2ICR_ISC3" + }, + { + "name": "ISC4", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 4, + "bit_size": 1, + "enum": "C2ICR_ISC4" + }, + { + "name": "ISC5", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 5, + "bit_size": 1, + "enum": "C2ICR_ISC5" + }, + { + "name": "ISC6", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 6, + "bit_size": 1, + "enum": "C2ICR_ISC6" + }, + { + "name": "ISC7", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 7, + "bit_size": 1, + "enum": "C2ICR_ISC7" + }, + { + "name": "ISC8", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 8, + "bit_size": 1, + "enum": "C2ICR_ISC8" + }, + { + "name": "ISC9", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 9, + "bit_size": 1, + "enum": "C2ICR_ISC9" + }, + { + "name": "ISC10", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 10, + "bit_size": 1, + "enum": "C2ICR_ISC10" + }, + { + "name": "ISC11", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 11, + "bit_size": 1, + "enum": "C2ICR_ISC11" + }, + { + "name": "ISC12", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 12, + "bit_size": 1, + "enum": "C2ICR_ISC12" + }, + { + "name": "ISC13", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 13, + "bit_size": 1, + "enum": "C2ICR_ISC13" + }, + { + "name": "ISC14", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 14, + "bit_size": 1, + "enum": "C2ICR_ISC14" + }, + { + "name": "ISC15", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 15, + "bit_size": 1, + "enum": "C2ICR_ISC15" + } + ] + }, + "fieldset/C2IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE0", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 0, + "bit_size": 1, + "enum": "C2IER_ISE0" + }, + { + "name": "ISE1", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 1, + "bit_size": 1, + "enum": "C2IER_ISE1" + }, + { + "name": "ISE2", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 2, + "bit_size": 1, + "enum": "C2IER_ISE2" + }, + { + "name": "ISE3", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 3, + "bit_size": 1, + "enum": "C2IER_ISE3" + }, + { + "name": "ISE4", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 4, + "bit_size": 1, + "enum": "C2IER_ISE4" + }, + { + "name": "ISE5", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 5, + "bit_size": 1, + "enum": "C2IER_ISE5" + }, + { + "name": "ISE6", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 6, + "bit_size": 1, + "enum": "C2IER_ISE6" + }, + { + "name": "ISE7", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 7, + "bit_size": 1, + "enum": "C2IER_ISE7" + }, + { + "name": "ISE8", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 8, + "bit_size": 1, + "enum": "C2IER_ISE8" + }, + { + "name": "ISE9", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 9, + "bit_size": 1, + "enum": "C2IER_ISE9" + }, + { + "name": "ISE10", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 10, + "bit_size": 1, + "enum": "C2IER_ISE10" + }, + { + "name": "ISE11", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 11, + "bit_size": 1, + "enum": "C2IER_ISE11" + }, + { + "name": "ISE12", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 12, + "bit_size": 1, + "enum": "C2IER_ISE12" + }, + { + "name": "ISE13", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 13, + "bit_size": 1, + "enum": "C2IER_ISE13" + }, + { + "name": "ISE14", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 14, + "bit_size": 1, + "enum": "C2IER_ISE14" + }, + { + "name": "ISE15", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 15, + "bit_size": 1, + "enum": "C2IER_ISE15" + } + ] + }, + "fieldset/C2ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF0", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "enum": "C2ISR_ISF0" + }, + { + "name": "ISF1", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 1, + "bit_size": 1, + "enum": "C2ISR_ISF1" + }, + { + "name": "ISF2", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 2, + "bit_size": 1, + "enum": "C2ISR_ISF2" + }, + { + "name": "ISF3", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 3, + "bit_size": 1, + "enum": "C2ISR_ISF3" + }, + { + "name": "ISF4", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 4, + "bit_size": 1, + "enum": "C2ISR_ISF4" + }, + { + "name": "ISF5", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 5, + "bit_size": 1, + "enum": "C2ISR_ISF5" + }, + { + "name": "ISF6", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 6, + "bit_size": 1, + "enum": "C2ISR_ISF6" + }, + { + "name": "ISF7", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 7, + "bit_size": 1, + "enum": "C2ISR_ISF7" + }, + { + "name": "ISF8", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 8, + "bit_size": 1, + "enum": "C2ISR_ISF8" + }, + { + "name": "ISF9", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 9, + "bit_size": 1, + "enum": "C2ISR_ISF9" + }, + { + "name": "ISF10", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 10, + "bit_size": 1, + "enum": "C2ISR_ISF10" + }, + { + "name": "ISF11", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 11, + "bit_size": 1, + "enum": "C2ISR_ISF11" + }, + { + "name": "ISF12", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 12, + "bit_size": 1, + "enum": "C2ISR_ISF12" + }, + { + "name": "ISF13", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 13, + "bit_size": 1, + "enum": "C2ISR_ISF13" + }, + { + "name": "ISF14", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 14, + "bit_size": 1, + "enum": "C2ISR_ISF14" + }, + { + "name": "ISF15", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 15, + "bit_size": 1, + "enum": "C2ISR_ISF15" + } + ] + }, + "fieldset/C2MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF0", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "enum": "C2MISR_MISF0" + }, + { + "name": "MISF1", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 1, + "bit_size": 1, + "enum": "C2MISR_MISF1" + }, + { + "name": "MISF2", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 2, + "bit_size": 1, + "enum": "C2MISR_MISF2" + }, + { + "name": "MISF3", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 3, + "bit_size": 1, + "enum": "C2MISR_MISF3" + }, + { + "name": "MISF4", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 4, + "bit_size": 1, + "enum": "C2MISR_MISF4" + }, + { + "name": "MISF5", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 5, + "bit_size": 1, + "enum": "C2MISR_MISF5" + }, + { + "name": "MISF6", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 6, + "bit_size": 1, + "enum": "C2MISR_MISF6" + }, + { + "name": "MISF7", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 7, + "bit_size": 1, + "enum": "C2MISR_MISF7" + }, + { + "name": "MISF8", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 8, + "bit_size": 1, + "enum": "C2MISR_MISF8" + }, + { + "name": "MISF9", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 9, + "bit_size": 1, + "enum": "C2MISR_MISF9" + }, + { + "name": "MISF10", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 10, + "bit_size": 1, + "enum": "C2MISR_MISF10" + }, + { + "name": "MISF11", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 11, + "bit_size": 1, + "enum": "C2MISR_MISF11" + }, + { + "name": "MISF12", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 12, + "bit_size": 1, + "enum": "C2MISR_MISF12" + }, + { + "name": "MISF13", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 13, + "bit_size": 1, + "enum": "C2MISR_MISF13" + }, + { + "name": "MISF14", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 14, + "bit_size": 1, + "enum": "C2MISR_MISF14" + }, + { + "name": "MISF15", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 15, + "bit_size": 1, + "enum": "C2MISR_MISF15" + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1, + "enum": "R_LOCK" + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1, + "enum": "RLR_LOCK" + } + ] + }, + "enum/C1ICR_ISC0": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC1": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC10": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC11": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC12": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC13": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC14": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC15": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC2": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC3": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC4": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC5": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC6": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC7": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC8": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1ICR_ISC9": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE0": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE1": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE10": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE11": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE12": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE13": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE14": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE15": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE2": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE3": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE4": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE5": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE6": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE7": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE8": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1IER_ISE9": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF0": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF1": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF10": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF11": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF12": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF13": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF14": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF15": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF2": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF3": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF4": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF5": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF6": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF7": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF8": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1ISR_ISF9": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF0": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF1": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF10": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF11": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF12": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF13": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF14": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF15": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF2": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF3": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF4": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF5": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF6": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF7": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF8": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C1MISR_MISF9": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC0": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC1": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC10": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC11": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC12": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC13": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC14": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC15": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC2": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC3": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC4": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC5": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC6": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC7": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC8": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2ICR_ISC9": { + "bit_size": 1, + "variants": [ + { + "name": "NoEffect", + "description": "Always reads 0.", + "value": 0 + }, + { + "name": "Clear", + "description": "Interrupt semaphore x status ISFx and masked status MISFx cleared.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE0": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE1": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE10": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE11": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE12": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE13": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE14": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE15": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE2": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE3": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE4": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE5": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE6": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE7": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE8": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2IER_ISE9": { + "bit_size": 1, + "variants": [ + { + "name": "Disabled", + "description": "Interrupt generation disabled.", + "value": 0 + }, + { + "name": "Enabled", + "description": "Interrupt generation enabled.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF0": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF1": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF10": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF11": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF12": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF13": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF14": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF15": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF2": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF3": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF4": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF5": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF6": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF7": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF8": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2ISR_ISF9": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF0": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF1": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF10": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF11": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF12": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF13": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF14": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF15": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF2": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF3": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF4": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF5": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF6": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF7": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF8": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/C2MISR_MISF9": { + "bit_size": 1, + "variants": [ + { + "name": "NotPending", + "description": "No interrupt pending after masking.", + "value": 0 + }, + { + "name": "Pending", + "description": "Interrupt pending after masking.", + "value": 1 + } + ] + }, + "enum/RLR_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "Free", + "description": "Semaphore is free.", + "value": 0 + }, + { + "name": "Locked", + "description": "Semaphore is locked.", + "value": 1 + } + ] + }, + "enum/R_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "Free", + "description": "Semaphore is free.", + "value": 0 + }, + { + "name": "R_Locked_W_TryLock", + "description": "Semaphore is locked.", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v8.json b/data/registers/hsem_v8.json new file mode 100644 index 0000000..94ba696 --- /dev/null +++ b/data/registers/hsem_v8.json @@ -0,0 +1,233 @@ +{ + "block/HSEM": { + "description": "Hardware semaphore.", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "C1IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 256, + "fieldset": "C1IER" + }, + { + "name": "C1ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 260, + "fieldset": "C1ICR" + }, + { + "name": "C1ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 264, + "access": "Read", + "fieldset": "C1ISR" + }, + { + "name": "C1MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "C1MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "access": "Write", + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/C1ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/C1IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/C1ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/C1MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "MASTERID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore MASTERID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1, + "enum": "R_LOCK" + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore MASTERID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1, + "enum": "RLR_LOCK" + } + ] + }, + "enum/RLR_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "Free", + "description": "Semaphore is free.", + "value": 0 + }, + { + "name": "Locked", + "description": "Semaphore is locked.", + "value": 1 + } + ] + }, + "enum/R_LOCK": { + "bit_size": 1, + "variants": [ + { + "name": "Free", + "description": "Semaphore is free.", + "value": 0 + }, + { + "name": "R_Locked_W_TryLock", + "description": "Semaphore is locked.", + "value": 1 + } + ] + } +} \ No newline at end of file