diff --git a/data/chips/STM32C071C8.json b/data/chips/STM32C071C8.json index f6a6b6f..39870b7 100644 --- a/data/chips/STM32C071C8.json +++ b/data/chips/STM32C071C8.json @@ -3736,6 +3736,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32C071CB.json b/data/chips/STM32C071CB.json index 71e3f01..4566640 100644 --- a/data/chips/STM32C071CB.json +++ b/data/chips/STM32C071CB.json @@ -3736,6 +3736,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32C071F8.json b/data/chips/STM32C071F8.json index a22c6f6..be99054 100644 --- a/data/chips/STM32C071F8.json +++ b/data/chips/STM32C071F8.json @@ -2512,6 +2512,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32C071FB.json b/data/chips/STM32C071FB.json index 9921160..83e76e6 100644 --- a/data/chips/STM32C071FB.json +++ b/data/chips/STM32C071FB.json @@ -2640,6 +2640,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32C071G8.json b/data/chips/STM32C071G8.json index 87633cb..ac717ab 100644 --- a/data/chips/STM32C071G8.json +++ b/data/chips/STM32C071G8.json @@ -2656,6 +2656,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32C071GB.json b/data/chips/STM32C071GB.json index 34b4f9f..b53082c 100644 --- a/data/chips/STM32C071GB.json +++ b/data/chips/STM32C071GB.json @@ -2656,6 +2656,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32C071K8.json b/data/chips/STM32C071K8.json index 213d37b..592afc0 100644 --- a/data/chips/STM32C071K8.json +++ b/data/chips/STM32C071K8.json @@ -3158,6 +3158,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32C071KB.json b/data/chips/STM32C071KB.json index 92c39ae..0a6d1ee 100644 --- a/data/chips/STM32C071KB.json +++ b/data/chips/STM32C071KB.json @@ -3158,6 +3158,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32C071R8.json b/data/chips/STM32C071R8.json index 45fd6a1..aa0b850 100644 --- a/data/chips/STM32C071R8.json +++ b/data/chips/STM32C071R8.json @@ -3508,6 +3508,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32C071RB.json b/data/chips/STM32C071RB.json index c6cf850..526be1b 100644 --- a/data/chips/STM32C071RB.json +++ b/data/chips/STM32C071RB.json @@ -3900,6 +3900,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32F042C4.json b/data/chips/STM32F042C4.json index 3dda44a..a225f3e 100644 --- a/data/chips/STM32F042C4.json +++ b/data/chips/STM32F042C4.json @@ -2777,6 +2777,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F042C6.json b/data/chips/STM32F042C6.json index b30871a..5f73514 100644 --- a/data/chips/STM32F042C6.json +++ b/data/chips/STM32F042C6.json @@ -2777,6 +2777,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F042F4.json b/data/chips/STM32F042F4.json index bd1a713..0ff11ff 100644 --- a/data/chips/STM32F042F4.json +++ b/data/chips/STM32F042F4.json @@ -1941,6 +1941,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F042F6.json b/data/chips/STM32F042F6.json index d7a1410..b0c61e8 100644 --- a/data/chips/STM32F042F6.json +++ b/data/chips/STM32F042F6.json @@ -1941,6 +1941,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F042G4.json b/data/chips/STM32F042G4.json index 073d6b4..a1aa0ff 100644 --- a/data/chips/STM32F042G4.json +++ b/data/chips/STM32F042G4.json @@ -2168,6 +2168,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F042G6.json b/data/chips/STM32F042G6.json index 02ed3d4..5f6d5c2 100644 --- a/data/chips/STM32F042G6.json +++ b/data/chips/STM32F042G6.json @@ -2168,6 +2168,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F042K4.json b/data/chips/STM32F042K4.json index ef1e3d1..2bd8a56 100644 --- a/data/chips/STM32F042K4.json +++ b/data/chips/STM32F042K4.json @@ -2418,6 +2418,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F042K6.json b/data/chips/STM32F042K6.json index e200e33..99b79e8 100644 --- a/data/chips/STM32F042K6.json +++ b/data/chips/STM32F042K6.json @@ -2418,6 +2418,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F042T6.json b/data/chips/STM32F042T6.json index 340bddc..6ac82b4 100644 --- a/data/chips/STM32F042T6.json +++ b/data/chips/STM32F042T6.json @@ -2268,6 +2268,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F048C6.json b/data/chips/STM32F048C6.json index 2862f75..2935499 100644 --- a/data/chips/STM32F048C6.json +++ b/data/chips/STM32F048C6.json @@ -2411,6 +2411,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F048G6.json b/data/chips/STM32F048G6.json index bd78fcc..ea8fde6 100644 --- a/data/chips/STM32F048G6.json +++ b/data/chips/STM32F048G6.json @@ -2077,6 +2077,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F048T6.json b/data/chips/STM32F048T6.json index e1a9ce5..4525604 100644 --- a/data/chips/STM32F048T6.json +++ b/data/chips/STM32F048T6.json @@ -2201,6 +2201,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F070C6.json b/data/chips/STM32F070C6.json index 76458b2..f837c40 100644 --- a/data/chips/STM32F070C6.json +++ b/data/chips/STM32F070C6.json @@ -1965,6 +1965,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F070CB.json b/data/chips/STM32F070CB.json index 2ae85d7..f61b48b 100644 --- a/data/chips/STM32F070CB.json +++ b/data/chips/STM32F070CB.json @@ -2423,6 +2423,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F070F6.json b/data/chips/STM32F070F6.json index 340862c..874aa8c 100644 --- a/data/chips/STM32F070F6.json +++ b/data/chips/STM32F070F6.json @@ -1627,6 +1627,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F070RB.json b/data/chips/STM32F070RB.json index 8b3afd3..4b9124a 100644 --- a/data/chips/STM32F070RB.json +++ b/data/chips/STM32F070RB.json @@ -2628,6 +2628,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F072C8.json b/data/chips/STM32F072C8.json index 9307b90..cb870bd 100644 --- a/data/chips/STM32F072C8.json +++ b/data/chips/STM32F072C8.json @@ -3450,6 +3450,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F072CB.json b/data/chips/STM32F072CB.json index e821f93..fc1be54 100644 --- a/data/chips/STM32F072CB.json +++ b/data/chips/STM32F072CB.json @@ -3748,6 +3748,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F072R8.json b/data/chips/STM32F072R8.json index d524bfb..1e43c04 100644 --- a/data/chips/STM32F072R8.json +++ b/data/chips/STM32F072R8.json @@ -3376,6 +3376,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F072RB.json b/data/chips/STM32F072RB.json index 06594c1..5d21a1b 100644 --- a/data/chips/STM32F072RB.json +++ b/data/chips/STM32F072RB.json @@ -4156,6 +4156,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F072V8.json b/data/chips/STM32F072V8.json index feb1e14..910ec2b 100644 --- a/data/chips/STM32F072V8.json +++ b/data/chips/STM32F072V8.json @@ -4485,6 +4485,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F072VB.json b/data/chips/STM32F072VB.json index dc81302..b780bb3 100644 --- a/data/chips/STM32F072VB.json +++ b/data/chips/STM32F072VB.json @@ -4485,6 +4485,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F078CB.json b/data/chips/STM32F078CB.json index 573dcab..7907dbe 100644 --- a/data/chips/STM32F078CB.json +++ b/data/chips/STM32F078CB.json @@ -3682,6 +3682,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F078RB.json b/data/chips/STM32F078RB.json index a2e5b51..31359c6 100644 --- a/data/chips/STM32F078RB.json +++ b/data/chips/STM32F078RB.json @@ -3700,6 +3700,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F078VB.json b/data/chips/STM32F078VB.json index 057aa9b..6aefc2b 100644 --- a/data/chips/STM32F078VB.json +++ b/data/chips/STM32F078VB.json @@ -4409,6 +4409,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32F429AG.json b/data/chips/STM32F429AG.json index 97e2f74..4fcfef9 100644 --- a/data/chips/STM32F429AG.json +++ b/data/chips/STM32F429AG.json @@ -3992,9 +3992,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429AI.json b/data/chips/STM32F429AI.json index 2bd8b03..6b780dc 100644 --- a/data/chips/STM32F429AI.json +++ b/data/chips/STM32F429AI.json @@ -3929,9 +3929,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429BE.json b/data/chips/STM32F429BE.json index 20c87d3..be7b8d1 100644 --- a/data/chips/STM32F429BE.json +++ b/data/chips/STM32F429BE.json @@ -4374,9 +4374,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429BG.json b/data/chips/STM32F429BG.json index 090186b..84e6190 100644 --- a/data/chips/STM32F429BG.json +++ b/data/chips/STM32F429BG.json @@ -4476,9 +4476,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429BI.json b/data/chips/STM32F429BI.json index f1ca901..4c9de11 100644 --- a/data/chips/STM32F429BI.json +++ b/data/chips/STM32F429BI.json @@ -4413,9 +4413,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429IE.json b/data/chips/STM32F429IE.json index 427e532..a6524cd 100644 --- a/data/chips/STM32F429IE.json +++ b/data/chips/STM32F429IE.json @@ -5254,9 +5254,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429IG.json b/data/chips/STM32F429IG.json index bc9f5be..be22928 100644 --- a/data/chips/STM32F429IG.json +++ b/data/chips/STM32F429IG.json @@ -5362,9 +5362,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429II.json b/data/chips/STM32F429II.json index 4b04d4d..1a50673 100644 --- a/data/chips/STM32F429II.json +++ b/data/chips/STM32F429II.json @@ -5299,9 +5299,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429NE.json b/data/chips/STM32F429NE.json index e4628ea..91b87ec 100644 --- a/data/chips/STM32F429NE.json +++ b/data/chips/STM32F429NE.json @@ -4422,9 +4422,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429NG.json b/data/chips/STM32F429NG.json index 53a0580..7bf4f86 100644 --- a/data/chips/STM32F429NG.json +++ b/data/chips/STM32F429NG.json @@ -4524,9 +4524,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429NI.json b/data/chips/STM32F429NI.json index 2ec2f57..cee7ce1 100644 --- a/data/chips/STM32F429NI.json +++ b/data/chips/STM32F429NI.json @@ -4461,9 +4461,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429VE.json b/data/chips/STM32F429VE.json index 81f8694..e46c849 100644 --- a/data/chips/STM32F429VE.json +++ b/data/chips/STM32F429VE.json @@ -2874,9 +2874,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429VG.json b/data/chips/STM32F429VG.json index df2dd98..210a09c 100644 --- a/data/chips/STM32F429VG.json +++ b/data/chips/STM32F429VG.json @@ -2976,9 +2976,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429VI.json b/data/chips/STM32F429VI.json index 50f0c33..80436f8 100644 --- a/data/chips/STM32F429VI.json +++ b/data/chips/STM32F429VI.json @@ -2913,9 +2913,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429ZE.json b/data/chips/STM32F429ZE.json index feb019a..998b7b1 100644 --- a/data/chips/STM32F429ZE.json +++ b/data/chips/STM32F429ZE.json @@ -3490,9 +3490,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429ZG.json b/data/chips/STM32F429ZG.json index c59d985..6da5dc3 100644 --- a/data/chips/STM32F429ZG.json +++ b/data/chips/STM32F429ZG.json @@ -4456,9 +4456,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F429ZI.json b/data/chips/STM32F429ZI.json index 77db73f..30e0140 100644 --- a/data/chips/STM32F429ZI.json +++ b/data/chips/STM32F429ZI.json @@ -4393,9 +4393,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F439AI.json b/data/chips/STM32F439AI.json index 7220edf..241a490 100644 --- a/data/chips/STM32F439AI.json +++ b/data/chips/STM32F439AI.json @@ -3998,9 +3998,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F439BG.json b/data/chips/STM32F439BG.json index 2c27f80..1434a46 100644 --- a/data/chips/STM32F439BG.json +++ b/data/chips/STM32F439BG.json @@ -4545,9 +4545,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F439BI.json b/data/chips/STM32F439BI.json index 75aa5eb..ee49504 100644 --- a/data/chips/STM32F439BI.json +++ b/data/chips/STM32F439BI.json @@ -4482,9 +4482,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F439IG.json b/data/chips/STM32F439IG.json index 028b06b..9562e30 100644 --- a/data/chips/STM32F439IG.json +++ b/data/chips/STM32F439IG.json @@ -5431,9 +5431,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F439II.json b/data/chips/STM32F439II.json index f52dea5..b5b4515 100644 --- a/data/chips/STM32F439II.json +++ b/data/chips/STM32F439II.json @@ -5368,9 +5368,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F439NG.json b/data/chips/STM32F439NG.json index cfdfe3f..f796fc9 100644 --- a/data/chips/STM32F439NG.json +++ b/data/chips/STM32F439NG.json @@ -4593,9 +4593,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F439NI.json b/data/chips/STM32F439NI.json index 0c716f3..26591b0 100644 --- a/data/chips/STM32F439NI.json +++ b/data/chips/STM32F439NI.json @@ -4530,9 +4530,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F439VG.json b/data/chips/STM32F439VG.json index 7917b1c..f6fed23 100644 --- a/data/chips/STM32F439VG.json +++ b/data/chips/STM32F439VG.json @@ -3045,9 +3045,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F439VI.json b/data/chips/STM32F439VI.json index ad20149..6369e52 100644 --- a/data/chips/STM32F439VI.json +++ b/data/chips/STM32F439VI.json @@ -2982,9 +2982,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F439ZG.json b/data/chips/STM32F439ZG.json index da22834..06e2100 100644 --- a/data/chips/STM32F439ZG.json +++ b/data/chips/STM32F439ZG.json @@ -4525,9 +4525,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F439ZI.json b/data/chips/STM32F439ZI.json index 9dc9be7..4e3fe6b 100644 --- a/data/chips/STM32F439ZI.json +++ b/data/chips/STM32F439ZI.json @@ -4462,9 +4462,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469AE.json b/data/chips/STM32F469AE.json index ec97ac0..d545992 100644 --- a/data/chips/STM32F469AE.json +++ b/data/chips/STM32F469AE.json @@ -4792,9 +4792,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469AG.json b/data/chips/STM32F469AG.json index eb00d0e..1c1ec62 100644 --- a/data/chips/STM32F469AG.json +++ b/data/chips/STM32F469AG.json @@ -4888,9 +4888,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469AI.json b/data/chips/STM32F469AI.json index 26b5111..e5963da 100644 --- a/data/chips/STM32F469AI.json +++ b/data/chips/STM32F469AI.json @@ -4825,9 +4825,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469BE.json b/data/chips/STM32F469BE.json index 8c53c02..367b26d 100644 --- a/data/chips/STM32F469BE.json +++ b/data/chips/STM32F469BE.json @@ -4431,9 +4431,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469BG.json b/data/chips/STM32F469BG.json index 0c9fd5a..ac350f0 100644 --- a/data/chips/STM32F469BG.json +++ b/data/chips/STM32F469BG.json @@ -4527,9 +4527,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469BI.json b/data/chips/STM32F469BI.json index 6252763..e82657a 100644 --- a/data/chips/STM32F469BI.json +++ b/data/chips/STM32F469BI.json @@ -4464,9 +4464,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469IE.json b/data/chips/STM32F469IE.json index e3a8152..a271ae8 100644 --- a/data/chips/STM32F469IE.json +++ b/data/chips/STM32F469IE.json @@ -5184,9 +5184,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469IG.json b/data/chips/STM32F469IG.json index cf7f3dc..e5e5cb7 100644 --- a/data/chips/STM32F469IG.json +++ b/data/chips/STM32F469IG.json @@ -5280,9 +5280,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469II.json b/data/chips/STM32F469II.json index 0e2a087..b1dfafc 100644 --- a/data/chips/STM32F469II.json +++ b/data/chips/STM32F469II.json @@ -5217,9 +5217,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469NE.json b/data/chips/STM32F469NE.json index eac3b1a..5e8a7b6 100644 --- a/data/chips/STM32F469NE.json +++ b/data/chips/STM32F469NE.json @@ -4479,9 +4479,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469NG.json b/data/chips/STM32F469NG.json index a57bbd3..bcbf860 100644 --- a/data/chips/STM32F469NG.json +++ b/data/chips/STM32F469NG.json @@ -4575,9 +4575,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469NI.json b/data/chips/STM32F469NI.json index 4a0114a..bc33c33 100644 --- a/data/chips/STM32F469NI.json +++ b/data/chips/STM32F469NI.json @@ -4512,9 +4512,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469VE.json b/data/chips/STM32F469VE.json index 35e4b44..21df9d8 100644 --- a/data/chips/STM32F469VE.json +++ b/data/chips/STM32F469VE.json @@ -2721,9 +2721,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469VG.json b/data/chips/STM32F469VG.json index 87f9a29..bb9a65d 100644 --- a/data/chips/STM32F469VG.json +++ b/data/chips/STM32F469VG.json @@ -2817,9 +2817,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469VI.json b/data/chips/STM32F469VI.json index b938a0c..6649d42 100644 --- a/data/chips/STM32F469VI.json +++ b/data/chips/STM32F469VI.json @@ -2754,9 +2754,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469ZE.json b/data/chips/STM32F469ZE.json index 9cbde52..f92d2c0 100644 --- a/data/chips/STM32F469ZE.json +++ b/data/chips/STM32F469ZE.json @@ -3342,9 +3342,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469ZG.json b/data/chips/STM32F469ZG.json index 707e3b4..cdce604 100644 --- a/data/chips/STM32F469ZG.json +++ b/data/chips/STM32F469ZG.json @@ -3438,9 +3438,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F469ZI.json b/data/chips/STM32F469ZI.json index f58d00d..d812191 100644 --- a/data/chips/STM32F469ZI.json +++ b/data/chips/STM32F469ZI.json @@ -3375,9 +3375,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479AG.json b/data/chips/STM32F479AG.json index 9670097..50c5c4d 100644 --- a/data/chips/STM32F479AG.json +++ b/data/chips/STM32F479AG.json @@ -4952,9 +4952,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479AI.json b/data/chips/STM32F479AI.json index 650dfdd..684875a 100644 --- a/data/chips/STM32F479AI.json +++ b/data/chips/STM32F479AI.json @@ -4889,9 +4889,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479BG.json b/data/chips/STM32F479BG.json index 560a9d1..a1e89e7 100644 --- a/data/chips/STM32F479BG.json +++ b/data/chips/STM32F479BG.json @@ -4591,9 +4591,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479BI.json b/data/chips/STM32F479BI.json index 6b881d1..c93f520 100644 --- a/data/chips/STM32F479BI.json +++ b/data/chips/STM32F479BI.json @@ -4528,9 +4528,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479IG.json b/data/chips/STM32F479IG.json index b23de7a..348f3af 100644 --- a/data/chips/STM32F479IG.json +++ b/data/chips/STM32F479IG.json @@ -5344,9 +5344,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479II.json b/data/chips/STM32F479II.json index bb645f9..6abd35e 100644 --- a/data/chips/STM32F479II.json +++ b/data/chips/STM32F479II.json @@ -5281,9 +5281,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479NG.json b/data/chips/STM32F479NG.json index b31d0ac..1ceb1bd 100644 --- a/data/chips/STM32F479NG.json +++ b/data/chips/STM32F479NG.json @@ -4639,9 +4639,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479NI.json b/data/chips/STM32F479NI.json index c50a3f3..ad10675 100644 --- a/data/chips/STM32F479NI.json +++ b/data/chips/STM32F479NI.json @@ -4576,9 +4576,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479VG.json b/data/chips/STM32F479VG.json index 9de405e..1dbee49 100644 --- a/data/chips/STM32F479VG.json +++ b/data/chips/STM32F479VG.json @@ -2881,9 +2881,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479VI.json b/data/chips/STM32F479VI.json index 7858d0f..a02c4e4 100644 --- a/data/chips/STM32F479VI.json +++ b/data/chips/STM32F479VI.json @@ -2818,9 +2818,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479ZG.json b/data/chips/STM32F479ZG.json index bf0fb65..42682e2 100644 --- a/data/chips/STM32F479ZG.json +++ b/data/chips/STM32F479ZG.json @@ -3502,9 +3502,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F479ZI.json b/data/chips/STM32F479ZI.json index d28267b..0d5e4de 100644 --- a/data/chips/STM32F479ZI.json +++ b/data/chips/STM32F479ZI.json @@ -3439,9 +3439,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F746BE.json b/data/chips/STM32F746BE.json index 1282bce..06dd405 100644 --- a/data/chips/STM32F746BE.json +++ b/data/chips/STM32F746BE.json @@ -4587,9 +4587,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F746BG.json b/data/chips/STM32F746BG.json index 83d5d78..7a9a01c 100644 --- a/data/chips/STM32F746BG.json +++ b/data/chips/STM32F746BG.json @@ -4587,9 +4587,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F746IE.json b/data/chips/STM32F746IE.json index 0bb9e6c..816f764 100644 --- a/data/chips/STM32F746IE.json +++ b/data/chips/STM32F746IE.json @@ -5467,9 +5467,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F746IG.json b/data/chips/STM32F746IG.json index 36f1387..29eb140 100644 --- a/data/chips/STM32F746IG.json +++ b/data/chips/STM32F746IG.json @@ -5467,9 +5467,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F746NE.json b/data/chips/STM32F746NE.json index ef39f9c..99c2704 100644 --- a/data/chips/STM32F746NE.json +++ b/data/chips/STM32F746NE.json @@ -4635,9 +4635,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F746NG.json b/data/chips/STM32F746NG.json index 5a18c83..1ae2826 100644 --- a/data/chips/STM32F746NG.json +++ b/data/chips/STM32F746NG.json @@ -4635,9 +4635,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F746VE.json b/data/chips/STM32F746VE.json index 4d99f42..d91a99d 100644 --- a/data/chips/STM32F746VE.json +++ b/data/chips/STM32F746VE.json @@ -3698,9 +3698,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F746VG.json b/data/chips/STM32F746VG.json index 0e25c43..c737463 100644 --- a/data/chips/STM32F746VG.json +++ b/data/chips/STM32F746VG.json @@ -3698,9 +3698,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F746ZE.json b/data/chips/STM32F746ZE.json index 9edc9bc..861a7dc 100644 --- a/data/chips/STM32F746ZE.json +++ b/data/chips/STM32F746ZE.json @@ -4547,9 +4547,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F746ZG.json b/data/chips/STM32F746ZG.json index 6fa0724..cd3032a 100644 --- a/data/chips/STM32F746ZG.json +++ b/data/chips/STM32F746ZG.json @@ -4547,9 +4547,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F750N8.json b/data/chips/STM32F750N8.json index 63b00c1..044ae1b 100644 --- a/data/chips/STM32F750N8.json +++ b/data/chips/STM32F750N8.json @@ -4658,9 +4658,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F750V8.json b/data/chips/STM32F750V8.json index 23daae0..8cac898 100644 --- a/data/chips/STM32F750V8.json +++ b/data/chips/STM32F750V8.json @@ -3115,9 +3115,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F750Z8.json b/data/chips/STM32F750Z8.json index 3e33545..7c811ac 100644 --- a/data/chips/STM32F750Z8.json +++ b/data/chips/STM32F750Z8.json @@ -3706,9 +3706,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F756BG.json b/data/chips/STM32F756BG.json index 90c1845..3fd6a9f 100644 --- a/data/chips/STM32F756BG.json +++ b/data/chips/STM32F756BG.json @@ -4656,9 +4656,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F756IG.json b/data/chips/STM32F756IG.json index 921ceba..88d38e4 100644 --- a/data/chips/STM32F756IG.json +++ b/data/chips/STM32F756IG.json @@ -5536,9 +5536,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F756NG.json b/data/chips/STM32F756NG.json index 2b80b31..42a8600 100644 --- a/data/chips/STM32F756NG.json +++ b/data/chips/STM32F756NG.json @@ -4704,9 +4704,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F756VG.json b/data/chips/STM32F756VG.json index 99af5d9..296a900 100644 --- a/data/chips/STM32F756VG.json +++ b/data/chips/STM32F756VG.json @@ -3767,9 +3767,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F756ZG.json b/data/chips/STM32F756ZG.json index e1635eb..4800ce9 100644 --- a/data/chips/STM32F756ZG.json +++ b/data/chips/STM32F756ZG.json @@ -4616,9 +4616,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F767BG.json b/data/chips/STM32F767BG.json index 3c63876..91791f1 100644 --- a/data/chips/STM32F767BG.json +++ b/data/chips/STM32F767BG.json @@ -5247,9 +5247,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F767BI.json b/data/chips/STM32F767BI.json index 80e80ca..b8a7f66 100644 --- a/data/chips/STM32F767BI.json +++ b/data/chips/STM32F767BI.json @@ -5225,9 +5225,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F767IG.json b/data/chips/STM32F767IG.json index 5a36084..6d966b3 100644 --- a/data/chips/STM32F767IG.json +++ b/data/chips/STM32F767IG.json @@ -6107,9 +6107,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F767II.json b/data/chips/STM32F767II.json index b350eaa..3bb13b8 100644 --- a/data/chips/STM32F767II.json +++ b/data/chips/STM32F767II.json @@ -6085,9 +6085,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F767NG.json b/data/chips/STM32F767NG.json index a1145f1..97db03b 100644 --- a/data/chips/STM32F767NG.json +++ b/data/chips/STM32F767NG.json @@ -5295,9 +5295,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F767NI.json b/data/chips/STM32F767NI.json index b58c423..c2941cd 100644 --- a/data/chips/STM32F767NI.json +++ b/data/chips/STM32F767NI.json @@ -5273,9 +5273,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F767VG.json b/data/chips/STM32F767VG.json index 413ecc1..19d69ca 100644 --- a/data/chips/STM32F767VG.json +++ b/data/chips/STM32F767VG.json @@ -4298,9 +4298,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F767VI.json b/data/chips/STM32F767VI.json index 15e83f8..c255048 100644 --- a/data/chips/STM32F767VI.json +++ b/data/chips/STM32F767VI.json @@ -4276,9 +4276,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F767ZG.json b/data/chips/STM32F767ZG.json index 488b3ed..ba5b3dc 100644 --- a/data/chips/STM32F767ZG.json +++ b/data/chips/STM32F767ZG.json @@ -4303,9 +4303,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F767ZI.json b/data/chips/STM32F767ZI.json index a8311b7..a4c3711 100644 --- a/data/chips/STM32F767ZI.json +++ b/data/chips/STM32F767ZI.json @@ -4281,9 +4281,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F768AI.json b/data/chips/STM32F768AI.json index 05a7d40..804368e 100644 --- a/data/chips/STM32F768AI.json +++ b/data/chips/STM32F768AI.json @@ -4304,9 +4304,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F769AG.json b/data/chips/STM32F769AG.json index d244a99..3e7452a 100644 --- a/data/chips/STM32F769AG.json +++ b/data/chips/STM32F769AG.json @@ -4326,9 +4326,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F769AI.json b/data/chips/STM32F769AI.json index 5966ddb..2232c12 100644 --- a/data/chips/STM32F769AI.json +++ b/data/chips/STM32F769AI.json @@ -4593,9 +4593,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F769BG.json b/data/chips/STM32F769BG.json index 11ab00b..78fd84d 100644 --- a/data/chips/STM32F769BG.json +++ b/data/chips/STM32F769BG.json @@ -5256,9 +5256,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F769BI.json b/data/chips/STM32F769BI.json index 23a42b3..7210b03 100644 --- a/data/chips/STM32F769BI.json +++ b/data/chips/STM32F769BI.json @@ -5234,9 +5234,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F769IG.json b/data/chips/STM32F769IG.json index ca0d481..492b335 100644 --- a/data/chips/STM32F769IG.json +++ b/data/chips/STM32F769IG.json @@ -4779,9 +4779,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F769II.json b/data/chips/STM32F769II.json index c4fc2f4..3772a2e 100644 --- a/data/chips/STM32F769II.json +++ b/data/chips/STM32F769II.json @@ -4757,9 +4757,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F769NG.json b/data/chips/STM32F769NG.json index 587a8c6..c485674 100644 --- a/data/chips/STM32F769NG.json +++ b/data/chips/STM32F769NG.json @@ -5304,9 +5304,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F769NI.json b/data/chips/STM32F769NI.json index b8be833..133cafe 100644 --- a/data/chips/STM32F769NI.json +++ b/data/chips/STM32F769NI.json @@ -5282,9 +5282,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F777BI.json b/data/chips/STM32F777BI.json index f7bbb7c..166e81f 100644 --- a/data/chips/STM32F777BI.json +++ b/data/chips/STM32F777BI.json @@ -5300,9 +5300,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F777II.json b/data/chips/STM32F777II.json index 11a226c..6a31953 100644 --- a/data/chips/STM32F777II.json +++ b/data/chips/STM32F777II.json @@ -6160,9 +6160,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F777NI.json b/data/chips/STM32F777NI.json index 6369765..662b6f0 100644 --- a/data/chips/STM32F777NI.json +++ b/data/chips/STM32F777NI.json @@ -5348,9 +5348,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F777VI.json b/data/chips/STM32F777VI.json index af0fd3b..ef5cbca 100644 --- a/data/chips/STM32F777VI.json +++ b/data/chips/STM32F777VI.json @@ -4351,9 +4351,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F777ZI.json b/data/chips/STM32F777ZI.json index e55e70b..cb3b78f 100644 --- a/data/chips/STM32F777ZI.json +++ b/data/chips/STM32F777ZI.json @@ -4356,9 +4356,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F778AI.json b/data/chips/STM32F778AI.json index c03e859..eceb9a0 100644 --- a/data/chips/STM32F778AI.json +++ b/data/chips/STM32F778AI.json @@ -4656,9 +4656,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F779AI.json b/data/chips/STM32F779AI.json index 58ca6f9..b62a5c2 100644 --- a/data/chips/STM32F779AI.json +++ b/data/chips/STM32F779AI.json @@ -4662,9 +4662,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F779BI.json b/data/chips/STM32F779BI.json index b13f2d4..0a5f11c 100644 --- a/data/chips/STM32F779BI.json +++ b/data/chips/STM32F779BI.json @@ -5303,9 +5303,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F779II.json b/data/chips/STM32F779II.json index 30c2205..7b68986 100644 --- a/data/chips/STM32F779II.json +++ b/data/chips/STM32F779II.json @@ -4826,9 +4826,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32F779NI.json b/data/chips/STM32F779NI.json index 1a1375c..7e436b9 100644 --- a/data/chips/STM32F779NI.json +++ b/data/chips/STM32F779NI.json @@ -5351,9 +5351,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32G0B0CE.json b/data/chips/STM32G0B0CE.json index cce69ca..c265008 100644 --- a/data/chips/STM32G0B0CE.json +++ b/data/chips/STM32G0B0CE.json @@ -3682,6 +3682,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32G0B0KE.json b/data/chips/STM32G0B0KE.json index ea63356..5dd0a3e 100644 --- a/data/chips/STM32G0B0KE.json +++ b/data/chips/STM32G0B0KE.json @@ -3257,6 +3257,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32G0B0RE.json b/data/chips/STM32G0B0RE.json index ca6e32c..51ab28c 100644 --- a/data/chips/STM32G0B0RE.json +++ b/data/chips/STM32G0B0RE.json @@ -4061,6 +4061,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32G0B0VE.json b/data/chips/STM32G0B0VE.json index d5a6264..864a545 100644 --- a/data/chips/STM32G0B0VE.json +++ b/data/chips/STM32G0B0VE.json @@ -4571,6 +4571,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32G0B1CB.json b/data/chips/STM32G0B1CB.json index c3c8164..d5ab662 100644 --- a/data/chips/STM32G0B1CB.json +++ b/data/chips/STM32G0B1CB.json @@ -5667,6 +5667,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1CC.json b/data/chips/STM32G0B1CC.json index c84d2a1..ee00517 100644 --- a/data/chips/STM32G0B1CC.json +++ b/data/chips/STM32G0B1CC.json @@ -5697,6 +5697,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1CE.json b/data/chips/STM32G0B1CE.json index da66ce8..d24b5e8 100644 --- a/data/chips/STM32G0B1CE.json +++ b/data/chips/STM32G0B1CE.json @@ -5678,6 +5678,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1KB.json b/data/chips/STM32G0B1KB.json index 3d79768..29012e5 100644 --- a/data/chips/STM32G0B1KB.json +++ b/data/chips/STM32G0B1KB.json @@ -4988,6 +4988,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1KC.json b/data/chips/STM32G0B1KC.json index 8f4b838..07912c6 100644 --- a/data/chips/STM32G0B1KC.json +++ b/data/chips/STM32G0B1KC.json @@ -5018,6 +5018,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1KE.json b/data/chips/STM32G0B1KE.json index f874d9d..6ef2182 100644 --- a/data/chips/STM32G0B1KE.json +++ b/data/chips/STM32G0B1KE.json @@ -4999,6 +4999,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1MB.json b/data/chips/STM32G0B1MB.json index fa1011e..d0b5759 100644 --- a/data/chips/STM32G0B1MB.json +++ b/data/chips/STM32G0B1MB.json @@ -5592,6 +5592,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1MC.json b/data/chips/STM32G0B1MC.json index bd8a69f..f90688e 100644 --- a/data/chips/STM32G0B1MC.json +++ b/data/chips/STM32G0B1MC.json @@ -5622,6 +5622,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1ME.json b/data/chips/STM32G0B1ME.json index 8e6ee75..0b834c2 100644 --- a/data/chips/STM32G0B1ME.json +++ b/data/chips/STM32G0B1ME.json @@ -5603,6 +5603,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1NE.json b/data/chips/STM32G0B1NE.json index 2018662..d3b2250 100644 --- a/data/chips/STM32G0B1NE.json +++ b/data/chips/STM32G0B1NE.json @@ -4514,6 +4514,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1RB.json b/data/chips/STM32G0B1RB.json index 996fe43..aa00427 100644 --- a/data/chips/STM32G0B1RB.json +++ b/data/chips/STM32G0B1RB.json @@ -6101,6 +6101,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1RC.json b/data/chips/STM32G0B1RC.json index c4303b3..e10fb35 100644 --- a/data/chips/STM32G0B1RC.json +++ b/data/chips/STM32G0B1RC.json @@ -6131,6 +6131,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1RE.json b/data/chips/STM32G0B1RE.json index 97ce51b..3b14536 100644 --- a/data/chips/STM32G0B1RE.json +++ b/data/chips/STM32G0B1RE.json @@ -6112,6 +6112,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1VB.json b/data/chips/STM32G0B1VB.json index 473a46c..22de9f2 100644 --- a/data/chips/STM32G0B1VB.json +++ b/data/chips/STM32G0B1VB.json @@ -6521,6 +6521,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1VC.json b/data/chips/STM32G0B1VC.json index e43ec44..fdc063a 100644 --- a/data/chips/STM32G0B1VC.json +++ b/data/chips/STM32G0B1VC.json @@ -6551,6 +6551,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0B1VE.json b/data/chips/STM32G0B1VE.json index b20998f..7bae750 100644 --- a/data/chips/STM32G0B1VE.json +++ b/data/chips/STM32G0B1VE.json @@ -6532,6 +6532,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0C1CC.json b/data/chips/STM32G0C1CC.json index e3371dc..101f8f1 100644 --- a/data/chips/STM32G0C1CC.json +++ b/data/chips/STM32G0C1CC.json @@ -5766,6 +5766,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0C1CE.json b/data/chips/STM32G0C1CE.json index 3a322e5..b27848d 100644 --- a/data/chips/STM32G0C1CE.json +++ b/data/chips/STM32G0C1CE.json @@ -5747,6 +5747,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0C1KC.json b/data/chips/STM32G0C1KC.json index cb27709..7f062de 100644 --- a/data/chips/STM32G0C1KC.json +++ b/data/chips/STM32G0C1KC.json @@ -5087,6 +5087,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0C1KE.json b/data/chips/STM32G0C1KE.json index d8ca8a5..eea6060 100644 --- a/data/chips/STM32G0C1KE.json +++ b/data/chips/STM32G0C1KE.json @@ -5068,6 +5068,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0C1MC.json b/data/chips/STM32G0C1MC.json index 2a96f26..8fcb99c 100644 --- a/data/chips/STM32G0C1MC.json +++ b/data/chips/STM32G0C1MC.json @@ -5691,6 +5691,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0C1ME.json b/data/chips/STM32G0C1ME.json index fa21a86..98b46fd 100644 --- a/data/chips/STM32G0C1ME.json +++ b/data/chips/STM32G0C1ME.json @@ -5672,6 +5672,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0C1NE.json b/data/chips/STM32G0C1NE.json index 0deaa6e..f2a56ad 100644 --- a/data/chips/STM32G0C1NE.json +++ b/data/chips/STM32G0C1NE.json @@ -4583,6 +4583,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0C1RC.json b/data/chips/STM32G0C1RC.json index 5ec7d30..759e86d 100644 --- a/data/chips/STM32G0C1RC.json +++ b/data/chips/STM32G0C1RC.json @@ -6200,6 +6200,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0C1RE.json b/data/chips/STM32G0C1RE.json index e5ff69c..9c600bc 100644 --- a/data/chips/STM32G0C1RE.json +++ b/data/chips/STM32G0C1RE.json @@ -6181,6 +6181,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0C1VC.json b/data/chips/STM32G0C1VC.json index f25ff36..f89f28d 100644 --- a/data/chips/STM32G0C1VC.json +++ b/data/chips/STM32G0C1VC.json @@ -6620,6 +6620,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32G0C1VE.json b/data/chips/STM32G0C1VE.json index 9cf49f0..9f1b0ae 100644 --- a/data/chips/STM32G0C1VE.json +++ b/data/chips/STM32G0C1VE.json @@ -6601,6 +6601,18 @@ "signal": "LP", "interrupt": "USB_UCPD1_2" }, + { + "signal": "OTG_HS", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB1", + "interrupt": "USB_UCPD1_2" + }, + { + "signal": "USB2", + "interrupt": "USB_UCPD1_2" + }, { "signal": "WKUP", "interrupt": "USB_UCPD1_2" diff --git a/data/chips/STM32H503CB.json b/data/chips/STM32H503CB.json index d2be60f..5cbe188 100644 --- a/data/chips/STM32H503CB.json +++ b/data/chips/STM32H503CB.json @@ -4723,6 +4723,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H503EB.json b/data/chips/STM32H503EB.json index 9095eae..0bffc1e 100644 --- a/data/chips/STM32H503EB.json +++ b/data/chips/STM32H503EB.json @@ -3579,6 +3579,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H503KB.json b/data/chips/STM32H503KB.json index db53245..530cfed 100644 --- a/data/chips/STM32H503KB.json +++ b/data/chips/STM32H503KB.json @@ -4017,6 +4017,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H503RB.json b/data/chips/STM32H503RB.json index 5daeabe..15b9fa0 100644 --- a/data/chips/STM32H503RB.json +++ b/data/chips/STM32H503RB.json @@ -5157,6 +5157,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H523CC.json b/data/chips/STM32H523CC.json index 761a972..7255a24 100644 --- a/data/chips/STM32H523CC.json +++ b/data/chips/STM32H523CC.json @@ -5017,6 +5017,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H523CE.json b/data/chips/STM32H523CE.json index 1e2b63f..c585452 100644 --- a/data/chips/STM32H523CE.json +++ b/data/chips/STM32H523CE.json @@ -5017,6 +5017,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H523HE.json b/data/chips/STM32H523HE.json index dcd5351..0898790 100644 --- a/data/chips/STM32H523HE.json +++ b/data/chips/STM32H523HE.json @@ -3966,6 +3966,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H523RC.json b/data/chips/STM32H523RC.json index 5f8b869..f797a6d 100644 --- a/data/chips/STM32H523RC.json +++ b/data/chips/STM32H523RC.json @@ -5735,6 +5735,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H523RE.json b/data/chips/STM32H523RE.json index 31f9d41..bb90a6e 100644 --- a/data/chips/STM32H523RE.json +++ b/data/chips/STM32H523RE.json @@ -5735,6 +5735,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H523VC.json b/data/chips/STM32H523VC.json index 529f261..3ae778d 100644 --- a/data/chips/STM32H523VC.json +++ b/data/chips/STM32H523VC.json @@ -7562,6 +7562,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H523VE.json b/data/chips/STM32H523VE.json index 11740ee..e543511 100644 --- a/data/chips/STM32H523VE.json +++ b/data/chips/STM32H523VE.json @@ -7562,6 +7562,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H523ZC.json b/data/chips/STM32H523ZC.json index f002474..a4c6234 100644 --- a/data/chips/STM32H523ZC.json +++ b/data/chips/STM32H523ZC.json @@ -8623,6 +8623,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H523ZE.json b/data/chips/STM32H523ZE.json index 3ba0e65..45a6ba1 100644 --- a/data/chips/STM32H523ZE.json +++ b/data/chips/STM32H523ZE.json @@ -8623,6 +8623,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H533CE.json b/data/chips/STM32H533CE.json index 5fd2ae0..1347d34 100644 --- a/data/chips/STM32H533CE.json +++ b/data/chips/STM32H533CE.json @@ -5142,6 +5142,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H533HE.json b/data/chips/STM32H533HE.json index 8757432..7fc79ad 100644 --- a/data/chips/STM32H533HE.json +++ b/data/chips/STM32H533HE.json @@ -4091,6 +4091,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H533RE.json b/data/chips/STM32H533RE.json index 400d484..6f43af8 100644 --- a/data/chips/STM32H533RE.json +++ b/data/chips/STM32H533RE.json @@ -5860,6 +5860,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H533VE.json b/data/chips/STM32H533VE.json index 6477518..9beab02 100644 --- a/data/chips/STM32H533VE.json +++ b/data/chips/STM32H533VE.json @@ -7687,6 +7687,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H533ZE.json b/data/chips/STM32H533ZE.json index 9f476ea..3cfba56 100644 --- a/data/chips/STM32H533ZE.json +++ b/data/chips/STM32H533ZE.json @@ -8748,6 +8748,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index ba08469..154d2c4 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -10292,6 +10292,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index 6c5cadc..4a5f058 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -10292,6 +10292,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index 98b2232..b7fa598 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -11621,6 +11621,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index df19449..b1f1884 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -11621,6 +11621,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index 482d3dd..89e5be2 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -7194,6 +7194,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index 1ef9891..9e9bd75 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -7194,6 +7194,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index 7b2ddb2..01e2207 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -8271,6 +8271,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index ae5b74d..3ee46ba 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -8271,6 +8271,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index 4962f79..c2bf16b 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -9513,6 +9513,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index aa3d480..06d1a05 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -9513,6 +9513,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index bdb8ee9..b0bb3d2 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -10702,6 +10702,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index f3c3100..211efae 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -11777,6 +11777,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 6c87bdb..de02bdd 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -12036,6 +12036,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index d537ee1..57f580e 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -14310,6 +14310,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index fadbb66..e288551 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -7323,6 +7323,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index 603f159..ced7eba 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -7412,6 +7412,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index fe5bab6..0466d49 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -7412,6 +7412,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index af90410..26dc86e 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -8494,6 +8494,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index c52b1fe..189d938 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -9135,6 +9135,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index deb8606..5e7bd17 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -9898,6 +9898,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index 9bfc2b2..51cb4ab 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -10833,6 +10833,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index d379075..cb7b4e7 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -11902,6 +11902,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index 3f1c6ad..f49cc43 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -14435,6 +14435,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index 80079d8..aa32e06 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -7448,6 +7448,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index d67f31f..7a37ec1 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -7537,6 +7537,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index 23709a1..cf5fb13 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -9260,6 +9260,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index e2e5b0a..163c970 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -10958,6 +10958,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32H723VE.json b/data/chips/STM32H723VE.json index a620ee2..7d8de7c 100644 --- a/data/chips/STM32H723VE.json +++ b/data/chips/STM32H723VE.json @@ -4919,9 +4919,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H723VG.json b/data/chips/STM32H723VG.json index 2c4f22f..4c0691a 100644 --- a/data/chips/STM32H723VG.json +++ b/data/chips/STM32H723VG.json @@ -4919,9 +4919,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H723ZE.json b/data/chips/STM32H723ZE.json index 05d9758..667506e 100644 --- a/data/chips/STM32H723ZE.json +++ b/data/chips/STM32H723ZE.json @@ -5919,9 +5919,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H723ZG.json b/data/chips/STM32H723ZG.json index b38d206..b8e0113 100644 --- a/data/chips/STM32H723ZG.json +++ b/data/chips/STM32H723ZG.json @@ -5919,9 +5919,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H725AE.json b/data/chips/STM32H725AE.json index 8f92c11..687d738 100644 --- a/data/chips/STM32H725AE.json +++ b/data/chips/STM32H725AE.json @@ -5359,9 +5359,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H725AG.json b/data/chips/STM32H725AG.json index 730b40e..e43e1b8 100644 --- a/data/chips/STM32H725AG.json +++ b/data/chips/STM32H725AG.json @@ -5365,9 +5365,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H725IE.json b/data/chips/STM32H725IE.json index 10451bc..492a8b4 100644 --- a/data/chips/STM32H725IE.json +++ b/data/chips/STM32H725IE.json @@ -6780,9 +6780,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H725IG.json b/data/chips/STM32H725IG.json index 5096456..4fe8490 100644 --- a/data/chips/STM32H725IG.json +++ b/data/chips/STM32H725IG.json @@ -6786,9 +6786,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H725RE.json b/data/chips/STM32H725RE.json index 81b7ff6..2dd87b7 100644 --- a/data/chips/STM32H725RE.json +++ b/data/chips/STM32H725RE.json @@ -3074,9 +3074,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H725RG.json b/data/chips/STM32H725RG.json index 7e6a49b..6ac4ad3 100644 --- a/data/chips/STM32H725RG.json +++ b/data/chips/STM32H725RG.json @@ -3080,9 +3080,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H725VE.json b/data/chips/STM32H725VE.json index bbd7749..a35271a 100644 --- a/data/chips/STM32H725VE.json +++ b/data/chips/STM32H725VE.json @@ -4809,9 +4809,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H725VG.json b/data/chips/STM32H725VG.json index 2bae379..e00771d 100644 --- a/data/chips/STM32H725VG.json +++ b/data/chips/STM32H725VG.json @@ -5511,9 +5511,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H725ZE.json b/data/chips/STM32H725ZE.json index a6511fe..c718bd2 100644 --- a/data/chips/STM32H725ZE.json +++ b/data/chips/STM32H725ZE.json @@ -4845,9 +4845,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H725ZG.json b/data/chips/STM32H725ZG.json index 19b757a..0a5eb07 100644 --- a/data/chips/STM32H725ZG.json +++ b/data/chips/STM32H725ZG.json @@ -4851,9 +4851,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index 78d6be2..fd53781 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -5450,9 +5450,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index 1b02515..19e8a2c 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -6871,9 +6871,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index 78d9f31..a9ce860 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -5004,9 +5004,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index 06cf1ff..c79d408 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -6004,9 +6004,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index 687b1c9..d6603e7 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -5004,9 +5004,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index 29e26a3..58b00b6 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -6004,9 +6004,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index 556352b..1d316b9 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -5455,9 +5455,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index 17b6412..6fb828d 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -6876,9 +6876,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H735RG.json b/data/chips/STM32H735RG.json index 42ba33c..19b18b2 100644 --- a/data/chips/STM32H735RG.json +++ b/data/chips/STM32H735RG.json @@ -3170,9 +3170,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index 68b9937..c0f7721 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -5601,9 +5601,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index 154258c..4984573 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -4941,9 +4941,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743AG.json b/data/chips/STM32H743AG.json index 12c545c..648df07 100644 --- a/data/chips/STM32H743AG.json +++ b/data/chips/STM32H743AG.json @@ -5308,9 +5308,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743AI.json b/data/chips/STM32H743AI.json index a69aa49..25258dd 100644 --- a/data/chips/STM32H743AI.json +++ b/data/chips/STM32H743AI.json @@ -5308,9 +5308,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743BG.json b/data/chips/STM32H743BG.json index adb87fd..98e87fa 100644 --- a/data/chips/STM32H743BG.json +++ b/data/chips/STM32H743BG.json @@ -5867,9 +5867,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743BI.json b/data/chips/STM32H743BI.json index bc41cde..9456419 100644 --- a/data/chips/STM32H743BI.json +++ b/data/chips/STM32H743BI.json @@ -5867,9 +5867,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743IG.json b/data/chips/STM32H743IG.json index 5064063..ad544ca 100644 --- a/data/chips/STM32H743IG.json +++ b/data/chips/STM32H743IG.json @@ -6722,9 +6722,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743II.json b/data/chips/STM32H743II.json index e3eef08..3995b6a 100644 --- a/data/chips/STM32H743II.json +++ b/data/chips/STM32H743II.json @@ -6722,9 +6722,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743VG.json b/data/chips/STM32H743VG.json index 3080861..9388400 100644 --- a/data/chips/STM32H743VG.json +++ b/data/chips/STM32H743VG.json @@ -4805,9 +4805,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743VI.json b/data/chips/STM32H743VI.json index f656d81..e4b0ff7 100644 --- a/data/chips/STM32H743VI.json +++ b/data/chips/STM32H743VI.json @@ -4805,9 +4805,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743XG.json b/data/chips/STM32H743XG.json index 2d77113..592cb48 100644 --- a/data/chips/STM32H743XG.json +++ b/data/chips/STM32H743XG.json @@ -6257,9 +6257,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743XI.json b/data/chips/STM32H743XI.json index bc11eed..4bc46b2 100644 --- a/data/chips/STM32H743XI.json +++ b/data/chips/STM32H743XI.json @@ -6257,9 +6257,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743ZG.json b/data/chips/STM32H743ZG.json index e374ef9..41fcea2 100644 --- a/data/chips/STM32H743ZG.json +++ b/data/chips/STM32H743ZG.json @@ -4890,9 +4890,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H743ZI.json b/data/chips/STM32H743ZI.json index 836c951..614d3e8 100644 --- a/data/chips/STM32H743ZI.json +++ b/data/chips/STM32H743ZI.json @@ -4890,9 +4890,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H745BG.json b/data/chips/STM32H745BG.json index 792b0f9..ddc713e 100644 --- a/data/chips/STM32H745BG.json +++ b/data/chips/STM32H745BG.json @@ -5748,9 +5748,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -16191,9 +16199,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H745BI.json b/data/chips/STM32H745BI.json index 542e508..531d9b1 100644 --- a/data/chips/STM32H745BI.json +++ b/data/chips/STM32H745BI.json @@ -5748,9 +5748,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -16191,9 +16199,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H745IG.json b/data/chips/STM32H745IG.json index 1a29f2a..816c38a 100644 --- a/data/chips/STM32H745IG.json +++ b/data/chips/STM32H745IG.json @@ -6662,9 +6662,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -16802,9 +16810,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H745II.json b/data/chips/STM32H745II.json index 2dd36c1..919ac52 100644 --- a/data/chips/STM32H745II.json +++ b/data/chips/STM32H745II.json @@ -6662,9 +6662,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -16802,9 +16810,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H745XG.json b/data/chips/STM32H745XG.json index edf3c21..40db300 100644 --- a/data/chips/STM32H745XG.json +++ b/data/chips/STM32H745XG.json @@ -6250,9 +6250,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -16921,9 +16929,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H745XI.json b/data/chips/STM32H745XI.json index 5446d32..2238fae 100644 --- a/data/chips/STM32H745XI.json +++ b/data/chips/STM32H745XI.json @@ -6250,9 +6250,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -16921,9 +16929,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H745ZG.json b/data/chips/STM32H745ZG.json index 52cb00e..7dab65e 100644 --- a/data/chips/STM32H745ZG.json +++ b/data/chips/STM32H745ZG.json @@ -4734,9 +4734,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -13963,9 +13971,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H745ZI.json b/data/chips/STM32H745ZI.json index 65a8e08..ff1e3b5 100644 --- a/data/chips/STM32H745ZI.json +++ b/data/chips/STM32H745ZI.json @@ -4734,9 +4734,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -13963,9 +13971,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index 4479956..36fe088 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -5079,9 +5079,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -14610,9 +14618,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index cb5d3b1..6efc7f6 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -5079,9 +5079,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -14610,9 +14618,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index df6043a..d9b3839 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -5751,9 +5751,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -16038,9 +16046,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index 00bff3b..eea6bd3 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -5751,9 +5751,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -16038,9 +16046,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index b013263..e16f149 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -5121,9 +5121,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -14652,9 +14660,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index 7cd7aa7..2a22360 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -5121,9 +5121,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -14652,9 +14660,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index fe76de0..f9a7619 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -6317,9 +6317,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -17039,9 +17047,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index fb2a8cb..d6d9fd0 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -6317,9 +6317,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -17039,9 +17047,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index a1f5380..0064695 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -4779,9 +4779,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -13710,9 +13718,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H750IB.json b/data/chips/STM32H750IB.json index 55f1d68..2c6f425 100644 --- a/data/chips/STM32H750IB.json +++ b/data/chips/STM32H750IB.json @@ -6767,9 +6767,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H750VB.json b/data/chips/STM32H750VB.json index 4365a40..6a77d2a 100644 --- a/data/chips/STM32H750VB.json +++ b/data/chips/STM32H750VB.json @@ -4244,9 +4244,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H750XB.json b/data/chips/STM32H750XB.json index a522c7c..60118a7 100644 --- a/data/chips/STM32H750XB.json +++ b/data/chips/STM32H750XB.json @@ -6302,9 +6302,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H750ZB.json b/data/chips/STM32H750ZB.json index d20a2c9..f31f047 100644 --- a/data/chips/STM32H750ZB.json +++ b/data/chips/STM32H750ZB.json @@ -4923,9 +4923,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H753AI.json b/data/chips/STM32H753AI.json index f4ba505..8094ac7 100644 --- a/data/chips/STM32H753AI.json +++ b/data/chips/STM32H753AI.json @@ -5387,9 +5387,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H753BI.json b/data/chips/STM32H753BI.json index 3fe31cc..56534c5 100644 --- a/data/chips/STM32H753BI.json +++ b/data/chips/STM32H753BI.json @@ -5946,9 +5946,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H753II.json b/data/chips/STM32H753II.json index b737c5f..5c6d3ae 100644 --- a/data/chips/STM32H753II.json +++ b/data/chips/STM32H753II.json @@ -6801,9 +6801,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H753VI.json b/data/chips/STM32H753VI.json index 8f2d833..0d431a6 100644 --- a/data/chips/STM32H753VI.json +++ b/data/chips/STM32H753VI.json @@ -4884,9 +4884,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H753XI.json b/data/chips/STM32H753XI.json index 8cfc00e..6eabcad 100644 --- a/data/chips/STM32H753XI.json +++ b/data/chips/STM32H753XI.json @@ -6336,9 +6336,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H753ZI.json b/data/chips/STM32H753ZI.json index d5a5db7..322ecdd 100644 --- a/data/chips/STM32H753ZI.json +++ b/data/chips/STM32H753ZI.json @@ -4969,9 +4969,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index 4ee13e1..39b9e35 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -5827,9 +5827,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -16347,9 +16355,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index 325ecc9..815b078 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -6741,9 +6741,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -16958,9 +16966,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index 9e49764..94d3f0f 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -6329,9 +6329,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -17077,9 +17085,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index 50e9cff..c227982 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -4813,9 +4813,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -14119,9 +14127,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index c51515a..66effb2 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -5158,9 +5158,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -14766,9 +14774,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index 9d5a938..e67d069 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -5830,9 +5830,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -16194,9 +16202,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index f8f08ae..635f1ce 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -5200,9 +5200,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -14808,9 +14816,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 16dd801..1aa9058 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -6396,9 +6396,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -17195,9 +17203,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index 261ae30..44087e4 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -4858,9 +4858,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, @@ -13866,9 +13874,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index 70efe5e..2a3d20b 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -4922,9 +4922,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index 59e702f..42b53c1 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -4922,9 +4922,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index 11eced3..0a780f6 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -8740,9 +8740,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index e0ff774..46e97ef 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -8740,9 +8740,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index adf3eac..0d7081e 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -5667,9 +5667,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index e459a52..f30c2b6 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -5673,9 +5673,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index 39ac85e..a98ac0c 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -5575,9 +5575,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index 51c6876..468cc26 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -5575,9 +5575,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index 2f2e0f8..bd08867 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -4330,9 +4330,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3RG.json b/data/chips/STM32H7A3RG.json index eaee2fb..051cec3 100644 --- a/data/chips/STM32H7A3RG.json +++ b/data/chips/STM32H7A3RG.json @@ -3064,9 +3064,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3RI.json b/data/chips/STM32H7A3RI.json index 138441e..5c8cc57 100644 --- a/data/chips/STM32H7A3RI.json +++ b/data/chips/STM32H7A3RI.json @@ -3064,9 +3064,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index 24f656f..1a8f56d 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -5838,9 +5838,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index 16dbe3d..f67c203 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -5838,9 +5838,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index 8f5c024..a29c55d 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -5478,9 +5478,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index e83b25a..8b9f4ab 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -5478,9 +5478,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index dc74250..443c7b0 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -4990,9 +4990,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index 8497502..78ca5df 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -6499,9 +6499,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index 0ddf395..44fb59b 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -3132,9 +3132,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index 82647d6..dfe10d9 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -4088,9 +4088,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index 6f0dac9..395b468 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -4676,9 +4676,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index 63000cd..c1b86a5 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -5012,9 +5012,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index a56ff0f..bfc296e 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -8830,9 +8830,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index a20a307..55292f0 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -5763,9 +5763,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index 10169fd..3a3e067 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -5665,9 +5665,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index e6d7627..d28ae95 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -4420,9 +4420,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 605b26b..4ccd76a 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -3154,9 +3154,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index 7e48017..373d349 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -5928,9 +5928,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index 98bd9de..e205a63 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -5568,9 +5568,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7R3A8.json b/data/chips/STM32H7R3A8.json index 192101e..8eac705 100644 --- a/data/chips/STM32H7R3A8.json +++ b/data/chips/STM32H7R3A8.json @@ -1816,7 +1816,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] diff --git a/data/chips/STM32H7R3I8.json b/data/chips/STM32H7R3I8.json index 185e0d9..d2aa36a 100644 --- a/data/chips/STM32H7R3I8.json +++ b/data/chips/STM32H7R3I8.json @@ -3107,7 +3107,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] diff --git a/data/chips/STM32H7R3L8.json b/data/chips/STM32H7R3L8.json index e4791f2..e433824 100644 --- a/data/chips/STM32H7R3L8.json +++ b/data/chips/STM32H7R3L8.json @@ -3588,7 +3588,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] diff --git a/data/chips/STM32H7R3Z8.json b/data/chips/STM32H7R3Z8.json index 667128f..d311d96 100644 --- a/data/chips/STM32H7R3Z8.json +++ b/data/chips/STM32H7R3Z8.json @@ -2512,7 +2512,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] diff --git a/data/chips/STM32H7R7A8.json b/data/chips/STM32H7R7A8.json index 6a65a56..c35e5b5 100644 --- a/data/chips/STM32H7R7A8.json +++ b/data/chips/STM32H7R7A8.json @@ -1786,7 +1786,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] @@ -4346,9 +4346,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7R7I8.json b/data/chips/STM32H7R7I8.json index ade72ac..4f49f8f 100644 --- a/data/chips/STM32H7R7I8.json +++ b/data/chips/STM32H7R7I8.json @@ -3082,7 +3082,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] @@ -5702,9 +5702,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7R7L8.json b/data/chips/STM32H7R7L8.json index 36bf85f..bea4680 100644 --- a/data/chips/STM32H7R7L8.json +++ b/data/chips/STM32H7R7L8.json @@ -3588,7 +3588,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] @@ -6518,9 +6518,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7R7Z8.json b/data/chips/STM32H7R7Z8.json index 7e1e37b..6cce069 100644 --- a/data/chips/STM32H7R7Z8.json +++ b/data/chips/STM32H7R7Z8.json @@ -1602,7 +1602,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] @@ -3937,9 +3937,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7S3A8.json b/data/chips/STM32H7S3A8.json index 04a4334..8afa64c 100644 --- a/data/chips/STM32H7S3A8.json +++ b/data/chips/STM32H7S3A8.json @@ -1855,7 +1855,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] diff --git a/data/chips/STM32H7S3I8.json b/data/chips/STM32H7S3I8.json index 04af97c..7eb639c 100644 --- a/data/chips/STM32H7S3I8.json +++ b/data/chips/STM32H7S3I8.json @@ -3146,7 +3146,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] diff --git a/data/chips/STM32H7S3L8.json b/data/chips/STM32H7S3L8.json index 79d42d1..9995c97 100644 --- a/data/chips/STM32H7S3L8.json +++ b/data/chips/STM32H7S3L8.json @@ -3627,7 +3627,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] diff --git a/data/chips/STM32H7S3Z8.json b/data/chips/STM32H7S3Z8.json index b6fb533..961f0e8 100644 --- a/data/chips/STM32H7S3Z8.json +++ b/data/chips/STM32H7S3Z8.json @@ -2551,7 +2551,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] diff --git a/data/chips/STM32H7S7A8.json b/data/chips/STM32H7S7A8.json index c42d0ed..d2093e9 100644 --- a/data/chips/STM32H7S7A8.json +++ b/data/chips/STM32H7S7A8.json @@ -1825,7 +1825,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] @@ -4385,9 +4385,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7S7I8.json b/data/chips/STM32H7S7I8.json index 2310631..92f0d60 100644 --- a/data/chips/STM32H7S7I8.json +++ b/data/chips/STM32H7S7I8.json @@ -3121,7 +3121,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] @@ -5741,9 +5741,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7S7L8.json b/data/chips/STM32H7S7L8.json index e4fff52..209568e 100644 --- a/data/chips/STM32H7S7L8.json +++ b/data/chips/STM32H7S7L8.json @@ -3627,7 +3627,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] @@ -6557,9 +6557,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32H7S7Z8.json b/data/chips/STM32H7S7Z8.json index 5d7f210..261fd18 100644 --- a/data/chips/STM32H7S7Z8.json +++ b/data/chips/STM32H7S7Z8.json @@ -1641,7 +1641,7 @@ ], "interrupts": [ { - "signal": "GLOBAL", + "signal": "CSI", "interrupt": "DCMIPP" } ] @@ -3976,9 +3976,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L052C6.json b/data/chips/STM32L052C6.json index 901de89..bb1ff79 100644 --- a/data/chips/STM32L052C6.json +++ b/data/chips/STM32L052C6.json @@ -2892,6 +2892,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L052C8.json b/data/chips/STM32L052C8.json index 9aae39a..ee7e7d7 100644 --- a/data/chips/STM32L052C8.json +++ b/data/chips/STM32L052C8.json @@ -2892,6 +2892,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L052K6.json b/data/chips/STM32L052K6.json index 41eecc8..2d8d2d4 100644 --- a/data/chips/STM32L052K6.json +++ b/data/chips/STM32L052K6.json @@ -2330,6 +2330,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L052K8.json b/data/chips/STM32L052K8.json index bfedb0f..7ad7996 100644 --- a/data/chips/STM32L052K8.json +++ b/data/chips/STM32L052K8.json @@ -2330,6 +2330,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L052R6.json b/data/chips/STM32L052R6.json index 9ece087..ab9f2de 100644 --- a/data/chips/STM32L052R6.json +++ b/data/chips/STM32L052R6.json @@ -3248,6 +3248,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L052R8.json b/data/chips/STM32L052R8.json index 3d980ba..288c347 100644 --- a/data/chips/STM32L052R8.json +++ b/data/chips/STM32L052R8.json @@ -3248,6 +3248,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L052T6.json b/data/chips/STM32L052T6.json index 918b8a5..90e9b3e 100644 --- a/data/chips/STM32L052T6.json +++ b/data/chips/STM32L052T6.json @@ -2311,6 +2311,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L052T8.json b/data/chips/STM32L052T8.json index 4e35b8b..5d69d87 100644 --- a/data/chips/STM32L052T8.json +++ b/data/chips/STM32L052T8.json @@ -2533,6 +2533,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L053C6.json b/data/chips/STM32L053C6.json index 78cfc2a..e22eb7b 100644 --- a/data/chips/STM32L053C6.json +++ b/data/chips/STM32L053C6.json @@ -3031,6 +3031,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L053C8.json b/data/chips/STM32L053C8.json index 13014f8..a15dfd1 100644 --- a/data/chips/STM32L053C8.json +++ b/data/chips/STM32L053C8.json @@ -3031,6 +3031,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L053R6.json b/data/chips/STM32L053R6.json index aff9511..fc1ccd5 100644 --- a/data/chips/STM32L053R6.json +++ b/data/chips/STM32L053R6.json @@ -3477,6 +3477,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L053R8.json b/data/chips/STM32L053R8.json index 050e8c3..85d9903 100644 --- a/data/chips/STM32L053R8.json +++ b/data/chips/STM32L053R8.json @@ -3477,6 +3477,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L062C8.json b/data/chips/STM32L062C8.json index 547912e..f3427e1 100644 --- a/data/chips/STM32L062C8.json +++ b/data/chips/STM32L062C8.json @@ -2623,6 +2623,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L062K8.json b/data/chips/STM32L062K8.json index 2588dc1..8c9df63 100644 --- a/data/chips/STM32L062K8.json +++ b/data/chips/STM32L062K8.json @@ -2367,6 +2367,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L063C8.json b/data/chips/STM32L063C8.json index 3065871..0fac35a 100644 --- a/data/chips/STM32L063C8.json +++ b/data/chips/STM32L063C8.json @@ -3068,6 +3068,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L063R8.json b/data/chips/STM32L063R8.json index a22903e..378fd1c 100644 --- a/data/chips/STM32L063R8.json +++ b/data/chips/STM32L063R8.json @@ -3124,6 +3124,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L072CB.json b/data/chips/STM32L072CB.json index b8f72d6..be44cda 100644 --- a/data/chips/STM32L072CB.json +++ b/data/chips/STM32L072CB.json @@ -3746,6 +3746,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L072CZ.json b/data/chips/STM32L072CZ.json index c4bb9d1..f9b3c4b 100644 --- a/data/chips/STM32L072CZ.json +++ b/data/chips/STM32L072CZ.json @@ -4046,6 +4046,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L072KB.json b/data/chips/STM32L072KB.json index c93c8df..6212e2a 100644 --- a/data/chips/STM32L072KB.json +++ b/data/chips/STM32L072KB.json @@ -2842,6 +2842,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L072KZ.json b/data/chips/STM32L072KZ.json index 569de89..cb3f18f 100644 --- a/data/chips/STM32L072KZ.json +++ b/data/chips/STM32L072KZ.json @@ -2842,6 +2842,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L072RB.json b/data/chips/STM32L072RB.json index 3c03149..3e832fd 100644 --- a/data/chips/STM32L072RB.json +++ b/data/chips/STM32L072RB.json @@ -4195,6 +4195,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L072RZ.json b/data/chips/STM32L072RZ.json index 050f827..1b769cf 100644 --- a/data/chips/STM32L072RZ.json +++ b/data/chips/STM32L072RZ.json @@ -4195,6 +4195,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L072V8.json b/data/chips/STM32L072V8.json index fb19dcc..4c8f65a 100644 --- a/data/chips/STM32L072V8.json +++ b/data/chips/STM32L072V8.json @@ -4465,6 +4465,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L072VB.json b/data/chips/STM32L072VB.json index 67b567e..5ed0abe 100644 --- a/data/chips/STM32L072VB.json +++ b/data/chips/STM32L072VB.json @@ -4476,6 +4476,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L072VZ.json b/data/chips/STM32L072VZ.json index f7102b0..b0d3920 100644 --- a/data/chips/STM32L072VZ.json +++ b/data/chips/STM32L072VZ.json @@ -4476,6 +4476,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L073CB.json b/data/chips/STM32L073CB.json index efe62b3..ec03863 100644 --- a/data/chips/STM32L073CB.json +++ b/data/chips/STM32L073CB.json @@ -3600,6 +3600,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L073CZ.json b/data/chips/STM32L073CZ.json index a83575b..72c1ee8 100644 --- a/data/chips/STM32L073CZ.json +++ b/data/chips/STM32L073CZ.json @@ -3900,6 +3900,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L073RB.json b/data/chips/STM32L073RB.json index 06891ca..0658791 100644 --- a/data/chips/STM32L073RB.json +++ b/data/chips/STM32L073RB.json @@ -4034,6 +4034,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L073RZ.json b/data/chips/STM32L073RZ.json index f4439e4..b0842b4 100644 --- a/data/chips/STM32L073RZ.json +++ b/data/chips/STM32L073RZ.json @@ -4424,6 +4424,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L073V8.json b/data/chips/STM32L073V8.json index 2f4eb82..218ee0f 100644 --- a/data/chips/STM32L073V8.json +++ b/data/chips/STM32L073V8.json @@ -4822,6 +4822,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L073VB.json b/data/chips/STM32L073VB.json index 9ed315f..a0aa6ab 100644 --- a/data/chips/STM32L073VB.json +++ b/data/chips/STM32L073VB.json @@ -4833,6 +4833,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L073VZ.json b/data/chips/STM32L073VZ.json index 50cb8b0..31f894c 100644 --- a/data/chips/STM32L073VZ.json +++ b/data/chips/STM32L073VZ.json @@ -4833,6 +4833,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L082CZ.json b/data/chips/STM32L082CZ.json index f03d742..8054afc 100644 --- a/data/chips/STM32L082CZ.json +++ b/data/chips/STM32L082CZ.json @@ -3489,6 +3489,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L082KB.json b/data/chips/STM32L082KB.json index 0c64455..63aa70c 100644 --- a/data/chips/STM32L082KB.json +++ b/data/chips/STM32L082KB.json @@ -2879,6 +2879,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L082KZ.json b/data/chips/STM32L082KZ.json index cc5269a..75bd9f2 100644 --- a/data/chips/STM32L082KZ.json +++ b/data/chips/STM32L082KZ.json @@ -2879,6 +2879,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L083CB.json b/data/chips/STM32L083CB.json index ed6a5ea..71a5092 100644 --- a/data/chips/STM32L083CB.json +++ b/data/chips/STM32L083CB.json @@ -3256,6 +3256,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L083CZ.json b/data/chips/STM32L083CZ.json index 082e48c..46cf3a3 100644 --- a/data/chips/STM32L083CZ.json +++ b/data/chips/STM32L083CZ.json @@ -3550,6 +3550,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L083RB.json b/data/chips/STM32L083RB.json index fe76385..0a64a7f 100644 --- a/data/chips/STM32L083RB.json +++ b/data/chips/STM32L083RB.json @@ -4071,6 +4071,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L083RZ.json b/data/chips/STM32L083RZ.json index 5f00af7..141dd97 100644 --- a/data/chips/STM32L083RZ.json +++ b/data/chips/STM32L083RZ.json @@ -4071,6 +4071,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L083V8.json b/data/chips/STM32L083V8.json index 0ee774d..44f43d1 100644 --- a/data/chips/STM32L083V8.json +++ b/data/chips/STM32L083V8.json @@ -4859,6 +4859,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L083VB.json b/data/chips/STM32L083VB.json index 3f96a2e..71604bd 100644 --- a/data/chips/STM32L083VB.json +++ b/data/chips/STM32L083VB.json @@ -4870,6 +4870,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L083VZ.json b/data/chips/STM32L083VZ.json index 606f926..ac58b16 100644 --- a/data/chips/STM32L083VZ.json +++ b/data/chips/STM32L083VZ.json @@ -4870,6 +4870,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L412C8.json b/data/chips/STM32L412C8.json index 2ca3470..5fa45f1 100644 --- a/data/chips/STM32L412C8.json +++ b/data/chips/STM32L412C8.json @@ -3488,6 +3488,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L412CB.json b/data/chips/STM32L412CB.json index 56f9eba..2602d75 100644 --- a/data/chips/STM32L412CB.json +++ b/data/chips/STM32L412CB.json @@ -4076,6 +4076,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L412K8.json b/data/chips/STM32L412K8.json index 8ac3c67..7ee08b3 100644 --- a/data/chips/STM32L412K8.json +++ b/data/chips/STM32L412K8.json @@ -2869,6 +2869,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L412KB.json b/data/chips/STM32L412KB.json index 269fb2f..7a6236c 100644 --- a/data/chips/STM32L412KB.json +++ b/data/chips/STM32L412KB.json @@ -2869,6 +2869,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L412R8.json b/data/chips/STM32L412R8.json index 809937c..d85805e 100644 --- a/data/chips/STM32L412R8.json +++ b/data/chips/STM32L412R8.json @@ -3881,6 +3881,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L412RB.json b/data/chips/STM32L412RB.json index 033ca80..417706a 100644 --- a/data/chips/STM32L412RB.json +++ b/data/chips/STM32L412RB.json @@ -4667,6 +4667,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L412T8.json b/data/chips/STM32L412T8.json index 612dccb..51956ee 100644 --- a/data/chips/STM32L412T8.json +++ b/data/chips/STM32L412T8.json @@ -2759,6 +2759,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L412TB.json b/data/chips/STM32L412TB.json index d4c2c5b..7b310ad 100644 --- a/data/chips/STM32L412TB.json +++ b/data/chips/STM32L412TB.json @@ -2981,6 +2981,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L422CB.json b/data/chips/STM32L422CB.json index 8fab9c0..46fcf87 100644 --- a/data/chips/STM32L422CB.json +++ b/data/chips/STM32L422CB.json @@ -3537,6 +3537,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L422KB.json b/data/chips/STM32L422KB.json index 15be08e..12c7ed6 100644 --- a/data/chips/STM32L422KB.json +++ b/data/chips/STM32L422KB.json @@ -2918,6 +2918,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L422RB.json b/data/chips/STM32L422RB.json index 60b094f..7af7711 100644 --- a/data/chips/STM32L422RB.json +++ b/data/chips/STM32L422RB.json @@ -3936,6 +3936,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L422TB.json b/data/chips/STM32L422TB.json index 72e88f5..fc839d3 100644 --- a/data/chips/STM32L422TB.json +++ b/data/chips/STM32L422TB.json @@ -2808,6 +2808,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L432KB.json b/data/chips/STM32L432KB.json index 91ba6cf..fc57454 100644 --- a/data/chips/STM32L432KB.json +++ b/data/chips/STM32L432KB.json @@ -3039,6 +3039,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L432KC.json b/data/chips/STM32L432KC.json index 147f852..57a0ca3 100644 --- a/data/chips/STM32L432KC.json +++ b/data/chips/STM32L432KC.json @@ -3039,6 +3039,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L433CB.json b/data/chips/STM32L433CB.json index cf53179..a1279e1 100644 --- a/data/chips/STM32L433CB.json +++ b/data/chips/STM32L433CB.json @@ -4457,6 +4457,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L433CC.json b/data/chips/STM32L433CC.json index 6e36247..7d84996 100644 --- a/data/chips/STM32L433CC.json +++ b/data/chips/STM32L433CC.json @@ -4457,6 +4457,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L433RB.json b/data/chips/STM32L433RB.json index bccd1ef..1d04c95 100644 --- a/data/chips/STM32L433RB.json +++ b/data/chips/STM32L433RB.json @@ -5131,6 +5131,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L433RC.json b/data/chips/STM32L433RC.json index 1381479..771a1a7 100644 --- a/data/chips/STM32L433RC.json +++ b/data/chips/STM32L433RC.json @@ -5527,6 +5527,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L433VC.json b/data/chips/STM32L433VC.json index 2eeb381..0a21307 100644 --- a/data/chips/STM32L433VC.json +++ b/data/chips/STM32L433VC.json @@ -5592,6 +5592,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L442KC.json b/data/chips/STM32L442KC.json index 0ee5627..1f15959 100644 --- a/data/chips/STM32L442KC.json +++ b/data/chips/STM32L442KC.json @@ -3088,6 +3088,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L443CC.json b/data/chips/STM32L443CC.json index eed8b75..25d7e64 100644 --- a/data/chips/STM32L443CC.json +++ b/data/chips/STM32L443CC.json @@ -4806,6 +4806,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L443RC.json b/data/chips/STM32L443RC.json index c7a66f7..0c08582 100644 --- a/data/chips/STM32L443RC.json +++ b/data/chips/STM32L443RC.json @@ -5180,6 +5180,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L443VC.json b/data/chips/STM32L443VC.json index 18d73e9..ebb9600 100644 --- a/data/chips/STM32L443VC.json +++ b/data/chips/STM32L443VC.json @@ -5641,6 +5641,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L452CC.json b/data/chips/STM32L452CC.json index 04d8363..d89e200 100644 --- a/data/chips/STM32L452CC.json +++ b/data/chips/STM32L452CC.json @@ -3922,6 +3922,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L452CE.json b/data/chips/STM32L452CE.json index 2385093..2ef7843 100644 --- a/data/chips/STM32L452CE.json +++ b/data/chips/STM32L452CE.json @@ -4510,6 +4510,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L452RC.json b/data/chips/STM32L452RC.json index 5be4e2f..cc50d9b 100644 --- a/data/chips/STM32L452RC.json +++ b/data/chips/STM32L452RC.json @@ -5169,6 +5169,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L452RE.json b/data/chips/STM32L452RE.json index 5106771..01f450c 100644 --- a/data/chips/STM32L452RE.json +++ b/data/chips/STM32L452RE.json @@ -5955,6 +5955,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L452VC.json b/data/chips/STM32L452VC.json index 47af629..aa56950 100644 --- a/data/chips/STM32L452VC.json +++ b/data/chips/STM32L452VC.json @@ -5655,6 +5655,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L452VE.json b/data/chips/STM32L452VE.json index 103cf26..8c00800 100644 --- a/data/chips/STM32L452VE.json +++ b/data/chips/STM32L452VE.json @@ -5655,6 +5655,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L462CE.json b/data/chips/STM32L462CE.json index 9199578..bb8e57e 100644 --- a/data/chips/STM32L462CE.json +++ b/data/chips/STM32L462CE.json @@ -4271,6 +4271,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L462RE.json b/data/chips/STM32L462RE.json index 0a85183..b585c9d 100644 --- a/data/chips/STM32L462RE.json +++ b/data/chips/STM32L462RE.json @@ -5218,6 +5218,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L462VE.json b/data/chips/STM32L462VE.json index 0b7b005..5816c62 100644 --- a/data/chips/STM32L462VE.json +++ b/data/chips/STM32L462VE.json @@ -5704,6 +5704,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32L4P5AE.json b/data/chips/STM32L4P5AE.json index ce42c3e..2df2083 100644 --- a/data/chips/STM32L4P5AE.json +++ b/data/chips/STM32L4P5AE.json @@ -4276,9 +4276,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4P5AG.json b/data/chips/STM32L4P5AG.json index af2cc2c..61b0781 100644 --- a/data/chips/STM32L4P5AG.json +++ b/data/chips/STM32L4P5AG.json @@ -5296,9 +5296,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4P5CE.json b/data/chips/STM32L4P5CE.json index 480f2de..8aa16e4 100644 --- a/data/chips/STM32L4P5CE.json +++ b/data/chips/STM32L4P5CE.json @@ -2590,9 +2590,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4P5CG.json b/data/chips/STM32L4P5CG.json index f9d7cb6..feb0179 100644 --- a/data/chips/STM32L4P5CG.json +++ b/data/chips/STM32L4P5CG.json @@ -3178,9 +3178,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4P5QE.json b/data/chips/STM32L4P5QE.json index 58d4dd5..8cfc4a1 100644 --- a/data/chips/STM32L4P5QE.json +++ b/data/chips/STM32L4P5QE.json @@ -3909,9 +3909,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4P5QG.json b/data/chips/STM32L4P5QG.json index 1fd12b3..77e1a51 100644 --- a/data/chips/STM32L4P5QG.json +++ b/data/chips/STM32L4P5QG.json @@ -5505,9 +5505,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4P5RE.json b/data/chips/STM32L4P5RE.json index fe2fcff..d52eb5c 100644 --- a/data/chips/STM32L4P5RE.json +++ b/data/chips/STM32L4P5RE.json @@ -2684,9 +2684,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4P5RG.json b/data/chips/STM32L4P5RG.json index 78824a5..4759fb5 100644 --- a/data/chips/STM32L4P5RG.json +++ b/data/chips/STM32L4P5RG.json @@ -3074,9 +3074,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4P5VE.json b/data/chips/STM32L4P5VE.json index 76aea10..ce8a375 100644 --- a/data/chips/STM32L4P5VE.json +++ b/data/chips/STM32L4P5VE.json @@ -4083,9 +4083,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4P5VG.json b/data/chips/STM32L4P5VG.json index eda8148..bc98aa0 100644 --- a/data/chips/STM32L4P5VG.json +++ b/data/chips/STM32L4P5VG.json @@ -5295,9 +5295,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4P5ZE.json b/data/chips/STM32L4P5ZE.json index 89fa325..4be74b8 100644 --- a/data/chips/STM32L4P5ZE.json +++ b/data/chips/STM32L4P5ZE.json @@ -3991,9 +3991,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4P5ZG.json b/data/chips/STM32L4P5ZG.json index 83c40ec..43bf840 100644 --- a/data/chips/STM32L4P5ZG.json +++ b/data/chips/STM32L4P5ZG.json @@ -4861,9 +4861,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4Q5AG.json b/data/chips/STM32L4Q5AG.json index a6e7f02..6ebadd3 100644 --- a/data/chips/STM32L4Q5AG.json +++ b/data/chips/STM32L4Q5AG.json @@ -5335,9 +5335,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4Q5CG.json b/data/chips/STM32L4Q5CG.json index 77bdd06..e9fc7d2 100644 --- a/data/chips/STM32L4Q5CG.json +++ b/data/chips/STM32L4Q5CG.json @@ -3217,9 +3217,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4Q5QG.json b/data/chips/STM32L4Q5QG.json index e2831a5..42290d0 100644 --- a/data/chips/STM32L4Q5QG.json +++ b/data/chips/STM32L4Q5QG.json @@ -4746,9 +4746,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4Q5RG.json b/data/chips/STM32L4Q5RG.json index dbb58a0..d02811d 100644 --- a/data/chips/STM32L4Q5RG.json +++ b/data/chips/STM32L4Q5RG.json @@ -3113,9 +3113,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4Q5VG.json b/data/chips/STM32L4Q5VG.json index b66e485..0da4eb9 100644 --- a/data/chips/STM32L4Q5VG.json +++ b/data/chips/STM32L4Q5VG.json @@ -5334,9 +5334,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4Q5ZG.json b/data/chips/STM32L4Q5ZG.json index f5caeac..b0d5d88 100644 --- a/data/chips/STM32L4Q5ZG.json +++ b/data/chips/STM32L4Q5ZG.json @@ -4900,9 +4900,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4R7AI.json b/data/chips/STM32L4R7AI.json index d899135..5f9648c 100644 --- a/data/chips/STM32L4R7AI.json +++ b/data/chips/STM32L4R7AI.json @@ -4190,9 +4190,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4R7VI.json b/data/chips/STM32L4R7VI.json index a84e746..e80ebb5 100644 --- a/data/chips/STM32L4R7VI.json +++ b/data/chips/STM32L4R7VI.json @@ -3346,9 +3346,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4R7ZI.json b/data/chips/STM32L4R7ZI.json index dd8273d..24e47bd 100644 --- a/data/chips/STM32L4R7ZI.json +++ b/data/chips/STM32L4R7ZI.json @@ -3905,9 +3905,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4R9AG.json b/data/chips/STM32L4R9AG.json index 117c6f4..a71ef07 100644 --- a/data/chips/STM32L4R9AG.json +++ b/data/chips/STM32L4R9AG.json @@ -4200,9 +4200,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4R9AI.json b/data/chips/STM32L4R9AI.json index a6a24ea..161d41d 100644 --- a/data/chips/STM32L4R9AI.json +++ b/data/chips/STM32L4R9AI.json @@ -4200,9 +4200,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4R9VG.json b/data/chips/STM32L4R9VG.json index ca95b90..4158a53 100644 --- a/data/chips/STM32L4R9VG.json +++ b/data/chips/STM32L4R9VG.json @@ -3288,9 +3288,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4R9VI.json b/data/chips/STM32L4R9VI.json index 5de8d1f..c8a4f0d 100644 --- a/data/chips/STM32L4R9VI.json +++ b/data/chips/STM32L4R9VI.json @@ -3288,9 +3288,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4R9ZG.json b/data/chips/STM32L4R9ZG.json index 6b0de23..2ba4451 100644 --- a/data/chips/STM32L4R9ZG.json +++ b/data/chips/STM32L4R9ZG.json @@ -5688,9 +5688,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4R9ZI.json b/data/chips/STM32L4R9ZI.json index 50dd60a..c74bffb 100644 --- a/data/chips/STM32L4R9ZI.json +++ b/data/chips/STM32L4R9ZI.json @@ -6564,9 +6564,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4S7AI.json b/data/chips/STM32L4S7AI.json index 2246d90..61f69e1 100644 --- a/data/chips/STM32L4S7AI.json +++ b/data/chips/STM32L4S7AI.json @@ -4263,9 +4263,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4S7VI.json b/data/chips/STM32L4S7VI.json index 56df37a..4f0f1b2 100644 --- a/data/chips/STM32L4S7VI.json +++ b/data/chips/STM32L4S7VI.json @@ -3419,9 +3419,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4S7ZI.json b/data/chips/STM32L4S7ZI.json index 395f0d1..566bb08 100644 --- a/data/chips/STM32L4S7ZI.json +++ b/data/chips/STM32L4S7ZI.json @@ -3978,9 +3978,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4S9AI.json b/data/chips/STM32L4S9AI.json index 6df1114..6680a53 100644 --- a/data/chips/STM32L4S9AI.json +++ b/data/chips/STM32L4S9AI.json @@ -4273,9 +4273,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4S9VI.json b/data/chips/STM32L4S9VI.json index 646e093..bd0af13 100644 --- a/data/chips/STM32L4S9VI.json +++ b/data/chips/STM32L4S9VI.json @@ -3361,9 +3361,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L4S9ZI.json b/data/chips/STM32L4S9ZI.json index 43be044..345bbe6 100644 --- a/data/chips/STM32L4S9ZI.json +++ b/data/chips/STM32L4S9ZI.json @@ -5761,9 +5761,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32L552CC.json b/data/chips/STM32L552CC.json index e1eb963..09f4f0b 100644 --- a/data/chips/STM32L552CC.json +++ b/data/chips/STM32L552CC.json @@ -4779,6 +4779,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L552CE.json b/data/chips/STM32L552CE.json index 2de95b4..79dfdd1 100644 --- a/data/chips/STM32L552CE.json +++ b/data/chips/STM32L552CE.json @@ -5397,6 +5397,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L552ME.json b/data/chips/STM32L552ME.json index bded6b2..3735976 100644 --- a/data/chips/STM32L552ME.json +++ b/data/chips/STM32L552ME.json @@ -5922,6 +5922,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L552QC.json b/data/chips/STM32L552QC.json index cf13a16..ccdf45e 100644 --- a/data/chips/STM32L552QC.json +++ b/data/chips/STM32L552QC.json @@ -6749,6 +6749,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L552QE.json b/data/chips/STM32L552QE.json index 7e8485d..9bfcba3 100644 --- a/data/chips/STM32L552QE.json +++ b/data/chips/STM32L552QE.json @@ -8375,6 +8375,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L552RC.json b/data/chips/STM32L552RC.json index 722aef8..a36606a 100644 --- a/data/chips/STM32L552RC.json +++ b/data/chips/STM32L552RC.json @@ -5147,6 +5147,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L552RE.json b/data/chips/STM32L552RE.json index e10a816..3318c14 100644 --- a/data/chips/STM32L552RE.json +++ b/data/chips/STM32L552RE.json @@ -5957,6 +5957,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L552VC.json b/data/chips/STM32L552VC.json index 6bba54a..522aba9 100644 --- a/data/chips/STM32L552VC.json +++ b/data/chips/STM32L552VC.json @@ -6137,6 +6137,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L552VE.json b/data/chips/STM32L552VE.json index 75d2da8..a1b003b 100644 --- a/data/chips/STM32L552VE.json +++ b/data/chips/STM32L552VE.json @@ -6773,6 +6773,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L552ZC.json b/data/chips/STM32L552ZC.json index 536602c..0340c2f 100644 --- a/data/chips/STM32L552ZC.json +++ b/data/chips/STM32L552ZC.json @@ -6930,6 +6930,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L552ZE.json b/data/chips/STM32L552ZE.json index d5a7f78..bea3e58 100644 --- a/data/chips/STM32L552ZE.json +++ b/data/chips/STM32L552ZE.json @@ -7830,6 +7830,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index f0592d5..5bfb616 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -5490,6 +5490,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index 3e702ed..0cccf91 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -6015,6 +6015,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index e4df9d1..3bf228d 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -8468,6 +8468,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index efdc00e..e7dae46 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -6050,6 +6050,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index ea1bab3..3029f6a 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -6866,6 +6866,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index eb44feb..df70fb1 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -7923,6 +7923,18 @@ "signal": "LP", "interrupt": "USB_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_FS" + }, { "signal": "WKUP", "interrupt": "USB_FS" diff --git a/data/chips/STM32N645A0.json b/data/chips/STM32N645A0.json new file mode 100644 index 0000000..4dca952 --- /dev/null +++ b/data/chips/STM32N645A0.json @@ -0,0 +1,7662 @@ +{ + "name": "STM32N645A0", + "family": "STM32N6", + "line": "STM32N6x5", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N645A0HxQ", + "package": "VFBGA169", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PE13" + ] + }, + { + "position": "A11", + "signals": [ + "PD7" + ] + }, + { + "position": "A12", + "signals": [ + "PD1" + ] + }, + { + "position": "A13", + "signals": [ + "VSS" + ] + }, + { + "position": "A2", + "signals": [] + }, + { + "position": "A3", + "signals": [ + "OTG2_HSDM" + ] + }, + { + "position": "A4", + "signals": [] + }, + { + "position": "A5", + "signals": [ + "OTG1_HSDM" + ] + }, + { + "position": "A6", + "signals": [ + "OTG1_TXRTUNE" + ] + }, + { + "position": "A7", + "signals": [ + "PH1" + ] + }, + { + "position": "A8", + "signals": [ + "PC11" + ] + }, + { + "position": "A9", + "signals": [ + "PE11" + ] + }, + { + "position": "B1", + "signals": [ + "PC14" + ] + }, + { + "position": "B10", + "signals": [ + "PE12" + ] + }, + { + "position": "B11", + "signals": [ + "PD10" + ] + }, + { + "position": "B12", + "signals": [ + "PD0" + ] + }, + { + "position": "B13", + "signals": [ + "PD15" + ] + }, + { + "position": "B2", + "signals": [ + "OTG2_ID" + ] + }, + { + "position": "B3", + "signals": [ + "OTG2_HSDP" + ] + }, + { + "position": "B4", + "signals": [ + "OTG1_ID" + ] + }, + { + "position": "B5", + "signals": [ + "OTG1_HSDP" + ] + }, + { + "position": "B6", + "signals": [ + "UCPD1_CC1" + ] + }, + { + "position": "B7", + "signals": [ + "PH0" + ] + }, + { + "position": "B8", + "signals": [ + "PC12" + ] + }, + { + "position": "B9", + "signals": [ + "PE14" + ] + }, + { + "position": "C1", + "signals": [ + "PC15" + ] + }, + { + "position": "C10", + "signals": [ + "PD2" + ] + }, + { + "position": "C11", + "signals": [ + "PE7" + ] + }, + { + "position": "C12", + "signals": [ + "PD3" + ] + }, + { + "position": "C13", + "signals": [ + "PD14" + ] + }, + { + "position": "C2", + "signals": [ + "VBAT" + ] + }, + { + "position": "C3", + "signals": [ + "OTG2_TXRTUNE" + ] + }, + { + "position": "C4", + "signals": [ + "VDDA18USB" + ] + }, + { + "position": "C5", + "signals": [ + "VDD33USB" + ] + }, + { + "position": "C6", + "signals": [ + "UCPD1_CC2" + ] + }, + { + "position": "C7", + "signals": [ + "PC9" + ] + }, + { + "position": "C8", + "signals": [ + "PH2" + ] + }, + { + "position": "C9", + "signals": [ + "PE5" + ] + }, + { + "position": "D1", + "signals": [ + "V08CAP" + ] + }, + { + "position": "D10", + "signals": [ + "PD6" + ] + }, + { + "position": "D11", + "signals": [ + "PD12" + ] + }, + { + "position": "D12", + "signals": [ + "PE8" + ] + }, + { + "position": "D13", + "signals": [ + "PD4" + ] + }, + { + "position": "D2", + "signals": [ + "PC13" + ] + }, + { + "position": "D3", + "signals": [ + "BOOT0" + ] + }, + { + "position": "D4", + "signals": [ + "PWR_ON" + ] + }, + { + "position": "D5", + "signals": [ + "VDDA18AON" + ] + }, + { + "position": "D6", + "signals": [ + "PC10" + ] + }, + { + "position": "D7", + "signals": [ + "PC8" + ] + }, + { + "position": "D8", + "signals": [ + "VDDIO4" + ] + }, + { + "position": "D9", + "signals": [ + "PE15" + ] + }, + { + "position": "E1", + "signals": [ + "VDDA18PMU" + ] + }, + { + "position": "E10", + "signals": [ + "PB3" + ] + }, + { + "position": "E11", + "signals": [ + "PD8" + ] + }, + { + "position": "E12", + "signals": [ + "PE10" + ] + }, + { + "position": "E13", + "signals": [ + "PE9" + ] + }, + { + "position": "E2", + "signals": [ + "VSSAPMU" + ] + }, + { + "position": "E3", + "signals": [ + "VFBSMPS" + ] + }, + { + "position": "E4", + "signals": [ + "NRST" + ] + }, + { + "position": "E5", + "signals": [ + "VSSAON" + ] + }, + { + "position": "E6", + "signals": [ + "VSS" + ] + }, + { + "position": "E7", + "signals": [ + "VDDCORE" + ] + }, + { + "position": "E8", + "signals": [ + "VSS" + ] + }, + { + "position": "E9", + "signals": [ + "VDD" + ] + }, + { + "position": "F1", + "signals": [ + "VSSSMPS" + ] + }, + { + "position": "F10", + "signals": [ + "PE2" + ] + }, + { + "position": "F11", + "signals": [ + "PE1" + ] + }, + { + "position": "F12", + "signals": [ + "PE0" + ] + }, + { + "position": "F13", + "signals": [ + "PD11" + ] + }, + { + "position": "F2", + "signals": [ + "VSSSMPS" + ] + }, + { + "position": "F3", + "signals": [ + "VSSSMPS" + ] + }, + { + "position": "F4", + "signals": [ + "VSSSMPS" + ] + }, + { + "position": "F5", + "signals": [ + "VSS" + ] + }, + { + "position": "F6", + "signals": [ + "VDDCORE" + ] + }, + { + "position": "F7", + "signals": [ + "VSS" + ] + }, + { + "position": "F8", + "signals": [ + "VDDCORE" + ] + }, + { + "position": "F9", + "signals": [ + "VSS" + ] + }, + { + "position": "G1", + "signals": [ + "VLXSMPS" + ] + }, + { + "position": "G10", + "signals": [ + "PB7" + ] + }, + { + "position": "G11", + "signals": [ + "PB6" + ] + }, + { + "position": "G12", + "signals": [ + "PB0" + ] + }, + { + "position": "G13", + "signals": [ + "PE3" + ] + }, + { + "position": "G2", + "signals": [ + "VLXSMPS" + ] + }, + { + "position": "G3", + "signals": [ + "VLXSMPS" + ] + }, + { + "position": "G4", + "signals": [ + "VLXSMPS" + ] + }, + { + "position": "G5", + "signals": [ + "VDDCORE" + ] + }, + { + "position": "G6", + "signals": [ + "VSS" + ] + }, + { + "position": "G7", + "signals": [ + "VDDCORE" + ] + }, + { + "position": "G8", + "signals": [ + "VSS" + ] + }, + { + "position": "G9", + "signals": [ + "VDD" + ] + }, + { + "position": "H1", + "signals": [ + "VDDSMPS" + ] + }, + { + "position": "H10", + "signals": [ + "VDDIO3" + ] + }, + { + "position": "H11", + "signals": [ + "PN11" + ] + }, + { + "position": "H12", + "signals": [ + "PN3" + ] + }, + { + "position": "H13", + "signals": [ + "PN1" + ] + }, + { + "position": "H2", + "signals": [ + "VDDSMPS" + ] + }, + { + "position": "H3", + "signals": [ + "VDDSMPS" + ] + }, + { + "position": "H4", + "signals": [ + "VDDSMPS" + ] + }, + { + "position": "H5", + "signals": [ + "VSS" + ] + }, + { + "position": "H6", + "signals": [ + "VDDCORE" + ] + }, + { + "position": "H7", + "signals": [ + "VSS" + ] + }, + { + "position": "H8", + "signals": [ + "VDDCORE" + ] + }, + { + "position": "H9", + "signals": [ + "VSS" + ] + }, + { + "position": "J1", + "signals": [ + "PF4" + ] + }, + { + "position": "J10", + "signals": [ + "VDDIO3" + ] + }, + { + "position": "J11", + "signals": [ + "PN2" + ] + }, + { + "position": "J12", + "signals": [ + "PN10" + ] + }, + { + "position": "J13", + "signals": [ + "PN0" + ] + }, + { + "position": "J2", + "signals": [ + "PF10" + ] + }, + { + "position": "J3", + "signals": [ + "PF5" + ] + }, + { + "position": "J4", + "signals": [ + "PF3" + ] + }, + { + "position": "J5", + "signals": [ + "VDDA18PLL" + ] + }, + { + "position": "J6", + "signals": [ + "VSS" + ] + }, + { + "position": "J7", + "signals": [ + "VDDCORE" + ] + }, + { + "position": "J8", + "signals": [ + "VSS" + ] + }, + { + "position": "J9", + "signals": [ + "VDD" + ] + }, + { + "position": "K1", + "signals": [ + "PF2" + ] + }, + { + "position": "K10", + "signals": [ + "PB12" + ] + }, + { + "position": "K11", + "signals": [ + "PN7" + ] + }, + { + "position": "K12", + "signals": [ + "PN6" + ] + }, + { + "position": "K13", + "signals": [ + "PN9" + ] + }, + { + "position": "K2", + "signals": [ + "PF14" + ] + }, + { + "position": "K3", + "signals": [ + "PF15" + ] + }, + { + "position": "K4", + "signals": [ + "PF7" + ] + }, + { + "position": "K5", + "signals": [ + "VSSA" + ] + }, + { + "position": "K6", + "signals": [ + "PG14" + ] + }, + { + "position": "K7", + "signals": [ + "PA12" + ] + }, + { + "position": "K8", + "signals": [ + "PA2" + ] + }, + { + "position": "K9", + "signals": [ + "PG13" + ] + }, + { + "position": "L1", + "signals": [ + "PF8" + ] + }, + { + "position": "L10", + "signals": [ + "PB11" + ] + }, + { + "position": "L11", + "signals": [ + "PB5" + ] + }, + { + "position": "L12", + "signals": [ + "PN4" + ] + }, + { + "position": "L13", + "signals": [ + "PN5" + ] + }, + { + "position": "L2", + "signals": [ + "PF11" + ] + }, + { + "position": "L3", + "signals": [ + "PF12" + ] + }, + { + "position": "L4", + "signals": [ + "PF13" + ] + }, + { + "position": "L5", + "signals": [ + "VDDA18ADC" + ] + }, + { + "position": "L6", + "signals": [ + "VDDCSI" + ] + }, + { + "position": "L7", + "signals": [ + "PA11" + ] + }, + { + "position": "L8", + "signals": [ + "PA8" + ] + }, + { + "position": "L9", + "signals": [ + "PA1" + ] + }, + { + "position": "M1", + "signals": [ + "VREF+" + ] + }, + { + "position": "M10", + "signals": [ + "PB10" + ] + }, + { + "position": "M11", + "signals": [ + "PB4" + ] + }, + { + "position": "M12", + "signals": [ + "PN12" + ] + }, + { + "position": "M13", + "signals": [ + "PN8" + ] + }, + { + "position": "M2", + "signals": [ + "CSI_D1N" + ] + }, + { + "position": "M3", + "signals": [ + "CSI_CKN" + ] + }, + { + "position": "M4", + "signals": [ + "CSI_D0N" + ] + }, + { + "position": "M5", + "signals": [ + "VDDA18CSI" + ] + }, + { + "position": "M6", + "signals": [ + "PA13" + ] + }, + { + "position": "M7", + "signals": [ + "PA9" + ] + }, + { + "position": "M8", + "signals": [ + "PA5" + ] + }, + { + "position": "M9", + "signals": [ + "PA0" + ] + }, + { + "position": "N1", + "signals": [ + "VSS" + ] + }, + { + "position": "N10", + "signals": [ + "PG2" + ] + }, + { + "position": "N11", + "signals": [ + "PA15" + ] + }, + { + "position": "N12", + "signals": [ + "PA3" + ] + }, + { + "position": "N13", + "signals": [ + "VSS" + ] + }, + { + "position": "N2", + "signals": [ + "CSI_D1P" + ] + }, + { + "position": "N3", + "signals": [ + "CSI_CKP" + ] + }, + { + "position": "N4", + "signals": [ + "CSI_D0P" + ] + }, + { + "position": "N5", + "signals": [ + "CSI_REXT" + ] + }, + { + "position": "N6", + "signals": [ + "PA14" + ] + }, + { + "position": "N7", + "signals": [ + "PA10" + ] + }, + { + "position": "N8", + "signals": [ + "PA6" + ] + }, + { + "position": "N9", + "signals": [ + "PG10" + ] + } + ] + } + ], + "memory": [ + [ + { + "name": "FLEXRAM", + "kind": "ram", + "address": 603979776, + "size": 409600 + }, + { + "name": "AXISRAM", + "kind": "ram", + "address": 604389376, + "size": 638976 + }, + { + "name": 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"signal": "INP9" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ADC1_2" + } + ] + }, + { + "name": "ADC12_COMMON", + "address": 1073881856 + }, + { + "name": "ADC2", + "address": 1073881344, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": { + "register": "CCIPR1", + "field": "ADC12SEL" + }, + "enable": { + "register": "AHB1ENR", + "field": "ADC12EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "ADC12RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "INN1" + }, + { + "pin": "PA0", + "signal": "INP0" + }, + { + "pin": "PA1", + "signal": "INP1" + }, + { + "pin": "PA10", + "signal": "INN10" + }, + { + "pin": "PA10", + "signal": "INP11" + }, + { + "pin": "PA11", + "signal": "INN11" + }, + { + "pin": "PA11", + "signal": "INP12" + }, + { + "pin": "PA12", + "signal": "INN12" + }, + { + "pin": "PA12", + "signal": "INP13" + }, + { + "pin": "PA2", + "signal": "INP14" + }, + { + "pin": "PA5", + "signal": "INP18" + }, + { + "pin": "PA6", + "signal": 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"interrupt": "EXTI15" + }, + { + "signal": "EXTI2", + "interrupt": "EXTI2" + }, + { + "signal": "EXTI3", + "interrupt": "EXTI3" + }, + { + "signal": "EXTI4", + "interrupt": "EXTI4" + }, + { + "signal": "EXTI5", + "interrupt": "EXTI5" + }, + { + "signal": "EXTI6", + "interrupt": "EXTI6" + }, + { + "signal": "EXTI7", + "interrupt": "EXTI7" + }, + { + "signal": "EXTI8", + "interrupt": "EXTI8" + }, + { + "signal": "EXTI9", + "interrupt": "EXTI9" + } + ] + }, + { + "name": "FDCAN1", + "address": 1073782784, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE11", + "signal": "TX", + "af": 6 + }, + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, 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"PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "DE", + "af": 9 + }, + { + "pin": "PD11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USART6", + "address": 1107301376, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART6EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART6RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PD3", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG14", + "signal": "TX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + { + "name": "EXTI2", + "number": 22 + }, + { + "name": "EXTI3", + "number": 23 + }, + { + "name": "EXTI4", + "number": 24 + }, + { + "name": "EXTI5", + "number": 25 + }, + { + "name": "EXTI6", + "number": 26 + }, + { + "name": "EXTI7", + "number": 27 + }, + { + "name": "EXTI8", + "number": 28 + }, + { + "name": "EXTI9", + "number": 29 + }, + { + "name": "EXTI10", + "number": 30 + }, + { + "name": "EXTI11", + "number": 31 + }, + { + "name": "EXTI12", + "number": 32 + }, + { + "name": "EXTI13", + "number": 33 + }, + { + "name": "EXTI14", + "number": 34 + }, + { + "name": "EXTI15", + "number": 35 + }, + { + "name": "PKA", + "number": 38 + }, + { + "name": "HASH", + "number": 39 + }, + { + "name": "RNG", + "number": 40 + }, + { + "name": "ADC1_2", + "number": 46 + }, + { + "name": "CSI", + "number": 47 + }, + { + "name": "DCMIPP", + "number": 48 + }, + { + "name": "PAHB_ERR", + "number": 52 + }, + { + "name": "LTDC_LO", + "number": 58 + }, + { + "name": "LTDC_LO_ERR", + "number": 59 + }, + { + "name": "DMA2D", + "number": 60 + }, + { + "name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": 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"interrupt": "ADC1_2" + } + ] + }, + { + "name": "ADC12_COMMON", + "address": 1073881856 + }, + { + "name": "ADC2", + "address": 1073881344, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": { + "register": "CCIPR1", + "field": "ADC12SEL" + }, + "enable": { + "register": "AHB1ENR", + "field": "ADC12EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "ADC12RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "INN1" + }, + { + "pin": "PA0", + "signal": "INP0" + }, + { + "pin": "PA1", + "signal": "INP1" + }, + { + "pin": "PA10", + "signal": "INN10" + }, + { + "pin": "PA10", + "signal": "INP11" + }, + { + "pin": "PA11", + "signal": "INN11" + }, + { + "pin": "PA11", + "signal": "INP12" + }, + { + "pin": "PA12", + "signal": "INN12" + }, + { + "pin": "PA12", + "signal": "INP13" + }, + { + "pin": "PA2", + "signal": "INP14" + }, + { + "pin": "PA5", + "signal": "INP18" + }, + { + "pin": "PA6", + "signal": "INP3" + }, + { + "pin": "PA8", + "signal": "INP5" + }, + { + "pin": "PA9", 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"interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "DCMIPP", + "address": 1207967744, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR1", + "field": "DCMIPPSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "DCMIPPEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "DCMIPPRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PIXCLK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "VSYNC", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + 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"enable": { + "register": "APB4HENR", + "field": "DTSEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "DTSRST" + } + } + }, + { + "name": "ETH1", + "address": 1208180736, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "ETH1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "ETH1RST" + } + }, + "pins": [ + { + "pin": "PD1", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD12", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PD3", + "signal": "PHY_INTN", + "af": 11 + }, + { + "pin": "PF0", + "signal": "RGMII_GTX_CLK", + "af": 12 + }, + { + "pin": "PF0", + "signal": "TX_CLK", + "af": 11 + }, + { + "pin": "PF1", + "signal": "TX_ER", + "af": 11 + }, + { + "pin": "PF10", + "signal": "CRS_DV", + "af": 11 + }, + { + "pin": "PF10", + "signal": "RGMII_RX_CTL", + "af": 11 + }, + { + "pin": "PF10", + "signal": "RX_DV", + "af": 11 + }, + { + "pin": "PF11", + "signal": "RGMII_TX_CTL", + "af": 11 + }, + { + "pin": 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"pin": "PF8", + "signal": "RGMII_RXD2", + "af": 11 + }, + { + "pin": "PF8", + "signal": "RXD2", + "af": 11 + }, + { + "pin": "PF9", + "signal": "RGMII_RXD3", + "af": 11 + }, + { + "pin": "PF9", + "signal": "RXD3", + "af": 11 + }, + { + "pin": "PG0", + "signal": "PHY_INTN", + "af": 11 + }, + { + "pin": "PG11", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PG15", + "signal": "REF_CLK", + "af": 11 + }, + { + "pin": "PG15", + "signal": "RX_CLK", + "af": 11 + }, + { + "pin": "PG3", + "signal": "RGMII_TXD2", + "af": 11 + }, + { + "pin": "PG3", + "signal": "TXD2", + "af": 11 + }, + { + "pin": "PG4", + "signal": "RGMII_TXD3", + "af": 11 + }, + { + "pin": "PG4", + "signal": "TXD3", + "af": 11 + }, + { + "pin": "PG5", + "signal": "RX_ER", + "af": 11 + }, + { + "pin": "PG6", + "signal": "CRS", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ETH1" + }, + { + "signal": "WKUP", + "interrupt": "ETH1" + } + ] + }, + { + "name": "EXTI", + "address": 1174556672, + "registers": { + "kind": "exti", + "version": "v1", + "block": "EXTI" + }, + "interrupts": [ + { + "signal": "EXTI0", + "interrupt": "EXTI0" + }, + { + "signal": "EXTI1", + "interrupt": "EXTI1" + }, + { + "signal": "EXTI10", + "interrupt": "EXTI10" + }, + { + "signal": "EXTI11", + "interrupt": "EXTI11" + }, + { + "signal": "EXTI12", + "interrupt": "EXTI12" + }, + { + "signal": "EXTI13", + "interrupt": "EXTI13" + }, + { + "signal": "EXTI14", + "interrupt": "EXTI14" + }, + { + "signal": "EXTI15", + "interrupt": "EXTI15" + }, + { + "signal": "EXTI2", + "interrupt": "EXTI2" + }, + { + "signal": "EXTI3", + "interrupt": "EXTI3" + }, + { + "signal": "EXTI4", + "interrupt": "EXTI4" + }, + { + "signal": "EXTI5", + "interrupt": "EXTI5" + }, + { + "signal": "EXTI6", + "interrupt": "EXTI6" + }, + { + "signal": "EXTI7", + "interrupt": "EXTI7" + }, + { + "signal": "EXTI8", + "interrupt": "EXTI8" + }, + { + "signal": "EXTI9", + "interrupt": "EXTI9" + } + ] + }, + { + "name": "FDCAN1", + "address": 1073782784, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE11", + "signal": "TX", + "af": 6 + }, + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FMC", + "address": 1208107008, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR3", + "field": "FMCSEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "FMCEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "FMCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "D7", + "af": 12 + }, + { + "pin": "PA0", + "signal": "DA7", + "af": 12 + }, + { + "pin": "PA1", + "signal": "D6", + "af": 12 + }, + { + "pin": "PA1", + "signal": "DA6", + "af": 12 + }, + { + "pin": "PA10", + "signal": "D2", + "af": 12 + }, + { + "pin": "PA10", + "signal": "DA2", + "af": 12 + }, + { + "pin": "PA11", + "signal": "D1", + "af": 12 + }, + { + "pin": "PA11", + "signal": "DA1", + "af": 12 + }, + { + "pin": "PA12", + "signal": "D0", + "af": 12 + }, + { + "pin": "PA12", + "signal": "DA0", + "af": 12 + }, + { + "pin": "PA15", + "signal": "D15", + "af": 12 + }, + { + "pin": "PA15", + "signal": "DA15", + "af": 12 + }, + { + "pin": "PA2", + "signal": "D5", + "af": 12 + }, + { + "pin": "PA2", + "signal": "DA5", + "af": 12 + }, + { + "pin": "PA3", + "signal": "A17", + "af": 12 + }, + { + "pin": "PA3", + "signal": "ALE", + "af": 12 + }, + { + "pin": "PA5", + "signal": "NOE", + "af": 12 + }, + { + "pin": "PA8", + "signal": "D4", + "af": 12 + }, + { + "pin": "PA8", + "signal": "DA4", + "af": 12 + }, + { + "pin": "PA9", + "signal": "D3", + "af": 12 + }, + { + "pin": "PA9", + "signal": "DA3", + "af": 12 + }, + { + "pin": "PB0", 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"PC10", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PC12", + "signal": "NL", + "af": 12 + }, + { + "pin": "PC8", + "signal": "NE4", + "af": 12 + }, + { + "pin": "PD0", + "signal": "A22", + "af": 14 + }, + { + "pin": "PD0", + "signal": "A6", + "af": 12 + }, + { + "pin": "PD1", + "signal": "A23", + "af": 14 + }, + { + "pin": "PD1", + "signal": "A7", + "af": 12 + }, + { + "pin": "PD10", + "signal": "A19", + "af": 14 + }, + { + "pin": "PD10", + "signal": "A3", + "af": 12 + }, + { + "pin": "PD11", + "signal": "D8", + "af": 12 + }, + { + "pin": "PD11", + "signal": "DA8", + "af": 12 + }, + { + "pin": "PD12", + "signal": "A21", + "af": 14 + }, + { + "pin": "PD12", + "signal": "A5", + "af": 12 + }, + { + "pin": "PD14", + "signal": "A9", + "af": 12 + }, + { + "pin": "PD15", + "signal": "A8", + "af": 12 + }, + { + "pin": "PD2", + "signal": "A0", + "af": 12 + }, + { + "pin": "PD2", + "signal": "A16", + "af": 14 + }, + { + "pin": "PD2", + "signal": "CLE", + "af": 14 + }, + { + "pin": "PD3", + "signal": "A10", + "af": 12 + }, + { + "pin": "PD4", + "signal": "A11", + "af": 12 + }, + { + "pin": "PD5", + "signal": "D6", + "af": 12 + }, + { + "pin": "PD5", + "signal": "DA6", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A1", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A17", + "af": 14 + }, + { + "pin": "PD6", + "signal": "ALE", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A18", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A2", + "af": 12 + }, + { + "pin": "PD8", + "signal": "NBL0", + "af": 12 + }, + { + "pin": "PD9", + "signal": "SDCLK", + "af": 12 + }, + { + "pin": "PE0", + "signal": "D9", + "af": 12 + }, + { + "pin": "PE0", + "signal": "DA9", + "af": 12 + }, + { + "pin": "PE1", + "signal": "D10", + "af": 12 + }, + { + "pin": "PE1", + "signal": "DA10", + "af": 12 + }, + { + "pin": "PE10", + "signal": "A15", + "af": 12 + }, + { + "pin": "PE10", + "signal": "BA1", + "af": 12 + }, + { + "pin": "PE11", + "signal": "SDNWE", + "af": 12 + }, + { + "pin": "PE12", + "signal": "SDNRAS", + "af": 12 + }, + { + "pin": "PE13", + "signal": "SDNCAS", + "af": 12 + }, + { + "pin": "PE14", + "signal": "NWE", + "af": 14 + }, + { + "pin": "PE14", + "signal": "SDNE0", + "af": 12 + }, + { + "pin": "PE15", + "signal": "SDCKE0", + "af": 12 + }, + { + "pin": "PE2", + "signal": "D11", + "af": 12 + }, + { + "pin": "PE2", + "signal": "DA11", + "af": 12 + }, + { + "pin": "PE3", + "signal": "D12", + "af": 12 + }, + { + "pin": "PE3", + "signal": "DA12", + "af": 12 + }, + { + "pin": "PE5", + "signal": "SDNE1", + "af": 12 + }, + { + "pin": "PE6", + "signal": "SDCKE1", + "af": 12 + }, + { + "pin": "PE7", + "signal": "A20", + "af": 14 + }, + { + "pin": "PE7", + "signal": "A4", + "af": 12 + }, + { + "pin": "PE8", + "signal": "A12", + "af": 12 + }, + { + "pin": "PE9", + "signal": "A14", + "af": 12 + }, + { + "pin": "PE9", + "signal": "BA0", + "af": 12 + }, + { + "pin": "PF2", + "signal": "NWAIT", + "af": 12 + }, + { + "pin": "PF3", + "signal": "NL", + "af": 12 + }, + { + "pin": "PF5", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PF8", + "signal": "NWE", + "af": 12 + }, + { + "pin": "PG1", + "signal": "A19", + "af": 12 + }, + { + "pin": "PG10", + "signal": "A16", + "af": 12 + }, + { + "pin": "PG10", + "signal": "CLE", + "af": 12 + }, + { + "pin": "PG12", + "signal": "A18", + "af": 12 + }, + { + "pin": "PG13", + "signal": "NE1", + "af": 12 + }, + { + "pin": "PG14", + "signal": "NCE", + "af": 10 + }, + { + "pin": "PG14", + "signal": "NE2", + "af": 12 + }, + { + "pin": "PG15", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PG2", + "signal": "A21", + "af": 12 + }, + { + "pin": "PG8", + "signal": "A20", + "af": 12 + }, + { + "pin": "PG9", + "signal": "D8", + "af": 12 + }, + { + "pin": "PG9", + "signal": "DA8", + "af": 12 + }, + { + "pin": "PH2", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D9", + "af": 14 + }, + { + "pin": "PH9", + "signal": "DA9", + "af": 14 + }, + { + "pin": "PN0", + "signal": "A25", + "af": 12 + }, + { + "pin": "PN1", + "signal": "A24", + "af": 12 + }, + { + "pin": "PN2", + "signal": "A23", + "af": 12 + }, + { + "pin": "PN3", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO0", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO1", + "signal": "A23", + "af": 12 + }, + { + "pin": "PO2", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO4", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO4", + "signal": "NBL2", + "af": 14 + }, + { + "pin": "PO5", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO5", + "signal": "NBL3", + "af": 14 + }, + { + "pin": "PP0", + "signal": "D16", + "af": 12 + }, + { + "pin": "PP1", + "signal": "D17", + "af": 12 + }, + { + "pin": "PP2", + "signal": "D18", + "af": 12 + }, + { + "pin": "PP3", + "signal": "D19", + "af": 12 + }, + { + "pin": "PP4", + "signal": "D20", + "af": 12 + }, + { + "pin": "PP5", + "signal": "D21", + "af": 12 + }, + { + "pin": "PP6", + "signal": "D22", + "af": 12 + }, + { + "pin": "PP7", + "signal": "D23", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE1", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PF1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PG14", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM1" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF1", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPTIM5", + "address": 1174417408, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM5EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM5RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE2", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PE3", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF0", + "signal": "OUT", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM5" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA7", + "signal": "B1", + "af": 14 + }, + { + "pin": "PA7", + "signal": "R4", + "af": 10 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PD9", + "signal": "R1", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF6", + "signal": "DE", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PF9", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PG0", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG0", + "signal": "VSYNC", + "af": 10 + }, + { + "pin": "PG1", + "signal": "G1", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG11", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG12", + "signal": "G0", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG15", + "signal": "B0", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG4", + "signal": "B0", + "af": 14 + }, + { + "pin": "PG5", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG6", + "signal": "B3", + "af": 14 + }, + { + "pin": "PG8", + "signal": "G7", + "af": 14 + }, + { + "pin": "PG9", + "signal": "R7", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + }, + { + "pin": "PO2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PO4", + "signal": "B4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC6", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC7", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "DE", + "af": 9 + }, + { + "pin": "PD11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD5", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PD9", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE6", + "signal": "D1", + "af": 10 + }, + { + "pin": "PE6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF0", + "signal": "D9", + "af": 9 + }, + { + "pin": "PF1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG1", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG15", + "signal": "D4", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PG6", + "signal": "D12", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PH9", + "signal": "D6", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD5", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH3", + "af": 13 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PG5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG6", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF0", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PF1", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART2", + "address": 1073759232, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA1", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA2", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF2", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF2", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PF3", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF4", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG3", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG5", + "signal": "NSS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART2" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PH9", + "signal": "CK", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USART6", + "address": 1107301376, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART6EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART6RST" + } + }, + "pins": [ + { + "pin": "PC6", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PD3", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG14", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG6", + "signal": "CK", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + }, + { + "pin": "PO0", + "signal": "P1_NCS1", + "af": 9 + }, + { + "pin": "PO1", + "signal": "P1_NCS2", + "af": 9 + }, + { + "pin": "PO2", + "signal": "P1_DQS0", + "af": 9 + }, + { + "pin": "PO4", + "signal": "P1_CLK", + "af": 9 + }, + { + "pin": "PO5", + "signal": "P1_NCLK", + "af": 9 + }, + { + "pin": "PP0", + "signal": "P1_IO0", + "af": 9 + }, + { + "pin": "PP1", + "signal": "P1_IO1", + "af": 9 + }, + { + "pin": "PP2", + "signal": "P1_IO2", + "af": 9 + }, + { + "pin": "PP3", + "signal": "P1_IO3", + "af": 9 + }, + { + "pin": "PP4", + "signal": "P1_IO4", + "af": 9 + }, + { + "pin": "PP5", + "signal": "P1_IO5", + "af": 9 + }, + { + "pin": "PP6", + "signal": "P1_IO6", + "af": 9 + }, + { + "pin": "PP7", + "signal": "P1_IO7", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, 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"name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + }, + { + "name": "PO0" + }, + { + "name": "PO1" + }, + { + "name": "PO2" + }, + { + "name": "PO4" + }, + { + "name": "PO5" + }, + { + "name": "PP0" + }, + { + "name": "PP1" + }, + { + "name": "PP2" + }, + { + "name": "PP3" + }, + { + "name": "PP4" + }, + { + "name": "PP5" + }, + { + "name": "PP6" + }, + { + "name": "PP7" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N645I0.json b/data/chips/STM32N645I0.json new file mode 100644 index 0000000..54603a5 --- /dev/null +++ b/data/chips/STM32N645I0.json @@ -0,0 +1,9618 @@ +{ + "name": "STM32N645I0", + "family": "STM32N6", + "line": "STM32N6x5", + "die": "DIE486", + "device_id": 1158, + "packages": [ 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12 + }, + { + "pin": "PN2", + "signal": "A23", + "af": 12 + }, + { + "pin": "PN3", + "signal": "A22", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA7", + "signal": "B1", + "af": 14 + }, + { + "pin": "PA7", + "signal": "R4", + "af": 10 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB2", + "signal": "B2", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD13", + "signal": "R6", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PD9", + "signal": "R1", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF6", + "signal": "DE", + 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{ + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + 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"signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB2", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB2", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { 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"af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB2", + "signal": "CH1", + "af": 1 + }, + { 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"PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH3", + "af": 13 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD13", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART2", + "address": 1073759232, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA1", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA2", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF2", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF2", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PF3", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF4", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART2" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PH9", + "signal": "CK", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USART6", + "address": 1107301376, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART6EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART6RST" + } + }, + "pins": [ + { + "pin": "PC6", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PD3", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG14", + "signal": "TX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + 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{ + "name": "DMA2D", + "number": 60 + }, + { + "name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": 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}, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA3" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA7" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB2" + }, + { + "name": "PB3" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PC1" + }, + { + "name": "PC6" + }, + { + "name": "PC7" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD0" + }, + { + "name": "PD1" + }, + { + "name": "PD2" + }, + { + "name": "PD3" + }, + { + "name": "PD4" + }, + { + "name": "PD5" + }, + { + "name": "PD6" + }, + { + "name": "PD7" + }, + { + "name": "PD8" + }, + { + "name": "PD9" + }, + { + "name": "PD10" + }, + { + "name": "PD11" + }, + { + "name": "PD12" + }, + { + "name": "PD13" + }, + { + "name": "PD14" + }, + { + "name": "PD15" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE5" + }, + { + "name": "PE6" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": "PE9" + }, + { + "name": "PE10" + }, + { + "name": "PE11" + }, + { + "name": "PE12" + }, + { + "name": "PE13" + }, + { + "name": "PE14" + }, + { + "name": "PE15" + }, + { + "name": "PF2" + }, + { + "name": "PF3" + }, + { + "name": "PF4" + }, + { + "name": "PF5" + }, + { + "name": "PF6" + }, + { + "name": "PF7" + }, + { + "name": "PF8" + }, + { + "name": "PF10" + }, + { + "name": "PF11" + }, + { + "name": "PF12" + }, + { + "name": "PF13" + }, + { + "name": "PF14" + }, + { + "name": "PF15" + }, + { + "name": "PG0" + }, + { + "name": "PG1" + }, + { + "name": "PG2" + }, + { + "name": "PG8" + }, + { + "name": "PG10" + }, + { + "name": "PG12" + }, + { + "name": "PG13" + }, + { + "name": "PG14" + }, + { + "name": "PG15" + }, + { + "name": "PH0" + }, + { + "name": "PH1" + }, + { + "name": "PH2" + }, + { + "name": "PH9" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N645L0.json b/data/chips/STM32N645L0.json new file mode 100644 index 0000000..285c27e --- /dev/null +++ b/data/chips/STM32N645L0.json @@ -0,0 +1,11113 @@ +{ + "name": "STM32N645L0", + "family": "STM32N6", + "line": "STM32N6x5", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N645L0HxQ", + "package": "VFBGA223", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PD6" + ] + }, + { + "position": "A11", + "signals": [ + "PD12" + ] + }, + { + "position": "A12", + "signals": [ + "PD15" + ] + }, + { + "position": "A13", + "signals": [ + "PE8" + ] + }, + { + "position": "A14", + "signals": [ + "PB15" + ] + }, + { + "position": "A15", + "signals": [ + "PD5" + ] + }, + { + "position": "A16", + "signals": [ + "PB13" + ] + }, + { + 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"name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FMC", + "address": 1208107008, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR3", + "field": "FMCSEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "FMCEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "FMCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "D7", + "af": 12 + }, + { + "pin": "PA0", + "signal": "DA7", + "af": 12 + }, + { + "pin": "PA1", + "signal": "D6", + "af": 12 + }, + { + "pin": "PA1", + "signal": "DA6", + "af": 12 + }, + { + "pin": "PA10", + "signal": "D2", + "af": 12 + }, + { + "pin": "PA10", + "signal": "DA2", + "af": 12 + }, + { + "pin": "PA11", + "signal": "D1", + "af": 12 + }, + { + "pin": "PA11", + "signal": "DA1", + "af": 12 + }, + { + "pin": "PA12", + "signal": "D0", + "af": 12 + }, + { + "pin": "PA12", + "signal": "DA0", + "af": 12 + }, + { + "pin": "PA15", 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"signal": "DA10", + "af": 12 + }, + { + "pin": "PB12", + "signal": "D9", + "af": 12 + }, + { + "pin": "PB12", + "signal": "DA9", + "af": 12 + }, + { + "pin": "PB13", + "signal": "D5", + "af": 12 + }, + { + "pin": "PB13", + "signal": "DA5", + "af": 12 + }, + { + "pin": "PB14", + "signal": "D7", + "af": 12 + }, + { + "pin": "PB14", + "signal": "DA7", + "af": 12 + }, + { + "pin": "PB15", + "signal": "D0", + "af": 12 + }, + { + "pin": "PB15", + "signal": "DA0", + "af": 12 + }, + { + "pin": "PB2", + "signal": "D2", + "af": 12 + }, + { + "pin": "PB2", + "signal": "DA2", + "af": 12 + }, + { + "pin": "PB3", + "signal": "A23", + "af": 14 + }, + { + "pin": "PB3", + "signal": "NBL1", + "af": 12 + }, + { + "pin": "PB4", + "signal": "D13", + "af": 12 + }, + { + "pin": "PB4", + "signal": "DA13", + "af": 12 + }, + { + "pin": "PB5", + "signal": "D12", + "af": 12 + }, + { + "pin": "PB5", + "signal": "DA12", + "af": 12 + }, + { + "pin": "PB6", + "signal": "D14", + "af": 12 + }, + { + "pin": "PB6", + "signal": "DA14", + "af": 12 + }, + { + "pin": "PB7", + "signal": "D15", + "af": 12 + }, + { + "pin": "PB7", + "signal": "DA15", + "af": 12 + }, + { + "pin": "PB8", + "signal": "D1", + "af": 12 + }, + { + "pin": "PB8", + "signal": "DA1", + "af": 12 + }, + { + "pin": "PB9", + "signal": "D3", + "af": 12 + }, + { + "pin": "PB9", + "signal": "DA3", + "af": 12 + }, + { + "pin": "PC10", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PC12", + "signal": "NL", + "af": 12 + }, + { + "pin": "PC8", + "signal": "NE4", + "af": 12 + }, + { + "pin": "PD0", + "signal": "A22", + "af": 14 + }, + { + "pin": "PD0", + "signal": "A6", + "af": 12 + }, + { + "pin": "PD1", + "signal": "A23", + "af": 14 + }, + { + "pin": "PD1", + "signal": "A7", + "af": 12 + }, + { + "pin": "PD10", + "signal": "A19", + "af": 14 + }, + { + "pin": "PD10", + "signal": "A3", + "af": 12 + }, + { + "pin": "PD11", + "signal": "D8", + "af": 12 + }, + { + "pin": "PD11", + "signal": "DA8", + "af": 12 + }, + { + "pin": "PD12", + "signal": "A21", + "af": 14 + }, + { + "pin": "PD12", + "signal": "A5", + "af": 12 + }, + { + "pin": "PD13", + "signal": "D4", + "af": 12 + }, + { + "pin": "PD13", + "signal": "DA4", + "af": 12 + }, + { + "pin": "PD14", + "signal": "A9", + "af": 12 + }, + { + "pin": "PD15", + "signal": "A8", + "af": 12 + }, + { + "pin": "PD2", + "signal": "A0", + "af": 12 + }, + { + "pin": "PD2", + "signal": "A16", + "af": 14 + }, + { + "pin": "PD2", + "signal": "CLE", + "af": 14 + }, + { + "pin": "PD3", + "signal": "A10", + "af": 12 + }, + { + "pin": "PD4", + "signal": "A11", + "af": 12 + }, + { + "pin": "PD5", + "signal": "D6", + "af": 12 + }, + { + "pin": "PD5", + "signal": "DA6", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A1", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A17", + "af": 14 + }, + { + "pin": "PD6", + "signal": "ALE", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A18", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A2", + "af": 12 + }, + { + "pin": "PD8", + "signal": "NBL0", + "af": 12 + }, + { + "pin": "PD9", + "signal": "SDCLK", + "af": 12 + }, + { + "pin": "PE0", + "signal": "D9", + "af": 12 + }, + { + "pin": "PE0", + "signal": "DA9", + "af": 12 + }, + { + "pin": "PE1", + "signal": "D10", + "af": 12 + }, + { + "pin": "PE1", + "signal": "DA10", + "af": 12 + }, + { + "pin": "PE10", + "signal": "A15", + "af": 12 + }, + { + "pin": "PE10", + "signal": "BA1", + "af": 12 + }, + { + "pin": "PE11", + "signal": "SDNWE", + "af": 12 + }, + { + "pin": "PE12", + "signal": "SDNRAS", + "af": 12 + }, + { + "pin": "PE13", + "signal": "SDNCAS", + "af": 12 + }, + { + "pin": "PE14", + "signal": "NWE", + "af": 14 + }, + { + "pin": "PE14", + "signal": "SDNE0", + "af": 12 + }, + { + "pin": "PE15", + "signal": "SDCKE0", + "af": 12 + }, + { + "pin": "PE2", + "signal": "D11", + "af": 12 + }, + { + "pin": "PE2", + "signal": "DA11", + "af": 12 + }, + { + "pin": "PE3", + "signal": "D12", + "af": 12 + }, + { + "pin": "PE3", + "signal": "DA12", + "af": 12 + }, + { + "pin": "PE5", + "signal": "SDNE1", + "af": 12 + }, + { + "pin": "PE6", + "signal": "SDCKE1", + "af": 12 + }, + { + "pin": "PE7", + "signal": "A20", + "af": 14 + }, + { + "pin": "PE7", + "signal": "A4", + "af": 12 + }, + { + "pin": "PE8", + "signal": "A12", + "af": 12 + }, + { + "pin": "PE9", + "signal": "A14", + "af": 12 + }, + { + "pin": "PE9", + "signal": "BA0", + "af": 12 + }, + { + "pin": "PF2", + "signal": "NWAIT", + "af": 12 + }, + { + "pin": "PF3", + "signal": "NL", + "af": 12 + }, + { + "pin": "PF5", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PF8", + "signal": "NWE", + "af": 12 + }, + { + "pin": "PG1", + "signal": "A19", + "af": 12 + }, + { + "pin": "PG10", + "signal": "A16", + "af": 12 + }, + { + "pin": "PG10", + "signal": "CLE", + "af": 12 + }, + { + "pin": "PG12", + "signal": "A18", + "af": 12 + }, + { + "pin": "PG13", + "signal": "NE1", + "af": 12 + }, + { + "pin": "PG14", + "signal": "NCE", + "af": 10 + }, + { + "pin": "PG14", + "signal": "NE2", + "af": 12 + }, + { + "pin": "PG15", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PG2", + "signal": "A21", + "af": 12 + }, + { + "pin": "PG8", + "signal": "A20", + "af": 12 + }, + { + "pin": "PG9", + "signal": "D8", + "af": 12 + }, + { + "pin": "PG9", + "signal": "DA8", + "af": 12 + }, + { + "pin": "PH2", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D9", + "af": 14 + }, + { + "pin": "PH9", + "signal": "DA9", + "af": 14 + }, + { + "pin": "PN0", + "signal": "A25", + "af": 12 + }, + { + "pin": "PN1", + "signal": "A24", + "af": 12 + }, + { + "pin": "PN2", + "signal": "A23", + "af": 12 + }, + { + "pin": "PN3", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO0", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO1", + "signal": "A23", + "af": 12 + }, + { + "pin": "PO2", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO3", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO4", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO4", + "signal": "NBL2", + "af": 14 + }, + { + "pin": "PO5", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO5", + "signal": "NBL3", + "af": 14 + }, + { + "pin": "PP0", + "signal": "D16", + "af": 12 + }, + { + "pin": "PP1", + "signal": "D17", + "af": 12 + }, + { + "pin": "PP10", + "signal": "D26", + "af": 12 + }, + { + "pin": "PP11", + "signal": "D27", + "af": 12 + }, + { + "pin": "PP12", + "signal": "D28", + "af": 12 + }, + { + "pin": "PP13", + "signal": "D29", + "af": 12 + }, + { + "pin": "PP14", + "signal": "D30", + "af": 12 + }, + { + "pin": "PP15", + "signal": "D31", + "af": 12 + }, + { + "pin": "PP2", + "signal": "D18", + "af": 12 + }, + { + "pin": "PP3", + "signal": "D19", + "af": 12 + }, + { + "pin": "PP4", + "signal": "D20", + "af": 12 + }, + { + "pin": "PP5", + "signal": "D21", + "af": 12 + }, + { + "pin": "PP6", + "signal": "D22", + "af": 12 + }, + { + "pin": "PP7", + "signal": "D23", + "af": 12 + }, + { + "pin": "PP8", + "signal": "D24", + "af": 12 + }, + { + "pin": "PP9", + "signal": "D25", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB9", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PD13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 1 + }, + { + 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"register": "APB4LRSTR", + "field": "LPTIM5RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE2", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PE3", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF0", + "signal": "OUT", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM5" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA7", + "signal": "B1", + "af": 14 + }, + { + "pin": "PA7", + "signal": "R4", + "af": 10 + }, + { + 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"signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA4", + "signal": "D3", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + 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{ + "pin": "PD13", + "signal": "D13", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD5", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PD9", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE6", + "signal": "D1", + "af": 10 + }, + { + "pin": "PE6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF0", + "signal": "D9", + "af": 9 + }, + { + "pin": "PF1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG1", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG15", + "signal": "D4", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PG6", + "signal": "D12", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PH9", + "signal": "D6", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PB8", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD13", + "signal": "SCK_A", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, 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+ }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SDMMC2", + "address": 1208117248, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC2SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC2EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CMD", + "af": 11 + }, + { + "pin": "PB13", + "signal": "D6", + "af": 11 + }, + { + "pin": "PB4", + "signal": "D3", + "af": 11 + }, + { + "pin": "PB8", + "signal": "D0", + "af": 11 + }, + { + "pin": "PB9", + "signal": "D2", + "af": 11 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 11 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 11 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 11 + }, + { + "pin": "PD2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PD5", + "signal": "D7", + "af": 11 + }, + { + "pin": "PG8", + "signal": "D1", + "af": 11 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC2" + } + ] + }, + { + "name": "SPDIFRX1", + "address": 1073758208, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPDIFRX1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPDIFRX1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPDIFRX1RST" + } + }, + "pins": [ + { + "pin": "PB15", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PB8", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PB9", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PD10", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PD12", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PD8", + "signal": "IN1", + "af": 8 + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PP8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PP9", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB2", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB2", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA4", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB13", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB13", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB1", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB2", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD5", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 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"TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG6", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PB1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD13", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF0", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PF1", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART10", + "address": 1107303424, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART10EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART10RST" + } + }, + "pins": [ + { + "pin": "PB13", + "signal": "CTS", + "af": 6 + }, + { + "pin": "PB13", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB14", + "signal": "CK", + "af": 6 + }, + { + "pin": "PB9", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD14", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD15", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD3", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 6 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART10" + } + ] + }, + { + "name": "USART2", + "address": 1073759232, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA1", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA2", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF2", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF2", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PF3", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF4", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG3", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG5", + "signal": "NSS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART2" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PH9", + "signal": "CK", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USART6", + "address": 1107301376, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART6EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART6RST" + } + }, + "pins": [ + { + "pin": "PA4", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB13", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PB13", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PB14", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PB14", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PB15", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PB8", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC6", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PD3", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG14", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG6", + "signal": "CK", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + }, + { + "pin": "PO0", + "signal": "P1_NCS1", + "af": 9 + }, + { + "pin": "PO1", + "signal": "P1_NCS2", + "af": 9 + }, + { + "pin": "PO2", + "signal": "P1_DQS0", + "af": 9 + }, + { + "pin": "PO3", + "signal": "P1_DQS1", + "af": 9 + }, + { + "pin": "PO4", + "signal": "P1_CLK", + "af": 9 + }, + { + "pin": "PO5", + "signal": "P1_NCLK", + "af": 9 + }, + { + "pin": "PP0", + "signal": "P1_IO0", + "af": 9 + }, + { + "pin": "PP1", + "signal": "P1_IO1", + "af": 9 + }, + { + "pin": "PP10", + "signal": "P1_IO10", + "af": 9 + }, + { + "pin": "PP11", + "signal": "P1_IO11", + "af": 9 + }, + { + "pin": "PP12", + "signal": "P1_IO12", + "af": 9 + }, + { + "pin": "PP13", + "signal": "P1_IO13", + "af": 9 + }, + { + "pin": "PP14", + "signal": "P1_IO14", + "af": 9 + }, + { + "pin": "PP15", + "signal": "P1_IO15", + "af": 9 + }, + { + "pin": "PP2", + "signal": "P1_IO2", + "af": 9 + }, + { + "pin": "PP3", + "signal": "P1_IO3", + "af": 9 + }, + { + "pin": "PP4", + "signal": "P1_IO4", + "af": 9 + }, + { + "pin": "PP5", + "signal": "P1_IO5", + "af": 9 + }, + { + "pin": "PP6", + "signal": "P1_IO6", + "af": 9 + }, + { + "pin": "PP7", + "signal": "P1_IO7", + "af": 9 + }, + { + "pin": "PP8", + "signal": "P1_IO8", + "af": 9 + }, + { + "pin": "PP9", + "signal": "P1_IO9", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + { + "name": "EXTI2", + "number": 22 + }, + { + "name": "EXTI3", + "number": 23 + }, + { + "name": "EXTI4", + "number": 24 + }, + { + "name": "EXTI5", + "number": 25 + }, + { + "name": "EXTI6", + "number": 26 + }, + { + "name": "EXTI7", + "number": 27 + }, + { + "name": "EXTI8", + "number": 28 + }, + { + "name": "EXTI9", + "number": 29 + }, + { + "name": "EXTI10", + "number": 30 + }, + { + "name": "EXTI11", + "number": 31 + }, + { + "name": "EXTI12", + "number": 32 + }, + { + "name": "EXTI13", + "number": 33 + }, + { + "name": "EXTI14", + "number": 34 + }, + { + "name": "EXTI15", + "number": 35 + }, + { + "name": "PKA", + "number": 38 + }, + { + "name": "HASH", + "number": 39 + }, + { + "name": "RNG", + "number": 40 + }, + { + "name": "ADC1_2", + "number": 46 + }, + { + "name": "CSI", + "number": 47 + }, + { + "name": "DCMIPP", + "number": 48 + }, + { + "name": "PAHB_ERR", + "number": 52 + }, + { + "name": "LTDC_LO", + "number": 58 + }, + { + "name": "LTDC_LO_ERR", + "number": 59 + }, + { + "name": "DMA2D", + "number": 60 + }, + { + "name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA3" + }, + { + "name": "PA4" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA7" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB1" + }, + { + "name": "PB2" + }, + { + "name": "PB3" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB8" + }, + { + "name": "PB9" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PB13" + }, + { + "name": "PB14" + }, + { + "name": "PB15" + }, + { + "name": "PC1" + }, + { + "name": "PC6" + }, + { + "name": "PC7" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD0" + }, + { + "name": "PD1" + }, + { + "name": "PD2" + }, + { + "name": "PD3" + }, + { + "name": "PD4" + }, + { + "name": "PD5" + }, + { + "name": "PD6" + }, + { + "name": "PD7" + }, + { + "name": "PD8" + }, + { + "name": "PD9" + }, + { + "name": "PD10" + }, + { + "name": "PD11" + }, + { + "name": "PD12" + }, + { + "name": "PD13" + }, + { + "name": "PD14" + }, + { + "name": "PD15" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE5" + }, + { + "name": "PE6" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": 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}, + { + "name": "PH2" + }, + { + "name": "PH9" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + }, + { + "name": "PO0" + }, + { + "name": "PO1" + }, + { + "name": "PO2" + }, + { + "name": "PO3" + }, + { + "name": "PO4" + }, + { + "name": "PO5" + }, + { + "name": "PP0" + }, + { + "name": "PP1" + }, + { + "name": "PP2" + }, + { + "name": "PP3" + }, + { + "name": "PP4" + }, + { + "name": "PP5" + }, + { + "name": "PP6" + }, + { + "name": "PP7" + }, + { + "name": "PP8" + }, + { + "name": "PP9" + }, + { + "name": "PP10" + }, + { + "name": "PP11" + }, + { + "name": "PP12" + }, + { + "name": "PP13" + }, + { + "name": "PP14" + }, + { + "name": "PP15" + } + ] + } + ] +} \ No newline at end of file diff --git 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"field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PH7", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PH8", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB9", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PD13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE1", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PE4", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PF1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PG14", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM1" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PC4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF1", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPTIM4", + "address": 1174416384, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM4RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB4", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB5", + "signal": "OUT", + "af": 3 + }, + { + "pin": "PC0", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM4" + } + ] + }, + { + "name": "LPTIM5", + "address": 1174417408, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM5EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM5RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE2", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PE3", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF0", + "signal": "OUT", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM5" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + 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"registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA4", + "signal": "D3", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB14", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PB8", + "signal": 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1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { 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"PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG7", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PB8", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PC5", 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"interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { 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"PC1", + "signal": "D5", + "af": 11 + }, + { + "pin": "PC2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PC3", + "signal": "CMD", + "af": 11 + }, + { + "pin": "PC4", + "signal": "D0", + "af": 11 + }, + { + "pin": "PC5", + "signal": "D1", + "af": 11 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 11 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 11 + }, + { + "pin": "PD2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PD5", + "signal": "D7", + "af": 11 + }, + { + "pin": "PE4", + "signal": "D3", + "af": 11 + }, + { + "pin": "PG8", + "signal": "D1", + "af": 11 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC2" + } + ] + }, + { + "name": "SPDIFRX1", + "address": 1073758208, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPDIFRX1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPDIFRX1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPDIFRX1RST" + } + }, + "pins": [ + { + "pin": "PB15", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PB8", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PB9", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PC3", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PD10", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PD12", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PD8", + "signal": "IN1", + "af": 8 + }, + { + "pin": "PE4", + "signal": "IN1", + "af": 8 + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PC0", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC0", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PC3", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PC3", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PC5", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC5", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PC4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PP8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PP9", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB2", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB2", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC0", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC0", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PC2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA4", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PH5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PH6", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PH7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PH8", + "signal": "MISO", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB13", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB13", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC0", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PC0", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PE4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + }, + { + "pin": "PH4", + "signal": "IN4" + }, + { + "pin": "PH4", + "signal": "OUT3" + }, + { + "pin": "PQ7", + "signal": "IN2" + }, + { + "pin": "PQ7", + "signal": "OUT1" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB1", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + 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+ "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PC4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": 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"CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 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+ "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC0", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM8", + "address": 1107297280, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM8EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM8RST" + } + }, + "pins": [ + { + "pin": "PB13", + "signal": "CH3N", + "af": 2 + }, + { + "pin": "PB14", + "signal": "CH4N", + "af": 2 + }, + { + "pin": "PG14", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PQ0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PQ1", + "signal": "BKIN", + "af": 2 + }, + { + "pin": "PQ2", + "signal": "BKIN2", + "af": 2 + }, + { + "pin": "PQ3", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PQ4", + "signal": "CH1N", + "af": 2 + }, + { + "pin": "PQ5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PQ6", + "signal": "CH2N", + "af": 2 + }, + { + "pin": "PQ7", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM8_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM8_CC" + }, + { + "signal": "COM", + "interrupt": "TIM8_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM8_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM8_UP" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PB1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PC4", + "signal": "DE", + "af": 8 + }, + { + "pin": "PC4", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PC0", + "signal": "RX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH3", + "signal": "TX", + "af": 8 + }, + { + "pin": "PH4", + "signal": "TX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD13", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF0", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PF1", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC4", + "signal": "TX", + "af": 4 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART10", + "address": 1107303424, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART10EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART10RST" + } + }, + "pins": [ + { + "pin": "PB13", + "signal": "CTS", + "af": 6 + }, + { + "pin": "PB13", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB14", + "signal": "CK", + "af": 6 + }, + { + "pin": "PB9", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD14", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD15", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD3", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 6 + }, + { + "pin": "PE4", + "signal": "RX", + "af": 6 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART10" + } + ] + }, + { + "name": "USART2", + "address": 1073759232, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA1", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA2", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC2", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF2", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF2", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PF3", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF4", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG3", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG5", + "signal": "NSS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART2" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PH9", + "signal": "CK", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USART6", + "address": 1107301376, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART6EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART6RST" + } + }, + "pins": [ + { + "pin": "PA4", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB13", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PB13", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PB14", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PB14", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PB15", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PB8", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC6", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PD3", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PE4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG14", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG6", + "signal": "CK", + "af": 7 + }, + { + "pin": "PG7", + "signal": "CK", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + }, + { + "pin": "PO0", + "signal": "P1_NCS1", + "af": 9 + }, + { + "pin": "PO1", + "signal": "P1_NCS2", + "af": 9 + }, + { + "pin": "PO2", + "signal": "P1_DQS0", + "af": 9 + }, + { + "pin": "PO3", + "signal": "P1_DQS1", + "af": 9 + }, + { + "pin": "PO4", + "signal": "P1_CLK", + "af": 9 + }, + { + "pin": "PO5", + "signal": "P1_NCLK", + "af": 9 + }, + { + "pin": "PP0", + "signal": "P1_IO0", + "af": 9 + }, + { + "pin": "PP1", + "signal": "P1_IO1", + "af": 9 + }, + { + "pin": "PP10", + "signal": "P1_IO10", + "af": 9 + }, + { + "pin": "PP11", + "signal": "P1_IO11", + "af": 9 + }, + { + "pin": "PP12", + "signal": "P1_IO12", + "af": 9 + }, + { + "pin": "PP13", + "signal": "P1_IO13", + "af": 9 + }, + { + "pin": "PP14", + "signal": "P1_IO14", + "af": 9 + }, + { + "pin": "PP15", + "signal": "P1_IO15", + "af": 9 + }, + { + "pin": "PP2", + "signal": "P1_IO2", + "af": 9 + }, + { + "pin": "PP3", + "signal": "P1_IO3", + "af": 9 + }, + { + "pin": "PP4", + "signal": "P1_IO4", + "af": 9 + }, + { + "pin": "PP5", + "signal": "P1_IO5", + "af": 9 + }, + { + "pin": "PP6", + "signal": "P1_IO6", + "af": 9 + }, + { + "pin": "PP7", + "signal": "P1_IO7", + "af": 9 + }, + { + "pin": "PP8", + "signal": "P1_IO8", + "af": 9 + }, + { + "pin": "PP9", + "signal": "P1_IO9", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + { + "name": "EXTI2", + "number": 22 + }, + { + "name": "EXTI3", + "number": 23 + }, + { + "name": "EXTI4", + "number": 24 + }, + { + "name": "EXTI5", + "number": 25 + }, + { + "name": "EXTI6", + "number": 26 + }, + { + "name": "EXTI7", + "number": 27 + }, + { + "name": "EXTI8", + "number": 28 + }, + { + "name": "EXTI9", + "number": 29 + }, + { + "name": "EXTI10", + "number": 30 + }, + { + "name": "EXTI11", + "number": 31 + }, + { + "name": "EXTI12", + "number": 32 + }, + { + "name": "EXTI13", + "number": 33 + }, + { + "name": "EXTI14", + "number": 34 + }, + { + "name": "EXTI15", + "number": 35 + }, + { + "name": "PKA", + "number": 38 + }, + { + "name": "HASH", + "number": 39 + }, + { + "name": "RNG", + "number": 40 + }, + { + "name": "ADC1_2", + "number": 46 + }, + { + "name": "CSI", + "number": 47 + }, + { + "name": "DCMIPP", + "number": 48 + }, + { + "name": "PAHB_ERR", + "number": 52 + }, + { + "name": "LTDC_LO", + "number": 58 + }, + { + "name": "LTDC_LO_ERR", + "number": 59 + }, + { + "name": "DMA2D", + "number": 60 + }, + { + "name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA3" + }, + { + "name": "PA4" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA7" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB1" + }, + { + "name": "PB2" + }, + { + "name": "PB3" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB8" + }, + { + "name": "PB9" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PB13" + }, + { + "name": "PB14" + }, + { + "name": "PB15" + }, + { + "name": "PC0" + }, + { + "name": "PC1" + }, + { + "name": "PC2" + }, + { + "name": "PC3" + }, + { + "name": "PC4" + }, + { + "name": "PC5" + }, + { + "name": "PC6" + }, + { + "name": "PC7" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD0" + }, + { + "name": "PD1" + }, + { + "name": "PD2" + }, + { + "name": "PD3" + }, + { + "name": "PD4" + }, + { + "name": "PD5" + }, + { + "name": "PD6" + }, + { + "name": "PD7" + }, + { + "name": "PD8" + }, + { + "name": "PD9" + }, + { + "name": "PD10" + }, + { + "name": "PD11" + }, + { + "name": "PD12" + }, + { + "name": "PD13" + }, + { + "name": "PD14" + }, + { + "name": "PD15" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE4" + }, + { + "name": "PE5" + }, + { + "name": "PE6" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": "PE9" + }, + { + "name": "PE10" + }, + { + "name": "PE11" + }, + { + "name": "PE12" + }, + { + "name": "PE13" + }, + { + "name": "PE14" + }, + { + "name": "PE15" + }, + { + "name": "PF0" + }, + { + "name": "PF1" + }, + { + "name": "PF2" + }, + { + "name": "PF3" + }, + { + "name": "PF4" + }, + { + "name": "PF5" + }, + { + "name": "PF6" + }, + { + "name": "PF7" + }, + { + "name": "PF8" + }, + { + "name": "PF9" + }, + { + "name": "PF10" + }, + { + "name": "PF11" + }, + { + "name": "PF12" + }, + { + "name": "PF13" + }, + { + "name": "PF14" + }, + { + "name": "PF15" + }, + { + "name": "PG0" + }, + { + "name": "PG1" + }, + { + "name": "PG2" + }, + { + "name": "PG3" + }, + { + "name": "PG4" + }, + { + "name": "PG5" + }, + { + "name": "PG6" + }, + { + "name": "PG7" + }, + { + "name": "PG8" + }, + { + "name": "PG9" + }, + { + "name": "PG10" + }, + { + "name": "PG11" + }, + { + "name": "PG12" + }, + { + "name": "PG13" + }, + { + "name": "PG14" + }, + { + "name": "PG15" + }, + { + "name": "PH0" + }, + { + "name": "PH1" + }, + { + "name": "PH2" + }, + { + "name": "PH3" + }, + { + "name": "PH4" + }, + { + "name": "PH5" + }, + { + "name": "PH6" + }, + { + "name": "PH7" + }, + { + "name": "PH8" + }, + { + "name": "PH9" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + }, + { + "name": "PO0" + }, + { + "name": "PO1" + }, + { + "name": "PO2" + }, + { + "name": "PO3" + }, + { + "name": "PO4" + }, + { + "name": "PO5" + }, + { + "name": "PP0" + }, + { + "name": "PP1" + }, + { + "name": "PP2" + }, + { + "name": "PP3" + }, + { + "name": "PP4" + }, + { + "name": "PP5" + }, + { + "name": "PP6" + }, + { + "name": "PP7" + }, + { + "name": "PP8" + }, + { + "name": "PP9" + }, + { + "name": "PP10" + }, + { + "name": "PP11" + }, + { + "name": "PP12" + }, + { + "name": "PP13" + }, + { + "name": "PP14" + }, + { + "name": "PP15" + }, + { + "name": "PQ0" + }, + { + "name": "PQ1" + }, + { + "name": "PQ2" + }, + { + "name": "PQ3" + }, + { + "name": "PQ4" + }, + { + "name": "PQ5" + }, + { + "name": "PQ6" + }, + { + "name": "PQ7" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N645Z0.json b/data/chips/STM32N645Z0.json new file mode 100644 index 0000000..35d77c3 --- /dev/null +++ b/data/chips/STM32N645Z0.json @@ -0,0 +1,6499 @@ +{ + "name": "STM32N645Z0", + "family": "STM32N6", + "line": "STM32N6x5", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N645Z0HxQ", + "package": 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"DMA2D" + } + ] + }, + { + "name": "DTS", + "address": 1174446080, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "DTSEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "DTSRST" + } + } + }, + { + "name": "EXTI", + "address": 1174556672, + "registers": { + "kind": "exti", + "version": "v1", + "block": "EXTI" + }, + "interrupts": [ + { + "signal": "EXTI0", + "interrupt": "EXTI0" + }, + { + "signal": "EXTI1", + "interrupt": "EXTI1" + }, + { + "signal": "EXTI10", + "interrupt": "EXTI10" + }, + { + "signal": "EXTI11", + "interrupt": "EXTI11" + }, + { + "signal": "EXTI12", + "interrupt": "EXTI12" + }, + { + "signal": "EXTI13", + "interrupt": "EXTI13" + }, + { + "signal": "EXTI14", + "interrupt": "EXTI14" + }, + { + "signal": "EXTI15", + "interrupt": "EXTI15" + }, + { + "signal": "EXTI2", + "interrupt": "EXTI2" + }, + { + "signal": "EXTI3", + "interrupt": "EXTI3" + }, + { + "signal": "EXTI4", + "interrupt": "EXTI4" + }, + { + "signal": "EXTI5", + "interrupt": "EXTI5" + }, + { + "signal": "EXTI6", + "interrupt": "EXTI6" + }, + { + "signal": "EXTI7", + "interrupt": "EXTI7" + }, + { + "signal": "EXTI8", + "interrupt": "EXTI8" + }, + { + "signal": "EXTI9", + "interrupt": "EXTI9" + } + ] + }, + { + "name": "FDCAN1", + "address": 1073782784, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + { + "name": "EXTI2", + "number": 22 + }, + { + "name": "EXTI3", + "number": 23 + }, + { + "name": "EXTI4", + "number": 24 + }, + { + "name": "EXTI5", + "number": 25 + }, + { + "name": "EXTI6", + "number": 26 + }, + { + "name": "EXTI7", + "number": 27 + }, + { + "name": "EXTI8", + "number": 28 + }, + { + "name": "EXTI9", + "number": 29 + }, + { + "name": "EXTI10", + "number": 30 + }, + { + "name": "EXTI11", + "number": 31 + }, + { + "name": "EXTI12", + "number": 32 + }, + { + "name": "EXTI13", + "number": 33 + }, + { + "name": "EXTI14", + "number": 34 + }, + { + "name": "EXTI15", + "number": 35 + }, + { + "name": "PKA", + "number": 38 + }, + { + "name": "HASH", + "number": 39 + }, + { + "name": "RNG", + "number": 40 + }, + { + "name": "ADC1_2", + "number": 46 + }, + { + "name": "CSI", + "number": 47 + }, + { + "name": "DCMIPP", + "number": 48 + }, + { + "name": "PAHB_ERR", + "number": 52 + }, + { + "name": "LTDC_LO", + "number": 58 + }, + { + "name": "LTDC_LO_ERR", + "number": 59 + }, + { + "name": "DMA2D", + "number": 60 + }, + { + "name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD1" + }, + { + "name": "PD8" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": "PE9" + }, + { + "name": "PE10" + }, + { + "name": "PE12" + }, + { + "name": "PE13" + }, + { + "name": "PE14" + }, + { + "name": "PE15" + }, + { + "name": "PF2" + }, + { + "name": "PF3" + }, + { + "name": "PF4" + }, + { + "name": "PF5" + }, + { + "name": "PF7" + }, + { + "name": "PF8" + }, + { + "name": "PF10" + }, + { + "name": "PF11" + }, + { + "name": "PF12" + }, + { + "name": "PF13" + }, + { + "name": "PF14" + }, + { + "name": "PF15" + }, + { + "name": "PG2" + }, + { + "name": "PG10" + }, + { + "name": "PG13" + }, + { + "name": "PG14" + }, + { + "name": "PH0" + }, + { + "name": "PH1" + }, + { + "name": "PH2" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N647A0.json b/data/chips/STM32N647A0.json new file mode 100644 index 0000000..6c16418 --- /dev/null +++ b/data/chips/STM32N647A0.json @@ -0,0 +1,7686 @@ +{ + "name": "STM32N647A0", + "family": "STM32N6", + "line": "STM32N6x7", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N647A0HxQ", + "package": "VFBGA169", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PE13" + ] + }, + { + "position": "A11", + "signals": [ + "PD7" + ] + }, + { + "position": "A12", + "signals": [ + "PD1" + ] + }, + { + "position": "A13", + "signals": [ + "VSS" + ] + }, + { + "position": "A2", + "signals": [] + }, + { + "position": "A3", + "signals": [ + "OTG2_HSDM" + ] + }, + { + "position": "A4", + "signals": [] + }, + { + "position": "A5", + "signals": [ + "OTG1_HSDM" + ] + }, + { + "position": "A6", + "signals": [ + "OTG1_TXRTUNE" + ] + }, + { + "position": "A7", + "signals": [ + "PH1" + ] + }, + { + "position": "A8", + "signals": [ + "PC11" + ] + }, + { + "position": "A9", + "signals": [ + "PE11" + ] + }, + { + "position": "B1", + "signals": [ + "PC14" + ] + }, + { + "position": "B10", + "signals": [ + "PE12" + ] + }, + { + "position": "B11", + "signals": [ + "PD10" + ] + }, + { + "position": "B12", + "signals": [ + "PD0" + ] + }, + { + "position": "B13", + "signals": [ + "PD15" + ] + }, + { + "position": "B2", + "signals": [ + "OTG2_ID" + ] + }, + { + "position": "B3", + "signals": [ + "OTG2_HSDP" + ] + }, + { + "position": "B4", + "signals": [ + "OTG1_ID" + ] + }, + { + "position": "B5", + "signals": [ + "OTG1_HSDP" + ] + }, + { + "position": "B6", + "signals": [ + "UCPD1_CC1" + ] + }, + { + "position": "B7", + "signals": [ + "PH0" + ] + }, + { + "position": "B8", + "signals": [ + "PC12" + ] + }, + { + "position": "B9", + "signals": [ + "PE14" + ] + }, + { + "position": "C1", + "signals": [ + "PC15" + ] + }, + { + "position": "C10", + "signals": [ + "PD2" + ] + }, + { + "position": "C11", + "signals": [ + "PE7" + ] + }, + { + "position": "C12", + "signals": [ + "PD3" + ] + }, + { + "position": "C13", + "signals": [ + "PD14" + ] + }, + { + "position": "C2", + "signals": [ + "VBAT" + ] + }, + { + "position": "C3", + "signals": [ + "OTG2_TXRTUNE" + ] + }, + { + "position": "C4", + "signals": [ + "VDDA18USB" + ] + }, + { + "position": "C5", + "signals": [ + "VDD33USB" + ] + }, + { + "position": "C6", + "signals": [ + "UCPD1_CC2" + ] + }, + { + "position": "C7", + "signals": [ + "PC9" + ] + }, + { + "position": "C8", + "signals": [ + "PH2" + ] + }, + { + "position": "C9", + "signals": [ + "PE5" + ] + }, + { + "position": "D1", + "signals": [ + "V08CAP" + ] + }, + { + "position": "D10", + "signals": [ + "PD6" + ] + }, + { + "position": "D11", + "signals": [ + "PD12" + ] + }, + { + "position": "D12", + "signals": [ + "PE8" + ] + }, + { + "position": "D13", + "signals": [ + "PD4" + ] + }, + { + "position": "D2", + "signals": [ + "PC13" + ] + }, + { + "position": "D3", + "signals": [ + "BOOT0" + ] + }, + { + "position": "D4", + "signals": [ + "PWR_ON" + ] + }, + { + "position": "D5", + "signals": [ + "VDDA18AON" + ] + }, + { + "position": "D6", + "signals": [ + "PC10" + ] + }, + { + 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"signal": "CSI", + "interrupt": "CSI" + } + ] + }, + { + "name": "DMA2D", + "address": 1208094720, + "registers": { + "kind": "dma2d", + "version": "v1", + "block": "DMA2D" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "DMA2DEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "DMA2DRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DMA2D" + } + ] + }, + { + "name": "DTS", + "address": 1174446080, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "DTSEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "DTSRST" + } + } + }, + { + "name": "ETH1", + "address": 1208180736, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "ETH1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "ETH1RST" + } + }, + "pins": [ + { + "pin": "PD1", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD12", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PD3", + "signal": "PHY_INTN", + "af": 11 + }, + { + "pin": "PF10", + "signal": "CRS_DV", + "af": 11 + }, + { + "pin": "PF10", + "signal": "RGMII_RX_CTL", + "af": 11 + }, + { + "pin": "PF10", + "signal": "RX_DV", + "af": 11 + }, + { + "pin": "PF11", + "signal": "RGMII_TX_CTL", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TX_EN", + "af": 11 + }, + { + "pin": "PF12", + "signal": "RGMII_TXD0", + "af": 11 + }, + { + "pin": "PF12", + "signal": "TXD0", + "af": 11 + }, + { + "pin": "PF13", + "signal": "RGMII_TXD1", + "af": 11 + }, + { + "pin": "PF13", + "signal": "TXD1", + "af": 11 + }, + { + "pin": "PF14", + "signal": "RGMII_RXD0", + "af": 11 + }, + { + "pin": "PF14", + "signal": "RXD0", + "af": 11 + }, + { + "pin": "PF15", + "signal": "RGMII_RXD1", + "af": 11 + }, + { + "pin": "PF15", + "signal": "RXD1", + "af": 11 + }, + { + "pin": "PF2", + "signal": "RGMII_CLK125", + "af": 11 + }, + { + "pin": "PF3", + "signal": "PPS_OUT", + "af": 11 + }, + { + "pin": "PF4", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PF5", + "signal": "CLK", + "af": 11 + }, + { + "pin": "PF7", + "signal": "REF_CLK", + "af": 11 + }, + { + "pin": "PF7", + "signal": "RGMII_RX_CLK", + "af": 11 + }, + { + "pin": "PF7", + "signal": "RX_CLK", + "af": 11 + }, + { + "pin": "PF8", + "signal": "RGMII_RXD2", + "af": 11 + }, + { + "pin": "PF8", + "signal": "RXD2", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ETH1" + }, + { + "signal": "WKUP", + "interrupt": "ETH1" + } + ] + }, + { + "name": "EXTI", + "address": 1174556672, + "registers": { + "kind": "exti", + "version": "v1", + "block": "EXTI" + }, + "interrupts": [ + { + "signal": "EXTI0", + "interrupt": "EXTI0" + }, + { + "signal": "EXTI1", + "interrupt": "EXTI1" + }, + { + "signal": "EXTI10", + "interrupt": "EXTI10" + }, + { + "signal": "EXTI11", + "interrupt": "EXTI11" + }, + { + "signal": "EXTI12", + "interrupt": "EXTI12" + }, + { + "signal": "EXTI13", + "interrupt": "EXTI13" + }, + { + "signal": "EXTI14", + "interrupt": "EXTI14" + }, + { + "signal": "EXTI15", + "interrupt": "EXTI15" + }, + { + "signal": "EXTI2", + "interrupt": "EXTI2" + }, + { + "signal": "EXTI3", + "interrupt": "EXTI3" + }, + { + "signal": "EXTI4", + "interrupt": "EXTI4" + }, + { + "signal": "EXTI5", + "interrupt": "EXTI5" + }, + { + "signal": "EXTI6", + "interrupt": "EXTI6" + }, + { + "signal": "EXTI7", + "interrupt": "EXTI7" + }, + { + "signal": "EXTI8", + "interrupt": "EXTI8" + }, + { + "signal": "EXTI9", + "interrupt": "EXTI9" + } + ] + }, + { + "name": "FDCAN1", + "address": 1073782784, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE11", + "signal": "TX", + "af": 6 + }, + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "DE", + "af": 9 + }, + { + "pin": "PD11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USART6", + "address": 1107301376, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART6EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART6RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PD3", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG14", + "signal": "TX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + { + "name": "EXTI2", + "number": 22 + }, + { + "name": "EXTI3", + "number": 23 + }, + { + "name": "EXTI4", + "number": 24 + }, + { + "name": "EXTI5", + "number": 25 + }, + { + "name": "EXTI6", + "number": 26 + }, + { + "name": "EXTI7", + "number": 27 + }, + { + "name": "EXTI8", + "number": 28 + }, + { + "name": "EXTI9", + "number": 29 + }, + { + "name": "EXTI10", + "number": 30 + }, + { + "name": "EXTI11", + "number": 31 + }, + { + "name": "EXTI12", + "number": 32 + }, + { + "name": "EXTI13", + "number": 33 + }, + { + "name": "EXTI14", + "number": 34 + }, + { + "name": "EXTI15", + "number": 35 + }, + { + "name": "PKA", + "number": 38 + }, + { + "name": "HASH", + "number": 39 + }, + { + "name": "RNG", + "number": 40 + }, + { + "name": "ADC1_2", + "number": 46 + }, + { + "name": "CSI", + "number": 47 + }, + { + "name": "DCMIPP", + "number": 48 + }, + { + "name": "PAHB_ERR", + "number": 52 + }, + { + "name": "NPU0", + "number": 53 + }, + { + "name": "NPU1", + "number": 54 + }, + { + "name": "NPU2", + "number": 55 + }, + { + "name": "NPU3", + "number": 56 + }, + { + "name": "CACHEAXI", + "number": 57 + }, + { + "name": "LTDC_LO", + "number": 58 + }, + { + "name": "LTDC_LO_ERR", + "number": 59 + }, + { + "name": "DMA2D", + "number": 60 + }, + { + "name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA3" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB3" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD0" + }, + { + "name": "PD1" + }, + { + "name": "PD2" + }, + { + "name": "PD3" + }, + { + "name": "PD4" + }, + { + "name": "PD6" + }, + { + "name": "PD7" + }, + { + "name": "PD8" + }, + { + "name": "PD10" + }, + { + "name": "PD11" + }, + { + "name": "PD12" + }, + { + "name": "PD14" + }, + { + "name": "PD15" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE5" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": "PE9" + }, + { + "name": "PE10" + }, + { + "name": "PE11" + }, + { + "name": "PE12" + }, + { + "name": "PE13" + }, + { + "name": "PE14" + }, + { + "name": "PE15" + }, + { + "name": "PF2" + }, + { + "name": "PF3" + }, + { + "name": "PF4" + }, + { + "name": "PF5" + }, + { + "name": "PF7" + }, + { + "name": "PF8" + }, + { + "name": "PF10" + }, + { + "name": "PF11" + }, + { + "name": "PF12" + }, + { + "name": "PF13" + }, + { + "name": "PF14" + }, + { + "name": "PF15" + }, + { + "name": "PG2" + }, + { + "name": "PG10" + }, + { + "name": "PG13" + }, + { + "name": "PG14" + }, + { + "name": "PH0" + }, + { + "name": "PH1" + }, + { + "name": "PH2" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N647B0.json b/data/chips/STM32N647B0.json new file mode 100644 index 0000000..3ecf05d --- /dev/null +++ b/data/chips/STM32N647B0.json @@ -0,0 +1,10230 @@ +{ + "name": "STM32N647B0", + "family": "STM32N6", + "line": "STM32N6x7", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N647B0HxQ", + "package": "VFBGA198", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PD6" + ] + }, + { + "position": "A11", + "signals": [ + "PD12" + ] + }, + { + "position": "A12", + "signals": [ + "PD3" + ] + }, + { + "position": "A13", + "signals": [ + "PE10" + ] + }, + { + "position": "A14", + "signals": [ + "PB3" + ] + }, + { + "position": "A15", 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] + }, + { + "position": "B4", + "signals": [ + "OTG1_HSDM" + ] + }, + { + "position": "B5", + "signals": [ + "PH1" + ] + }, + { + "position": "B6", + "signals": [ + "PC9" + ] + }, + { + "position": "B7", + "signals": [ + "PC6" + ] + }, + { + "position": "B8", + "signals": [ + "PE14" + ] + }, + { + "position": "B9", + "signals": [ + "PE13" + ] + }, + { + "position": "C1", + "signals": [ + "PC14" + ] + }, + { + "position": "C10", + "signals": [ + "PD10" + ] + }, + { + "position": "C11", + "signals": [ + "PD0" + ] + }, + { + "position": "C12", + "signals": [ + "PE8" + ] + }, + { + "position": "C13", + "signals": [ + "PD5" + ] + }, + { + "position": "C14", + "signals": [ + "PE0" + ] + }, + { + "position": "C15", + "signals": [ + "PE3" + ] + }, + { + "position": "C2", + "signals": [] + }, + { + "position": "C3", + "signals": [ + "VDDA18USB" + ] + }, + { + "position": "C4", + "signals": [ + "OTG1_ID" + ] + }, + { + "position": "C5", + "signals": [ + "OTG1_TXRTUNE" + ] + }, + { + "position": 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"PF15", + "signal": "RXD1", + "af": 11 + }, + { + "pin": "PF2", + "signal": "RGMII_CLK125", + "af": 11 + }, + { + "pin": "PF3", + "signal": "PPS_OUT", + "af": 11 + }, + { + "pin": "PF4", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PF5", + "signal": "CLK", + "af": 11 + }, + { + "pin": "PF6", + "signal": "COL", + "af": 11 + }, + { + "pin": "PF7", + "signal": "REF_CLK", + "af": 11 + }, + { + "pin": "PF7", + "signal": "RGMII_RX_CLK", + "af": 11 + }, + { + "pin": "PF7", + "signal": "RX_CLK", + "af": 11 + }, + { + "pin": "PF8", + "signal": "RGMII_RXD2", + "af": 11 + }, + { + "pin": "PF8", + "signal": "RXD2", + "af": 11 + }, + { + "pin": "PF9", + "signal": "RGMII_RXD3", + "af": 11 + }, + { + "pin": "PF9", + "signal": "RXD3", + "af": 11 + }, + { + "pin": "PG0", + "signal": "PHY_INTN", + "af": 11 + }, + { + "pin": "PG11", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PG15", + "signal": "REF_CLK", + "af": 11 + }, + { + "pin": "PG15", + "signal": "RX_CLK", + "af": 11 + }, + { + "pin": "PG3", + "signal": "RGMII_TXD2", + "af": 11 + }, + { + "pin": "PG3", + "signal": "TXD2", + "af": 11 + }, + { + "pin": "PG4", + "signal": "RGMII_TXD3", + "af": 11 + }, + { + "pin": "PG4", + "signal": "TXD3", + "af": 11 + }, + { + "pin": "PG5", + "signal": "RX_ER", + "af": 11 + }, + { + "pin": "PG6", + "signal": "CRS", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ETH1" + }, + { + "signal": "WKUP", + "interrupt": "ETH1" + } + ] + }, + { + "name": "EXTI", + "address": 1174556672, + "registers": { + "kind": "exti", + "version": "v1", + "block": "EXTI" + }, + "interrupts": [ + { + "signal": "EXTI0", + "interrupt": "EXTI0" + }, + { + "signal": "EXTI1", + "interrupt": "EXTI1" + }, + { + "signal": "EXTI10", + "interrupt": "EXTI10" + }, + { + "signal": "EXTI11", + "interrupt": "EXTI11" + }, + { + "signal": "EXTI12", + "interrupt": "EXTI12" + }, + { + "signal": "EXTI13", + "interrupt": "EXTI13" + }, + { + "signal": "EXTI14", + "interrupt": "EXTI14" + }, + { + "signal": "EXTI15", + "interrupt": "EXTI15" + }, + { + "signal": "EXTI2", + "interrupt": "EXTI2" + }, + { + "signal": "EXTI3", + "interrupt": "EXTI3" + }, + { + "signal": "EXTI4", + "interrupt": "EXTI4" + }, + { + "signal": "EXTI5", + "interrupt": "EXTI5" + }, + { + "signal": "EXTI6", + "interrupt": "EXTI6" + }, + { + "signal": "EXTI7", + "interrupt": "EXTI7" + }, + { + "signal": "EXTI8", + "interrupt": "EXTI8" + }, + { + "signal": "EXTI9", + "interrupt": "EXTI9" + } + ] + }, + { + "name": "FDCAN1", + "address": 1073782784, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE11", + "signal": "TX", + "af": 6 + }, + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FMC", + "address": 1208107008, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR3", + "field": "FMCSEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "FMCEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "FMCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "D7", + "af": 12 + }, + { + "pin": "PA0", + "signal": "DA7", + "af": 12 + }, + { + "pin": "PA1", + "signal": "D6", + "af": 12 + }, + { + "pin": "PA1", + "signal": "DA6", + "af": 12 + }, + { + "pin": "PA10", + "signal": "D2", + "af": 12 + }, + { + "pin": "PA10", + "signal": "DA2", + "af": 12 + }, + { + "pin": "PA11", + "signal": "D1", + "af": 12 + }, + { + "pin": "PA11", + "signal": "DA1", + "af": 12 + }, + { + "pin": "PA12", + "signal": "D0", + "af": 12 + }, + { + "pin": "PA12", + "signal": "DA0", + "af": 12 + }, + { + "pin": "PA15", + "signal": "D15", + "af": 12 + }, + { + "pin": "PA15", + "signal": "DA15", + "af": 12 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}, + { + "pin": "PG15", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PG2", + "signal": "A21", + "af": 12 + }, + { + "pin": "PG8", + "signal": "A20", + "af": 12 + }, + { + "pin": "PG9", + "signal": "D8", + "af": 12 + }, + { + "pin": "PG9", + "signal": "DA8", + "af": 12 + }, + { + "pin": "PH2", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D9", + "af": 14 + }, + { + "pin": "PH9", + "signal": "DA9", + "af": 14 + }, + { + "pin": "PN0", + "signal": "A25", + "af": 12 + }, + { + "pin": "PN1", + "signal": "A24", + "af": 12 + }, + { + "pin": "PN2", + "signal": "A23", + "af": 12 + }, + { + "pin": "PN3", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO0", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO1", + "signal": "A23", + "af": 12 + }, + { + "pin": "PO2", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO4", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO4", + "signal": "NBL2", + "af": 14 + }, + { + "pin": "PO5", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO5", + "signal": "NBL3", + "af": 14 + }, + { + "pin": "PP0", + "signal": "D16", + "af": 12 + }, + { + "pin": "PP1", + "signal": "D17", + "af": 12 + }, + { + "pin": "PP2", + "signal": "D18", + "af": 12 + }, + { + "pin": "PP3", + "signal": "D19", + "af": 12 + }, + { + "pin": "PP4", + "signal": "D20", + "af": 12 + }, + { + "pin": "PP5", + "signal": "D21", + "af": 12 + }, + { + "pin": "PP6", + "signal": "D22", + "af": 12 + }, + { + "pin": "PP7", + "signal": "D23", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE1", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PF1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PG14", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM1" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF1", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPTIM5", + "address": 1174417408, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM5EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM5RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE2", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PE3", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF0", + "signal": "OUT", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM5" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA7", + "signal": "B1", + "af": 14 + }, + { + "pin": "PA7", + "signal": "R4", + "af": 10 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PD9", + "signal": "R1", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF6", + "signal": "DE", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PF9", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PG0", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG0", + "signal": "VSYNC", + "af": 10 + }, + { + "pin": "PG1", + "signal": "G1", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG11", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG12", + "signal": "G0", + "af": 14 + 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"signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 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"signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { 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"PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, 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+ "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD5", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH3", + "af": 13 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PG5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG6", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF0", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PF1", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART2", + "address": 1073759232, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA1", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA2", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF2", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF2", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PF3", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF4", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG3", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG5", + "signal": "NSS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART2" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PH9", + "signal": "CK", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USART6", + "address": 1107301376, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART6EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART6RST" + } + }, + "pins": [ + { + "pin": "PC6", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PD3", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG14", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG6", + "signal": "CK", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + }, + { + "pin": "PO0", + "signal": "P1_NCS1", + "af": 9 + }, + { + "pin": "PO1", + "signal": "P1_NCS2", + "af": 9 + }, + { + "pin": "PO2", + "signal": "P1_DQS0", + "af": 9 + }, + { + "pin": "PO4", + "signal": "P1_CLK", + "af": 9 + }, + { + "pin": "PO5", + "signal": "P1_NCLK", + "af": 9 + }, + { + "pin": "PP0", + "signal": "P1_IO0", + "af": 9 + }, + { + "pin": "PP1", + "signal": "P1_IO1", + "af": 9 + }, + { + "pin": "PP2", + "signal": "P1_IO2", + "af": 9 + }, + { + "pin": "PP3", + "signal": "P1_IO3", + "af": 9 + }, + { + "pin": "PP4", + "signal": "P1_IO4", + "af": 9 + }, + { + "pin": "PP5", + "signal": "P1_IO5", + "af": 9 + }, + { + "pin": "PP6", + "signal": "P1_IO6", + "af": 9 + }, + { + "pin": "PP7", + "signal": "P1_IO7", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + { + "name": "EXTI2", + "number": 22 + }, + { + "name": "EXTI3", + "number": 23 + }, + { + "name": "EXTI4", + "number": 24 + }, + { + "name": "EXTI5", + "number": 25 + }, + { + "name": "EXTI6", + "number": 26 + }, + { + "name": "EXTI7", + "number": 27 + }, + { + "name": "EXTI8", + "number": 28 + }, + { + "name": "EXTI9", + "number": 29 + }, + { + "name": "EXTI10", + "number": 30 + }, + { + "name": "EXTI11", + "number": 31 + }, + { + "name": "EXTI12", + "number": 32 + }, + { + "name": "EXTI13", + "number": 33 + }, + { + "name": "EXTI14", + "number": 34 + }, + { + "name": "EXTI15", + "number": 35 + }, + { + "name": "PKA", + "number": 38 + }, + { + "name": "HASH", + "number": 39 + }, + { + "name": "RNG", + "number": 40 + }, + { + "name": "ADC1_2", + "number": 46 + }, + { + "name": "CSI", + "number": 47 + }, + { + "name": "DCMIPP", + "number": 48 + }, + { + "name": "PAHB_ERR", + "number": 52 + }, + { + "name": "NPU0", + "number": 53 + }, + { + "name": "NPU1", + "number": 54 + }, + { + "name": "NPU2", + "number": 55 + }, + { + "name": "NPU3", + "number": 56 + }, + { + "name": "CACHEAXI", + "number": 57 + }, + { + "name": "LTDC_LO", + "number": 58 + }, + { + "name": "LTDC_LO_ERR", + "number": 59 + }, + { + "name": "DMA2D", + "number": 60 + }, + { + "name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA3" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA7" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB3" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PC1" + }, + { + "name": "PC6" + }, + { + "name": "PC7" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD0" + }, + { + "name": "PD1" + }, + { + "name": "PD2" + }, + { + "name": "PD3" + }, + { + "name": "PD4" + }, + { + "name": "PD5" + }, + { + "name": "PD6" + }, + { + "name": "PD7" + }, + { + "name": "PD8" + }, + { + "name": "PD9" + }, + { + "name": "PD10" + }, + { + "name": "PD11" + }, + { + "name": "PD12" + }, + { + "name": "PD14" + }, + { + "name": "PD15" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE5" + }, + { + "name": "PE6" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": "PE9" + }, + { + "name": "PE10" + }, + { + "name": "PE11" + }, + { + "name": "PE12" + }, + { + "name": "PE13" + }, + { + "name": "PE14" + }, + { + "name": "PE15" + }, + { + "name": "PF0" + }, + { + "name": "PF1" + }, + { + "name": "PF2" + }, + { + "name": "PF3" + }, + { + "name": "PF4" + }, + { + "name": "PF5" + }, + { + "name": "PF6" + }, + { + "name": "PF7" + }, + { + "name": "PF8" + }, + { + "name": "PF9" + }, + { + "name": "PF10" + }, + { + "name": "PF11" + }, + { + "name": "PF12" + }, + { + "name": "PF13" + }, + { + "name": "PF14" + }, + { + "name": "PF15" + }, + { + "name": "PG0" + }, + { + "name": "PG1" + }, + { + "name": "PG2" + }, + { + "name": "PG3" + }, + { + "name": "PG4" + }, + { + "name": "PG5" + }, + { + "name": "PG6" + }, + { + "name": "PG8" + }, + { + "name": "PG9" + }, + { + "name": "PG10" + }, + { + "name": "PG11" + }, + { + "name": "PG12" + }, + { + "name": "PG13" + }, + { + "name": "PG14" + }, + { + "name": "PG15" + }, + { + "name": "PH0" + }, + { + "name": "PH1" + }, + { + "name": "PH2" + }, + { + "name": "PH9" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + }, + { + "name": "PO0" + }, + { + "name": "PO1" + }, + { + "name": "PO2" + }, + { + "name": "PO4" + }, + { + "name": "PO5" + }, + { + "name": "PP0" + }, + { + "name": "PP1" + }, + { + "name": "PP2" + }, + { + "name": "PP3" + }, + { + "name": "PP4" + }, + { + "name": "PP5" + }, + { + "name": "PP6" + }, + { + "name": "PP7" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N647I0.json b/data/chips/STM32N647I0.json new file mode 100644 index 0000000..b71326a --- /dev/null +++ b/data/chips/STM32N647I0.json @@ -0,0 +1,9642 @@ +{ + "name": "STM32N647I0", + "family": "STM32N6", + "line": "STM32N6x7", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N647I0HxQ", + "package": "VFBGA178", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PE6" + ] + }, + { + "position": "A11", + "signals": [ + "PD6" + ] + }, + { + "position": "A12", + "signals": [ + "PD0" + ] + }, + { + "position": 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"DA6", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A1", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A17", + "af": 14 + }, + { + "pin": "PD6", + "signal": "ALE", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A18", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A2", + "af": 12 + }, + { + "pin": "PD8", + "signal": "NBL0", + "af": 12 + }, + { + "pin": "PD9", + "signal": "SDCLK", + "af": 12 + }, + { + "pin": "PE0", + "signal": "D9", + "af": 12 + }, + { + "pin": "PE0", + "signal": "DA9", + "af": 12 + }, + { + "pin": "PE1", + "signal": "D10", + "af": 12 + }, + { + "pin": "PE1", + "signal": "DA10", + "af": 12 + }, + { + "pin": "PE10", + "signal": "A15", + "af": 12 + }, + { + "pin": "PE10", + "signal": "BA1", + "af": 12 + }, + { + "pin": "PE11", + "signal": "SDNWE", + "af": 12 + }, + { + "pin": "PE12", + "signal": "SDNRAS", + "af": 12 + }, + { + "pin": "PE13", + "signal": "SDNCAS", + "af": 12 + }, + { + "pin": "PE14", + "signal": "NWE", + "af": 14 + }, + { + "pin": "PE14", + "signal": "SDNE0", + "af": 12 + }, + { + "pin": "PE15", + "signal": "SDCKE0", + "af": 12 + }, + { + "pin": "PE2", + "signal": "D11", + "af": 12 + }, + { + "pin": "PE2", + "signal": "DA11", + "af": 12 + }, + { + "pin": "PE3", + "signal": "D12", + "af": 12 + }, + { + "pin": "PE3", + "signal": "DA12", + "af": 12 + }, + { + "pin": "PE5", + "signal": "SDNE1", + "af": 12 + }, + { + "pin": "PE6", + "signal": "SDCKE1", + "af": 12 + }, + { + "pin": "PE7", + "signal": "A20", + "af": 14 + }, + { + "pin": "PE7", + "signal": "A4", + "af": 12 + }, + { + "pin": "PE8", + "signal": "A12", + "af": 12 + }, + { + "pin": "PE9", + "signal": "A14", + "af": 12 + }, + { + "pin": "PE9", + "signal": "BA0", + "af": 12 + }, + { + "pin": "PF2", + "signal": "NWAIT", + "af": 12 + }, + { + "pin": "PF3", + "signal": "NL", + "af": 12 + }, + { + "pin": "PF5", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PF8", + "signal": "NWE", + "af": 12 + }, + { + "pin": "PG1", + "signal": "A19", + "af": 12 + }, + { + "pin": "PG10", + "signal": "A16", + "af": 12 + }, + { + "pin": "PG10", + "signal": "CLE", + "af": 12 + }, + { + "pin": "PG12", + "signal": "A18", + "af": 12 + }, + { + "pin": "PG13", + "signal": "NE1", + "af": 12 + }, + { + "pin": "PG14", + "signal": "NCE", + "af": 10 + }, + { + "pin": "PG14", + "signal": "NE2", + "af": 12 + }, + { + "pin": "PG15", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PG2", + "signal": "A21", + "af": 12 + }, + { + "pin": "PG8", + "signal": "A20", + "af": 12 + }, + { + "pin": "PH2", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D9", + "af": 14 + }, + { + "pin": "PH9", + "signal": "DA9", + "af": 14 + }, + { + "pin": "PN0", + "signal": "A25", + "af": 12 + }, + { + "pin": "PN1", + "signal": "A24", + "af": 12 + }, + { + "pin": "PN2", + "signal": "A23", + "af": 12 + }, + { + "pin": "PN3", + "signal": "A22", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA7", + "signal": "B1", + "af": 14 + }, + { + "pin": "PA7", + "signal": "R4", + "af": 10 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB2", + "signal": "B2", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD13", + "signal": "R6", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PD9", + "signal": "R1", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF6", + "signal": "DE", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG0", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG0", + "signal": "VSYNC", + "af": 10 + }, + { + "pin": "PG1", + "signal": "G1", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG12", + "signal": "G0", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG15", + "signal": "B0", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG8", + "signal": "G7", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC6", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC7", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "DE", + "af": 9 + }, + { + "pin": "PD11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD13", + "signal": "D13", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD5", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PD9", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE6", + "signal": "D1", + "af": 10 + }, + { + "pin": "PE6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG1", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG15", + "signal": "D4", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PH9", + "signal": "D6", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD13", + "signal": "SCK_A", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB2", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB2", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB2", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD5", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH3", + "af": 13 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD13", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART2", + "address": 1073759232, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA1", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA2", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF2", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF2", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PF3", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF4", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART2" + } + ] + }, + { + "name": "USART3", + "address": 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"TX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": 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"name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": 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"pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB9", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PD13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE1", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PF1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PG14", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM1" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF1", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPTIM5", + "address": 1174417408, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM5EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM5RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE2", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PE3", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF0", + "signal": "OUT", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM5" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA7", + "signal": "B1", + "af": 14 + }, + { + "pin": "PA7", + "signal": "R4", + "af": 10 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB1", + "signal": "R1", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB13", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PB14", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PB15", + "signal": "G4", + "af": 14 + }, + { + "pin": "PB2", + "signal": "B2", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD13", + "signal": "R6", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PD9", + "signal": "R1", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF6", + "signal": "DE", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PF9", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PG0", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG0", + "signal": "VSYNC", + "af": 10 + }, + { + "pin": "PG1", + "signal": "G1", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG11", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG12", + "signal": "G0", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG15", + "signal": "B0", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG4", + "signal": "B0", + "af": 14 + }, + { + "pin": "PG5", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG6", + "signal": "B3", + "af": 14 + }, + { + "pin": "PG8", + "signal": "G7", + "af": 14 + }, + { + "pin": "PG9", + "signal": "R7", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + }, + { + "pin": "PO2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PO3", + "signal": "G3", + "af": 14 + }, + { + "pin": "PO4", + "signal": "B4", + "af": 10 + }, + { + "pin": "PP15", + "signal": "B5", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA4", + "signal": "D3", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + 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"address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PB8", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD13", + "signal": "SCK_A", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, 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+ }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SDMMC2", + "address": 1208117248, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC2SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC2EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CMD", + "af": 11 + }, + { + "pin": "PB13", + "signal": "D6", + "af": 11 + }, + { + "pin": "PB4", + "signal": "D3", + "af": 11 + }, + { + "pin": "PB8", + "signal": "D0", + "af": 11 + }, + { + "pin": "PB9", + "signal": "D2", + "af": 11 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 11 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 11 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 11 + }, + { + "pin": "PD2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PD5", + "signal": "D7", + "af": 11 + }, + { + "pin": "PG8", + "signal": "D1", + "af": 11 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC2" + } + ] + }, + { + "name": "SPDIFRX1", + "address": 1073758208, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPDIFRX1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPDIFRX1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPDIFRX1RST" + } + }, + "pins": [ + { + "pin": "PB15", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PB8", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PB9", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PD10", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PD12", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PD8", + "signal": "IN1", + "af": 8 + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + 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}, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB2", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB2", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA4", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB13", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB13", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB1", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB2", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", 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"TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG6", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PB1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD13", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF0", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PF1", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART10", + "address": 1107303424, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART10EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART10RST" + } + }, + "pins": [ + { + "pin": "PB13", + "signal": "CTS", + "af": 6 + }, + { + "pin": "PB13", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB14", + "signal": "CK", + "af": 6 + }, + { + "pin": "PB9", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD14", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD15", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD3", + "signal": "RX", + "af": 6 + }, + { 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1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + 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"name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA3" + }, + { + "name": "PA4" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA7" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB1" + }, + { + "name": "PB2" + }, + { + "name": "PB3" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB8" + }, + { + "name": "PB9" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PB13" + }, + { + "name": "PB14" + }, + { + "name": "PB15" + }, + { + "name": "PC1" + }, + { + "name": "PC6" + }, + { + "name": "PC7" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD0" + }, + { + "name": "PD1" + }, + { + "name": "PD2" + }, + { + "name": "PD3" + }, + { + "name": "PD4" + }, + { + "name": "PD5" + }, + { + "name": "PD6" + }, + { + "name": "PD7" + }, + { + "name": "PD8" + }, + { + "name": "PD9" + }, + { + "name": "PD10" + }, + { + "name": "PD11" + }, + { + "name": "PD12" + }, + { + "name": "PD13" + }, + { + "name": "PD14" + }, + { + "name": "PD15" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE5" + }, + { + "name": "PE6" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": "PE9" + }, + { + "name": "PE10" + }, + { + "name": "PE11" + }, + { + "name": "PE12" + }, + { + "name": "PE13" + }, + { + "name": "PE14" + }, + { + "name": "PE15" + }, + { + "name": "PF0" + }, + { + "name": "PF1" + }, + { + "name": "PF2" + }, + { + "name": "PF3" + }, + { + "name": "PF4" + }, + { + "name": "PF5" + }, + { + "name": "PF6" + }, + { + "name": "PF7" + }, + { + "name": "PF8" + }, + { + "name": "PF9" + }, + { + "name": "PF10" + }, + { + "name": "PF11" + }, + { + "name": "PF12" + }, + { + "name": "PF13" + }, + { + "name": "PF14" + }, + { + "name": "PF15" + }, + { + "name": "PG0" + }, + { + "name": "PG1" + }, + { + "name": "PG2" + }, + { + "name": "PG3" + }, + { + "name": "PG4" + }, + { + "name": "PG5" + }, + { + "name": "PG6" + }, + { + "name": "PG8" + }, + { + "name": "PG9" + }, + { + "name": "PG10" + }, + { + "name": "PG11" + }, + { + "name": "PG12" + }, + { + "name": "PG13" + }, + { + "name": "PG14" + }, + { + "name": "PG15" + }, + { + "name": "PH0" + }, + { + "name": "PH1" + }, + { + "name": "PH2" + }, + { + "name": "PH9" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + }, + { + "name": "PO0" + }, + { + "name": "PO1" + }, + { + "name": "PO2" + }, + { + "name": "PO3" + }, + { + "name": "PO4" + }, + { + "name": "PO5" + }, + { + "name": "PP0" + }, + { + "name": "PP1" + }, + { + "name": "PP2" + }, + { + "name": "PP3" + }, + { + "name": "PP4" + }, + { + "name": "PP5" + }, + { + "name": "PP6" + }, + { + "name": "PP7" + }, + { + "name": "PP8" + }, + { + "name": "PP9" + }, + { + "name": "PP10" + }, + { + "name": "PP11" + }, + { + "name": "PP12" + }, + { + "name": "PP13" + }, + { + "name": "PP14" + }, + { + "name": "PP15" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N647X0.json b/data/chips/STM32N647X0.json new file mode 100644 index 0000000..48e3d18 --- /dev/null +++ b/data/chips/STM32N647X0.json @@ -0,0 +1,12057 @@ +{ + "name": "STM32N647X0", + "family": "STM32N6", + "line": "STM32N6x7", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N647X0HxQ", + "package": "VFBGA264", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PC4" + ] + }, + { + "position": "A11", + "signals": [ + "PE13" + ] + }, + { + "position": "A12", + "signals": [ + "PE15" + ] + }, + { + "position": "A13", + "signals": [ + "PD10" + ] + }, + { + "position": "A14", + "signals": [ + "PD1" + ] + }, + { + "position": "A15", + "signals": [ + "PE8" + ] + }, + { + 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{ + "pin": "PH9", + "signal": "DA9", + "af": 14 + }, + { + "pin": "PN0", + "signal": "A25", + "af": 12 + }, + { + "pin": "PN1", + "signal": "A24", + "af": 12 + }, + { + "pin": "PN2", + "signal": "A23", + "af": 12 + }, + { + "pin": "PN3", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO0", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO1", + "signal": "A23", + "af": 12 + }, + { + "pin": "PO2", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO3", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO4", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO4", + "signal": "NBL2", + "af": 14 + }, + { + "pin": "PO5", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO5", + "signal": "NBL3", + "af": 14 + }, + { + "pin": "PP0", + "signal": "D16", + "af": 12 + }, + { + "pin": "PP1", + "signal": "D17", + "af": 12 + }, + { + "pin": "PP10", + "signal": "D26", + "af": 12 + }, + { + "pin": "PP11", + "signal": "D27", + "af": 12 + }, + { + "pin": "PP12", + "signal": "D28", + "af": 12 + }, + { + "pin": "PP13", + "signal": "D29", + "af": 12 + }, + { + "pin": "PP14", + "signal": "D30", + "af": 12 + }, + { + "pin": "PP15", + "signal": "D31", + "af": 12 + }, + { + "pin": "PP2", + "signal": "D18", + "af": 12 + }, + { + "pin": "PP3", + "signal": "D19", + "af": 12 + }, + { + "pin": "PP4", + "signal": "D20", + "af": 12 + }, + { + "pin": "PP5", + "signal": "D21", + "af": 12 + }, + { + "pin": "PP6", + "signal": "D22", + "af": 12 + }, + { + "pin": "PP7", + "signal": "D23", + "af": 12 + }, + { + "pin": "PP8", + "signal": "D24", + "af": 12 + }, + { + "pin": "PP9", + "signal": "D25", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PH7", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PH8", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB9", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PD13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE1", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PE4", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PF1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PG14", + "signal": "ETR", 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"LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPTIM4", + "address": 1174416384, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM4RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB4", + "signal": "ETR", + "af": 3 + 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"signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA4", + "signal": "D3", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB14", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB4", + 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"pin": "PH9", + "signal": "D6", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PC2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PC2", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG7", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PB8", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PC5", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD13", + "signal": "SCK_A", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PQ2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PQ5", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PQ6", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PQ7", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SDMMC2", + "address": 1208117248, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC2SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC2EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CMD", + "af": 11 + }, + { + "pin": "PB13", + "signal": "D6", + "af": 11 + }, + { + "pin": "PB4", + "signal": "D3", + "af": 11 + }, + { + "pin": "PB8", + "signal": "D0", + "af": 11 + }, + { + "pin": "PB9", + "signal": "D2", + "af": 11 + }, + { + "pin": "PC0", + "signal": "D2", + "af": 11 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 11 + }, + { + "pin": "PC2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PC3", + "signal": "CMD", + "af": 11 + }, + { + "pin": "PC4", + "signal": "D0", + "af": 11 + }, + { + "pin": "PC5", + "signal": "D1", + "af": 11 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 11 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 11 + }, + { + "pin": "PD2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PD5", + "signal": "D7", + "af": 11 + }, + { + "pin": "PE4", + "signal": "D3", + "af": 11 + }, + { + "pin": "PG8", + "signal": "D1", + "af": 11 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC2" + } + ] + }, + { + "name": "SPDIFRX1", + "address": 1073758208, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPDIFRX1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPDIFRX1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPDIFRX1RST" + } + }, + "pins": [ + { + "pin": "PB15", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PB8", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PB9", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PC3", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PD10", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PD12", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PD8", + "signal": "IN1", + "af": 8 + }, + { + "pin": "PE4", + "signal": "IN1", + "af": 8 + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PC0", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC0", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PC3", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PC3", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PC5", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC5", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PC4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PP8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PP9", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB2", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB2", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC0", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC0", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PC2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA4", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PH5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PH6", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PH7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PH8", + "signal": "MISO", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB13", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB13", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC0", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PC0", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PE4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + }, + { + "pin": "PH4", + "signal": "IN4" + }, + { + "pin": "PH4", + "signal": "OUT3" + }, + { + "pin": "PQ7", + "signal": "IN2" + }, + { + "pin": "PQ7", + "signal": "OUT1" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB1", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB2", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC4", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD5", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH3", + "af": 13 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PG5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PC4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG6", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC0", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM8", + "address": 1107297280, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM8EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM8RST" + } + }, + "pins": [ + { + "pin": "PB13", + "signal": "CH3N", + "af": 2 + }, + { + "pin": "PB14", + "signal": "CH4N", + "af": 2 + }, + { + "pin": "PG14", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PQ0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PQ1", + "signal": "BKIN", + "af": 2 + }, + { + "pin": "PQ2", + "signal": "BKIN2", + "af": 2 + }, + { + "pin": "PQ3", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PQ4", + "signal": "CH1N", + "af": 2 + }, + { + "pin": "PQ5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PQ6", + "signal": "CH2N", + "af": 2 + }, + { + "pin": "PQ7", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM8_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM8_CC" + }, + { + "signal": "COM", + "interrupt": "TIM8_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM8_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM8_UP" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PB1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PC4", + "signal": "DE", + "af": 8 + }, + { + "pin": "PC4", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PC0", + "signal": "RX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH3", + "signal": "TX", + "af": 8 + }, + { + "pin": "PH4", + "signal": "TX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD13", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF0", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PF1", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC4", + "signal": "TX", + "af": 4 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART10", + "address": 1107303424, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART10EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART10RST" + } + }, + "pins": [ + { + "pin": "PB13", + "signal": "CTS", + "af": 6 + }, + { + "pin": "PB13", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB14", + "signal": "CK", + "af": 6 + }, + { + "pin": "PB9", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD14", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD15", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD3", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 6 + }, + { + "pin": "PE4", + "signal": "RX", + "af": 6 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART10" + } + ] + }, + { + "name": "USART2", + "address": 1073759232, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA1", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA2", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC2", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF2", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF2", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PF3", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF4", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG3", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG5", + "signal": "NSS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART2" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 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+ "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USART6", + "address": 1107301376, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART6EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART6RST" + } + }, + "pins": [ + { + "pin": "PA4", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB13", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PB13", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PB14", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PB14", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PB15", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PB8", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC6", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PD3", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD4", + "signal": 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"APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": 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"name": "PA6" + }, + { + "name": "PA7" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB1" + }, + { + "name": "PB2" + }, + { + "name": "PB3" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB8" + }, + { + "name": "PB9" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PB13" + }, + { + "name": "PB14" + }, + { + "name": "PB15" + }, + { + "name": "PC0" + }, + { + "name": "PC1" + }, + { + "name": "PC2" + }, + { + "name": "PC3" + }, + { + "name": "PC4" + }, + { + "name": "PC5" + }, + { + "name": "PC6" + }, + { + "name": "PC7" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": 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"af": 3 + }, + { + "pin": "PE14", + "signal": "CCK1", + "af": 3 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "ADF1_FLT0" + } + ] + }, + { + "name": "BSEC", + "address": 1174441984, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "BSECEN" + } + } + }, + { + "name": "CACHEAXI", + "address": 1208876032 + }, + { + "name": "CRC", + "address": 1174555648, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "CRCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "CRCRST" + } + } + }, + { + "name": "CSI", + "address": 1207984128, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "CSIEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "CSIRST" + } + } + }, + { + "name": "DBGMCU", + "address": 1140854784 + }, + { + "name": "DCMI", + "address": 1208124416, + "registers": { + "kind": "dcmi", + "version": "v1", + "block": "DCMI" + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PIXCLK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "VSYNC", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF4", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "DCMIPP", + "address": 1207967744, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR1", + "field": "DCMIPPSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "DCMIPPEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "DCMIPPRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PIXCLK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "VSYNC", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF4", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "CSI", + "interrupt": "CSI" + } + ] + }, + { + "name": "DMA2D", + "address": 1208094720, + "registers": { + "kind": "dma2d", + "version": "v1", + "block": "DMA2D" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "DMA2DEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "DMA2DRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DMA2D" + } + ] + }, + { + "name": "DTS", + "address": 1174446080, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "DTSEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "DTSRST" + } + } + }, + { + "name": "EXTI", + "address": 1174556672, + "registers": { + "kind": "exti", + "version": "v1", + "block": "EXTI" + }, + "interrupts": [ + { + "signal": "EXTI0", + "interrupt": "EXTI0" + }, + { + "signal": "EXTI1", + "interrupt": "EXTI1" + }, + { + "signal": "EXTI10", + "interrupt": "EXTI10" + }, + { + "signal": "EXTI11", + "interrupt": "EXTI11" + }, + { + "signal": "EXTI12", + "interrupt": "EXTI12" + }, + { + "signal": "EXTI13", + "interrupt": "EXTI13" + }, + { + "signal": "EXTI14", + "interrupt": "EXTI14" + }, + { + "signal": "EXTI15", + "interrupt": "EXTI15" + }, + { + "signal": "EXTI2", + "interrupt": "EXTI2" + }, + { + "signal": "EXTI3", + "interrupt": "EXTI3" + }, + { + "signal": "EXTI4", + "interrupt": "EXTI4" + }, + { + "signal": "EXTI5", + "interrupt": "EXTI5" + }, + { + "signal": "EXTI6", + "interrupt": "EXTI6" + }, + { + "signal": "EXTI7", + "interrupt": "EXTI7" + }, + { + "signal": "EXTI8", + "interrupt": "EXTI8" + }, + { + "signal": "EXTI9", + "interrupt": "EXTI9" + } + ] + }, + { + "name": "FDCAN1", + "address": 1073782784, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + { + "name": "EXTI2", + "number": 22 + }, + { + "name": "EXTI3", + "number": 23 + }, + { + "name": "EXTI4", + "number": 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"HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": 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"signal": "INN4" + }, + { + "pin": "PB10", + "signal": "INP8" + }, + { + "pin": "PB11", + "signal": "INP4" + }, + { + "pin": "PF13", + "signal": "INP2" + }, + { + "pin": "PF14", + "signal": "INN2" + }, + { + "pin": "PF14", + "signal": "INP6" + }, + { + "pin": "PF7", + "signal": "INN5" + }, + { + "pin": "PF7", + "signal": "INP9" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ADC1_2" + } + ] + }, + { + "name": "ADF1", + "address": 1107451904, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ADF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "ADF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "ADF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI0", + "af": 3 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 3 + }, + { + "pin": "PB7", + "signal": "SDI0", + "af": 3 + }, + { + "pin": "PD2", + "signal": "SDI0", + "af": 3 + }, + { + "pin": "PE13", + "signal": "CCK0", + "af": 3 + }, + { + "pin": "PE14", + "signal": "CCK1", + "af": 3 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "ADF1_FLT0" + } + ] + }, + { + "name": "BSEC", + "address": 1174441984, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "BSECEN" + } + } + }, + { + "name": "CRC", + "address": 1174555648, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "CRCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "CRCRST" + } + } + }, + { + "name": "CRYP", + "address": 1140983808, + "registers": { + "kind": "cryp", + "version": "v2", + "block": "CRYP" + }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "CRYPEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "CRYPRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "CRYP" + } + ] + }, + { + "name": "CSI", + "address": 1207984128, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "CSIEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "CSIRST" + } + } + }, + { + "name": "DBGMCU", + "address": 1140854784 + }, + { + "name": "DCMI", + "address": 1208124416, + "registers": { + "kind": "dcmi", + "version": "v1", + "block": "DCMI" + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PIXCLK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "VSYNC", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF4", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "DCMIPP", + "address": 1207967744, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR1", + "field": "DCMIPPSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "DCMIPPEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "DCMIPPRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PIXCLK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "VSYNC", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PD11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF4", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "CSI", + "interrupt": "CSI" + } + ] + }, + { + "name": "DMA2D", + "address": 1208094720, + "registers": { + "kind": "dma2d", + "version": "v1", + "block": "DMA2D" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "DMA2DEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "DMA2DRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DMA2D" + } + ] + }, + { + "name": "DTS", + "address": 1174446080, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "DTSEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "DTSRST" + } + } + }, + { + "name": "ETH1", + "address": 1208180736, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "ETH1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "ETH1RST" + } + }, + "pins": [ + { + "pin": "PD1", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD12", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PD3", + "signal": "PHY_INTN", + "af": 11 + }, + { + "pin": "PF10", + "signal": "CRS_DV", + "af": 11 + }, + { + "pin": "PF10", + "signal": "RGMII_RX_CTL", + "af": 11 + }, + { + "pin": "PF10", + "signal": "RX_DV", + "af": 11 + }, + { + "pin": "PF11", + "signal": "RGMII_TX_CTL", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TX_EN", + "af": 11 + }, + { + "pin": "PF12", + "signal": "RGMII_TXD0", + "af": 11 + }, + { + "pin": "PF12", + "signal": "TXD0", + "af": 11 + }, + { + "pin": "PF13", + "signal": "RGMII_TXD1", + "af": 11 + }, + { + "pin": "PF13", + "signal": "TXD1", + "af": 11 + }, + { + "pin": "PF14", + "signal": "RGMII_RXD0", + "af": 11 + }, + { + "pin": "PF14", + "signal": "RXD0", + "af": 11 + }, + { + "pin": "PF15", + "signal": "RGMII_RXD1", + "af": 11 + }, + { + "pin": "PF15", + "signal": "RXD1", + "af": 11 + }, + { + "pin": "PF2", + "signal": "RGMII_CLK125", + "af": 11 + }, + { + "pin": "PF3", + "signal": "PPS_OUT", + "af": 11 + }, + { + "pin": "PF4", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PF5", + "signal": "CLK", + "af": 11 + }, + { + "pin": "PF7", + "signal": "REF_CLK", + "af": 11 + }, + { + "pin": "PF7", + "signal": "RGMII_RX_CLK", + "af": 11 + }, + { + "pin": "PF7", + "signal": "RX_CLK", + "af": 11 + }, + { + "pin": "PF8", + "signal": "RGMII_RXD2", + "af": 11 + }, + { + "pin": "PF8", + "signal": "RXD2", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ETH1" + }, + { + "signal": "WKUP", + "interrupt": "ETH1" + } + ] + }, + { + "name": "EXTI", + "address": 1174556672, + "registers": { + "kind": "exti", + "version": "v1", + "block": "EXTI" + }, + "interrupts": [ + { + "signal": "EXTI0", + "interrupt": "EXTI0" + }, + { + "signal": "EXTI1", + "interrupt": "EXTI1" + }, + { + "signal": "EXTI10", + "interrupt": "EXTI10" + }, + { + "signal": "EXTI11", + "interrupt": "EXTI11" + }, + { + "signal": "EXTI12", + "interrupt": "EXTI12" + }, + { + "signal": "EXTI13", + "interrupt": "EXTI13" + }, + { + "signal": "EXTI14", + "interrupt": "EXTI14" + }, + { + "signal": "EXTI15", + "interrupt": "EXTI15" + }, + { + "signal": "EXTI2", + "interrupt": "EXTI2" + }, + { + "signal": "EXTI3", + "interrupt": "EXTI3" + }, + { + "signal": "EXTI4", + "interrupt": "EXTI4" + }, + { + "signal": "EXTI5", + "interrupt": "EXTI5" + }, + { + "signal": "EXTI6", + "interrupt": "EXTI6" + }, + { + "signal": "EXTI7", + "interrupt": "EXTI7" + }, + { + "signal": "EXTI8", + "interrupt": "EXTI8" + }, + { + "signal": "EXTI9", + "interrupt": "EXTI9" + } + ] + }, + { + "name": "FDCAN1", + "address": 1073782784, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE11", + "signal": "TX", + "af": 6 + }, + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MCE1", + "address": 1208137728, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE1EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE1" + } + ] + }, + { + "name": "MCE2", + "address": 1208138752, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE2EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE2" + } + ] + }, + { + "name": "MCE3", + "address": 1208139776, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE3EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE3" + } + ] + }, + { + "name": "MCE4", + "address": 1208147968, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE4EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "MCE4RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE4" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PKA", + "address": 1140989952, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "PKAEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "PKARST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "PKA" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "DE", + "af": 9 + }, + { + "pin": "PD11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { 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+ }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USART6", + "address": 1107301376, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART6EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART6RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PD3", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG14", + "signal": "TX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": 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"number": 45 + }, + { + "name": "ADC1_2", + "number": 46 + }, + { + "name": "CSI", + "number": 47 + }, + { + "name": "DCMIPP", + "number": 48 + }, + { + "name": "PAHB_ERR", + "number": 52 + }, + { + "name": "LTDC_LO", + "number": 58 + }, + { + "name": "LTDC_LO_ERR", + "number": 59 + }, + { + "name": "DMA2D", + "number": 60 + }, + { + "name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA3" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB3" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD0" + }, + { + "name": "PD1" + }, + { + "name": "PD2" + }, + { + "name": "PD3" + }, + { + "name": "PD4" + }, + { + "name": "PD6" + }, + { + "name": "PD7" + }, + { + "name": "PD8" + }, + { + "name": "PD10" + }, + { + "name": "PD11" + }, + { + "name": "PD12" + }, + { + "name": "PD14" + }, + { + "name": "PD15" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE5" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": "PE9" + }, + { + "name": "PE10" + }, + { + "name": "PE11" + }, + { + "name": "PE12" + }, + { + "name": "PE13" + }, + { + "name": "PE14" + }, + { + "name": "PE15" + }, + { + "name": "PF2" + }, + { + "name": "PF3" + }, + { + "name": "PF4" + }, + { + "name": "PF5" + }, + { + "name": "PF7" + }, + { + "name": "PF8" + }, + { + "name": "PF10" + }, + { + "name": "PF11" + }, + { + "name": "PF12" + }, + { + "name": "PF13" + }, + { + "name": "PF14" + }, + { + "name": "PF15" + }, + { + "name": "PG2" + }, + { + "name": "PG10" + }, + { + "name": "PG13" + }, + { + "name": "PG14" + }, + { + "name": "PH0" + }, + { + "name": "PH1" + }, + { + "name": "PH2" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N655B0.json b/data/chips/STM32N655B0.json new file mode 100644 index 0000000..8793719 --- /dev/null +++ b/data/chips/STM32N655B0.json @@ -0,0 +1,10377 @@ +{ + "name": "STM32N655B0", + "family": "STM32N6", + "line": "STM32N6x5", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N655B0HxQ", + "package": "VFBGA198", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PD6" + ] + }, + { + "position": "A11", + "signals": [ + "PD12" + ] + }, + { + "position": "A12", + "signals": [ + "PD3" + ] + }, + { + "position": "A13", + "signals": [ + "PE10" + ] + }, + { + "position": "A14", + "signals": [ + "PB3" + ] + }, + { + "position": "A15", + "signals": [ + "VSS" + ] + }, + { + "position": "A2", + "signals": [ + "OTG2_HSDP" + ] + }, + { + "position": "A3", + "signals": [] + }, + { + "position": "A4", + "signals": [ + "OTG1_HSDP" + ] + }, + { + "position": "A5", + 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"field": "CRCRST" + } + } + }, + { + "name": "CRYP", + "address": 1140983808, + "registers": { + "kind": "cryp", + "version": "v2", + "block": "CRYP" + }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "CRYPEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "CRYPRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "CRYP" + } + ] + }, + { + "name": "CSI", + "address": 1207984128, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "CSIEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "CSIRST" + } + } + }, + { + "name": "DBGMCU", + "address": 1140854784 + }, + { + "name": "DCMI", + "address": 1208124416, + "registers": { + "kind": "dcmi", + "version": "v1", + "block": "DCMI" + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": 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"interrupt": "CSI" + } + ] + }, + { + "name": "DMA2D", + "address": 1208094720, + "registers": { + "kind": "dma2d", + "version": "v1", + "block": "DMA2D" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "DMA2DEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "DMA2DRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DMA2D" + } + ] + }, + { + "name": "DTS", + "address": 1174446080, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "DTSEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "DTSRST" + } + } + }, + { + "name": "ETH1", + "address": 1208180736, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "ETH1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "ETH1RST" + } + }, + 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+ }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE11", + "signal": "TX", + "af": 6 + }, + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FMC", + "address": 1208107008, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR3", + "field": "FMCSEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "FMCEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "FMCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "D7", + "af": 12 + }, + { + "pin": "PA0", + "signal": "DA7", + "af": 12 + }, + { + "pin": "PA1", + "signal": "D6", + "af": 12 + }, + { + "pin": "PA1", + "signal": "DA6", + "af": 12 + }, + { + "pin": "PA10", + "signal": "D2", + "af": 12 + }, + { + "pin": "PA10", + "signal": "DA2", + "af": 12 + }, + { + "pin": "PA11", + "signal": "D1", + "af": 12 + }, + { + "pin": "PA11", + "signal": "DA1", + "af": 12 + }, + { + "pin": "PA12", + "signal": "D0", + "af": 12 + }, + { + "pin": "PA12", + "signal": "DA0", + "af": 12 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}, + { + "pin": "PB12", + "signal": "DA9", + "af": 12 + }, + { + "pin": "PB3", + "signal": "A23", + "af": 14 + }, + { + "pin": "PB3", + "signal": "NBL1", + "af": 12 + }, + { + "pin": "PB4", + "signal": "D13", + "af": 12 + }, + { + "pin": "PB4", + "signal": "DA13", + "af": 12 + }, + { + "pin": "PB5", + "signal": "D12", + "af": 12 + }, + { + "pin": "PB5", + "signal": "DA12", + "af": 12 + }, + { + "pin": "PB6", + "signal": "D14", + "af": 12 + }, + { + "pin": "PB6", + "signal": "DA14", + "af": 12 + }, + { + "pin": "PB7", + "signal": "D15", + "af": 12 + }, + { + "pin": "PB7", + "signal": "DA15", + "af": 12 + }, + { + "pin": "PC10", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PC12", + "signal": "NL", + "af": 12 + }, + { + "pin": "PC8", + "signal": "NE4", + "af": 12 + }, + { + "pin": "PD0", + "signal": "A22", + "af": 14 + }, + { + "pin": "PD0", + "signal": "A6", + "af": 12 + }, + { + "pin": "PD1", + "signal": "A23", + "af": 14 + }, + { + "pin": "PD1", + "signal": "A7", + "af": 12 + }, + { + "pin": "PD10", + "signal": "A19", + "af": 14 + }, + { + "pin": "PD10", + "signal": "A3", + "af": 12 + }, + { + "pin": "PD11", + "signal": "D8", + "af": 12 + }, + { + "pin": "PD11", + "signal": "DA8", + "af": 12 + }, + { + "pin": "PD12", + "signal": "A21", + "af": 14 + }, + { + "pin": "PD12", + "signal": "A5", + "af": 12 + }, + { + "pin": "PD14", + "signal": "A9", + "af": 12 + }, + { + "pin": "PD15", + "signal": "A8", + "af": 12 + }, + { + "pin": "PD2", + "signal": "A0", + "af": 12 + }, + { + "pin": "PD2", + "signal": "A16", + "af": 14 + }, + { + "pin": "PD2", + "signal": "CLE", + "af": 14 + }, + { + "pin": "PD3", + "signal": "A10", + "af": 12 + }, + { + "pin": "PD4", + "signal": "A11", + "af": 12 + }, + { + "pin": "PD5", + "signal": "D6", + "af": 12 + }, + { + "pin": "PD5", + "signal": "DA6", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A1", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A17", + "af": 14 + }, + { + "pin": "PD6", + "signal": "ALE", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A18", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A2", + "af": 12 + }, + { + "pin": "PD8", + "signal": "NBL0", + "af": 12 + }, + { + "pin": "PD9", + "signal": "SDCLK", + "af": 12 + }, + { + "pin": "PE0", + "signal": "D9", + "af": 12 + }, + { + "pin": "PE0", + "signal": "DA9", + "af": 12 + }, + { + "pin": "PE1", + "signal": "D10", + "af": 12 + }, + { + "pin": "PE1", + "signal": "DA10", + "af": 12 + }, + { + "pin": "PE10", + "signal": "A15", + "af": 12 + }, + { + "pin": "PE10", + "signal": "BA1", + "af": 12 + }, + { + "pin": "PE11", + "signal": "SDNWE", + "af": 12 + }, + { + "pin": "PE12", + "signal": "SDNRAS", + "af": 12 + }, + { + "pin": "PE13", + "signal": "SDNCAS", + "af": 12 + }, + { + "pin": "PE14", + "signal": "NWE", + "af": 14 + }, + { + "pin": "PE14", + "signal": "SDNE0", + "af": 12 + }, + { + "pin": "PE15", + "signal": "SDCKE0", + "af": 12 + }, + { + "pin": "PE2", + "signal": "D11", + "af": 12 + }, + { + "pin": "PE2", + "signal": "DA11", + "af": 12 + }, + { + "pin": "PE3", + "signal": "D12", + "af": 12 + }, + { + "pin": "PE3", + "signal": "DA12", + "af": 12 + }, + { + "pin": "PE5", + "signal": "SDNE1", + "af": 12 + }, + { + "pin": "PE6", + "signal": "SDCKE1", + "af": 12 + }, + { + "pin": "PE7", + "signal": "A20", + "af": 14 + }, + { + "pin": "PE7", + "signal": "A4", + "af": 12 + }, + { + "pin": "PE8", + "signal": "A12", + "af": 12 + }, + { + "pin": "PE9", + "signal": "A14", + "af": 12 + }, + { + "pin": "PE9", + "signal": "BA0", + "af": 12 + }, + { + "pin": "PF2", + "signal": "NWAIT", + "af": 12 + }, + { + "pin": "PF3", + "signal": "NL", + "af": 12 + }, + { + "pin": "PF5", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PF8", + "signal": "NWE", + "af": 12 + }, + { + "pin": "PG1", + "signal": "A19", + "af": 12 + }, + { + "pin": "PG10", + "signal": "A16", + "af": 12 + }, + { + "pin": "PG10", + "signal": "CLE", + "af": 12 + }, + { + "pin": "PG12", + "signal": "A18", + "af": 12 + }, + { + "pin": "PG13", + "signal": "NE1", + "af": 12 + }, + { + "pin": "PG14", + "signal": "NCE", + "af": 10 + }, + { + "pin": "PG14", + "signal": "NE2", + "af": 12 + }, + { + "pin": "PG15", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PG2", + "signal": "A21", + "af": 12 + }, + { + "pin": "PG8", + "signal": "A20", + "af": 12 + }, + { + "pin": "PG9", + "signal": "D8", + "af": 12 + }, + { + "pin": "PG9", + "signal": "DA8", + "af": 12 + }, + { + "pin": "PH2", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D9", + "af": 14 + }, + { + "pin": "PH9", + "signal": "DA9", + "af": 14 + }, + { + "pin": "PN0", + "signal": "A25", + "af": 12 + }, + { + "pin": "PN1", + "signal": "A24", + "af": 12 + }, + { + "pin": "PN2", + "signal": "A23", + "af": 12 + }, + { + "pin": "PN3", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO0", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO1", + "signal": "A23", + "af": 12 + }, + { + "pin": "PO2", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO4", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO4", + "signal": "NBL2", + "af": 14 + }, + { + "pin": "PO5", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO5", + "signal": "NBL3", + "af": 14 + }, + { + "pin": "PP0", + "signal": "D16", + "af": 12 + }, + { + "pin": "PP1", + "signal": "D17", + "af": 12 + }, + { + "pin": "PP2", + "signal": "D18", + "af": 12 + }, + { + "pin": "PP3", + "signal": "D19", + "af": 12 + }, + { + "pin": "PP4", + "signal": "D20", + "af": 12 + }, + { + "pin": "PP5", + "signal": "D21", + "af": 12 + }, + { + "pin": "PP6", + "signal": "D22", + "af": 12 + }, + { + "pin": "PP7", + "signal": "D23", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": 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"interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE1", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PF1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PG14", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM1" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF1", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", 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"LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": 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"address": 1208137728, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE1EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE1" + } + ] + }, + { + "name": "MCE2", + "address": 1208138752, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE2EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE2" + } + ] + }, + { + "name": "MCE3", + "address": 1208139776, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE3EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE3" + } + ] + }, + { + "name": "MCE4", + "address": 1208147968, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE4EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "MCE4RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE4" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": 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"MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PKA", + "address": 1140989952, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "PKAEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "PKARST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "PKA" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } 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+ "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD5", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH3", + "af": 13 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PG5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG6", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF0", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PF1", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART2", + "address": 1073759232, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA1", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA2", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF2", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF2", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PF3", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF4", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG3", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG5", + "signal": "NSS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART2" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PH9", + "signal": "CK", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USART6", + "address": 1107301376, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART6EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART6RST" + } + }, + "pins": [ + { + "pin": "PC6", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PD3", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG14", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG6", + "signal": "CK", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + }, + { + "pin": "PO0", + "signal": "P1_NCS1", + "af": 9 + }, + { + "pin": "PO1", + "signal": "P1_NCS2", + "af": 9 + }, + { + "pin": "PO2", + "signal": "P1_DQS0", + "af": 9 + }, + { + "pin": "PO4", + "signal": "P1_CLK", + "af": 9 + }, + { + "pin": "PO5", + "signal": "P1_NCLK", + "af": 9 + }, + { + "pin": "PP0", + "signal": "P1_IO0", + "af": 9 + }, + { + "pin": "PP1", + "signal": "P1_IO1", + "af": 9 + }, + { + "pin": "PP2", + "signal": "P1_IO2", + "af": 9 + }, + { + "pin": "PP3", + "signal": "P1_IO3", + "af": 9 + }, + { + "pin": "PP4", + "signal": "P1_IO4", + "af": 9 + }, + { + "pin": "PP5", + "signal": "P1_IO5", + "af": 9 + }, + { + "pin": "PP6", + "signal": "P1_IO6", + "af": 9 + }, + { + "pin": "PP7", + "signal": "P1_IO7", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + { + "name": "EXTI2", + "number": 22 + }, + { + "name": "EXTI3", + "number": 23 + }, + { + "name": "EXTI4", + "number": 24 + }, + { + "name": "EXTI5", + "number": 25 + }, + { + "name": "EXTI6", + "number": 26 + }, + { + "name": "EXTI7", + "number": 27 + }, + { + "name": "EXTI8", + "number": 28 + }, + { + "name": "EXTI9", + "number": 29 + }, + { + "name": "EXTI10", + "number": 30 + }, + { + "name": "EXTI11", + "number": 31 + }, + { + "name": "EXTI12", + "number": 32 + }, + { + "name": "EXTI13", + "number": 33 + }, + { + "name": "EXTI14", + "number": 34 + }, + { + "name": "EXTI15", + "number": 35 + }, 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86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": 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"name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + 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{ + "name": "PF12" + }, + { + "name": "PF13" + }, + { + "name": "PF14" + }, + { + "name": "PF15" + }, + { + "name": "PG0" + }, + { + "name": "PG1" + }, + { + "name": "PG2" + }, + { + "name": "PG3" + }, + { + "name": "PG4" + }, + { + "name": "PG5" + }, + { + "name": "PG6" + }, + { + "name": "PG8" + }, + { + "name": "PG9" + }, + { + "name": "PG10" + }, + { + "name": "PG11" + }, + { + "name": "PG12" + }, + { + "name": "PG13" + }, + { + "name": "PG14" + }, + { + "name": "PG15" + }, + { + "name": "PH0" + }, + { + "name": "PH1" + }, + { + "name": "PH2" + }, + { + "name": "PH9" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + }, + { + "name": "PO0" + }, + { + "name": "PO1" + }, + { + "name": "PO2" + }, + { + "name": "PO4" + }, + { + "name": "PO5" + }, + { + "name": "PP0" + }, + { + "name": "PP1" + }, + { + "name": "PP2" + }, + { + "name": "PP3" + }, + { + "name": "PP4" + }, + { + "name": "PP5" + }, + { + "name": "PP6" + }, + { + "name": "PP7" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N655I0.json b/data/chips/STM32N655I0.json new file mode 100644 index 0000000..2e2176b --- /dev/null +++ b/data/chips/STM32N655I0.json @@ -0,0 +1,9789 @@ +{ + "name": "STM32N655I0", + "family": "STM32N6", + "line": "STM32N6x5", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N655I0HxQ", + "package": "VFBGA178", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PE6" + ] + }, + { + "position": "A11", + "signals": [ + "PD6" + ] + }, + { + "position": "A12", + "signals": [ + "PD0" + ] + }, + { + "position": "A13", + "signals": [ + "PD3" + ] + }, + { + "position": "A14", + "signals": [ + "VSS" + ] + }, + { + "position": "A2", + "signals": [ + "OTG2_HSDM" + ] + }, + { + "position": "A3", + "signals": [] + }, + { + "position": "A4", + "signals": [ + "VDD33USB" + ] + }, + { + "position": "A5", + "signals": [ + "OTG1_HSDM" + ] + }, + { + "position": "A6", + "signals": [ + "UCPD1_CC1" + ] + }, + { + "position": "A7", + "signals": [ + "PH1" + ] + }, + { + "position": "A8", + "signals": [ + "PC6" + ] + }, + { + "position": "A9", + "signals": [ + "PC7" + ] + }, + { + "position": "B1", + "signals": [ + "PC14" + ] + }, + { + "position": "B10", + "signals": [ + "PE15" + ] + }, + { + "position": "B11", + "signals": [ + "PD7" + ] + }, + { + "position": "B12", + "signals": [ + "PD1" + ] + }, + { + "position": "B13", + "signals": [ + "PD4" + ] + }, + { + "position": "B14", + "signals": [ + "PE9" + ] + }, + { + "position": "B2", + "signals": [ + "OTG2_HSDP" + ] + }, + { + "position": "B3", + "signals": [ + "OTG1_ID" + ] + }, + { + "position": "B4", + "signals": [ + "OTG2_TXRTUNE" + ] + }, + { + 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12 + }, + { + "pin": "PN2", + "signal": "A23", + "af": 12 + }, + { + "pin": "PN3", + "signal": "A22", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA7", + "signal": "B1", + "af": 14 + }, + { + "pin": "PA7", + "signal": "R4", + "af": 10 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB2", + "signal": "B2", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD13", + "signal": "R6", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PD9", + "signal": "R1", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF6", + "signal": "DE", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG0", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG0", + "signal": "VSYNC", + "af": 10 + }, + { + "pin": "PG1", + "signal": "G1", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG12", + "signal": "G0", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG15", + "signal": "B0", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG8", + "signal": "G7", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MCE1", + "address": 1208137728, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE1EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE1" + } + ] + }, + { + "name": "MCE2", + "address": 1208138752, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE2EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE2" + } + ] + }, + { + "name": "MCE3", + "address": 1208139776, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE3EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE3" + } + ] + }, + { + "name": "MCE4", + "address": 1208147968, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE4EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "MCE4RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE4" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PKA", + "address": 1140989952, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "PKAEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "PKARST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "PKA" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } 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"kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD13", + "signal": "SCK_A", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB2", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB2", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB2", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD5", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH3", + "af": 13 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD13", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART2", + "address": 1073759232, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA1", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA2", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF2", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF2", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PF3", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF4", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART2" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + 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"TX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 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}, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + 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"number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA3" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA7" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB2" + }, + { + "name": "PB3" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PC1" + }, + { + "name": "PC6" + }, + { + "name": "PC7" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD0" + }, + { + "name": "PD1" + }, + { + "name": "PD2" + }, + { + "name": "PD3" + }, + { + "name": "PD4" + }, + { + "name": "PD5" + }, + { + "name": "PD6" + }, + { + "name": "PD7" + }, + { + "name": "PD8" + }, + { + "name": "PD9" + }, + { + "name": "PD10" + }, + { + "name": "PD11" + }, + { + "name": "PD12" + }, + { + "name": "PD13" + }, + { + "name": "PD14" + }, + { + "name": "PD15" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE5" + }, + { + "name": "PE6" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": "PE9" + }, + { + "name": "PE10" + }, + { + "name": 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}, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N655L0.json b/data/chips/STM32N655L0.json new file mode 100644 index 0000000..b7330ca --- /dev/null +++ b/data/chips/STM32N655L0.json @@ -0,0 +1,11284 @@ +{ + "name": "STM32N655L0", + "family": "STM32N6", + "line": "STM32N6x5", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N655L0HxQ", + "package": "VFBGA223", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PD6" + ] + }, + { + "position": "A11", + "signals": [ + "PD12" + ] + }, + { + "position": "A12", + "signals": [ + "PD15" + ] + }, + { + "position": "A13", + "signals": [ + "PE8" + ] + }, + { + "position": "A14", + "signals": [ + "PB15" + ] + }, + { + "position": "A15", + "signals": [ + "PD5" + ] + }, + { + "position": "A16", + "signals": [ + "PB13" + ] + }, + { + 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"field": "CRYPEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "CRYPRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "CRYP" + } + ] + }, + { + "name": "CSI", + "address": 1207984128, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "CSIEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "CSIRST" + } + } + }, + { + "name": "DBGMCU", + "address": 1140854784 + }, + { + "name": "DCMI", + "address": 1208124416, + "registers": { + "kind": "dcmi", + "version": "v1", + "block": "DCMI" + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA4", + "signal": "D3", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PIXCLK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB14", 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"APB4HRSTR", + "field": "DTSRST" + } + } + }, + { + "name": "ETH1", + "address": 1208180736, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "ETH1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "ETH1RST" + } + }, + "pins": [ + { + "pin": "PD1", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD12", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PD3", + "signal": "PHY_INTN", + "af": 11 + }, + { + "pin": "PF0", + "signal": "RGMII_GTX_CLK", + "af": 12 + }, + { + "pin": "PF0", + "signal": "TX_CLK", + "af": 11 + }, + { + "pin": "PF1", + "signal": "TX_ER", + "af": 11 + }, + { + "pin": "PF10", + "signal": "CRS_DV", + "af": 11 + }, + { + "pin": "PF10", + "signal": "RGMII_RX_CTL", + "af": 11 + }, + { + "pin": "PF10", + "signal": "RX_DV", + "af": 11 + }, + { + "pin": "PF11", + "signal": "RGMII_TX_CTL", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TX_EN", + "af": 11 + }, + { + "pin": "PF12", + "signal": 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"bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE11", + "signal": "TX", + "af": 6 + }, + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FMC", + "address": 1208107008, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR3", + "field": "FMCSEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "FMCEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "FMCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "D7", + "af": 12 + }, + { + "pin": "PA0", + "signal": "DA7", + "af": 12 + }, + { + "pin": "PA1", + "signal": "D6", + "af": 12 + }, + { + "pin": "PA1", + "signal": "DA6", + "af": 12 + }, + { + "pin": "PA10", + "signal": "D2", + "af": 12 + }, + { + "pin": "PA10", + "signal": "DA2", + "af": 12 + }, + { + "pin": "PA11", + "signal": "D1", + "af": 12 + }, + { + "pin": "PA11", + "signal": "DA1", + "af": 12 + }, + { + "pin": "PA12", + "signal": "D0", + "af": 12 + }, + { + "pin": "PA12", + "signal": "DA0", + "af": 12 + }, + { + "pin": "PA15", + "signal": "D15", + "af": 12 + }, + { + "pin": "PA15", + "signal": "DA15", + "af": 12 + }, + { + "pin": "PA2", + "signal": "D5", + "af": 12 + }, + { + "pin": "PA2", + "signal": "DA5", + "af": 12 + }, + { + "pin": "PA3", + "signal": "A17", + "af": 12 + }, + { + "pin": "PA3", + "signal": "ALE", + "af": 12 + }, + { + "pin": "PA4", + "signal": "A13", + "af": 12 + }, + { + "pin": "PA5", + "signal": "NOE", + "af": 12 + }, + { + "pin": "PA8", + "signal": "D4", + "af": 12 + }, + { + "pin": "PA8", + "signal": "DA4", + "af": 12 + }, + { + "pin": "PA9", + "signal": "D3", + "af": 12 + }, + { + "pin": "PA9", + "signal": "DA3", + "af": 12 + }, + { + "pin": "PB0", + "signal": "D13", + "af": 12 + }, + { + "pin": "PB0", + "signal": "DA13", + "af": 12 + }, + { + "pin": "PB1", + "signal": "NOE", + "af": 12 + }, + { + "pin": "PB10", + "signal": "D11", + "af": 12 + }, + { + "pin": "PB10", + "signal": "DA11", + "af": 12 + }, + { + "pin": "PB11", + "signal": "D10", + "af": 12 + }, + { + "pin": "PB11", + "signal": "DA10", + "af": 12 + }, + { + "pin": "PB12", + "signal": "D9", + "af": 12 + }, + { + "pin": "PB12", + "signal": "DA9", + "af": 12 + }, + { + "pin": "PB13", + "signal": "D5", + "af": 12 + }, + { + "pin": "PB13", + "signal": "DA5", + "af": 12 + }, + { + "pin": "PB14", + "signal": "D7", + "af": 12 + }, + { + "pin": "PB14", + "signal": "DA7", + "af": 12 + }, + { + "pin": "PB15", + "signal": "D0", + "af": 12 + }, + { + "pin": "PB15", + "signal": "DA0", + "af": 12 + }, + { + "pin": "PB2", + "signal": "D2", + "af": 12 + }, + { + "pin": "PB2", + "signal": "DA2", + "af": 12 + }, + { + "pin": "PB3", + "signal": "A23", + "af": 14 + }, + { + "pin": "PB3", + "signal": "NBL1", + "af": 12 + }, + { + "pin": "PB4", + "signal": "D13", + "af": 12 + }, + { + "pin": "PB4", + "signal": "DA13", + "af": 12 + }, + { + "pin": "PB5", + "signal": "D12", + "af": 12 + }, + { + "pin": "PB5", + "signal": "DA12", + "af": 12 + }, + { + "pin": "PB6", + "signal": "D14", + "af": 12 + }, + { + "pin": "PB6", + "signal": "DA14", + "af": 12 + }, + { + "pin": "PB7", + "signal": "D15", + "af": 12 + }, + { + "pin": "PB7", + "signal": "DA15", + "af": 12 + }, + { + "pin": "PB8", + "signal": "D1", + "af": 12 + }, + { + "pin": "PB8", + "signal": "DA1", + "af": 12 + }, + { + "pin": "PB9", + "signal": "D3", + "af": 12 + }, + { + "pin": "PB9", + "signal": "DA3", + "af": 12 + }, + { + "pin": "PC10", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PC12", + "signal": "NL", + "af": 12 + }, + { + "pin": "PC8", + "signal": "NE4", + "af": 12 + }, + { + "pin": "PD0", + "signal": "A22", + "af": 14 + }, + { + "pin": "PD0", + "signal": "A6", + "af": 12 + }, + { + "pin": "PD1", + "signal": "A23", + "af": 14 + }, + { + "pin": "PD1", + "signal": "A7", + "af": 12 + }, + { + "pin": "PD10", + "signal": "A19", + "af": 14 + }, + { + "pin": "PD10", + "signal": "A3", + "af": 12 + }, + { + "pin": "PD11", + "signal": "D8", + "af": 12 + }, + { + "pin": "PD11", + "signal": "DA8", + "af": 12 + }, + { + "pin": "PD12", + "signal": "A21", + "af": 14 + }, + { + "pin": "PD12", + "signal": "A5", + "af": 12 + }, + { + "pin": "PD13", + "signal": "D4", + "af": 12 + }, + { + "pin": "PD13", + "signal": "DA4", + "af": 12 + }, + { + "pin": "PD14", + "signal": "A9", + "af": 12 + }, + { + "pin": "PD15", + "signal": "A8", + "af": 12 + }, + { + "pin": "PD2", + "signal": "A0", + "af": 12 + }, + { + "pin": "PD2", + "signal": "A16", + "af": 14 + }, + { + "pin": "PD2", + "signal": "CLE", + "af": 14 + }, + { + "pin": "PD3", + "signal": "A10", + "af": 12 + }, + { + "pin": "PD4", + "signal": "A11", + "af": 12 + }, + { + "pin": "PD5", + "signal": "D6", + "af": 12 + }, + { + "pin": "PD5", + "signal": "DA6", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A1", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A17", + "af": 14 + }, + { + "pin": "PD6", + "signal": "ALE", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A18", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A2", + "af": 12 + }, + { + "pin": "PD8", + "signal": "NBL0", + "af": 12 + }, + { + "pin": "PD9", + "signal": "SDCLK", + "af": 12 + }, + { + "pin": "PE0", + "signal": "D9", + "af": 12 + }, + { + "pin": "PE0", + "signal": "DA9", + "af": 12 + }, + { + "pin": "PE1", + "signal": "D10", + "af": 12 + }, + { + "pin": "PE1", + "signal": "DA10", + "af": 12 + }, + { + "pin": "PE10", + "signal": "A15", + "af": 12 + }, + { + "pin": "PE10", + "signal": "BA1", + "af": 12 + }, + { + "pin": "PE11", + "signal": "SDNWE", + "af": 12 + }, + { + "pin": "PE12", + "signal": "SDNRAS", + "af": 12 + }, + { + "pin": "PE13", + "signal": "SDNCAS", + "af": 12 + }, + { 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"pin": "PN3", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO0", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO1", + "signal": "A23", + "af": 12 + }, + { + "pin": "PO2", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO3", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO4", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO4", + "signal": "NBL2", + "af": 14 + }, + { + "pin": "PO5", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO5", + "signal": "NBL3", + "af": 14 + }, + { + "pin": "PP0", + "signal": "D16", + "af": 12 + }, + { + "pin": "PP1", + "signal": "D17", + "af": 12 + }, + { + "pin": "PP10", + "signal": "D26", + "af": 12 + }, + { + "pin": "PP11", + "signal": "D27", + "af": 12 + }, + { + "pin": "PP12", + "signal": "D28", + "af": 12 + }, + { + "pin": "PP13", + "signal": "D29", + "af": 12 + }, + { + "pin": "PP14", + "signal": "D30", + "af": 12 + }, + { + "pin": "PP15", + "signal": "D31", + "af": 12 + }, + { + "pin": "PP2", + "signal": "D18", + "af": 12 + }, + { + "pin": "PP3", + "signal": "D19", + "af": 12 + }, + { + "pin": "PP4", + "signal": "D20", + "af": 12 + }, + { + "pin": "PP5", + "signal": "D21", + "af": 12 + }, + { + "pin": "PP6", + "signal": "D22", + "af": 12 + }, + { + "pin": "PP7", + "signal": "D23", + "af": 12 + }, + { + "pin": "PP8", + "signal": "D24", + "af": 12 + }, + { + "pin": "PP9", + "signal": "D25", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB9", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PD13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE1", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PF1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PG14", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM1" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF1", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPTIM5", + "address": 1174417408, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM5EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM5RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE2", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PE3", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF0", + "signal": "OUT", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM5" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA7", + "signal": "B1", + "af": 14 + }, + { + "pin": "PA7", + "signal": "R4", + "af": 10 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB1", + "signal": "R1", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB13", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PB14", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PB15", + "signal": "G4", + "af": 14 + }, + { + "pin": "PB2", + "signal": "B2", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD13", + "signal": "R6", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PD9", + "signal": "R1", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF6", + "signal": "DE", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PF9", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PG0", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG0", + "signal": "VSYNC", + "af": 10 + }, + { + "pin": "PG1", + "signal": "G1", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG11", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG12", + "signal": "G0", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG15", + "signal": "B0", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG4", + "signal": "B0", + "af": 14 + }, + { + "pin": "PG5", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG6", + "signal": "B3", + "af": 14 + }, + { + "pin": "PG8", + "signal": "G7", + "af": 14 + }, + { + "pin": "PG9", + "signal": "R7", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + }, + { + "pin": "PO2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PO3", + "signal": "G3", + "af": 14 + }, + { + "pin": "PO4", + "signal": "B4", + "af": 10 + }, + { + "pin": "PP15", + "signal": "B5", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MCE1", + "address": 1208137728, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE1EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE1" + } + ] + }, + { + "name": "MCE2", + "address": 1208138752, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE2EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE2" + } + ] + }, + { + "name": "MCE3", + "address": 1208139776, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE3EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE3" + } + ] + }, + { + "name": "MCE4", + "address": 1208147968, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE4EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "MCE4RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE4" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PKA", + "address": 1140989952, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "PKAEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "PKARST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "PKA" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA4", + "signal": "D3", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB14", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PB8", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PC1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC6", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC7", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "DE", + "af": 9 + }, + { + "pin": "PD11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD13", + "signal": "D13", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD5", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PD9", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE6", + "signal": "D1", + "af": 10 + }, + { + "pin": "PE6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF0", + "signal": "D9", + "af": 9 + }, + { + "pin": "PF1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG1", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG15", + "signal": "D4", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PG6", + "signal": "D12", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PH9", + "signal": "D6", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PB8", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD13", + "signal": "SCK_A", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SDMMC2", + "address": 1208117248, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC2SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC2EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CMD", + "af": 11 + }, + { + "pin": "PB13", + "signal": "D6", + "af": 11 + }, + { + "pin": "PB4", + "signal": "D3", + "af": 11 + }, + { + "pin": "PB8", + "signal": "D0", + "af": 11 + }, + { + "pin": "PB9", + "signal": "D2", + "af": 11 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 11 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 11 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 11 + }, + { + "pin": "PD2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PD5", + "signal": "D7", + "af": 11 + }, + { + "pin": "PG8", + "signal": "D1", + "af": 11 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC2" + } + ] + }, + { + "name": "SPDIFRX1", + "address": 1073758208, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPDIFRX1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPDIFRX1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPDIFRX1RST" + } + }, + "pins": [ + { + "pin": "PB15", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PB8", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PB9", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PD10", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PD12", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PD8", + "signal": "IN1", + "af": 8 + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PP8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PP9", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB2", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB2", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, 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}, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB13", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB13", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB1", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB2", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD5", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH3", + "af": 13 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PG5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG6", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PB1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD13", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF0", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PF1", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART10", + "address": 1107303424, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART10EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART10RST" + } + }, + "pins": [ + { + "pin": "PB13", + "signal": "CTS", + "af": 6 + }, + { + "pin": "PB13", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB14", + "signal": "CK", + "af": 6 + }, + { + "pin": "PB9", + "signal": "TX", + "af": 6 + }, + { + "pin": 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"FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA3" + }, + { + "name": "PA4" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA7" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + 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"name": "PP2" + }, + { + "name": "PP3" + }, + { + "name": "PP4" + }, + { + "name": "PP5" + }, + { + "name": "PP6" + }, + { + "name": "PP7" + }, + { + "name": "PP8" + }, + { + "name": "PP9" + }, + { + "name": "PP10" + }, + { + "name": "PP11" + }, + { + "name": "PP12" + }, + { + "name": "PP13" + }, + { + "name": "PP14" + }, + { + "name": "PP15" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N655X0.json b/data/chips/STM32N655X0.json new file mode 100644 index 0000000..066988f --- /dev/null +++ b/data/chips/STM32N655X0.json @@ -0,0 +1,12204 @@ +{ + "name": "STM32N655X0", + "family": "STM32N6", + "line": "STM32N6x5", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N655X0HxQ", + "package": "VFBGA264", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PC4" + ] + }, + { + "position": "A11", + "signals": [ + "PE13" + ] + }, + { + "position": "A12", + "signals": [ + "PE15" + ] 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+ "signal": "NE1", + "af": 12 + }, + { + "pin": "PG14", + "signal": "NCE", + "af": 10 + }, + { + "pin": "PG14", + "signal": "NE2", + "af": 12 + }, + { + "pin": "PG15", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PG2", + "signal": "A21", + "af": 12 + }, + { + "pin": "PG8", + "signal": "A20", + "af": 12 + }, + { + "pin": "PG9", + "signal": "D8", + "af": 12 + }, + { + "pin": "PG9", + "signal": "DA8", + "af": 12 + }, + { + "pin": "PH2", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D9", + "af": 14 + }, + { + "pin": "PH9", + "signal": "DA9", + "af": 14 + }, + { + "pin": "PN0", + "signal": "A25", + "af": 12 + }, + { + "pin": "PN1", + "signal": "A24", + "af": 12 + }, + { + "pin": "PN2", + "signal": "A23", + "af": 12 + }, + { + "pin": "PN3", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO0", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO1", + "signal": "A23", + "af": 12 + }, + { + "pin": "PO2", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO3", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO4", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO4", + "signal": "NBL2", + "af": 14 + }, + { + "pin": "PO5", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO5", + "signal": "NBL3", + "af": 14 + }, + { + "pin": "PP0", + "signal": "D16", + "af": 12 + }, + { + "pin": "PP1", + "signal": "D17", + "af": 12 + }, + { + "pin": "PP10", + "signal": "D26", + "af": 12 + }, + { + "pin": "PP11", + "signal": "D27", + "af": 12 + }, + { + "pin": "PP12", + "signal": "D28", + "af": 12 + }, + { + "pin": "PP13", + "signal": "D29", + "af": 12 + }, + { + "pin": "PP14", + "signal": "D30", + "af": 12 + }, + { + "pin": "PP15", + "signal": "D31", + "af": 12 + }, + { + "pin": "PP2", + "signal": "D18", + "af": 12 + }, + { + "pin": "PP3", + "signal": "D19", + "af": 12 + }, + { + "pin": "PP4", + "signal": "D20", + "af": 12 + }, + { + "pin": "PP5", + "signal": "D21", + "af": 12 + }, + { + "pin": "PP6", + "signal": "D22", + "af": 12 + }, + { + "pin": "PP7", + "signal": "D23", + "af": 12 + }, + { + "pin": "PP8", + "signal": "D24", + "af": 12 + }, + { + "pin": "PP9", + "signal": "D25", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PH7", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PH8", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": 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"pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PC2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PC2", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG7", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PB8", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PC5", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD13", + "signal": "SCK_A", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PQ2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PQ5", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PQ6", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PQ7", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SDMMC2", + "address": 1208117248, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC2SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC2EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CMD", + "af": 11 + }, + { + "pin": "PB13", + "signal": "D6", + "af": 11 + }, + { + "pin": "PB4", + "signal": "D3", + "af": 11 + }, + { + "pin": "PB8", + "signal": "D0", + "af": 11 + }, + { + "pin": "PB9", + "signal": "D2", + "af": 11 + }, + { + "pin": "PC0", + "signal": "D2", + "af": 11 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 11 + }, + { + "pin": "PC2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PC3", + "signal": "CMD", + "af": 11 + }, + { + "pin": "PC4", + "signal": "D0", + "af": 11 + }, + { + "pin": "PC5", + "signal": "D1", + "af": 11 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 11 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 11 + }, + { + "pin": "PD2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PD5", + "signal": "D7", + "af": 11 + }, + { + "pin": "PE4", + "signal": "D3", + "af": 11 + }, + { + "pin": "PG8", + "signal": "D1", + "af": 11 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC2" + } + ] + }, + { + "name": "SPDIFRX1", + "address": 1073758208, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPDIFRX1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPDIFRX1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPDIFRX1RST" + } + }, + "pins": [ + { + "pin": "PB15", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PB8", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PB9", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PC3", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PD10", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PD12", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PD8", + "signal": "IN1", + "af": 8 + }, + { + "pin": "PE4", + "signal": "IN1", + "af": 8 + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PC0", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC0", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PC3", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PC3", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PC5", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC5", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PC4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PP8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PP9", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB2", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB2", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC0", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC0", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PC2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { 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{ + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA4", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 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"af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB13", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB13", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC0", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PC0", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PE4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + }, + { + "pin": "PH4", + "signal": "IN4" + }, + { + "pin": "PH4", + "signal": "OUT3" + }, + { + "pin": "PQ7", + "signal": "IN2" + }, + { + "pin": "PQ7", + "signal": "OUT1" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB1", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB2", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC4", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", 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"CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PG5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PC4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG6", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC0", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM8", + "address": 1107297280, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM8EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM8RST" + } + }, + "pins": [ + { + "pin": "PB13", + "signal": "CH3N", + "af": 2 + }, + { + "pin": "PB14", + "signal": "CH4N", + "af": 2 + }, + { + "pin": "PG14", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PQ0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PQ1", + "signal": "BKIN", + "af": 2 + }, + { + "pin": "PQ2", + "signal": "BKIN2", + "af": 2 + }, + { + "pin": "PQ3", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PQ4", + "signal": "CH1N", + "af": 2 + }, + { + "pin": "PQ5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PQ6", + "signal": "CH2N", + "af": 2 + }, + { + "pin": "PQ7", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM8_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM8_CC" + }, + { + "signal": "COM", + "interrupt": "TIM8_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM8_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM8_UP" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PB1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PC4", + "signal": "DE", + "af": 8 + }, + { + "pin": "PC4", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PC0", + "signal": "RX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH3", + "signal": "TX", + "af": 8 + }, + { + "pin": "PH4", + "signal": "TX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD13", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF0", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PF1", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC4", + "signal": "TX", + "af": 4 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART10", + "address": 1107303424, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART10EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART10RST" + } + }, + "pins": [ + { + "pin": "PB13", + "signal": "CTS", + "af": 6 + }, + { + "pin": "PB13", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB14", + "signal": "CK", + "af": 6 + }, + { + "pin": "PB9", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD14", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD15", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD3", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 6 + }, + { + "pin": "PE4", + "signal": "RX", + "af": 6 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART10" + } + ] + }, + { + "name": "USART2", + "address": 1073759232, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA1", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA2", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC2", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF2", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF2", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PF3", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF4", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG3", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG5", + "signal": "NSS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART2" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, 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"interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + 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"INN2" + }, + { + "pin": "PF12", + "signal": "INP6" + }, + { + "pin": "PF3", + "signal": "INP16" + }, + { + "pin": "PF4", + "signal": "INP18" + }, + { + "pin": "PF7", + "signal": "INN5" + }, + { + "pin": "PF7", + "signal": "INP9" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ADC1_2" + } + ] + }, + { + "name": "ADC12_COMMON", + "address": 1073881856 + }, + { + "name": "ADC2", + "address": 1073881344, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": { + "register": "CCIPR1", + "field": "ADC12SEL" + }, + "enable": { + "register": "AHB1ENR", + "field": "ADC12EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "ADC12RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "INN1" + }, + { + "pin": "PA0", + "signal": "INP0" + }, + { + "pin": "PA1", + "signal": "INP1" + }, + { + "pin": "PA10", + "signal": "INN10" + }, + { + "pin": "PA10", + "signal": "INP11" + }, + { + "pin": "PA11", + "signal": "INN11" + }, + { + "pin": "PA11", + "signal": "INP12" + }, + { + "pin": "PA12", + "signal": "INN12" + }, + { + "pin": "PA12", + "signal": "INP13" + }, + { + "pin": "PA2", + "signal": "INP14" + }, + { + "pin": "PA5", + "signal": "INP18" + }, + { + "pin": "PA6", + "signal": "INP3" + }, + { + "pin": "PA8", + "signal": "INP5" + }, + { + "pin": "PA9", + "signal": "INP10" + }, + { + "pin": "PB10", + "signal": "INN4" + }, + { + "pin": "PB10", + "signal": "INP8" + }, + { + "pin": "PB11", + "signal": "INP4" + }, + { + "pin": "PF13", + "signal": "INP2" + }, + { + "pin": "PF14", + "signal": "INN2" + }, + { + "pin": "PF14", + "signal": "INP6" + }, + { + "pin": "PF7", + "signal": "INN5" + }, + { + "pin": "PF7", + "signal": "INP9" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ADC1_2" + } + ] + }, + { + "name": "ADF1", + "address": 1107451904, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ADF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "ADF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "ADF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI0", + "af": 3 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 3 + }, + { + "pin": "PB7", + "signal": "SDI0", + "af": 3 + }, + { + "pin": "PE13", + "signal": "CCK0", + "af": 3 + }, + { + "pin": "PE14", + "signal": "CCK1", + "af": 3 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "ADF1_FLT0" + } + ] + }, + { + "name": "BSEC", + "address": 1174441984, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "BSECEN" + } + } + }, + { + "name": "CRC", + "address": 1174555648, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "CRCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "CRCRST" + } + } + }, + { + "name": "CRYP", + "address": 1140983808, + "registers": { + "kind": "cryp", + "version": "v2", + "block": "CRYP" + }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "CRYPEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "CRYPRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "CRYP" + } + ] + }, + { + "name": "CSI", + "address": 1207984128, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "CSIEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "CSIRST" + } + } + }, + { + "name": "DBGMCU", + "address": 1140854784 + }, + { + "name": "DCMI", + "address": 1208124416, + "registers": { + "kind": "dcmi", + "version": "v1", + "block": "DCMI" + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PIXCLK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "VSYNC", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF4", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "DCMIPP", + "address": 1207967744, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR1", + "field": "DCMIPPSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "DCMIPPEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "DCMIPPRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PIXCLK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "VSYNC", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF4", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "CSI", + "interrupt": "CSI" + } + ] + }, + { + "name": "DMA2D", + "address": 1208094720, + "registers": { + "kind": "dma2d", + "version": "v1", + "block": "DMA2D" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "DMA2DEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "DMA2DRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DMA2D" + } + ] + }, + { + "name": "DTS", + "address": 1174446080, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "DTSEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "DTSRST" + } + } + }, + { + "name": "EXTI", + "address": 1174556672, + "registers": { + "kind": "exti", + "version": "v1", + "block": "EXTI" + }, + "interrupts": [ + { + "signal": "EXTI0", + "interrupt": "EXTI0" + }, + { + "signal": "EXTI1", + "interrupt": "EXTI1" + }, + { + "signal": "EXTI10", + "interrupt": "EXTI10" + }, + { + "signal": "EXTI11", + "interrupt": "EXTI11" + }, + { + "signal": "EXTI12", + "interrupt": "EXTI12" + }, + { + "signal": "EXTI13", + "interrupt": "EXTI13" + }, + { + "signal": "EXTI14", + "interrupt": "EXTI14" + }, + { + "signal": "EXTI15", + "interrupt": "EXTI15" + }, + { + "signal": "EXTI2", + "interrupt": "EXTI2" + }, + { + "signal": "EXTI3", + "interrupt": "EXTI3" + }, + { + "signal": "EXTI4", + "interrupt": "EXTI4" + }, + { + "signal": "EXTI5", + "interrupt": "EXTI5" + }, + { + "signal": "EXTI6", + "interrupt": "EXTI6" + }, + { + "signal": "EXTI7", + "interrupt": "EXTI7" + }, + { + "signal": "EXTI8", + "interrupt": "EXTI8" + }, + { + "signal": "EXTI9", + "interrupt": "EXTI9" + } + ] + }, + { + "name": "FDCAN1", + "address": 1073782784, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MCE1", + "address": 1208137728, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE1EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE1" + } + ] + }, + { + "name": "MCE2", + "address": 1208138752, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE2EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE2" + } + ] + }, + { + "name": "MCE3", + "address": 1208139776, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE3EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE3" + } + ] + }, + { + "name": "MCE4", + "address": 1208147968, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE4EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "MCE4RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE4" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PKA", + "address": 1140989952, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "PKAEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "PKARST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "PKA" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + { + "name": "EXTI2", + "number": 22 + }, + { + "name": "EXTI3", + "number": 23 + }, + { + "name": "EXTI4", + "number": 24 + }, + { + "name": "EXTI5", + "number": 25 + }, + { + "name": "EXTI6", + "number": 26 + }, + { + "name": "EXTI7", + "number": 27 + }, + { + "name": "EXTI8", + "number": 28 + }, + { + "name": "EXTI9", + "number": 29 + }, + { + "name": "EXTI10", + "number": 30 + }, + { + "name": "EXTI11", + "number": 31 + }, + { + "name": "EXTI12", + "number": 32 + }, + { + "name": "EXTI13", + "number": 33 + }, + { + "name": "EXTI14", + "number": 34 + }, + { + "name": "EXTI15", + "number": 35 + }, + { + "name": "SAES", + "number": 36 + }, + { + "name": "CRYP", + "number": 37 + }, + { + "name": "PKA", + "number": 38 + }, + { + "name": "HASH", + "number": 39 + }, + { + "name": "RNG", + "number": 40 + }, + { + "name": "MCE1", + "number": 42 + }, + { + "name": "MCE2", + "number": 43 + }, + { + "name": "MCE3", + "number": 44 + }, + { + "name": "MCE4", + "number": 45 + }, + { + "name": "ADC1_2", + "number": 46 + }, + { + "name": "CSI", + "number": 47 + }, + { + "name": "DCMIPP", + "number": 48 + }, + { + "name": "PAHB_ERR", + "number": 52 + }, + { + "name": "LTDC_LO", + "number": 58 + }, + { + "name": "LTDC_LO_ERR", + "number": 59 + }, + { + "name": "DMA2D", + "number": 60 + }, + { + "name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + 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"field": "CRCRST" + } + } + }, + { + "name": "CRYP", + "address": 1140983808, + "registers": { + "kind": "cryp", + "version": "v2", + "block": "CRYP" + }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "CRYPEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "CRYPRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "CRYP" + } + ] + }, + { + "name": "CSI", + "address": 1207984128, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "CSIEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "CSIRST" + } + } + }, + { + "name": "DBGMCU", + "address": 1140854784 + }, + { + "name": "DCMI", + "address": 1208124416, + "registers": { + "kind": "dcmi", + "version": "v1", + "block": "DCMI" + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": 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"version": "v1", + "block": "DTS" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "DTSEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "DTSRST" + } + } + }, + { + "name": "ETH1", + "address": 1208180736, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "ETH1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "ETH1RST" + } + }, + "pins": [ + { + "pin": "PD1", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD12", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PD3", + "signal": "PHY_INTN", + "af": 11 + }, + { + "pin": "PF10", + "signal": "CRS_DV", + "af": 11 + }, + { + "pin": "PF10", + "signal": "RGMII_RX_CTL", + "af": 11 + }, + { + "pin": "PF10", + "signal": "RX_DV", + "af": 11 + }, + { + "pin": "PF11", + "signal": "RGMII_TX_CTL", + "af": 11 + }, + { + "pin": "PF11", + "signal": "TX_EN", + "af": 11 + }, + { + "pin": "PF12", + "signal": "RGMII_TXD0", + "af": 11 + }, + { + "pin": "PF12", + "signal": "TXD0", + "af": 11 + }, + { + "pin": "PF13", + "signal": "RGMII_TXD1", + "af": 11 + }, + { + "pin": "PF13", + "signal": "TXD1", + "af": 11 + }, + { + "pin": "PF14", + "signal": "RGMII_RXD0", + "af": 11 + }, + { + "pin": "PF14", + "signal": "RXD0", + "af": 11 + }, + { + "pin": "PF15", + "signal": "RGMII_RXD1", + "af": 11 + }, + { + "pin": "PF15", + "signal": "RXD1", + "af": 11 + }, + { + "pin": "PF2", + "signal": "RGMII_CLK125", + "af": 11 + }, + { + "pin": "PF3", + "signal": "PPS_OUT", + "af": 11 + }, + { + "pin": "PF4", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PF5", + "signal": "CLK", + "af": 11 + }, + { + "pin": "PF7", + "signal": "REF_CLK", + "af": 11 + }, + { + "pin": "PF7", + "signal": "RGMII_RX_CLK", + "af": 11 + }, + { + "pin": "PF7", + "signal": "RX_CLK", + "af": 11 + }, + { + "pin": "PF8", + "signal": "RGMII_RXD2", + "af": 11 + }, + { + "pin": "PF8", + "signal": "RXD2", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ETH1" + }, + { + "signal": "WKUP", + "interrupt": "ETH1" + } + ] + }, + { + "name": "EXTI", + "address": 1174556672, + "registers": { + "kind": "exti", + "version": "v1", + "block": "EXTI" + }, + "interrupts": [ + { + "signal": "EXTI0", + "interrupt": "EXTI0" + }, + { + "signal": "EXTI1", + "interrupt": "EXTI1" + }, + { + "signal": "EXTI10", + "interrupt": "EXTI10" + }, + { + "signal": "EXTI11", + "interrupt": "EXTI11" + }, + { + "signal": "EXTI12", + "interrupt": "EXTI12" + }, + { + "signal": "EXTI13", + "interrupt": "EXTI13" + }, + { + "signal": "EXTI14", + "interrupt": "EXTI14" + }, + { + "signal": "EXTI15", + "interrupt": "EXTI15" + }, + { + "signal": "EXTI2", + "interrupt": "EXTI2" + }, + { + "signal": "EXTI3", + "interrupt": "EXTI3" + }, + { + "signal": "EXTI4", + "interrupt": "EXTI4" + }, + { + "signal": "EXTI5", + "interrupt": "EXTI5" + }, + { + "signal": "EXTI6", + "interrupt": "EXTI6" + }, + { + "signal": "EXTI7", + "interrupt": "EXTI7" + }, + { + "signal": "EXTI8", + "interrupt": "EXTI8" + }, + { + "signal": "EXTI9", + "interrupt": "EXTI9" + } + ] + }, + { + "name": "FDCAN1", + "address": 1073782784, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE11", + "signal": "TX", + "af": 6 + }, + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MCE1", + "address": 1208137728, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE1EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE1" + } + ] + }, + { + "name": "MCE2", + "address": 1208138752, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE2EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE2" + } + ] + }, + { + "name": "MCE3", + "address": 1208139776, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE3EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE3" + } + ] + }, + { + "name": "MCE4", + "address": 1208147968, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE4EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "MCE4RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE4" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PKA", + "address": 1140989952, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "PKAEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "PKARST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "PKA" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "DE", + "af": 9 + }, + { + "pin": "PD11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + 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"USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + { + "name": "EXTI2", + "number": 22 + }, + { + "name": "EXTI3", + "number": 23 + }, + { + "name": "EXTI4", + "number": 24 + }, + { + "name": "EXTI5", + "number": 25 + }, + { + "name": "EXTI6", + "number": 26 + }, + { + "name": "EXTI7", + "number": 27 + }, + { + "name": "EXTI8", + "number": 28 + }, + { + "name": "EXTI9", + "number": 29 + }, + { + "name": "EXTI10", + "number": 30 + }, + { + "name": "EXTI11", + "number": 31 + }, + { + "name": "EXTI12", + "number": 32 + }, + { + "name": "EXTI13", + "number": 33 + }, + { + "name": "EXTI14", + "number": 34 + }, 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"name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + 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"IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE11", + "signal": "TX", + "af": 6 + }, + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FMC", + "address": 1208107008, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR3", + "field": "FMCSEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "FMCEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "FMCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "D7", + "af": 12 + }, + { + "pin": "PA0", + "signal": "DA7", + "af": 12 + }, + { + "pin": "PA1", + "signal": "D6", + "af": 12 + }, + { + "pin": "PA1", + "signal": "DA6", + "af": 12 + }, + { + "pin": "PA10", + "signal": "D2", + "af": 12 + }, + { + "pin": "PA10", + "signal": "DA2", + "af": 12 + }, + { + "pin": "PA11", + "signal": "D1", + "af": 12 + }, + { + "pin": "PA11", + "signal": "DA1", + "af": 12 + }, + { + "pin": "PA12", + "signal": "D0", + "af": 12 + }, + { + "pin": "PA12", + "signal": "DA0", + "af": 12 + }, + { + "pin": "PA15", + "signal": "D15", + "af": 12 + }, + { + "pin": "PA15", + "signal": "DA15", + "af": 12 + }, + { + "pin": "PA2", + "signal": "D5", + "af": 12 + }, + { + "pin": "PA2", + "signal": "DA5", + "af": 12 + }, + { + "pin": "PA3", + "signal": "A17", + "af": 12 + }, + { + "pin": "PA3", + "signal": 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"D18", + "af": 12 + }, + { + "pin": "PP3", + "signal": "D19", + "af": 12 + }, + { + "pin": "PP4", + "signal": "D20", + "af": 12 + }, + { + "pin": "PP5", + "signal": "D21", + "af": 12 + }, + { + "pin": "PP6", + "signal": "D22", + "af": 12 + }, + { + "pin": "PP7", + "signal": "D23", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE1", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PF1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PG14", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM1" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF1", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPTIM5", + "address": 1174417408, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM5EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM5RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE2", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PE3", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF0", + "signal": "OUT", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM5" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA7", + "signal": "B1", + "af": 14 + }, + { + "pin": "PA7", + "signal": "R4", + "af": 10 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PD9", + "signal": "R1", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF6", + "signal": "DE", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PF9", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PG0", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG0", + "signal": "VSYNC", + "af": 10 + }, + { + "pin": "PG1", + "signal": "G1", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG11", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG12", + "signal": "G0", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG15", + "signal": "B0", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG4", + "signal": "B0", + "af": 14 + }, + { + "pin": "PG5", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG6", + "signal": "B3", + "af": 14 + }, + { + "pin": "PG8", + "signal": "G7", + "af": 14 + }, + { + "pin": "PG9", + "signal": "R7", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + }, + { + "pin": "PO2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PO4", + "signal": "B4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MCE1", + "address": 1208137728, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE1EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE1" + } + ] + }, + { + "name": "MCE2", + "address": 1208138752, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE2EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE2" + } + ] + }, + { + "name": "MCE3", + "address": 1208139776, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE3EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE3" + } + ] + }, + { + "name": "MCE4", + "address": 1208147968, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE4EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "MCE4RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE4" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PKA", + "address": 1140989952, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "PKAEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "PKARST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "PKA" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC6", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC7", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "DE", + "af": 9 + }, + { + "pin": "PD11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD5", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PD9", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE6", + "signal": "D1", + "af": 10 + }, + { + "pin": "PE6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF0", + "signal": "D9", + "af": 9 + }, + { + "pin": "PF1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG1", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG15", + "signal": "D4", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PG6", + "signal": "D12", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PH9", + "signal": "D6", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD5", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH3", + "af": 13 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PG5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG6", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF0", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PF1", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + }, + { + "pin": "PG8", + "signal": "RX", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART2", + "address": 1073759232, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA1", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA2", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF2", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF2", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PF3", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF4", + "signal": "CK", + "af": 7 + }, + { + "pin": "PF6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PG14", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG3", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG5", + "signal": "NSS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART2" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PD9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG15", + "signal": "CK", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PH9", + "signal": "CK", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USART6", + "address": 1107301376, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART6EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART6RST" + } + }, + "pins": [ + { + "pin": "PC6", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC9", + "signal": "RX", + "af": 7 + }, + { + "pin": "PD3", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD4", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG14", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG6", + "signal": "CK", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART6" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + }, + { + "pin": "PO0", + "signal": "P1_NCS1", + "af": 9 + }, + { + "pin": "PO1", + "signal": "P1_NCS2", + "af": 9 + }, + { + "pin": "PO2", + "signal": "P1_DQS0", + "af": 9 + }, + { + "pin": "PO4", + "signal": "P1_CLK", + "af": 9 + }, + { + "pin": "PO5", + "signal": "P1_NCLK", + "af": 9 + }, + { + "pin": "PP0", + "signal": "P1_IO0", + "af": 9 + }, + { + "pin": "PP1", + "signal": "P1_IO1", + "af": 9 + }, + { + "pin": "PP2", + "signal": "P1_IO2", + "af": 9 + }, + { + "pin": "PP3", + "signal": "P1_IO3", + "af": 9 + }, + { + "pin": "PP4", + "signal": "P1_IO4", + "af": 9 + }, + { + "pin": "PP5", + "signal": "P1_IO5", + "af": 9 + }, + { + "pin": "PP6", + "signal": "P1_IO6", + "af": 9 + }, + { + "pin": "PP7", + "signal": "P1_IO7", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 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"name": "MCE3", + "number": 44 + }, + { + "name": "MCE4", + "number": 45 + }, + { + "name": "ADC1_2", + "number": 46 + }, + { + "name": "CSI", + "number": 47 + }, + { + "name": "DCMIPP", + "number": 48 + }, + { + "name": "PAHB_ERR", + "number": 52 + }, + { + "name": "NPU0", + "number": 53 + }, + { + "name": "NPU1", + "number": 54 + }, + { + "name": "NPU2", + "number": 55 + }, + { + "name": "NPU3", + "number": 56 + }, + { + "name": "CACHEAXI", + "number": 57 + }, + { + "name": "LTDC_LO", + "number": 58 + }, + { + "name": "LTDC_LO_ERR", + "number": 59 + }, + { + "name": "DMA2D", + "number": 60 + }, + { + "name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA3" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA7" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB3" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PC1" + }, + { + "name": "PC6" + }, + { + "name": "PC7" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD0" + }, + { + "name": "PD1" + }, + { + "name": "PD2" + }, + { + "name": "PD3" + }, + { + "name": "PD4" + }, + { + "name": "PD5" + }, + { + "name": "PD6" + }, + { + "name": "PD7" + }, + { + "name": "PD8" + }, + { + "name": "PD9" + }, + { + "name": "PD10" + }, + { + "name": "PD11" + }, + { + "name": "PD12" + }, + { + "name": "PD14" + }, + { + "name": "PD15" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE5" + }, + { + "name": "PE6" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": "PE9" + }, + { + "name": "PE10" + }, + { + "name": "PE11" + }, + { + "name": "PE12" + }, + { + "name": "PE13" + }, + { + "name": "PE14" + }, + { + "name": "PE15" + }, + { + "name": "PF0" + }, + { + "name": "PF1" + }, + { + "name": "PF2" + }, + { + "name": "PF3" + }, + { + "name": "PF4" + }, + { + "name": "PF5" + }, + { + "name": "PF6" + }, + { + "name": "PF7" + }, + { + "name": "PF8" + }, + { + "name": "PF9" + }, + { + "name": "PF10" + }, + { + "name": "PF11" + }, + { + "name": "PF12" + }, + { + "name": "PF13" + }, + { + "name": "PF14" + }, + { + "name": "PF15" + }, + { + "name": "PG0" + }, + { + "name": "PG1" + }, + { + "name": "PG2" + }, + { + "name": "PG3" + }, + { + "name": "PG4" + }, + { + "name": "PG5" + }, + { + "name": "PG6" + }, + { + "name": "PG8" + }, + { + "name": "PG9" + }, + { + "name": "PG10" + }, + { + "name": "PG11" + }, + { + "name": "PG12" + }, + { + "name": "PG13" + }, + { + "name": "PG14" + }, + { + "name": "PG15" + }, + { + "name": "PH0" + }, + { + "name": "PH1" + }, + { + "name": "PH2" + }, + { + "name": "PH9" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + }, + { + "name": "PO0" + }, + { + "name": "PO1" + }, + { + "name": "PO2" + }, + { + "name": "PO4" + }, + { + "name": "PO5" + }, + { + "name": "PP0" + }, + { + "name": "PP1" + }, + { + "name": "PP2" + }, + { + "name": "PP3" + }, + { + "name": "PP4" + }, + { + "name": "PP5" + }, + { + "name": "PP6" + }, + { + "name": "PP7" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N657I0.json b/data/chips/STM32N657I0.json new file mode 100644 index 0000000..9f2a235 --- /dev/null +++ b/data/chips/STM32N657I0.json @@ -0,0 +1,9813 @@ +{ + "name": "STM32N657I0", + "family": "STM32N6", + "line": "STM32N6x7", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N657I0HxQ", + "package": "VFBGA178", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PE6" + ] + }, + { + "position": "A11", + "signals": [ + "PD6" + ] + }, + { + "position": "A12", + "signals": [ + "PD0" + ] + }, + { + "position": "A13", + "signals": [ + "PD3" + ] + }, + { + "position": "A14", + "signals": [ + "VSS" + ] + }, + { + "position": "A2", + "signals": [ + "OTG2_HSDM" + ] + }, + { + "position": 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"signal": "SDNWE", + "af": 12 + }, + { + "pin": "PE12", + "signal": "SDNRAS", + "af": 12 + }, + { + "pin": "PE13", + "signal": "SDNCAS", + "af": 12 + }, + { + "pin": "PE14", + "signal": "NWE", + "af": 14 + }, + { + "pin": "PE14", + "signal": "SDNE0", + "af": 12 + }, + { + "pin": "PE15", + "signal": "SDCKE0", + "af": 12 + }, + { + "pin": "PE2", + "signal": "D11", + "af": 12 + }, + { + "pin": "PE2", + "signal": "DA11", + "af": 12 + }, + { + "pin": "PE3", + "signal": "D12", + "af": 12 + }, + { + "pin": "PE3", + "signal": "DA12", + "af": 12 + }, + { + "pin": "PE5", + "signal": "SDNE1", + "af": 12 + }, + { + "pin": "PE6", + "signal": "SDCKE1", + "af": 12 + }, + { + "pin": "PE7", + "signal": "A20", + "af": 14 + }, + { + "pin": "PE7", + "signal": "A4", + "af": 12 + }, + { + "pin": "PE8", + "signal": "A12", + "af": 12 + }, + { + "pin": "PE9", + "signal": "A14", + "af": 12 + }, + { + "pin": "PE9", + "signal": "BA0", + "af": 12 + }, + { + "pin": "PF2", + "signal": "NWAIT", + "af": 12 + }, + { + "pin": "PF3", + "signal": "NL", + "af": 12 + }, + { + "pin": "PF5", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PF8", + "signal": "NWE", + "af": 12 + }, + { + "pin": "PG1", + "signal": "A19", + "af": 12 + }, + { + "pin": "PG10", + "signal": "A16", + "af": 12 + }, + { + "pin": "PG10", + "signal": "CLE", + "af": 12 + }, + { + "pin": "PG12", + "signal": "A18", + "af": 12 + }, + { + "pin": "PG13", + "signal": "NE1", + "af": 12 + }, + { + "pin": "PG14", + "signal": "NCE", + "af": 10 + }, + { + "pin": "PG14", + "signal": "NE2", + "af": 12 + }, + { + "pin": "PG15", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PG2", + "signal": "A21", + "af": 12 + }, + { + "pin": "PG8", + "signal": "A20", + "af": 12 + }, + { + "pin": "PH2", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D9", + "af": 14 + }, + { + "pin": "PH9", + "signal": "DA9", + "af": 14 + }, + { + "pin": "PN0", + "signal": "A25", + "af": 12 + }, + { + "pin": "PN1", + "signal": "A24", + "af": 12 + }, + { + "pin": "PN2", + "signal": "A23", + "af": 12 + }, + { + "pin": "PN3", + "signal": "A22", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA7", + "signal": "B1", + "af": 14 + }, + { + "pin": "PA7", + "signal": "R4", + "af": 10 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB2", + "signal": "B2", + "af": 14 + }, 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"PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG0", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG0", + "signal": "VSYNC", + "af": 10 + }, + { + "pin": "PG1", + "signal": "G1", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG12", + "signal": "G0", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG15", + "signal": "B0", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PG8", + "signal": "G7", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MCE1", + "address": 1208137728, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE1EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE1" + } + ] + }, + { + "name": "MCE2", + "address": 1208138752, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE2EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE2" + } + ] + }, + { + "name": "MCE3", + "address": 1208139776, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE3EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE3" + } + ] + }, + { + "name": "MCE4", + "address": 1208147968, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE4EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "MCE4RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE4" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PKA", + "address": 1140989952, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "PKAEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "PKARST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "PKA" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC6", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC7", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "DE", + "af": 9 + }, + { + "pin": "PD11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD13", + "signal": "D13", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD5", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PD9", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE6", + "signal": "D1", + "af": 10 + }, + { + "pin": "PE6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG1", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG15", + "signal": "D4", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PH9", + "signal": "D6", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": 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+ "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB2", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB2", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PA8", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA9", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB0", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PB12", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PB2", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB3", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PB7", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PC10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC12", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD10", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PD2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PD4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PD5", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PD6", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PD7", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE10", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH3", + "af": 13 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD13", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": 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"interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ETH1" + }, + { + "signal": "WKUP", + "interrupt": "ETH1" + } + ] + }, + { + "name": "EXTI", + "address": 1174556672, + "registers": { + "kind": "exti", + "version": "v1", + "block": "EXTI" + }, + "interrupts": [ + { + "signal": "EXTI0", + "interrupt": "EXTI0" + }, + { + "signal": "EXTI1", + "interrupt": "EXTI1" + }, + { + "signal": "EXTI10", + "interrupt": "EXTI10" + }, + { + "signal": "EXTI11", + "interrupt": "EXTI11" + }, + { + "signal": "EXTI12", + "interrupt": "EXTI12" + }, + { + "signal": "EXTI13", + "interrupt": "EXTI13" + }, + { + "signal": "EXTI14", + "interrupt": "EXTI14" + }, + { + "signal": "EXTI15", + "interrupt": "EXTI15" + }, + { + "signal": "EXTI2", + "interrupt": "EXTI2" + }, + { + "signal": "EXTI3", + "interrupt": "EXTI3" + }, + { + "signal": "EXTI4", + "interrupt": "EXTI4" + }, + { + "signal": "EXTI5", + "interrupt": "EXTI5" + }, + { + "signal": "EXTI6", + "interrupt": "EXTI6" + }, + { + "signal": "EXTI7", + "interrupt": "EXTI7" + }, + { + "signal": "EXTI8", + "interrupt": "EXTI8" + }, + { + "signal": "EXTI9", + "interrupt": "EXTI9" + } + ] + }, + { + "name": "FDCAN1", + "address": 1073782784, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 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+ } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB9", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PD13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE1", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PF1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PG14", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM1" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF1", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPTIM3", + "address": 1174415360, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM3EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM3RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA1", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PA2", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PA6", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PF4", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF6", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM3" + } + ] + }, + { + "name": "LPTIM5", + "address": 1174417408, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM5EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM5RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE2", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PE3", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF0", + "signal": "OUT", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM5" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA7", + "signal": "B1", + "af": 14 + }, + { + "pin": "PA7", + "signal": "R4", + "af": 10 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB1", + "signal": "R1", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB13", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PB14", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PB15", + "signal": "G4", + "af": 14 + }, + { + "pin": "PB2", + "signal": "B2", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD13", + "signal": "R6", + "af": 14 + }, + { + "pin": "PD15", + "signal": "R2", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PD9", + "signal": "R1", + "af": 14 + }, + { + "pin": "PE11", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + 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"enable": { + "register": "AHB5ENR", + "field": "MCE2EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE2" + } + ] + }, + { + "name": "MCE3", + "address": 1208139776, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE3EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE3" + } + ] + }, + { + "name": "MCE4", + "address": 1208147968, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE4EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "MCE4RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE4" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + 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"FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PKA", + "address": 1140989952, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "PKAEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "PKARST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "PKA" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA4", + "signal": "D3", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + 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"GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PB8", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD13", + "signal": "SCK_A", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + 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"pin": "PC7", + "signal": "D7", + "af": 11 + }, + { + "pin": "PD2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PD5", + "signal": "D7", + "af": 11 + }, + { + "pin": "PG8", + "signal": "D1", + "af": 11 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC2" + } + ] + }, + { + "name": "SPDIFRX1", + "address": 1073758208, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPDIFRX1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPDIFRX1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPDIFRX1RST" + } + }, + "pins": [ + { + "pin": "PB15", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PB8", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PB9", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PD10", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PD12", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PD8", + "signal": "IN1", + "af": 8 + } + ] + }, + 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"pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD11", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PD6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PD7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF2", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PG10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG8", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG8", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PP8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PP9", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI2" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB2", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB2", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PC7", + "signal": "I2S_MCK", + "af": 6 + }, + { + "pin": "PD7", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PD7", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA4", + "signal": "MOSI", + "af": 5 + }, + { + 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"APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PB13", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB13", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PF6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD4", + "signal": "IN7" + }, + { + "pin": "PD4", + "signal": "OUT8" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PD9", + "signal": "IN5" + }, + { + "pin": "PD9", + "signal": "OUT6" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM1", + "address": 1107296256, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PA12", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PA6", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PA7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": 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"signal": "CH2N", + "af": 1 + }, + { + "pin": "PE11", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PE12", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PE13", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PE14", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PE15", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PE2", + "signal": "CH2N", + "af": 13 + }, + { + "pin": "PE7", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE8", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE9", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PF2", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PF5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH3", + "af": 13 + }, + { + "pin": "PF7", + "signal": "CH2N", + "af": 1 + }, + { + "pin": "PG0", + "signal": "CH4N", + "af": 1 + }, + { + "pin": "PG10", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG15", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PG4", + "signal": "BKIN2", + "af": 1 + }, + { + "pin": "PG5", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PG8", + "signal": "CH3N", + "af": 1 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG6", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PB1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + 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"register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + 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"GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA3" + }, + { + "name": "PA4" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA7" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB1" + }, + { + "name": "PB2" + }, + { + "name": "PB3" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB8" + }, + { + "name": "PB9" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PB13" + }, + { + "name": "PB14" + }, + { + "name": "PB15" + }, + { + "name": "PC1" + }, + { + "name": "PC6" + }, + { + "name": "PC7" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD0" + }, + { + "name": "PD1" + }, + { + "name": "PD2" + }, + { + "name": "PD3" + }, + { + "name": "PD4" + }, + { + "name": "PD5" + }, + { + "name": "PD6" + }, + { + "name": "PD7" + }, + { + "name": "PD8" + }, + { + "name": "PD9" + }, + { + "name": "PD10" + }, + { + "name": "PD11" + }, + { + "name": "PD12" + }, + { + "name": "PD13" + }, + { + "name": "PD14" + }, + { + "name": "PD15" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE5" + }, + { + "name": "PE6" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": "PE9" + }, + { + "name": "PE10" + }, + { + "name": "PE11" + }, + { + "name": "PE12" + }, + { + "name": "PE13" + }, + { + "name": "PE14" + }, + { + "name": "PE15" + }, + { + "name": "PF0" + }, + { + "name": "PF1" + }, + { + "name": "PF2" + }, + { + "name": "PF3" + }, + { + "name": "PF4" + }, + { + "name": "PF5" + }, + { + "name": "PF6" + }, + { + "name": "PF7" + }, + { + "name": "PF8" + }, + { + "name": "PF9" + }, + { + "name": "PF10" + }, + { + "name": "PF11" + }, + { + "name": "PF12" + }, + { + "name": "PF13" + }, + { + "name": "PF14" + }, + { + "name": "PF15" + }, + { + "name": "PG0" + }, + { + "name": "PG1" + }, + { + "name": "PG2" + }, + { + "name": "PG3" + }, + { + "name": "PG4" + }, + { + "name": "PG5" + }, + { + "name": "PG6" + }, + { + "name": "PG8" + }, + { + "name": "PG9" + }, + { + "name": "PG10" + }, + { + "name": "PG11" + }, + { + "name": "PG12" + }, + { + "name": "PG13" + }, + { + "name": "PG14" + }, + { + "name": "PG15" + }, + { + "name": "PH0" + }, + { + "name": "PH1" + }, + { + "name": "PH2" + }, + { + "name": "PH9" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + }, + { + "name": "PO0" + }, + { + "name": "PO1" + }, + { + "name": "PO2" + }, + { + "name": "PO3" + }, + { + "name": "PO4" + }, + { + "name": "PO5" + }, + { + "name": "PP0" + }, + { + "name": "PP1" + }, + { + "name": "PP2" + }, + { + "name": "PP3" + }, + { + "name": "PP4" + }, + { + "name": "PP5" + }, + { + "name": "PP6" + }, + { + "name": "PP7" + }, + { + "name": "PP8" + }, + { + "name": "PP9" + }, + { + "name": "PP10" + }, + { + "name": "PP11" + }, + { + "name": "PP12" + }, + { + "name": "PP13" + }, + { + "name": "PP14" + }, + { + "name": "PP15" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N657X0.json b/data/chips/STM32N657X0.json new file mode 100644 index 0000000..36b74c9 --- /dev/null +++ b/data/chips/STM32N657X0.json @@ -0,0 +1,12228 @@ +{ + "name": "STM32N657X0", + "family": "STM32N6", + "line": "STM32N6x7", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N657X0HxQ", + "package": "VFBGA264", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PC4" + ] + }, + { + "position": "A11", + "signals": [ + "PE13" + ] + }, + { + "position": "A12", + "signals": [ + "PE15" + ] + }, + { + "position": "A13", + "signals": [ + "PD10" + ] + }, + { + "position": "A14", + "signals": [ + "PD1" + ] + }, + { + "position": "A15", + "signals": [ + "PE8" + ] + }, + { + "position": "A16", + "signals": [ + "PE9" + ] + }, + { + "position": "A17", + "signals": [ + "VSS" + ] + }, + { + "position": "A2", + "signals": [ + "PQ6" + ] + }, + { + "position": "A3", + "signals": [ + "OTG2_HSDM" + ] + }, + { + "position": "A4", + "signals": [ + "VDD33USB" + ] + }, + { + "position": "A5", + "signals": [ + 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"signal": "A8", + "af": 12 + }, + { + "pin": "PD2", + "signal": "A0", + "af": 12 + }, + { + "pin": "PD2", + "signal": "A16", + "af": 14 + }, + { + "pin": "PD2", + "signal": "CLE", + "af": 14 + }, + { + "pin": "PD3", + "signal": "A10", + "af": 12 + }, + { + "pin": "PD4", + "signal": "A11", + "af": 12 + }, + { + "pin": "PD5", + "signal": "D6", + "af": 12 + }, + { + "pin": "PD5", + "signal": "DA6", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A1", + "af": 12 + }, + { + "pin": "PD6", + "signal": "A17", + "af": 14 + }, + { + "pin": "PD6", + "signal": "ALE", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A18", + "af": 14 + }, + { + "pin": "PD7", + "signal": "A2", + "af": 12 + }, + { + "pin": "PD8", + "signal": "NBL0", + "af": 12 + }, + { + "pin": "PD9", + "signal": "SDCLK", + "af": 12 + }, + { + "pin": "PE0", + "signal": "D9", + "af": 12 + }, + { + "pin": "PE0", + "signal": "DA9", + "af": 12 + }, + { + "pin": "PE1", + "signal": "D10", + "af": 12 + }, + { + "pin": "PE1", + "signal": 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"PE9", + "signal": "A14", + "af": 12 + }, + { + "pin": "PE9", + "signal": "BA0", + "af": 12 + }, + { + "pin": "PF2", + "signal": "NWAIT", + "af": 12 + }, + { + "pin": "PF3", + "signal": "NL", + "af": 12 + }, + { + "pin": "PF5", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PF8", + "signal": "NWE", + "af": 12 + }, + { + "pin": "PG1", + "signal": "A19", + "af": 12 + }, + { + "pin": "PG10", + "signal": "A16", + "af": 12 + }, + { + "pin": "PG10", + "signal": "CLE", + "af": 12 + }, + { + "pin": "PG12", + "signal": "A18", + "af": 12 + }, + { + "pin": "PG13", + "signal": "NE1", + "af": 12 + }, + { + "pin": "PG14", + "signal": "NCE", + "af": 10 + }, + { + "pin": "PG14", + "signal": "NE2", + "af": 12 + }, + { + "pin": "PG15", + "signal": "CLK", + "af": 12 + }, + { + "pin": "PG2", + "signal": "A21", + "af": 12 + }, + { + "pin": "PG8", + "signal": "A20", + "af": 12 + }, + { + "pin": "PG9", + "signal": "D8", + "af": 12 + }, + { + "pin": "PG9", + "signal": "DA8", + "af": 12 + }, + { + "pin": "PH2", + "signal": "NE3", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D9", + "af": 14 + }, + { + "pin": "PH9", + "signal": "DA9", + "af": 14 + }, + { + "pin": "PN0", + "signal": "A25", + "af": 12 + }, + { + "pin": "PN1", + "signal": "A24", + "af": 12 + }, + { + "pin": "PN2", + "signal": "A23", + "af": 12 + }, + { + "pin": "PN3", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO0", + "signal": "A22", + "af": 12 + }, + { + "pin": "PO1", + "signal": "A23", + "af": 12 + }, + { + "pin": "PO2", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO3", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO4", + "signal": "A24", + "af": 12 + }, + { + "pin": "PO4", + "signal": "NBL2", + "af": 14 + }, + { + "pin": "PO5", + "signal": "A25", + "af": 12 + }, + { + "pin": "PO5", + "signal": "NBL3", + "af": 14 + }, + { + "pin": "PP0", + "signal": "D16", + "af": 12 + }, + { + "pin": "PP1", + "signal": "D17", + "af": 12 + }, + { + "pin": "PP10", + "signal": "D26", + "af": 12 + }, + { + "pin": "PP11", + "signal": "D27", + "af": 12 + }, + { + "pin": "PP12", + "signal": "D28", + "af": 12 + }, + { + "pin": "PP13", + "signal": "D29", + "af": 12 + }, + { + "pin": "PP14", + "signal": "D30", + "af": 12 + }, + { + "pin": "PP15", + "signal": "D31", + "af": 12 + }, + { + "pin": "PP2", + "signal": "D18", + "af": 12 + }, + { + "pin": "PP3", + "signal": "D19", + "af": 12 + }, + { + "pin": "PP4", + "signal": "D20", + "af": 12 + }, + { + "pin": "PP5", + "signal": "D21", + "af": 12 + }, + { + "pin": "PP6", + "signal": "D22", + "af": 12 + }, + { + "pin": "PP7", + "signal": "D23", + "af": 12 + }, + { + "pin": "PP8", + "signal": "D24", + "af": 12 + }, + { + "pin": "PP9", + "signal": "D25", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "FMC" + } + ] + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PB3", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PB3", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PD10", + "signal": "TE", + "af": 13 + }, + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF6", + "signal": "FCKCAL", + "af": 12 + }, + { + "pin": "PF6", + "signal": "LCKCAL", + "af": 8 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C1", + "address": 1073763328, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C1RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C1_ER" + }, + { + "signal": "EV", + "interrupt": "I2C1_EV" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD14", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PD15", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD3", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PD4", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PD11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC1", + "signal": "SDA", + "af": 7 + }, + { + "pin": "PE5", + "signal": "SCL", + "af": 5 + }, + { + "pin": "PE6", + "signal": "SDA", + "af": 5 + }, + { + "pin": "PH9", + "signal": "SCL", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + 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+ }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM1", + "address": 1073751040, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "LPTIM1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "LPTIM1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PB9", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PD13", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PE1", + "signal": "IN2", + "af": 1 + }, + { + "pin": "PE4", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PF1", + "signal": "CH2", + "af": 1 + }, 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}, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB4", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB5", + "signal": "OUT", + "af": 3 + }, + { + "pin": "PC0", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM4" + } + ] + }, + { + "name": "LPTIM5", + "address": 1174417408, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM5EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM5RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PE2", + "signal": "IN1", + "af": 1 + }, + { + "pin": "PE3", + "signal": "ETR", + "af": 1 + }, + { + "pin": "PF0", + "signal": "OUT", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM5" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 3 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": 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"field": "MCE1EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE1" + } + ] + }, + { + "name": "MCE2", + "address": 1208138752, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE2EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE2" + } + ] + }, + { + "name": "MCE3", + "address": 1208139776, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE3EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE3" + } + ] + }, + { + "name": "MCE4", + "address": 1208147968, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE4EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "MCE4RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE4" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PB3", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PC0", + "signal": "CKI1", + "af": 4 + }, + { + "pin": "PC2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PD10", + "signal": "CKI3", + "af": 4 + }, + { + "pin": "PD12", + "signal": "SDI3", + "af": 4 + }, + { + "pin": "PD2", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE11", + "signal": "CKI5", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + 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"pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + }, + { + "pin": "PD2", + "signal": "MDC", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PKA", + "address": 1140989952, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "PKAEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "PKARST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "PKA" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA4", + "signal": "D3", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB14", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PB8", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PC0", + "signal": "DE", + "af": 9 + }, + { + "pin": "PC1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC2", + "signal": "D13", + "af": 9 + }, + { + "pin": "PC3", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC5", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC6", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC7", + "signal": "D1", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD0", + "signal": "DE", + "af": 9 + }, + { + "pin": "PD11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PD12", + "signal": "D12", + "af": 9 + }, + { + "pin": "PD13", + "signal": "D13", + "af": 9 + }, + { + "pin": "PD3", + "signal": "D14", + "af": 9 + }, + { + "pin": "PD4", + "signal": "D9", + "af": 9 + }, + { + "pin": "PD5", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PD7", + "signal": "D0", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PD9", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE4", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE5", + "signal": "D5", + "af": 9 + }, + { + "pin": "PE6", + "signal": "D1", + "af": 10 + }, + { + "pin": "PE6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF0", + "signal": "D9", + "af": 9 + }, + { + "pin": "PF1", + "signal": "D7", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG1", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG15", + "signal": "D4", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PG6", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG7", + "signal": "D13", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PH9", + "signal": "D6", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + }, + { + "pin": "PD2", + "signal": "WKUP4" + }, + { + "pin": "PG8", + "signal": "PVD_IN" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PB2", + "signal": "OUT2", + "af": 0 + }, + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + }, + { + "pin": "PG8", + "signal": "REFIN", + "af": 0 + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PC2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PC2", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PD12", + "signal": "D3", + "af": 2 + }, + { + "pin": "PD2", + "signal": "D1", + "af": 2 + }, + { + "pin": "PD2", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG1", + "signal": "SCK_B", + "af": 6 + }, + { + "pin": "PG12", + "signal": "MCLK_B", + "af": 6 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + }, + { + "pin": "PG7", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PG8", + "signal": "SCK_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB3", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PB8", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PC5", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PD10", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PD13", + "signal": "SCK_A", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PQ2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PQ5", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PQ6", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PQ7", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SDMMC1", + "address": 1208119296, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC1SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC1RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CDIR", + "af": 12 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 10 + }, + { + "pin": "PC10", + "signal": "D2", + "af": 10 + }, + { + "pin": "PC11", + "signal": "D3", + "af": 10 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 10 + }, + { + "pin": "PC6", + "signal": "D0DIR", + "af": 12 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 10 + }, + { + "pin": "PC7", + "signal": "D123DIR", + "af": 12 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 10 + }, + { + "pin": "PC8", + "signal": "D0", + "af": 10 + }, + { + "pin": "PC9", + "signal": "D1", + "af": 10 + }, + { + "pin": "PD11", + "signal": "D0", + "af": 10 + }, + { + "pin": "PE15", + "signal": "D0", + "af": 10 + }, + { + "pin": "PH2", + "signal": "CMD", + "af": 10 + }, + { + "pin": "PH9", + "signal": "CKIN", + "af": 12 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC1" + } + ] + }, + { + "name": "SDMMC2", + "address": 1208117248, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR8", + "field": "SDMMC2SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "SDMMC2EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "SDMMC2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CMD", + "af": 11 + }, + { + "pin": "PB13", + "signal": "D6", + "af": 11 + }, + { + "pin": "PB4", + "signal": "D3", + "af": 11 + }, + { + "pin": "PB8", + "signal": "D0", + "af": 11 + }, + { + "pin": "PB9", + "signal": "D2", + "af": 11 + }, + { + "pin": "PC0", + "signal": "D2", + "af": 11 + }, + { + "pin": "PC1", + "signal": "D5", + "af": 11 + }, + { + "pin": "PC2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PC3", + "signal": "CMD", + "af": 11 + }, + { + "pin": "PC4", + "signal": "D0", + "af": 11 + }, + { + "pin": "PC5", + "signal": "D1", + "af": 11 + }, + { + "pin": "PC6", + "signal": "D6", + "af": 11 + }, + { + "pin": "PC7", + "signal": "D7", + "af": 11 + }, + { + "pin": "PD2", + "signal": "CK", + "af": 11 + }, + { + "pin": "PD5", + "signal": "D7", + "af": 11 + }, + { + "pin": "PE4", + "signal": "D3", + "af": 11 + }, + { + "pin": "PG8", + "signal": "D1", + "af": 11 + }, + { + "pin": "PH9", + "signal": "D4", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SDMMC2" + } + ] + }, + { + "name": "SPDIFRX1", + "address": 1073758208, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPDIFRX1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPDIFRX1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPDIFRX1RST" + } + }, + "pins": [ + { + "pin": "PB15", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PB8", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PB9", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PC3", + "signal": "IN0", + "af": 8 + }, + { + "pin": "PD10", + "signal": "IN2", + "af": 8 + }, + { + "pin": "PD12", + "signal": "IN3", + "af": 8 + }, + { + "pin": "PD8", + "signal": "IN1", + "af": 8 + }, + { + "pin": "PE4", + "signal": "IN1", + "af": 8 + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PA7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB8", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PC0", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC0", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PC3", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PC3", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PC5", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC5", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PD10", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 10 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI2", + "address": 1073756160, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI2RST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA9", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PB10", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PB12", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PB12", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PB4", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PC1", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PC1", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PC4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PC4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PC6", + "signal": "I2S_MCK", + "af": 5 + }, + { + "pin": "PD11", + "signal": "I2S_SDI", + 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"register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE11", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 6 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA4", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PD4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF6", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PG1", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PG12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG15", + "signal": "RDY", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PH5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PH6", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PH7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PH8", + "signal": "MISO", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PA7", + "signal": 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{ + "signal": "BRK", + "interrupt": "TIM1_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM1_CC" + }, + { + "signal": "COM", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM1_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM1_UP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM12", + "address": 1073747968, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM12EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM12RST" + } + }, + "pins": [ + { + "pin": "PC4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PG8", + "signal": "CH2", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM12" + }, + { + "signal": "CC", + "interrupt": "TIM12" + }, + { + "signal": "COM", + "interrupt": "TIM12" + }, + { + "signal": "TRG", + "interrupt": "TIM12" + }, + { + "signal": "UP", + "interrupt": "TIM12" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + }, + { + "pin": "PG1", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PA7", + "signal": "CH1", + "af": 11 + }, + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PD2", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PD6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PD7", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PF6", + "signal": "CH2", + "af": 4 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM16", + "address": 1107313664, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM16EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM16RST" + } + }, + "pins": [ + { + "pin": "PA3", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PB4", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC7", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PE5", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PF10", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PG1", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PH9", + "signal": "CH1", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM16" + }, + { + "signal": "CC", + "interrupt": "TIM16" + }, + { + "signal": "COM", + "interrupt": "TIM16" + }, + { + "signal": "TRG", + "interrupt": "TIM16" + }, + { + "signal": "UP", + "interrupt": "TIM16" + } + ] + }, + { + "name": "TIM17", + "address": 1107314688, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM17EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM17RST" + } + }, + "pins": [ + { + "pin": "PB5", + "signal": "BKIN", + "af": 1 + }, + { + "pin": "PC1", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PE6", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG12", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PG2", + "signal": "CH1N", + "af": 1 + }, + { + "pin": "PG6", + "signal": "BKIN", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM17" + }, + { + "signal": "CC", + "interrupt": "TIM17" + }, + { + "signal": "COM", + "interrupt": "TIM17" + }, + { + "signal": "TRG", + "interrupt": "TIM17" + }, + { + "signal": "UP", + "interrupt": "TIM17" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PC0", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PB1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM4", + "address": 1073743872, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM4RST" + } + }, + "pins": [ + { + "pin": "PC1", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PD13", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PE5", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PE6", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PF0", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF1", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PG13", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PH9", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM4" + }, + { + "signal": "CC", + "interrupt": "TIM4" + }, + { + "signal": "COM", + "interrupt": "TIM4" + }, + { + "signal": "TRG", + "interrupt": "TIM4" + }, + { + "signal": "UP", + "interrupt": "TIM4" + } + ] + }, + { + "name": "TIM5", + "address": 1073744896, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM5RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PF4", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PF6", + "signal": "CH4", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM5" + }, + { + "signal": "CC", + "interrupt": "TIM5" + }, + { + "signal": "COM", + "interrupt": "TIM5" + }, + { + "signal": "TRG", + "interrupt": "TIM5" + }, + { + "signal": "UP", + "interrupt": "TIM5" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM8", + "address": 1107297280, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM8EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM8RST" + } + }, + "pins": [ + { + "pin": "PB13", + "signal": "CH3N", + "af": 2 + }, + { + "pin": "PB14", + "signal": "CH4N", + "af": 2 + }, + { + "pin": "PG14", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PQ0", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PQ1", + "signal": "BKIN", + "af": 2 + }, + { + "pin": "PQ2", + "signal": "BKIN2", + "af": 2 + }, + { + "pin": "PQ3", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PQ4", + "signal": "CH1N", + "af": 2 + }, + { + "pin": "PQ5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PQ6", + "signal": "CH2N", + "af": 2 + }, + { + "pin": "PQ7", + "signal": "CH3", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM8_BRK" + }, + { + "signal": "CC", + "interrupt": "TIM8_CC" + }, + { + "signal": "COM", + "interrupt": "TIM8_TRG_COM" + }, + { + "signal": "TRG", + "interrupt": "TIM8_TRG_COM" + }, + { + "signal": "UP", + "interrupt": "TIM8_UP" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PB1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PC6", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PC7", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PC4", + "signal": "DE", + "af": 8 + }, + { + "pin": "PC4", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PD0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PG8", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH9", + "signal": "RX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 11 + }, + { + "pin": "PE6", + "signal": "TX", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA3", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PC0", + "signal": "RX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG1", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PG11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PH3", + "signal": "TX", + "af": 8 + }, + { + "pin": "PH4", + "signal": "TX", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UART8", + "address": 1073773568, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART8EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART8RST" + } + }, + "pins": [ + { + "pin": "PE0", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF0", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF1", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART8" + } + ] + }, + { + "name": "UART9", + "address": 1107302400, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "UART9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "UART9RST" + } + }, + "pins": [ + { + "pin": "PD0", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PD13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PF0", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF1", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PG0", + "signal": "RX", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART9" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD10", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD11", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PD12", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PD13", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF0", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PF1", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA7", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB3", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC4", + "signal": "TX", + "af": 4 + }, + { + "pin": "PE5", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE6", + "signal": "RX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + 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}, + { + "name": "PQ4" + }, + { + "name": "PQ5" + }, + { + "name": "PQ6" + }, + { + "name": "PQ7" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32N657Z0.json b/data/chips/STM32N657Z0.json new file mode 100644 index 0000000..6550f8b --- /dev/null +++ b/data/chips/STM32N657Z0.json @@ -0,0 +1,6694 @@ +{ + "name": "STM32N657Z0", + "family": "STM32N6", + "line": "STM32N6x7", + "die": "DIE486", + "device_id": 1158, + "packages": [ + { + "name": "STM32N657Z0HxQ", + "package": "VFBGA142", + "pins": [ + { + "position": "A1", + "signals": [ + "PDR_ON" + ] + }, + { + "position": "A10", + "signals": [ + "PC12" + ] + }, + { + "position": "A11", + "signals": [ + "PE13" + ] + }, + { + "position": "A12", + "signals": [ + "PE7" + ] + }, + { + "position": "A13", + "signals": [ + "PE9" + ] + }, + { + "position": "A14", + "signals": [ + "PE0" + ] + }, + { + "position": "A15", + "signals": [ + "VSS" + ] + }, + { + "position": "A2", + "signals": [ + "OTG2_ID" + ] + }, + { + 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"pins": [ + { + "pin": "PA0", + "signal": "INN1" + }, + { + "pin": "PA0", + "signal": "INP0" + }, + { + "pin": "PA1", + "signal": "INP1" + }, + { + "pin": "PA10", + "signal": "INN10" + }, + { + "pin": "PA10", + "signal": "INP11" + }, + { + "pin": "PA11", + "signal": "INN11" + }, + { + "pin": "PA11", + "signal": "INP12" + }, + { + "pin": "PA12", + "signal": "INN12" + }, + { + "pin": "PA12", + "signal": "INP13" + }, + { + "pin": "PA2", + "signal": "INP14" + }, + { + "pin": "PA6", + "signal": "INP3" + }, + { + "pin": "PA8", + "signal": "INP5" + }, + { + "pin": "PA9", + "signal": "INP10" + }, + { + "pin": "PB10", + "signal": "INN4" + }, + { + "pin": "PB10", + "signal": "INP8" + }, + { + "pin": "PB11", + "signal": "INP4" + }, + { + "pin": "PF11", + "signal": "INP2" + }, + { + "pin": "PF12", + "signal": "INN2" + }, + { + "pin": "PF12", + "signal": "INP6" + }, + { + "pin": "PF3", + "signal": "INP16" + }, + { + "pin": "PF4", + "signal": "INP18" + }, + { + "pin": "PF7", + "signal": "INN5" + }, + { + "pin": "PF7", + "signal": "INP9" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ADC1_2" + } + ] + }, + { + "name": "ADC12_COMMON", + "address": 1073881856 + }, + { + "name": "ADC2", + "address": 1073881344, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": { + "register": "CCIPR1", + "field": "ADC12SEL" + }, + "enable": { + "register": "AHB1ENR", + "field": "ADC12EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "ADC12RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "INN1" + }, + { + "pin": "PA0", + "signal": "INP0" + }, + { + "pin": "PA1", + "signal": "INP1" + }, + { + "pin": "PA10", + "signal": "INN10" + }, + { + "pin": "PA10", + "signal": "INP11" + }, + { + "pin": "PA11", + "signal": "INN11" + }, + { + "pin": "PA11", + "signal": "INP12" + }, + { + "pin": "PA12", + "signal": "INN12" + }, + { + "pin": "PA12", + "signal": "INP13" + }, + { + "pin": "PA2", + "signal": "INP14" + }, + { + "pin": "PA5", + "signal": "INP18" + }, + { + "pin": "PA6", + "signal": "INP3" + }, + { + "pin": "PA8", + "signal": "INP5" + }, + { + "pin": "PA9", + "signal": "INP10" + }, + { + "pin": "PB10", + "signal": "INN4" + }, + { + "pin": "PB10", + "signal": "INP8" + }, + { + "pin": "PB11", + "signal": "INP4" + }, + { + "pin": "PF13", + "signal": "INP2" + }, + { + "pin": "PF14", + "signal": "INN2" + }, + { + "pin": "PF14", + "signal": "INP6" + }, + { + "pin": "PF7", + "signal": "INN5" + }, + { + "pin": "PF7", + "signal": "INP9" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ADC1_2" + } + ] + }, + { + "name": "ADF1", + "address": 1107451904, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR1", + "field": "ADF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "ADF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "ADF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI0", + "af": 3 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 3 + }, + { + "pin": "PB7", + "signal": "SDI0", + "af": 3 + }, + { + "pin": "PE13", + "signal": "CCK0", + "af": 3 + }, + { + "pin": "PE14", + "signal": "CCK1", + "af": 3 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "ADF1_FLT0" + } + ] + }, + { + "name": "BSEC", + "address": 1174441984, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "BSECEN" + } + } + }, + { + "name": "CACHEAXI", + "address": 1208876032 + }, + { + "name": "CRC", + "address": 1174555648, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "CRCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "CRCRST" + } + } + }, + { + "name": "CRYP", + "address": 1140983808, + "registers": { + "kind": "cryp", + "version": "v2", + "block": "CRYP" + }, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "CRYPEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "CRYPRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "CRYP" + } + ] + }, + { + "name": "CSI", + "address": 1207984128, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "CSIEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "CSIRST" + } + } + }, + { + "name": "DBGMCU", + "address": 1140854784 + }, + { + "name": "DCMI", + "address": 1208124416, + "registers": { + "kind": "dcmi", + "version": "v1", + "block": "DCMI" + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PIXCLK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "VSYNC", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF4", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "DCMIPP", + "address": 1207967744, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR1", + "field": "DCMIPPSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "DCMIPPEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "DCMIPPRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PIXCLK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "VSYNC", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF4", + "signal": "HSYNC", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "CSI", + "interrupt": "CSI" + } + ] + }, + { + "name": "DMA2D", + "address": 1208094720, + "registers": { + "kind": "dma2d", + "version": "v1", + "block": "DMA2D" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "DMA2DEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "DMA2DRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DMA2D" + } + ] + }, + { + "name": "DTS", + "address": 1174446080, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "DTSEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "DTSRST" + } + } + }, + { + "name": "EXTI", + "address": 1174556672, + "registers": { + "kind": "exti", + "version": "v1", + "block": "EXTI" + }, + "interrupts": [ + { + "signal": "EXTI0", + "interrupt": "EXTI0" + }, + { + "signal": "EXTI1", + "interrupt": "EXTI1" + }, + { + "signal": "EXTI10", + "interrupt": "EXTI10" + }, + { + "signal": "EXTI11", + "interrupt": "EXTI11" + }, + { + "signal": "EXTI12", + "interrupt": "EXTI12" + }, + { + "signal": "EXTI13", + "interrupt": "EXTI13" + }, + { + "signal": "EXTI14", + "interrupt": "EXTI14" + }, + { + "signal": "EXTI15", + "interrupt": "EXTI15" + }, + { + "signal": "EXTI2", + "interrupt": "EXTI2" + }, + { + "signal": "EXTI3", + "interrupt": "EXTI3" + }, + { + "signal": "EXTI4", + "interrupt": "EXTI4" + }, + { + "signal": "EXTI5", + "interrupt": "EXTI5" + }, + { + "signal": "EXTI6", + "interrupt": "EXTI6" + }, + { + "signal": "EXTI7", + "interrupt": "EXTI7" + }, + { + "signal": "EXTI8", + "interrupt": "EXTI8" + }, + { + "signal": "EXTI9", + "interrupt": "EXTI9" + } + ] + }, + { + "name": "FDCAN1", + "address": 1073782784, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PA11", + "signal": "RX", + "af": 6 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 6 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 6 + }, + { + "pin": "PH2", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN1_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN1_IT1" + } + ] + }, + { + "name": "FDCAN2", + "address": 1073783808, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 6 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN2_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN2_IT1" + } + ] + }, + { + "name": "FDCAN3", + "address": 1073801216, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR3", + "field": "FDCANSEL" + }, + "enable": { + "register": "APB1HENR", + "field": "FDCANEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "FDCANRST" + } + }, + "pins": [ + { + "pin": "PE12", + "signal": "RX", + "af": 6 + }, + { + "pin": "PF2", + "signal": "TX", + "af": 6 + }, + { + "pin": "PF3", + "signal": "RX", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "IT0", + "interrupt": "FDCAN3_IT0" + }, + { + "signal": "IT1", + "interrupt": "FDCAN3_IT1" + } + ] + }, + { + "name": "FDCANRAM1", + "address": 1073790976, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM2", + "address": 1073791824, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "FDCANRAM3", + "address": 1073792672, + "registers": { + "kind": "fdcanram", + "version": "v1", + "block": "FDCANRAM" + } + }, + { + "name": "GFXMMU", + "address": 1208156160, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "GFXMMUEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "GFXMMURST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXMMU" + } + ] + }, + { + "name": "GFXTIM", + "address": 1207975936, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "GFXTIMEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "GFXTIMRST" + } + }, + "pins": [ + { + "pin": "PE14", + "signal": "FCKCAL", + "af": 2 + }, + { + "pin": "PE14", + "signal": "LCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "FCKCAL", + "af": 13 + }, + { + "pin": "PE15", + "signal": "LCKCAL", + "af": 2 + }, + { + "pin": "PF7", + "signal": "TE", + "af": 12 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "GFXTIM" + } + ] + }, + { + "name": "GPDMA1", + "address": 1073876992, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK1", + "kernel_clock": "HCLK1", + "enable": { + "register": "AHB1ENR", + "field": "GPDMA1EN" + }, + "reset": { + "register": "AHB1RSTR", + "field": "GPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "GPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "GPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "GPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "GPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "GPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "GPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "GPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "GPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "GPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "GPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "GPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "GPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "GPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "GPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "GPDMA1_Channel9" + } + ] + }, + { + "name": "GPIOA", + "address": 1174536192, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOAEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOARST" + } + } + }, + { + "name": "GPIOB", + "address": 1174537216, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOBEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOBRST" + } + } + }, + { + "name": "GPIOC", + "address": 1174538240, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOCEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOCRST" + } + } + }, + { + "name": "GPIOD", + "address": 1174539264, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIODEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIODRST" + } + } + }, + { + "name": "GPIOE", + "address": 1174540288, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOEEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOERST" + } + } + }, + { + "name": "GPIOF", + "address": 1174541312, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOFEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOFRST" + } + } + }, + { + "name": "GPIOG", + "address": 1174542336, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOGEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOGRST" + } + } + }, + { + "name": "GPIOH", + "address": 1174543360, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOHEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOHRST" + } + } + }, + { + "name": "GPION", + "address": 1174549504, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIONEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIONRST" + } + } + }, + { + "name": "GPIOO", + "address": 1174550528, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOOEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOORST" + } + } + }, + { + "name": "GPIOP", + "address": 1174551552, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOPEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOPRST" + } + } + }, + { + "name": "GPIOQ", + "address": 1174552576, + "registers": { + "kind": "gpio", + "version": "v2", + "block": "GPIO" + }, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "GPIOQEN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "GPIOQRST" + } + } + }, + { + "name": "GPU2D", + "address": 1208172544, + "interrupts": [ + { + "signal": "ER", + "interrupt": "GPU2D_ER" + } + ] + }, + { + "name": "HASH", + "address": 1140982784, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "HASHEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "HASHRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "HASH" + } + ] + }, + { + "name": "HPDMA1", + "address": 1208090624, + "registers": { + "kind": "gpdma", + "version": "v1", + "block": "GPDMA" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "HPDMA1EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "HPDMA1RST" + } + }, + "interrupts": [ + { + "signal": "CH0", + "interrupt": "HPDMA1_Channel0" + }, + { + "signal": "CH1", + "interrupt": "HPDMA1_Channel1" + }, + { + "signal": "CH10", + "interrupt": "HPDMA1_Channel10" + }, + { + "signal": "CH11", + "interrupt": "HPDMA1_Channel11" + }, + { + "signal": "CH12", + "interrupt": "HPDMA1_Channel12" + }, + { + "signal": "CH13", + "interrupt": "HPDMA1_Channel13" + }, + { + "signal": "CH15", + "interrupt": "HPDMA1_Channel15" + }, + { + "signal": "CH2", + "interrupt": "HPDMA1_Channel2" + }, + { + "signal": "CH3", + "interrupt": "HPDMA1_Channel3" + }, + { + "signal": "CH4", + "interrupt": "HPDMA1_Channel4" + }, + { + "signal": "CH5", + "interrupt": "HPDMA1_Channel5" + }, + { + "signal": "CH6", + "interrupt": "HPDMA1_Channel6" + }, + { + "signal": "CH7", + "interrupt": "HPDMA1_Channel7" + }, + { + "signal": "CH8", + "interrupt": "HPDMA1_Channel8" + }, + { + "signal": "CH9", + "interrupt": "HPDMA1_Channel9" + } + ] + }, + { + "name": "I2C2", + "address": 1073764352, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C2RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PB12", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C2_ER" + }, + { + "signal": "EV", + "interrupt": "I2C2_EV" + } + ] + }, + { + "name": "I2C3", + "address": 1073765376, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I2C3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I2C3RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PC8", + "signal": "SMBA", + "af": 4 + }, + { + "pin": "PC9", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C3_ER" + }, + { + "signal": "EV", + "interrupt": "I2C3_EV" + } + ] + }, + { + "name": "I2C4", + "address": 1174412288, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR4", + "field": "I2C4SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "I2C4EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "I2C4RST" + } + }, + "pins": [ + { + "pin": "PC10", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE13", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PE14", + "signal": "SDA", + "af": 4 + }, + { + "pin": "PE15", + "signal": "SMBA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I2C4_ER" + }, + { + "signal": "EV", + "interrupt": "I2C4_EV" + } + ] + }, + { + "name": "I3C1", + "address": 1073766400, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C1SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C1EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C1RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "SCL", + "af": 4 + }, + { + "pin": "PA6", + "signal": "SDA", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C1_ER" + }, + { + "signal": "EV", + "interrupt": "I3C1_EV" + } + ] + }, + { + "name": "I3C2", + "address": 1073767424, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR4", + "field": "I3C2SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "I3C2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "I3C2RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PA9", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PB10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PB11", + "signal": "SDA", + "af": 2 + }, + { + "pin": "PC10", + "signal": "SCL", + "af": 2 + }, + { + "pin": "PC11", + "signal": "SDA", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "ER", + "interrupt": "I3C2_ER" + }, + { + "signal": "EV", + "interrupt": "I3C2_EV" + } + ] + }, + { + "name": "ICACHE", + "address": 1208176640, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "ICACHE" + } + ] + }, + { + "name": "IWDG", + "address": 1174423552, + "registers": { + "kind": "iwdg", + "version": "v3", + "block": "IWDG" + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "IWDG" + } + ] + }, + { + "name": "JPEG", + "address": 1208102912, + "registers": { + "kind": "jpeg", + "version": "v1", + "block": "JPEG" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "JPEGEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "JPEGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "JPEG" + } + ] + }, + { + "name": "LPTIM2", + "address": 1174414336, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPTIM2EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPTIM2RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PB10", + "signal": "IN1", + "af": 3 + }, + { + "pin": "PB11", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PB12", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PE0", + "signal": "ETR", + "af": 3 + }, + { + "pin": "PE1", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF5", + "signal": "IN2", + "af": 3 + }, + { + "pin": "PG10", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PG13", + "signal": "IN1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPTIM2" + } + ] + }, + { + "name": "LPUART1", + "address": 1174408192, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "LPUART1EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "LPUART1RST" + }, + "stop_mode": "Stop2" + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 3 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 3 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 3 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "LPUART1" + } + ] + }, + { + "name": "LTDC", + "address": 1207963648, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": { + "register": "CCIPR4", + "field": "LTDCSEL" + }, + "enable": { + "register": "APB5ENR", + "field": "LTDCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "LTDCRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "G3", + "af": 14 + }, + { + "pin": "PA1", + "signal": "G2", + "af": 14 + }, + { + "pin": "PA10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PA11", + "signal": "B3", + "af": 14 + }, + { + "pin": "PA12", + "signal": "B2", + "af": 14 + }, + { + "pin": "PA15", + "signal": "R5", + "af": 14 + }, + { + "pin": "PA2", + "signal": "B7", + "af": 14 + }, + { + "pin": "PA5", + "signal": "CLK", + "af": 14 + }, + { + "pin": "PA6", + "signal": "B7", + "af": 12 + }, + { + "pin": "PA6", + "signal": "HSYNC", + "af": 14 + }, + { + "pin": "PA8", + "signal": "B6", + "af": 14 + }, + { + "pin": "PA9", + "signal": "B5", + "af": 14 + }, + { + "pin": "PB10", + "signal": "G7", + "af": 14 + }, + { + "pin": "PB11", + "signal": "G6", + "af": 14 + }, + { + "pin": "PB12", + "signal": "G5", + "af": 14 + }, + { + "pin": "PB4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PB5", + "signal": "R2", + "af": 14 + }, + { + "pin": "PC8", + "signal": "B0", + "af": 14 + }, + { + "pin": "PC9", + "signal": "B3", + "af": 14 + }, + { + "pin": "PD8", + "signal": "R7", + "af": 14 + }, + { + "pin": "PF10", + "signal": "R1", + "af": 14 + }, + { + "pin": "PF11", + "signal": "B0", + "af": 14 + }, + { + "pin": "PF14", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF15", + "signal": "G1", + "af": 14 + }, + { + "pin": "PF2", + "signal": "B1", + "af": 14 + }, + { + "pin": "PF3", + "signal": "R4", + "af": 14 + }, + { + "pin": "PF4", + "signal": "R3", + "af": 14 + }, + { + "pin": "PF5", + "signal": "G0", + "af": 14 + }, + { + "pin": "PF7", + "signal": "VSYNC", + "af": 14 + }, + { + "pin": "PF8", + "signal": "R6", + "af": 14 + }, + { + "pin": "PG10", + "signal": "G4", + "af": 14 + }, + { + "pin": "PG13", + "signal": "DE", + "af": 14 + }, + { + "pin": "PG14", + "signal": "B1", + "af": 14 + }, + { + "pin": "PG2", + "signal": "R0", + "af": 14 + }, + { + "pin": "PN10", + "signal": "B4", + "af": 14 + }, + { + "pin": "PN11", + "signal": "B6", + "af": 14 + } + ], + "interrupts": [ + { + "signal": "ERR", + "interrupt": "LTDC_LO_ERR" + }, + { + "signal": "LO", + "interrupt": "LTDC_LO" + } + ] + }, + { + "name": "MCE1", + "address": 1208137728, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE1EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE1" + } + ] + }, + { + "name": "MCE2", + "address": 1208138752, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE2EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE2" + } + ] + }, + { + "name": "MCE3", + "address": 1208139776, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE3EN" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE3" + } + ] + }, + { + "name": "MCE4", + "address": 1208147968, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "MCE4EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "MCE4RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MCE4" + } + ] + }, + { + "name": "MDF1", + "address": 1107447808, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": { + "register": "CCIPR5", + "field": "MDF1SEL" + }, + "enable": { + "register": "AHB2ENR", + "field": "MDF1EN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "MDF1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "SDI2", + "af": 4 + }, + { + "pin": "PB6", + "signal": "CCK1", + "af": 4 + }, + { + "pin": "PB7", + "signal": "SDI1", + "af": 4 + }, + { + "pin": "PE10", + "signal": "SDI4", + "af": 4 + }, + { + "pin": "PE12", + "signal": "SDI5", + "af": 4 + }, + { + "pin": "PE2", + "signal": "CCK0", + "af": 4 + }, + { + "pin": "PE3", + "signal": "CKI2", + "af": 4 + }, + { + "pin": "PE7", + "signal": "CKI0", + "af": 4 + }, + { + "pin": "PE8", + "signal": "SDI0", + "af": 4 + }, + { + "pin": "PE9", + "signal": "CKI4", + "af": 4 + }, + { + "pin": "PF10", + "signal": "SDI3", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "FLT0", + "interrupt": "MDF1_FLT0" + }, + { + "signal": "FLT1", + "interrupt": "MDF1_FLT1" + }, + { + "signal": "FLT2", + "interrupt": "MDF1_FLT2" + }, + { + "signal": "FLT3", + "interrupt": "MDF1_FLT3" + }, + { + "signal": "FLT4", + "interrupt": "MDF1_FLT4" + }, + { + "signal": "FLT5", + "interrupt": "MDF1_FLT5" + } + ] + }, + { + "name": "MDIOS", + "address": 1073779712, + "registers": { + "kind": "mdios", + "version": "v1", + "block": "MDIOS" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "MDIOSEN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "MDIOSRST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA2", + "signal": "MDIO", + "af": 11 + }, + { + "pin": "PA6", + "signal": "MDC", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "MDIOS" + }, + { + "signal": "WKUP", + "interrupt": "MDIOS" + } + ] + }, + { + "name": "PKA", + "address": 1140989952, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "PKAEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "PKARST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "PKA" + } + ] + }, + { + "name": "PSSI", + "address": 1208116224, + "registers": { + "kind": "pssi", + "version": "v1", + "block": "PSSI" + }, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR7", + "field": "PSSISEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "PSSIEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "PSSIRST" + } + }, + "pins": [ + { + "pin": "PA1", + "signal": "D0", + "af": 9 + }, + { + "pin": "PA10", + "signal": "D1", + "af": 9 + }, + { + "pin": "PA5", + "signal": "D8", + "af": 9 + }, + { + "pin": "PA6", + "signal": "PDCK", + "af": 9 + }, + { + "pin": "PA9", + "signal": "D0", + "af": 9 + }, + { + "pin": "PB0", + "signal": "D4", + "af": 9 + }, + { + "pin": "PB4", + "signal": "RDY", + "af": 9 + }, + { + "pin": "PB5", + "signal": "D10", + "af": 9 + }, + { + "pin": "PB6", + "signal": "D6", + "af": 9 + }, + { + "pin": "PB7", + "signal": "D7", + "af": 9 + }, + { + "pin": "PC10", + "signal": "D14", + "af": 9 + }, + { + "pin": "PC11", + "signal": "D4", + "af": 9 + }, + { + "pin": "PC12", + "signal": "D9", + "af": 9 + }, + { + "pin": "PC8", + "signal": "D2", + "af": 9 + }, + { + "pin": "PC9", + "signal": "D3", + "af": 9 + }, + { + "pin": "PD8", + "signal": "D11", + "af": 9 + }, + { + "pin": "PE0", + "signal": "D2", + "af": 9 + }, + { + "pin": "PE1", + "signal": "D8", + "af": 9 + }, + { + "pin": "PE10", + "signal": "D3", + "af": 9 + }, + { + "pin": "PE8", + "signal": "D4", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D11", + "af": 9 + }, + { + "pin": "PF10", + "signal": "D15", + "af": 10 + }, + { + "pin": "PF11", + "signal": "D15", + "af": 9 + }, + { + "pin": "PF12", + "signal": "D13", + "af": 9 + }, + { + "pin": "PF13", + "signal": "D10", + "af": 9 + }, + { + "pin": "PF3", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF4", + "signal": "DE", + "af": 9 + }, + { + "pin": "PF5", + "signal": "D6", + "af": 9 + }, + { + "pin": "PG10", + "signal": "D2", + "af": 9 + }, + { + "pin": "PG13", + "signal": "D12", + "af": 9 + }, + { + "pin": "PG14", + "signal": "D11", + "af": 9 + }, + { + "pin": "PG2", + "signal": "D6", + "af": 9 + }, + { + "pin": "PH2", + "signal": "D11", + "af": 9 + }, + { + "pin": "PN9", + "signal": "D5", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "DCMI_PSSI" + } + ] + }, + { + "name": "PWR", + "address": 1174554624, + "rcc": { + "bus_clock": "HCLK4", + "kernel_clock": "HCLK4", + "enable": { + "register": "AHB4ENR", + "field": "PWREN" + }, + "reset": { + "register": "AHB4RSTR", + "field": "PWRRST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "WKUP1" + }, + { + "pin": "PA10", + "signal": "CSLEEP", + "af": 0 + }, + { + "pin": "PA2", + "signal": "WKUP2" + }, + { + "pin": "PA5", + "signal": "CSTOP", + "af": 0 + }, + { + "pin": "PC13", + "signal": "WKUP3" + } + ] + }, + { + "name": "RAMCFG", + "address": 1107439616, + "rcc": { + "bus_clock": "HCLK2", + "kernel_clock": "HCLK2", + "enable": { + "register": "AHB2ENR", + "field": "RAMCFGEN" + }, + "reset": { + "register": "AHB2RSTR", + "field": "RAMCFGRST" + } + }, + "interrupts": [ + { + "signal": "BKP", + "interrupt": "BKP_ECC" + }, + { + "signal": "ECC", + "interrupt": "BKP_ECC" + } + ] + }, + { + "name": "RCC", + "address": 1174568960, + "registers": { + "kind": "rcc", + "version": "n6", + "block": "RCC" + }, + "pins": [ + { + "pin": "PA8", + "signal": "MCO_1", + "af": 0 + }, + { + "pin": "PC14", + "signal": "OSC32_IN" + }, + { + "pin": "PC15", + "signal": "OSC32_OUT" + }, + { + "pin": "PC9", + "signal": "MCO_2", + "af": 0 + }, + { + "pin": "PH0", + "signal": "OSC_IN" + }, + { + "pin": "PH1", + "signal": "OSC_OUT" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RCC" + } + ] + }, + { + "name": "RNG", + "address": 1140981760, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "RNGEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "RNGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "RNG" + } + ] + }, + { + "name": "RTC", + "address": 1174421504, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR7", + "field": "RTCSEL" + }, + "enable": { + "register": "APB4LENR", + "field": "RTCEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "RTCRST" + }, + "stop_mode": "Standby" + }, + "pins": [ + { + "pin": "PC13", + "signal": "OUT1" + }, + { + "pin": "PC13", + "signal": "TS" + } + ], + "interrupts": [ + { + "signal": "ALARM", + "interrupt": "RTC" + }, + { + "signal": "SSRU", + "interrupt": "RTC" + }, + { + "signal": "STAMP", + "interrupt": "RTC" + }, + { + "signal": "TAMP", + "interrupt": "RTC" + }, + { + "signal": "WKUP", + "interrupt": "RTC" + } + ] + }, + { + "name": "SAES", + "address": 1140985856, + "rcc": { + "bus_clock": "HCLK3", + "kernel_clock": "HCLK3", + "enable": { + "register": "AHB3ENR", + "field": "SAESEN" + }, + "reset": { + "register": "AHB3RSTR", + "field": "SAESRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SAES" + } + ] + }, + { + "name": "SAI1", + "address": 1107318784, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI1RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "D2", + "af": 2 + }, + { + "pin": "PB0", + "signal": "FS_A", + "af": 6 + }, + { + "pin": "PB6", + "signal": "CK2", + "af": 2 + }, + { + "pin": "PB6", + "signal": "SCK_A", + "af": 6 + }, + { + "pin": "PB7", + "signal": "D1", + "af": 2 + }, + { + "pin": "PB7", + "signal": "SD_A", + "af": 6 + }, + { + "pin": "PE2", + "signal": "CK1", + "af": 2 + }, + { + "pin": "PE2", + "signal": "MCLK_A", + "af": 6 + }, + { + "pin": "PE3", + "signal": "SD_B", + "af": 6 + }, + { + "pin": "PF10", + "signal": "D3", + "af": 2 + }, + { + "pin": "PG2", + "signal": "FS_B", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI1_A" + }, + { + "signal": "B", + "interrupt": "SAI1_B" + } + ] + }, + { + "name": "SAI2", + "address": 1107319808, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR7", + "field": "SAI2SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SAI2EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SAI2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PA1", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PA12", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PA2", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PB7", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE0", + "signal": "MCLK_A", + "af": 10 + }, + { + "pin": "PE12", + "signal": "SCK_B", + "af": 10 + }, + { + "pin": "PE13", + "signal": "FS_B", + "af": 10 + }, + { + "pin": "PE14", + "signal": "MCLK_B", + "af": 10 + }, + { + "pin": "PE7", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF11", + "signal": "SD_B", + "af": 10 + }, + { + "pin": "PF5", + "signal": "SD_A", + "af": 10 + }, + { + "pin": "PG13", + "signal": "FS_A", + "af": 10 + }, + { + "pin": "PG2", + "signal": "MCLK_B", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "A", + "interrupt": "SAI2_A" + }, + { + "signal": "B", + "interrupt": "SAI2_B" + } + ] + }, + { + "name": "SPI1", + "address": 1107308544, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI1SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI1RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 5 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF7", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PF7", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI1" + } + ] + }, + { + "name": "SPI3", + "address": 1073757184, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI3SEL" + }, + "enable": { + "register": "APB1LENR", + "field": "SPI3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "SPI3RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 6 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 7 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 7 + }, + { + "pin": "PC10", + "signal": "I2S_CK", + "af": 6 + }, + { + "pin": "PC10", + "signal": "SCK", + "af": 6 + }, + { + "pin": "PC11", + "signal": "I2S_SDI", + "af": 6 + }, + { + "pin": "PC11", + "signal": "MISO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "I2S_SDO", + "af": 6 + }, + { + "pin": "PC12", + "signal": "MOSI", + "af": 6 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 6 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI3" + } + ] + }, + { + "name": "SPI4", + "address": 1107309568, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI4SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI4EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI4RST" + } + }, + "pins": [ + { + "pin": "PB0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PB6", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PB7", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PE13", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PE14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PE2", + "signal": "SCK", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI4" + } + ] + }, + { + "name": "SPI5", + "address": 1107316736, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI5SEL" + }, + "enable": { + "register": "APB2ENR", + "field": "SPI5EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "SPI5RST" + } + }, + "pins": [ + { + "pin": "PE15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF11", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF12", + "signal": "MISO", + "af": 5 + }, + { + "pin": "PF13", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PF14", + "signal": "MOSI", + "af": 5 + }, + { + "pin": "PF15", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PG2", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI5" + } + ] + }, + { + "name": "SPI6", + "address": 1174410240, + "registers": { + "kind": "spi", + "version": "v4", + "block": "SPI" + }, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": { + "register": "CCIPR9", + "field": "SPI6SEL" + }, + "enable": { + "register": "APB4LENR", + "field": "SPI6EN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "SPI6RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "I2S_WS", + "af": 5 + }, + { + "pin": "PA0", + "signal": "NSS", + "af": 5 + }, + { + "pin": "PA15", + "signal": "I2S_WS", + "af": 7 + }, + { + "pin": "PA15", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA5", + "signal": "I2S_CK", + "af": 8 + }, + { + "pin": "PA5", + "signal": "SCK", + "af": 8 + }, + { + "pin": "PA6", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PA6", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB4", + "signal": "I2S_SDI", + "af": 8 + }, + { + "pin": "PB4", + "signal": "MISO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "I2S_SDO", + "af": 8 + }, + { + "pin": "PB5", + "signal": "MOSI", + "af": 8 + }, + { + "pin": "PC12", + "signal": "I2S_CK", + "af": 5 + }, + { + "pin": "PC12", + "signal": "SCK", + "af": 5 + }, + { + "pin": "PF4", + "signal": "I2S_WS", + "af": 8 + }, + { + "pin": "PF4", + "signal": "NSS", + "af": 8 + }, + { + "pin": "PG14", + "signal": "I2S_SDO", + "af": 5 + }, + { + "pin": "PG14", + "signal": "MOSI", + "af": 5 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "SPI6" + } + ] + }, + { + "name": "SYSCFG", + "address": 1174437888, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4HENR", + "field": "SYSCFGEN" + }, + "reset": { + "register": "APB4HRSTR", + "field": "SYSCFGRST" + } + } + }, + { + "name": "TAMP", + "address": 1174422528, + "pins": [ + { + "pin": "PC13", + "signal": "IN1" + }, + { + "pin": "PC13", + "signal": "OUT2" + }, + { + "pin": "PD8", + "signal": "IN3" + }, + { + "pin": "PD8", + "signal": "OUT4" + }, + { + "pin": "PE0", + "signal": "IN6" + }, + { + "pin": "PE0", + "signal": "OUT5" + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "TAMP" + } + ] + }, + { + "name": "TIM10", + "address": 1073754112, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM10EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM10RST" + } + }, + "pins": [ + { + "pin": "PA5", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM10" + }, + { + "signal": "CC", + "interrupt": "TIM10" + }, + { + "signal": "COM", + "interrupt": "TIM10" + }, + { + "signal": "TRG", + "interrupt": "TIM10" + }, + { + "signal": "UP", + "interrupt": "TIM10" + } + ] + }, + { + "name": "TIM11", + "address": 1073755136, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM11EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM11RST" + } + }, + "pins": [ + { + "pin": "PA8", + "signal": "CH1", + "af": 9 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM11" + }, + { + "signal": "CC", + "interrupt": "TIM11" + }, + { + "signal": "COM", + "interrupt": "TIM11" + }, + { + "signal": "TRG", + "interrupt": "TIM11" + }, + { + "signal": "UP", + "interrupt": "TIM11" + } + ] + }, + { + "name": "TIM13", + "address": 1073748992, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM13EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM13RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 10 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM13" + }, + { + "signal": "CC", + "interrupt": "TIM13" + }, + { + "signal": "COM", + "interrupt": "TIM13" + }, + { + "signal": "TRG", + "interrupt": "TIM13" + }, + { + "signal": "UP", + "interrupt": "TIM13" + } + ] + }, + { + "name": "TIM14", + "address": 1073750016, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM14EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM14RST" + } + }, + "pins": [ + { + "pin": "PG2", + "signal": "CH1", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM14" + }, + { + "signal": "CC", + "interrupt": "TIM14" + }, + { + "signal": "COM", + "interrupt": "TIM14" + }, + { + "signal": "TRG", + "interrupt": "TIM14" + }, + { + "signal": "UP", + "interrupt": "TIM14" + } + ] + }, + { + "name": "TIM15", + "address": 1107312640, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM15EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM15RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "BKIN", + "af": 4 + }, + { + "pin": "PA1", + "signal": "CH1N", + "af": 4 + }, + { + "pin": "PA2", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PB0", + "signal": "CH1N", + "af": 7 + }, + { + "pin": "PB6", + "signal": "CH1", + "af": 7 + }, + { + "pin": "PB7", + "signal": "CH2", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CH1", + "af": 4 + }, + { + "pin": "PE3", + "signal": "BKIN", + "af": 7 + }, + { + "pin": "PH2", + "signal": "BKIN", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM15" + }, + { + "signal": "CC", + "interrupt": "TIM15" + }, + { + "signal": "COM", + "interrupt": "TIM15" + }, + { + "signal": "TRG", + "interrupt": "TIM15" + }, + { + "signal": "UP", + "interrupt": "TIM15" + } + ] + }, + { + "name": "TIM18", + "address": 1107311616, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM18EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM18RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM18" + }, + { + "signal": "CC", + "interrupt": "TIM18" + }, + { + "signal": "COM", + "interrupt": "TIM18" + }, + { + "signal": "TRG", + "interrupt": "TIM18" + }, + { + "signal": "UP", + "interrupt": "TIM18" + } + ] + }, + { + "name": "TIM2", + "address": 1073741824, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM2EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM2RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA1", + "signal": "CH2", + "af": 1 + }, + { + "pin": "PA15", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA15", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PA2", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PA5", + "signal": "CH1", + "af": 1 + }, + { + "pin": "PA5", + "signal": "ETR", + "af": 2 + }, + { + "pin": "PB10", + "signal": "CH3", + "af": 1 + }, + { + "pin": "PB11", + "signal": "CH4", + "af": 1 + }, + { + "pin": "PF14", + "signal": "CH2", + "af": 1 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM2" + }, + { + "signal": "CC", + "interrupt": "TIM2" + }, + { + "signal": "COM", + "interrupt": "TIM2" + }, + { + "signal": "TRG", + "interrupt": "TIM2" + }, + { + "signal": "UP", + "interrupt": "TIM2" + } + ] + }, + { + "name": "TIM3", + "address": 1073742848, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM3RST" + } + }, + "pins": [ + { + "pin": "PA6", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB4", + "signal": "CH1", + "af": 2 + }, + { + "pin": "PB5", + "signal": "CH2", + "af": 2 + }, + { + "pin": "PC8", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PC9", + "signal": "CH4", + "af": 2 + }, + { + "pin": "PF7", + "signal": "CH3", + "af": 2 + }, + { + "pin": "PH2", + "signal": "ETR", + "af": 2 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM3" + }, + { + "signal": "CC", + "interrupt": "TIM3" + }, + { + "signal": "COM", + "interrupt": "TIM3" + }, + { + "signal": "TRG", + "interrupt": "TIM3" + }, + { + "signal": "UP", + "interrupt": "TIM3" + } + ] + }, + { + "name": "TIM6", + "address": 1073745920, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM6EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM6RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM6" + }, + { + "signal": "CC", + "interrupt": "TIM6" + }, + { + "signal": "COM", + "interrupt": "TIM6" + }, + { + "signal": "TRG", + "interrupt": "TIM6" + }, + { + "signal": "UP", + "interrupt": "TIM6" + } + ] + }, + { + "name": "TIM7", + "address": 1073746944, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1_TIM", + "enable": { + "register": "APB1LENR", + "field": "TIM7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "TIM7RST" + } + }, + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM7" + }, + { + "signal": "CC", + "interrupt": "TIM7" + }, + { + "signal": "COM", + "interrupt": "TIM7" + }, + { + "signal": "TRG", + "interrupt": "TIM7" + }, + { + "signal": "UP", + "interrupt": "TIM7" + } + ] + }, + { + "name": "TIM9", + "address": 1107315712, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2_TIM", + "enable": { + "register": "APB2ENR", + "field": "TIM9EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "TIM9RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "CH1", + "af": 3 + }, + { + "pin": "PA5", + "signal": "CH2", + "af": 3 + }, + { + "pin": "PF7", + "signal": "CH1", + "af": 3 + } + ], + "interrupts": [ + { + "signal": "BRK", + "interrupt": "TIM9" + }, + { + "signal": "CC", + "interrupt": "TIM9" + }, + { + "signal": "COM", + "interrupt": "TIM9" + }, + { + "signal": "TRG", + "interrupt": "TIM9" + }, + { + "signal": "UP", + "interrupt": "TIM9" + } + ] + }, + { + "name": "UART4", + "address": 1073761280, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART4EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART4RST" + } + }, + "pins": [ + { + "pin": "PA0", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA1", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PA12", + "signal": "TX", + "af": 8 + }, + { + "pin": "PA15", + "signal": "DE", + "af": 8 + }, + { + "pin": "PA15", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 8 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 8 + }, + { + "pin": "PD1", + "signal": "TX", + "af": 8 + }, + { + "pin": "PF7", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART4" + } + ] + }, + { + "name": "UART5", + "address": 1073762304, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART5EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART5RST" + } + }, + "pins": [ + { + "pin": "PB12", + "signal": "RX", + "af": 11 + }, + { + "pin": "PB5", + "signal": "RX", + "af": 11 + }, + { + "pin": "PC12", + "signal": "TX", + "af": 11 + }, + { + "pin": "PC8", + "signal": "DE", + "af": 11 + }, + { + "pin": "PC8", + "signal": "RTS", + "af": 11 + }, + { + "pin": "PC9", + "signal": "CTS", + "af": 11 + }, + { + "pin": "PG10", + "signal": "TX", + "af": 11 + }, + { + "pin": "PH2", + "signal": "RX", + "af": 11 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART5" + } + ] + }, + { + "name": "UART7", + "address": 1073772544, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "UART7EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "UART7RST" + } + }, + "pins": [ + { + "pin": "PA15", + "signal": "TX", + "af": 10 + }, + { + "pin": "PA8", + "signal": "RX", + "af": 10 + }, + { + "pin": "PB4", + "signal": "TX", + "af": 10 + }, + { + "pin": "PE10", + "signal": "CTS", + "af": 8 + }, + { + "pin": "PE7", + "signal": "RX", + "af": 8 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 8 + }, + { + "pin": "PE9", + "signal": "RTS", + "af": 8 + }, + { + "pin": "PF10", + "signal": "RX", + "af": 8 + }, + { + "pin": "PG2", + "signal": "CTS", + "af": 8 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UART7" + } + ] + }, + { + "name": "UCPD1", + "address": 1073806336, + "registers": { + "kind": "ucpd", + "version": "v1", + "block": "UCPD" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1HENR", + "field": "UCPD1EN" + }, + "reset": { + "register": "APB1HRSTR", + "field": "UCPD1RST" + } + }, + "pins": [ + { + "pin": "PC8", + "signal": "FRSTX1", + "af": 6 + }, + { + "pin": "PC9", + "signal": "FRSTX2", + "af": 6 + }, + { + "pin": "PE2", + "signal": "FRSTX1", + "af": 7 + }, + { + "pin": "PF10", + "signal": "FRSTX1", + "af": 6 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "UCPD1" + } + ] + }, + { + "name": "UID", + "address": 1174442004, + "registers": { + "kind": "uid", + "version": "v1", + "block": "UID" + } + }, + { + "name": "USART1", + "address": 1107300352, + "rcc": { + "bus_clock": "PCLK2", + "kernel_clock": "PCLK2", + "enable": { + "register": "APB2ENR", + "field": "USART1EN" + }, + "reset": { + "register": "APB2RSTR", + "field": "USART1RST" + } + }, + "pins": [ + { + "pin": "PA10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PA11", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PA11", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PA12", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PA8", + "signal": "CK", + "af": 7 + }, + { + "pin": "PA9", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF12", + "signal": "RX", + "af": 4 + }, + { + "pin": "PF13", + "signal": "TX", + "af": 4 + }, + { + "pin": "PF14", + "signal": "CTS", + "af": 4 + }, + { + "pin": "PF15", + "signal": "RTS", + "af": 4 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART1" + } + ] + }, + { + "name": "USART3", + "address": 1073760256, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "USART3EN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "USART3RST" + } + }, + "pins": [ + { + "pin": "PB10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PB11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PB12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PC10", + "signal": "TX", + "af": 7 + }, + { + "pin": "PC11", + "signal": "RX", + "af": 7 + }, + { + "pin": "PC12", + "signal": "CK", + "af": 7 + }, + { + "pin": "PD8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE0", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE1", + "signal": "TX", + "af": 7 + }, + { + "pin": "PE10", + "signal": "RX", + "af": 7 + }, + { + "pin": "PE8", + "signal": "TX", + "af": 7 + }, + { + "pin": "PF5", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PF5", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "CTS", + "af": 7 + }, + { + "pin": "PG10", + "signal": "NSS", + "af": 7 + }, + { + "pin": "PG13", + "signal": "RTS", + "af": 7 + }, + { + "pin": "PG2", + "signal": "RTS", + "af": 7 + } + ], + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "USART3" + } + ] + }, + { + "name": "USB1_OTG_HS", + "address": 1208221696, + "registers": { + "kind": "otg", + "version": "v1", + "block": "OTG" + }, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB1_OTG_HS" + }, + { + "signal": "USB1", + "interrupt": "USB1_OTG_HS" + } + ] + }, + { + "name": "USB2_OTG_HS", + "address": 1208483840, + "interrupts": [ + { + "signal": "OTG_HS", + "interrupt": "USB2_OTG_HS" + }, + { + "signal": "USB2", + "interrupt": "USB2_OTG_HS" + } + ] + }, + { + "name": "VENC", + "address": 1207980032, + "rcc": { + "bus_clock": "PCLK5", + "kernel_clock": "PCLK5", + "enable": { + "register": "APB5ENR", + "field": "VENCEN" + }, + "reset": { + "register": "APB5RSTR", + "field": "VENCRST" + } + } + }, + { + "name": "VREFBUF", + "address": 1174420480, + "rcc": { + "bus_clock": "PCLK4", + "kernel_clock": "PCLK4", + "enable": { + "register": "APB4LENR", + "field": "VREFBUFEN" + }, + "reset": { + "register": "APB4LRSTR", + "field": "VREFBUFRST" + } + } + }, + { + "name": "WWDG", + "address": 1073753088, + "registers": { + "kind": "wwdg", + "version": "v2", + "block": "WWDG" + }, + "rcc": { + "bus_clock": "PCLK1", + "kernel_clock": "PCLK1", + "enable": { + "register": "APB1LENR", + "field": "WWDGEN" + }, + "reset": { + "register": "APB1LRSTR", + "field": "WWDGRST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "WWDG" + }, + { + "signal": "RST", + "interrupt": "WWDG" + } + ] + }, + { + "name": "XSPI3", + "address": 2147483648, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": { + "register": "CCIPR6", + "field": "XSPI3SEL" + }, + "enable": { + "register": "AHB5ENR", + "field": "XSPI3EN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPI3RST" + } + }, + "interrupts": [ + { + "signal": "GLOBAL", + "interrupt": "XSPI3" + } + ] + }, + { + "name": "XSPIM", + "address": 1208136704, + "rcc": { + "bus_clock": "HCLK5", + "kernel_clock": "HCLK5", + "enable": { + "register": "AHB5ENR", + "field": "XSPIMEN" + }, + "reset": { + "register": "AHB5RSTR", + "field": "XSPIMRST" + } + }, + "pins": [ + { + "pin": "PN0", + "signal": "P2_DQS0", + "af": 9 + }, + { + "pin": "PN1", + "signal": "P2_NCS1", + "af": 9 + }, + { + "pin": "PN10", + "signal": "P2_IO6", + "af": 9 + }, + { + "pin": "PN11", + "signal": "P2_IO7", + "af": 9 + }, + { + "pin": "PN12", + "signal": "P2_NCS2", + "af": 9 + }, + { + "pin": "PN2", + "signal": "P2_IO0", + "af": 9 + }, + { + "pin": "PN3", + "signal": "P2_IO1", + "af": 9 + }, + { + "pin": "PN4", + "signal": "P2_IO2", + "af": 9 + }, + { + "pin": "PN5", + "signal": "P2_IO3", + "af": 9 + }, + { + "pin": "PN6", + "signal": "P2_CLK", + "af": 9 + }, + { + "pin": "PN7", + "signal": "P2_NCLK", + "af": 9 + }, + { + "pin": "PN8", + "signal": "P2_IO4", + "af": 9 + }, + { + "pin": "PN9", + "signal": "P2_IO5", + "af": 9 + } + ] + } + ], + "nvic_priority_bits": 4, + "interrupts": [ + { + "name": "PVD_PVM", + "number": 0 + }, + { + "name": "DTS", + "number": 2 + }, + { + "name": "RCC", + "number": 3 + }, + { + "name": "LOCKUP", + "number": 4 + }, + { + "name": "CACHE_ECC", + "number": 5 + }, + { + "name": "TCM_ECC", + "number": 6 + }, + { + "name": "BKP_ECC", + "number": 7 + }, + { + "name": "FPU", + "number": 8 + }, + { + "name": "RTC_S", + "number": 10 + }, + { + "name": "TAMP", + "number": 11 + }, + { + "name": "RIFSC_TAMPER", + "number": 12 + }, + { + "name": "IAC", + "number": 13 + }, + { + "name": "RCC_S", + "number": 14 + }, + { + "name": "RTC", + "number": 16 + }, + { + "name": "IWDG", + "number": 18 + }, + { + "name": "WWDG", + "number": 19 + }, + { + "name": "EXTI0", + "number": 20 + }, + { + "name": "EXTI1", + "number": 21 + }, + { + "name": "EXTI2", + "number": 22 + }, + { + "name": "EXTI3", + "number": 23 + }, + { + "name": "EXTI4", + "number": 24 + }, + { + "name": "EXTI5", + "number": 25 + }, + { + "name": "EXTI6", + "number": 26 + }, + { + "name": "EXTI7", + "number": 27 + }, + { + "name": "EXTI8", + "number": 28 + }, + { + "name": "EXTI9", + "number": 29 + }, + { + "name": "EXTI10", + "number": 30 + }, + { + "name": "EXTI11", + "number": 31 + }, + { + "name": "EXTI12", + "number": 32 + }, + { + "name": "EXTI13", + "number": 33 + }, + { + "name": "EXTI14", + "number": 34 + }, + { + "name": "EXTI15", + "number": 35 + }, + { + "name": "SAES", + "number": 36 + }, + { + "name": "CRYP", + "number": 37 + }, + { + "name": "PKA", + "number": 38 + }, + { + "name": "HASH", + "number": 39 + }, + { + "name": "RNG", + "number": 40 + }, + { + "name": "MCE1", + "number": 42 + }, + { + "name": "MCE2", + "number": 43 + }, + { + "name": "MCE3", + "number": 44 + }, + { + "name": "MCE4", + "number": 45 + }, + { + "name": "ADC1_2", + "number": 46 + }, + { + "name": "CSI", + "number": 47 + }, + { + "name": "DCMIPP", + "number": 48 + }, + { + "name": "PAHB_ERR", + "number": 52 + }, + { + "name": "NPU0", + "number": 53 + }, + { + "name": "NPU1", + "number": 54 + }, + { + "name": "NPU2", + "number": 55 + }, + { + "name": "NPU3", + "number": 56 + }, + { + "name": "CACHEAXI", + "number": 57 + }, + { + "name": "LTDC_LO", + "number": 58 + }, + { + "name": "LTDC_LO_ERR", + "number": 59 + }, + { + "name": "DMA2D", + "number": 60 + }, + { + "name": "JPEG", + "number": 61 + }, + { + "name": "VENC", + "number": 62 + }, + { + "name": "GFXMMU", + "number": 63 + }, + { + "name": "GFXTIM", + "number": 64 + }, + { + "name": "GPU2D", + "number": 65 + }, + { + "name": "GPU2D_ER", + "number": 66 + }, + { + "name": "ICACHE", + "number": 67 + }, + { + "name": "HPDMA1_Channel0", + "number": 68 + }, + { + "name": "HPDMA1_Channel1", + "number": 69 + }, + { + "name": "HPDMA1_Channel2", + "number": 70 + }, + { + "name": "HPDMA1_Channel3", + "number": 71 + }, + { + "name": "HPDMA1_Channel4", + "number": 72 + }, + { + "name": "HPDMA1_Channel5", + "number": 73 + }, + { + "name": "HPDMA1_Channel6", + "number": 74 + }, + { + "name": "HPDMA1_Channel7", + "number": 75 + }, + { + "name": "HPDMA1_Channel8", + "number": 76 + }, + { + "name": "HPDMA1_Channel9", + "number": 77 + }, + { + "name": "HPDMA1_Channel10", + "number": 78 + }, + { + "name": "HPDMA1_Channel11", + "number": 79 + }, + { + "name": "HPDMA1_Channel12", + "number": 80 + }, + { + "name": "HPDMA1_Channel13", + "number": 81 + }, + { + "name": "HPDMA1_Channel14", + "number": 82 + }, + { + "name": "HPDMA1_Channel15", + "number": 83 + }, + { + "name": "GPDMA1_Channel0", + "number": 84 + }, + { + "name": "GPDMA1_Channel1", + "number": 85 + }, + { + "name": "GPDMA1_Channel2", + "number": 86 + }, + { + "name": "GPDMA1_Channel3", + "number": 87 + }, + { + "name": "GPDMA1_Channel4", + "number": 88 + }, + { + "name": "GPDMA1_Channel5", + "number": 89 + }, + { + "name": "GPDMA1_Channel6", + "number": 90 + }, + { + "name": "GPDMA1_Channel7", + "number": 91 + }, + { + "name": "GPDMA1_Channel8", + "number": 92 + }, + { + "name": "GPDMA1_Channel9", + "number": 93 + }, + { + "name": "GPDMA1_Channel10", + "number": 94 + }, + { + "name": "GPDMA1_Channel11", + "number": 95 + }, + { + "name": "GPDMA1_Channel12", + "number": 96 + }, + { + "name": "GPDMA1_Channel13", + "number": 97 + }, + { + "name": "GPDMA1_Channel14", + "number": 98 + }, + { + "name": "GPDMA1_Channel15", + "number": 99 + }, + { + "name": "I2C1_EV", + "number": 100 + }, + { + "name": "I2C1_ER", + "number": 101 + }, + { + "name": "I2C2_EV", + "number": 102 + }, + { + "name": "I2C2_ER", + "number": 103 + }, + { + "name": "I2C3_EV", + "number": 104 + }, + { + "name": "I2C3_ER", + "number": 105 + }, + { + "name": "I2C4_EV", + "number": 106 + }, + { + "name": "I2C4_ER", + "number": 107 + }, + { + "name": "I3C1_EV", + "number": 108 + }, + { + "name": "I3C1_ER", + "number": 109 + }, + { + "name": "I3C2_EV", + "number": 110 + }, + { + "name": "I3C2_ER", + "number": 111 + }, + { + "name": "TIM1_BRK", + "number": 112 + }, + { + "name": "TIM1_UP", + "number": 113 + }, + { + "name": "TIM1_TRG_COM", + "number": 114 + }, + { + "name": "TIM1_CC", + "number": 115 + }, + { + "name": "TIM2", + "number": 116 + }, + { + "name": "TIM3", + "number": 117 + }, + { + "name": "TIM4", + "number": 118 + }, + { + "name": "TIM5", + "number": 119 + }, + { + "name": "TIM6", + "number": 120 + }, + { + "name": "TIM7", + "number": 121 + }, + { + "name": "TIM8_BRK", + "number": 122 + }, + { + "name": "TIM8_UP", + "number": 123 + }, + { + "name": "TIM8_TRG_COM", + "number": 124 + }, + { + "name": "TIM8_CC", + "number": 125 + }, + { + "name": "TIM9", + "number": 126 + }, + { + "name": "TIM10", + "number": 127 + }, + { + "name": "TIM11", + "number": 128 + }, + { + "name": "TIM12", + "number": 129 + }, + { + "name": "TIM13", + "number": 130 + }, + { + "name": "TIM14", + "number": 131 + }, + { + "name": "TIM15", + "number": 132 + }, + { + "name": "TIM16", + "number": 133 + }, + { + "name": "TIM17", + "number": 134 + }, + { + "name": "TIM18", + "number": 135 + }, + { + "name": "LPTIM1", + "number": 136 + }, + { + "name": "LPTIM2", + "number": 137 + }, + { + "name": "LPTIM3", + "number": 138 + }, + { + "name": "LPTIM4", + "number": 139 + }, + { + "name": "LPTIM5", + "number": 140 + }, + { + "name": "ADF1_FLT0", + "number": 141 + }, + { + "name": "MDF1_FLT0", + "number": 142 + }, + { + "name": "MDF1_FLT1", + "number": 143 + }, + { + "name": "MDF1_FLT2", + "number": 144 + }, + { + "name": "MDF1_FLT3", + "number": 145 + }, + { + "name": "MDF1_FLT4", + "number": 146 + }, + { + "name": "MDF1_FLT5", + "number": 147 + }, + { + "name": "SAI1_A", + "number": 148 + }, + { + "name": "SAI1_B", + "number": 149 + }, + { + "name": "SAI2_A", + "number": 150 + }, + { + "name": "SAI2_B", + "number": 151 + }, + { + "name": "SPDIFRX1", + "number": 152 + }, + { + "name": "SPI1", + "number": 153 + }, + { + "name": "SPI2", + "number": 154 + }, + { + "name": "SPI3", + "number": 155 + }, + { + "name": "SPI4", + "number": 156 + }, + { + "name": "SPI5", + "number": 157 + }, + { + "name": "SPI6", + "number": 158 + }, + { + "name": "USART1", + "number": 159 + }, + { + "name": "USART2", + "number": 160 + }, + { + "name": "USART3", + "number": 161 + }, + { + "name": "UART4", + "number": 162 + }, + { + "name": "UART5", + "number": 163 + }, + { + "name": "USART6", + "number": 164 + }, + { + "name": "UART7", + "number": 165 + }, + { + "name": "UART8", + "number": 166 + }, + { + "name": "UART9", + "number": 167 + }, + { + "name": "USART10", + "number": 168 + }, + { + "name": "LPUART1", + "number": 169 + }, + { + "name": "XSPI1", + "number": 170 + }, + { + "name": "XSPI2", + "number": 171 + }, + { + "name": "XSPI3", + "number": 172 + }, + { + "name": "FMC", + "number": 173 + }, + { + "name": "SDMMC1", + "number": 174 + }, + { + "name": "SDMMC2", + "number": 175 + }, + { + "name": "UCPD1", + "number": 176 + }, + { + "name": "USB1_OTG_HS", + "number": 177 + }, + { + "name": "USB2_OTG_HS", + "number": 178 + }, + { + "name": "ETH1", + "number": 179 + }, + { + "name": "FDCAN1_IT0", + "number": 180 + }, + { + "name": "FDCAN1_IT1", + "number": 181 + }, + { + "name": "FDCAN2_IT0", + "number": 182 + }, + { + "name": "FDCAN2_IT1", + "number": 183 + }, + { + "name": "FDCAN3_IT0", + "number": 184 + }, + { + "name": "FDCAN3_IT1", + "number": 185 + }, + { + "name": "FDCAN_CU", + "number": 186 + }, + { + "name": "MDIOS", + "number": 187 + }, + { + "name": "DCMI_PSSI", + "number": 188 + }, + { + "name": "WAKEUP_PIN", + "number": 189 + }, + { + "name": "CTI_INT0", + "number": 190 + }, + { + "name": "CTI_INT1", + "number": 191 + }, + { + "name": "LTDC_UP", + "number": 193 + }, + { + "name": "LTDC_UP_ERR", + "number": 194 + } + ], + "dma_channels": [], + "pins": [ + { + "name": "PA0" + }, + { + "name": "PA1" + }, + { + "name": "PA2" + }, + { + "name": "PA5" + }, + { + "name": "PA6" + }, + { + "name": "PA8" + }, + { + "name": "PA9" + }, + { + "name": "PA10" + }, + { + "name": "PA11" + }, + { + "name": "PA12" + }, + { + "name": "PA13" + }, + { + "name": "PA14" + }, + { + "name": "PA15" + }, + { + "name": "PB0" + }, + { + "name": "PB4" + }, + { + "name": "PB5" + }, + { + "name": "PB6" + }, + { + "name": "PB7" + }, + { + "name": "PB10" + }, + { + "name": "PB11" + }, + { + "name": "PB12" + }, + { + "name": "PC8" + }, + { + "name": "PC9" + }, + { + "name": "PC10" + }, + { + "name": "PC11" + }, + { + "name": "PC12" + }, + { + "name": "PC13" + }, + { + "name": "PC14" + }, + { + "name": "PC15" + }, + { + "name": "PD1" + }, + { + "name": "PD8" + }, + { + "name": "PE0" + }, + { + "name": "PE1" + }, + { + "name": "PE2" + }, + { + "name": "PE3" + }, + { + "name": "PE7" + }, + { + "name": "PE8" + }, + { + "name": "PE9" + }, + { + "name": "PE10" + }, + { + "name": "PE12" + }, + { + "name": "PE13" + }, + { + "name": "PE14" + }, + { + "name": "PE15" + }, + { + "name": "PF2" + }, + { + "name": "PF3" + }, + { + "name": "PF4" + }, + { + "name": "PF5" + }, + { + "name": "PF7" + }, + { + "name": "PF8" + }, + { + "name": "PF10" + }, + { + "name": "PF11" + }, + { + "name": "PF12" + }, + { + "name": "PF13" + }, + { + "name": "PF14" + }, + { + "name": "PF15" + }, + { + "name": "PG2" + }, + { + "name": "PG10" + }, + { + "name": "PG13" + }, + { + "name": "PG14" + }, + { + "name": "PH0" + }, + { + "name": "PH1" + }, + { + "name": "PH2" + }, + { + "name": "PN0" + }, + { + "name": "PN1" + }, + { + "name": "PN2" + }, + { + "name": "PN3" + }, + { + "name": "PN4" + }, + { + "name": "PN5" + }, + { + "name": "PN6" + }, + { + "name": "PN7" + }, + { + "name": "PN8" + }, + { + "name": "PN9" + }, + { + "name": "PN10" + }, + { + "name": "PN11" + }, + { + "name": "PN12" + } + ] + } + ] +} \ No newline at end of file diff --git a/data/chips/STM32U073C8.json b/data/chips/STM32U073C8.json index aca57f4..e787f4d 100644 --- a/data/chips/STM32U073C8.json +++ b/data/chips/STM32U073C8.json @@ -4125,6 +4125,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073CB.json b/data/chips/STM32U073CB.json index 6fa5119..3f8baf5 100644 --- a/data/chips/STM32U073CB.json +++ b/data/chips/STM32U073CB.json @@ -4125,6 +4125,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073CC.json b/data/chips/STM32U073CC.json index c53ec8e..f8d0403 100644 --- a/data/chips/STM32U073CC.json +++ b/data/chips/STM32U073CC.json @@ -4125,6 +4125,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073H8.json b/data/chips/STM32U073H8.json index 6ce0dc3..d2c8e9d 100644 --- a/data/chips/STM32U073H8.json +++ b/data/chips/STM32U073H8.json @@ -3547,6 +3547,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073HB.json b/data/chips/STM32U073HB.json index c8c991e..e15253d 100644 --- a/data/chips/STM32U073HB.json +++ b/data/chips/STM32U073HB.json @@ -3547,6 +3547,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073HC.json b/data/chips/STM32U073HC.json index abf08a0..e8811cc 100644 --- a/data/chips/STM32U073HC.json +++ b/data/chips/STM32U073HC.json @@ -3547,6 +3547,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073K8.json b/data/chips/STM32U073K8.json index 854160d..10932c2 100644 --- a/data/chips/STM32U073K8.json +++ b/data/chips/STM32U073K8.json @@ -3337,6 +3337,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073KB.json b/data/chips/STM32U073KB.json index aa56421..46ea9e3 100644 --- a/data/chips/STM32U073KB.json +++ b/data/chips/STM32U073KB.json @@ -3337,6 +3337,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073KC.json b/data/chips/STM32U073KC.json index b7afe91..c4a9e86 100644 --- a/data/chips/STM32U073KC.json +++ b/data/chips/STM32U073KC.json @@ -3337,6 +3337,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073M8.json b/data/chips/STM32U073M8.json index 9b27092..fd6b8a0 100644 --- a/data/chips/STM32U073M8.json +++ b/data/chips/STM32U073M8.json @@ -5228,6 +5228,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073MB.json b/data/chips/STM32U073MB.json index 04ed30e..0b722b8 100644 --- a/data/chips/STM32U073MB.json +++ b/data/chips/STM32U073MB.json @@ -5228,6 +5228,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073MC.json b/data/chips/STM32U073MC.json index 52ba1ce..c2a8c14 100644 --- a/data/chips/STM32U073MC.json +++ b/data/chips/STM32U073MC.json @@ -5228,6 +5228,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073R8.json b/data/chips/STM32U073R8.json index 4fc95fa..6345caa 100644 --- a/data/chips/STM32U073R8.json +++ b/data/chips/STM32U073R8.json @@ -4756,6 +4756,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073RB.json b/data/chips/STM32U073RB.json index 38174fc..cee969a 100644 --- a/data/chips/STM32U073RB.json +++ b/data/chips/STM32U073RB.json @@ -4756,6 +4756,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U073RC.json b/data/chips/STM32U073RC.json index ad39bf0..0b26093 100644 --- a/data/chips/STM32U073RC.json +++ b/data/chips/STM32U073RC.json @@ -4756,6 +4756,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U083CC.json b/data/chips/STM32U083CC.json index 596ce1e..1979ded 100644 --- a/data/chips/STM32U083CC.json +++ b/data/chips/STM32U083CC.json @@ -4158,6 +4158,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U083HC.json b/data/chips/STM32U083HC.json index 1f375a1..a21f2d0 100644 --- a/data/chips/STM32U083HC.json +++ b/data/chips/STM32U083HC.json @@ -3580,6 +3580,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U083KC.json b/data/chips/STM32U083KC.json index 7f642be..e9b6697 100644 --- a/data/chips/STM32U083KC.json +++ b/data/chips/STM32U083KC.json @@ -3370,6 +3370,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U083MC.json b/data/chips/STM32U083MC.json index 725370c..9e0b43e 100644 --- a/data/chips/STM32U083MC.json +++ b/data/chips/STM32U083MC.json @@ -5261,6 +5261,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U083RC.json b/data/chips/STM32U083RC.json index 060b060..d4bf484 100644 --- a/data/chips/STM32U083RC.json +++ b/data/chips/STM32U083RC.json @@ -4789,6 +4789,18 @@ "signal": "LP", "interrupt": "USB_DRD_FS" }, + { + "signal": "OTG_HS", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB1", + "interrupt": "USB_DRD_FS" + }, + { + "signal": "USB2", + "interrupt": "USB_DRD_FS" + }, { "signal": "WKUP", "interrupt": "USB_DRD_FS" diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index 1098e14..699ed0d 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -5445,6 +5445,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index 0b62a44..e2503e4 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -5445,6 +5445,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index b40541b..b7f7d66 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -5445,6 +5445,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index b7c8d47..aa1d662 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -4944,6 +4944,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index b8f7508..c4a9a96 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -4703,6 +4703,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index 355099a..17a1b45 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -4703,6 +4703,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index 62ea124..ee15a43 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -6420,6 +6420,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index 928415e..c54c562 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -6420,6 +6420,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index 1ebff1a..e563cfc 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -6420,6 +6420,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index 7b19cac..3d82298 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -8251,6 +8251,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index 77d5dd5..17da905 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -8251,6 +8251,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index ad8f9d1..18ff545 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -5580,6 +5580,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index 9381268..abb4b87 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -5079,6 +5079,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 9fb1f6d..7908b97 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -4838,6 +4838,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index 54c54df..cc994a5 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -6555,6 +6555,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index 524ffde..0e45c1e 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -8386,6 +8386,18 @@ "signal": "LP", "interrupt": "USB" }, + { + "signal": "OTG_HS", + "interrupt": "USB" + }, + { + "signal": "USB1", + "interrupt": "USB" + }, + { + "signal": "USB2", + "interrupt": "USB" + }, { "signal": "WKUP", "interrupt": "USB" diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index 5c9bece..3fc6bc9 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -5103,9 +5103,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index bc594e5..c65104e 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -5176,9 +5176,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index 38cb1e6..bc24cf2 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -5176,9 +5176,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index eb8daee..305e3fa 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -3676,9 +3676,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index 5e75923..66fec15 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -4354,9 +4354,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index cf0a9fa..ba6ddad 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -5326,9 +5326,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index fcad537..cf2a378 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -5326,9 +5326,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 4b3165f..4b202f8 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -5142,9 +5142,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index be25cbf..5d8f814 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -5215,9 +5215,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index cdfadce..14fb05c 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -3715,9 +3715,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index ed164f8..afaf002 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -5365,9 +5365,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5F7VI.json b/data/chips/STM32U5F7VI.json index 5e45511..dc154f6 100644 --- a/data/chips/STM32U5F7VI.json +++ b/data/chips/STM32U5F7VI.json @@ -4433,9 +4433,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5F7VJ.json b/data/chips/STM32U5F7VJ.json index 27cb707..2ab6d76 100644 --- a/data/chips/STM32U5F7VJ.json +++ b/data/chips/STM32U5F7VJ.json @@ -4433,9 +4433,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5F9BJ.json b/data/chips/STM32U5F9BJ.json index e4a883e..5c9ea4f 100644 --- a/data/chips/STM32U5F9BJ.json +++ b/data/chips/STM32U5F9BJ.json @@ -5187,9 +5187,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5F9NJ.json b/data/chips/STM32U5F9NJ.json index 0a9c7a1..baeb212 100644 --- a/data/chips/STM32U5F9NJ.json +++ b/data/chips/STM32U5F9NJ.json @@ -5260,9 +5260,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5F9VI.json b/data/chips/STM32U5F9VI.json index 2baddcc..207e834 100644 --- a/data/chips/STM32U5F9VI.json +++ b/data/chips/STM32U5F9VI.json @@ -3424,9 +3424,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5F9VJ.json b/data/chips/STM32U5F9VJ.json index b56c54b..27e1f1a 100644 --- a/data/chips/STM32U5F9VJ.json +++ b/data/chips/STM32U5F9VJ.json @@ -3424,9 +3424,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5F9ZI.json b/data/chips/STM32U5F9ZI.json index f80cc30..813c474 100644 --- a/data/chips/STM32U5F9ZI.json +++ b/data/chips/STM32U5F9ZI.json @@ -5223,9 +5223,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5F9ZJ.json b/data/chips/STM32U5F9ZJ.json index cb50f00..7642549 100644 --- a/data/chips/STM32U5F9ZJ.json +++ b/data/chips/STM32U5F9ZJ.json @@ -5223,9 +5223,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5G7VJ.json b/data/chips/STM32U5G7VJ.json index 766d341..988b5d4 100644 --- a/data/chips/STM32U5G7VJ.json +++ b/data/chips/STM32U5G7VJ.json @@ -4547,9 +4547,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5G9BJ.json b/data/chips/STM32U5G9BJ.json index 295ee90..4267329 100644 --- a/data/chips/STM32U5G9BJ.json +++ b/data/chips/STM32U5G9BJ.json @@ -5226,9 +5226,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5G9NJ.json b/data/chips/STM32U5G9NJ.json index 30536ec..c9e2b87 100644 --- a/data/chips/STM32U5G9NJ.json +++ b/data/chips/STM32U5G9NJ.json @@ -5394,9 +5394,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5G9VJ.json b/data/chips/STM32U5G9VJ.json index 4641008..4319a73 100644 --- a/data/chips/STM32U5G9VJ.json +++ b/data/chips/STM32U5G9VJ.json @@ -3548,9 +3548,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/chips/STM32U5G9ZJ.json b/data/chips/STM32U5G9ZJ.json index 853caf4..8de4fcf 100644 --- a/data/chips/STM32U5G9ZJ.json +++ b/data/chips/STM32U5G9ZJ.json @@ -5347,9 +5347,17 @@ "signal": "ER", "interrupt": "LTDC_ER" }, + { + "signal": "ERR", + "interrupt": "LTDC" + }, { "signal": "GLOBAL", "interrupt": "LTDC" + }, + { + "signal": "LO", + "interrupt": "LTDC" } ] }, diff --git a/data/registers/rcc_n6.json b/data/registers/rcc_n6.json new file mode 100644 index 0000000..96c1fa6 --- /dev/null +++ b/data/registers/rcc_n6.json @@ -0,0 +1,21851 @@ +{ + "block/RCC": { + "description": "Reset and clock control.", + "items": [ + { + "name": "CR", + "description": "RCC control register.", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "SR", + "description": "RCC status register.", + "byte_offset": 4, + "fieldset": "SR" + }, + { + "name": "STOPCR", + "description": "RCC Stop mode control register.", + "byte_offset": 8, + "fieldset": "STOPCR" + }, + { + "name": "CFGR1", + "description": "RCC configuration register 1.", + "byte_offset": 32, + "fieldset": "CFGR1" + }, + { + "name": "CFGR2", + "description": "RCC configuration register 2.", + "byte_offset": 36, + "fieldset": "CFGR2" + }, + { + "name": "CKPROTR", + "description": "RCC clock protection register.", + "byte_offset": 40, + "fieldset": "CKPROTR" + }, + { + "name": "BDCR", + "description": "RCC backup domain protection register.", + "byte_offset": 44, + "fieldset": "BDCR" + }, + { + "name": "HWRSR", + "description": "RCC reset status register for hardware.", + "byte_offset": 48, + "fieldset": "HWRSR" + }, + { + "name": "RSR", + "description": "RCC reset register.", + "byte_offset": 52, + "fieldset": "RSR" + }, + { + "name": "LSECFGR", + "description": "RCC LSE configuration register.", + "byte_offset": 64, + "fieldset": "LSECFGR" + }, + { + "name": "MSICFGR", + "description": "RCC MSI configuration register.", + "byte_offset": 68, + "fieldset": "MSICFGR" + }, + { + "name": "HSICFGR", + "description": "RCC HSI configuration register.", + "byte_offset": 72, + "fieldset": "HSICFGR" + }, + { + "name": "HSIMCR", + "description": "RCC HSI monitor control register.", + "byte_offset": 76, + "fieldset": "HSIMCR" + }, + { + "name": "HSIMSR", + "description": "RCC HSI monitor status register.", + "byte_offset": 80, + "fieldset": "HSIMSR" + }, + { + "name": "HSECFGR", + "description": "RCC HSE configuration register.", + "byte_offset": 84, + "fieldset": "HSECFGR" + }, + { + "name": "PLLCFGR1", + "description": "RCC PLL1 configuration register 1.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 128, + "fieldset": "PLL1CFGR1" + }, + { + "name": "PLLCFGR2", + "description": "RCC PLL1 configuration register 2.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 132, + "fieldset": "PLL1CFGR2" + }, + { + "name": "PLLCFGR3", + "description": "RCC PLL1 configuration register 3.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 136, + "fieldset": "PLL1CFGR3" + }, + { + "name": "PLL2CFGR1", + "description": "RCC PLL2 configuration register 1.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 144, + "fieldset": "PLL2CFGR1" + }, + { + "name": "PLL2CFGR2", + "description": "RCC PLL2 configuration register 2.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 148, + "fieldset": "PLL2CFGR2" + }, + { + "name": "PLL2CFGR3", + "description": "RCC PLL2 configuration register 3.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 152, + "fieldset": "PLL2CFGR3" + }, + { + "name": "PLL3CFGR1", + "description": "RCC PLL3 configuration register 1.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 160, + "fieldset": "PLL3CFGR1" + }, + { + "name": "PLL3CFGR2", + "description": "RCC PLL3 configuration register 2.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 164, + "fieldset": "PLL3CFGR2" + }, + { + "name": "PLL3CFGR3", + "description": "RCC PLL3 configuration register 3.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 168, + "fieldset": "PLL3CFGR3" + }, + { + "name": "PLL4CFGR1", + "description": "RCC PLL4 configuration register 1.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 176, + "fieldset": "PLL4CFGR1" + }, + { + "name": "PLL4CFGR2", + "description": "RCC PLL4 configuration register 2.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 180, + "fieldset": "PLL4CFGR2" + }, + { + "name": "PLL4CFGR3", + "description": "RCC PLL4 configuration register 3.", + "array": { + "len": 4, + "stride": 16 + }, + "byte_offset": 184, + "fieldset": "PLL4CFGR3" + }, + { + "name": "IC1CFGR", + "description": "RCC IC1 configuration register.", + "byte_offset": 196, + "fieldset": "IC1CFGR" + }, + { + "name": "IC2CFGR", + "description": "RCC IC2 configuration register.", + "byte_offset": 200, + "fieldset": "IC2CFGR" + }, + { + "name": "IC3CFGR", + "description": "RCC IC3 configuration register.", + "byte_offset": 204, + "fieldset": "IC3CFGR" + }, + { + "name": "IC4CFGR", + "description": "RCC IC4 configuration register.", + "byte_offset": 208, + "fieldset": "IC4CFGR" + }, + { + "name": "IC5CFGR", + "description": "RCC IC5 configuration register.", + "byte_offset": 212, + "fieldset": "IC5CFGR" + }, + { + "name": "IC6CFGR", + "description": "RCC IC6 configuration register.", + "byte_offset": 216, + "fieldset": "IC6CFGR" + }, + { + "name": "IC7CFGR", + "description": "RCC IC7 configuration register.", + "byte_offset": 220, + "fieldset": "IC7CFGR" + }, + { + "name": "IC8CFGR", + "description": "RCC IC8 configuration register.", + "byte_offset": 224, + "fieldset": "IC8CFGR" + }, + { + "name": "IC9CFGR", + "description": "RCC IC9 configuration register.", + "byte_offset": 228, + "fieldset": "IC9CFGR" + }, + { + "name": "IC10CFGR", + "description": "RCC IC10 configuration register.", + "byte_offset": 232, + "fieldset": "IC10CFGR" + }, + { + "name": "IC11CFGR", + "description": "RCC IC11 configuration register.", + "byte_offset": 236, + "fieldset": "IC11CFGR" + }, + { + "name": "IC12CFGR", + "description": "RCC IC12 configuration register.", + "byte_offset": 240, + "fieldset": "IC12CFGR" + }, + { + "name": "IC13CFGR", + "description": "RCC IC13 configuration register.", + "byte_offset": 244, + "fieldset": "IC13CFGR" + }, + { + "name": "IC14CFGR", + "description": "RCC IC14 configuration register.", + "byte_offset": 248, + "fieldset": "IC14CFGR" + }, + { + "name": "IC15CFGR", + "description": "RCC IC15 configuration register.", + "byte_offset": 252, + "fieldset": "IC15CFGR" + }, + { + "name": "IC16CFGR", + "description": "RCC IC16 configuration register.", + "byte_offset": 256, + "fieldset": "IC16CFGR" + }, + { + "name": "IC17CFGR", + "description": "RCC IC17 configuration register.", + "byte_offset": 260, + "fieldset": "IC17CFGR" + }, + { + "name": "IC18CFGR", + "description": "RCC IC18 configuration register.", + "byte_offset": 264, + "fieldset": "IC18CFGR" + }, + { + "name": "IC19CFGR", + "description": "RCC IC19 configuration register.", + "byte_offset": 268, + "fieldset": "IC19CFGR" + }, + { + "name": "IC20CFGR", + "description": "RCC IC20 configuration register.", + "byte_offset": 272, + "fieldset": "IC20CFGR" + }, + { + "name": "CIER", + "description": "RCC clock-source interrupt enable register.", + "byte_offset": 292, + "fieldset": "CIER" + }, + { + "name": "CIFR", + "description": "RCC clock-source interrupt flag register.", + "byte_offset": 296, + "fieldset": "CIFR" + }, + { + "name": "CICR", + "description": "RCC clock-source interrupt Clear register.", + "byte_offset": 300, + "fieldset": "CICR" + }, + { + "name": "CCIPR1", + "description": "RCC clock configuration for independent peripheral register1.", + "byte_offset": 324, + "fieldset": "CCIPR1" + }, + { + "name": "CCIPR2", + "description": "RCC clock configuration for independent peripheral register 2.", + "byte_offset": 328, + "fieldset": "CCIPR2" + }, + { + "name": "CCIPR3", + "description": "RCC clock configuration for independent peripheral register3.", + "byte_offset": 332, + "fieldset": "CCIPR3" + }, + { + "name": "CCIPR4", + "description": "RCC clock configuration for independent peripheral register4.", + "byte_offset": 336, + "fieldset": "CCIPR4" + }, + { + "name": "CCIPR5", + "description": "RCC lock configuration for independent peripheral register5.", + "byte_offset": 340, + "fieldset": "CCIPR5" + }, + { + "name": "CCIPR6", + "description": "RCC clock configuration for independent peripheral register6.", + "byte_offset": 344, + "fieldset": "CCIPR6" + }, + { + "name": "CCIPR7", + "description": "RCC clock configuration for independent peripheral register7.", + "byte_offset": 348, + "fieldset": "CCIPR7" + }, + { + "name": "CCIPR8", + "description": "RCC clock configuration for independent peripheral register8.", + "byte_offset": 352, + "fieldset": "CCIPR8" + }, + { + "name": "CCIPR9", + "description": "RCC clock configuration for independent peripheral register9.", + "byte_offset": 356, + "fieldset": "CCIPR9" + }, + { + "name": "CCIPR12", + "description": "RCC clock configuration for independent peripheral register12.", + "byte_offset": 368, + "fieldset": "CCIPR12" + }, + { + "name": "CCIPR13", + "description": "RCC clock configuration for independent peripheral register13.", + "byte_offset": 372, + "fieldset": "CCIPR13" + }, + { + "name": "CCIPR14", + "description": "RCC clock configuration for independent peripheral register14.", + "byte_offset": 376, + "fieldset": "CCIPR14" + }, + { + "name": "BUSRSTR", + "description": "RCC SoC buses reset register.", + "byte_offset": 516, + "fieldset": "BUSRSTR" + }, + { + "name": "MISCRSTR", + "description": "RCC miscellaneous configurations reset register.", + "byte_offset": 520, + "fieldset": "MISCRSTR" + }, + { + "name": "MEMRSTR", + "description": "RCC memories reset register.", + "byte_offset": 524, + "fieldset": "MEMRSTR" + }, + { + "name": "AHB1RSTR", + "description": "RCC AHB1 Reset register.", + "byte_offset": 528, + "fieldset": "AHB1RSTR" + }, + { + "name": "AHB2RSTR", + "description": "RCC AHB2 reset register.", + "byte_offset": 532, + "fieldset": "AHB2RSTR" + }, + { + "name": "AHB3RSTR", + "description": "RCC AHB3 reset register.", + "byte_offset": 536, + "fieldset": "AHB3RSTR" + }, + { + "name": "AHB4RSTR", + "description": "RCC AHB4 reset register.", + "byte_offset": 540, + "fieldset": "AHB4RSTR" + }, + { + "name": "AHB5RSTR", + "description": "RCC AHB5 reset register.", + "byte_offset": 544, + "fieldset": "AHB5RSTR" + }, + { + "name": "APB1LRSTR", + "description": "RCC APB1L reset register.", + "byte_offset": 548, + "fieldset": "APB1LRSTR" + }, + { + "name": "APB1HRSTR", + "description": "RCC APB1H reset register.", + "byte_offset": 552, + "fieldset": "APB1HRSTR" + }, + { + "name": "APB2RSTR", + "description": "RCC APB2 reset register.", + "byte_offset": 556, + "fieldset": "APB2RSTR" + }, + { + "name": "APB4LRSTR", + "description": "RCC APB4L reset register.", + "byte_offset": 564, + "fieldset": "APB4LRSTR" + }, + { + "name": "APB4HRSTR", + "description": "RCC APB4H reset register.", + "byte_offset": 568, + "fieldset": "APB4HRSTR" + }, + { + "name": "APB5RSTR", + "description": "RCC APB5 reset register.", + "byte_offset": 572, + "fieldset": "APB5RSTR" + }, + { + "name": "DIVENR", + "description": "RCC IC dividers enable register.", + "byte_offset": 576, + "fieldset": "DIVENR" + }, + { + "name": "BUSENR", + "description": "RCC SoC buses enable register.", + "byte_offset": 580, + "fieldset": "BUSENR" + }, + { + "name": "MISCENR", + "description": "RCC miscellaneous configuration enable register.", + "byte_offset": 584, + "fieldset": "MISCENR" + }, + { + "name": "MEMENR", + "description": "RCC memory enable register.", + "byte_offset": 588, + "fieldset": "MEMENR" + }, + { + "name": "AHB1ENR", + "description": "RCC AHB1 enable register.", + "byte_offset": 592, + "fieldset": "AHB1ENR" + }, + { + "name": "AHB2ENR", + "description": "RCC AHB2 enable register.", + "byte_offset": 596, + "fieldset": "AHB2ENR" + }, + { + "name": "AHB3ENR", + "description": "RCC AHB3 enable register.", + "byte_offset": 600, + "fieldset": "AHB3ENR" + }, + { + "name": "AHB4ENR", + "description": "RCC AHB4 enable register.", + "byte_offset": 604, + "fieldset": "AHB4ENR" + }, + { + "name": "AHB5ENR", + "description": "RCC AHB5 enable register.", + "byte_offset": 608, + "fieldset": "AHB5ENR" + }, + { + "name": "APB1LENR", + "description": "RCC APB1L enable register.", + "byte_offset": 612, + "fieldset": "APB1LENR" + }, + { + "name": "APB1HENR", + "description": "RCC APB1H enable register.", + "byte_offset": 616, + "fieldset": "APB1HENR" + }, + { + "name": "APB2ENR", + "description": "RCC APB2 enable register.", + "byte_offset": 620, + "fieldset": "APB2ENR" + }, + { + "name": "APB3ENR", + "description": "RCC APB3 enable register.", + "byte_offset": 624, + "fieldset": "APB3ENR" + }, + { + "name": "APB4LENR", + "description": "RCC APB4L enable register.", + "byte_offset": 628, + "fieldset": "APB4LENR" + }, + { + "name": "APB4HENR", + "description": "RCC APB4H enable register.", + "byte_offset": 632, + "fieldset": "APB4HENR" + }, + { + "name": "APB5ENR", + "description": "RCC APB5 enable register.", + "byte_offset": 636, + "fieldset": "APB5ENR" + }, + { + "name": "DIVLPENR", + "description": "RCC dividers Sleep enable register.", + "byte_offset": 640, + "fieldset": "DIVLPENR" + }, + { + "name": "BUSLPENR", + "description": "RCC SoC buses Sleep enable register.", + "byte_offset": 644, + "fieldset": "BUSLPENR" + }, + { + "name": "MISCLPENR", + "description": "RCC miscellaneous configurations Sleep enable register.", + "byte_offset": 648, + "fieldset": "MISCLPENR" + }, + { + "name": "MEMLPENR", + "description": "RCC memory Sleep enable register.", + "byte_offset": 652, + "fieldset": "MEMLPENR" + }, + { + "name": "AHB1LPENR", + "description": "RCC AHB1 Sleep enable register.", + "byte_offset": 656, + "fieldset": "AHB1LPENR" + }, + { + "name": "AHB2LPENR", + "description": "RCC AHB2 Sleep enable register.", + "byte_offset": 660, + "fieldset": "AHB2LPENR" + }, + { + "name": "AHB3LPENR", + "description": "RCC AHB3 Sleep enable register.", + "byte_offset": 664, + "fieldset": "AHB3LPENR" + }, + { + "name": "AHB4LPENR", + "description": "RCC AHB4 Sleep enable register.", + "byte_offset": 668, + "fieldset": "AHB4LPENR" + }, + { + "name": "AHB5LPENR", + "description": "RCC AHB5 Sleep enable register.", + "byte_offset": 672, + "fieldset": "AHB5LPENR" + }, + { + "name": "APB1LLPENR", + "description": "RCC APB1L Sleep enable register.", + "byte_offset": 676, + "fieldset": "APB1LLPENR" + }, + { + "name": "APB1HLPENR", + "description": "RCC APB1H Sleep enable register.", + "byte_offset": 680, + "fieldset": "APB1HLPENR" + }, + { + "name": "APB2LPENR", + "description": "RCC APB2 Sleep enable register.", + "byte_offset": 684, + "fieldset": "APB2LPENR" + }, + { + "name": "APB3LPENR", + "description": "RCC APB3 Sleep enable register.", + "byte_offset": 688, + "fieldset": "APB3LPENR" + }, + { + "name": "APB4LLPENR", + "description": "RCC APB4L Sleep enable register.", + "byte_offset": 692, + "fieldset": "APB4LLPENR" + }, + { + "name": "APB4HLPENR", + "description": "RCC APB4H Sleep enable register.", + "byte_offset": 696, + "fieldset": "APB4HLPENR" + }, + { + "name": "APB5LPENR", + "description": "RCC APB5 Sleep enable register.", + "byte_offset": 700, + "fieldset": "APB5LPENR" + }, + { + "name": "RDCR", + "description": "RCC APB5 Sleep enable register.", + "byte_offset": 1100, + "fieldset": "RDCR" + }, + { + "name": "SECCFGR0", + "description": "RCC oscillator secure configuration register0.", + "byte_offset": 1920, + "fieldset": "SECCFGR0" + }, + { + "name": "PRIVCFGR0", + "description": "RCC oscillator privilege configuration register0.", + "byte_offset": 1924, + "fieldset": "PRIVCFGR0" + }, + { + "name": "LOCKCFGR0", + "description": "RCC oscillator lock configuration register0.", + "byte_offset": 1928, + "fieldset": "LOCKCFGR0" + }, + { + "name": "PUBCFGR0", + "description": "RCC oscillator public configuration register0.", + "byte_offset": 1932, + "fieldset": "PUBCFGR0" + }, + { + "name": "SECCFGR1", + "description": "RCC PLL secure configuration register1.", + "byte_offset": 1936, + "fieldset": "SECCFGR1" + }, + { + "name": "PRIVCFGR1", + "description": "RCC PLL privilege configuration register1.", + "byte_offset": 1940, + "fieldset": "PRIVCFGR1" + }, + { + "name": "LOCKCFGR1", + "description": "RCC PLL lock configuration register1.", + "byte_offset": 1944, + "fieldset": "LOCKCFGR1" + }, + { + "name": "PUBCFGR1", + "description": "RCC PLL public configuration register1.", + "byte_offset": 1948, + "fieldset": "PUBCFGR1" + }, + { + "name": "SECCFGR2", + "description": "RCC divider secure configuration register2.", + "byte_offset": 1952, + "fieldset": "SECCFGR2" + }, + { + "name": "PRIVCFGR2", + "description": "RCC divider privilege configuration register2.", + "byte_offset": 1956, + "fieldset": "PRIVCFGR2" + }, + { + "name": "LOCKCFGR2", + "description": "RCC divider lock configuration register2.", + "byte_offset": 1960, + "fieldset": "LOCKCFGR2" + }, + { + "name": "PUBCFGR2", + "description": "RCC divider public configuration register2.", + "byte_offset": 1964, + "fieldset": "PUBCFGR2" + }, + { + "name": "SECCFGR3", + "description": "RCC system secure configuration register3.", + "byte_offset": 1968, + "fieldset": "SECCFGR3" + }, + { + "name": "PRIVCFGR3", + "description": "RCC system privilege configuration register3.", + "byte_offset": 1972, + "fieldset": "PRIVCFGR3" + }, + { + "name": "LOCKCFGR3", + "description": "RCC system lock configuration register3.", + "byte_offset": 1976, + "fieldset": "LOCKCFGR3" + }, + { + "name": "PUBCFGR3", + "description": "RCC system public configuration register3.", + "byte_offset": 1980, + "fieldset": "PUBCFGR3" + }, + { + "name": "SECCFGR4", + "description": "RCC bus secure configuration register4.", + "byte_offset": 1984, + "fieldset": "SECCFGR4" + }, + { + "name": "PRIVCFGR4", + "description": "RCC bus privilege configuration register4.", + "byte_offset": 1988, + "fieldset": "PRIVCFGR4" + }, + { + "name": "LOCKCFGR4", + "description": "RCC bus lock configuration register4.", + "byte_offset": 1992, + "fieldset": "LOCKCFGR4" + }, + { + "name": "PUBCFGR4", + "description": "RCC bus public configuration register4.", + "byte_offset": 1996, + "fieldset": "PUBCFGR4" + }, + { + "name": "PUBCFGR5", + "description": "RCC bus public configuration register4.", + "byte_offset": 2000, + "fieldset": "PUBCFGR5" + }, + { + "name": "CSR", + "description": "RCC control set register.", + "byte_offset": 2048, + "fieldset": "CSR" + }, + { + "name": "STOPCSR", + "description": "RCC Stop configuration register.", + "byte_offset": 2056, + "fieldset": "STOPCSR" + }, + { + "name": "BUSRSTSR", + "description": "RCC bus reset set register.", + "byte_offset": 2564, + "fieldset": "BUSRSTSR" + }, + { + "name": "MISCRSTSR", + "description": "RCC miscellaneous reset register.", + "byte_offset": 2568, + "fieldset": "MISCRSTSR" + }, + { + "name": "MEMRSTSR", + "description": "RCC memory reset register.", + "byte_offset": 2572, + "fieldset": "MEMRSTSR" + }, + { + "name": "AHB1RSTSR", + "description": "RCC AHB1 reset register.", + "byte_offset": 2576, + "fieldset": "AHB1RSTSR" + }, + { + "name": "AHB2RSTSR", + "description": "RCC AHB2 reset register.", + "byte_offset": 2580, + "fieldset": "AHB2RSTSR" + }, + { + "name": "AHB3RSTSR", + "description": "RCC AHB3 reset register.", + "byte_offset": 2584, + "fieldset": "AHB3RSTSR" + }, + { + "name": "AHB4RSTSR", + "description": "RCC AHB4 reset register.", + "byte_offset": 2588, + "fieldset": "AHB4RSTSR" + }, + { + "name": "AHB5RSTSR", + "description": "RCC AHB5 reset register.", + "byte_offset": 2592, + "fieldset": "AHB5RSTSR" + }, + { + "name": "APB1LRSTSR", + "description": "RCC APB1L reset register.", + "byte_offset": 2596, + "fieldset": "APB1LRSTSR" + }, + { + "name": "APB1HRSTSR", + "description": "RCC APB1H reset register.", + "byte_offset": 2600, + "fieldset": "APB1HRSTSR" + }, + { + "name": "APB2RSTSR", + "description": "RCC APB2 reset register.", + "byte_offset": 2604, + "fieldset": "APB2RSTSR" + }, + { + "name": "APB4LRSTSR", + "description": "RCC APB4L reset register.", + "byte_offset": 2612, + "fieldset": "APB4LRSTSR" + }, + { + "name": "APB4HRSTSR", + "description": "RCC APB4H reset register.", + "byte_offset": 2616, + "fieldset": "APB4HRSTSR" + }, + { + "name": "APB5RSTSR", + "description": "RCC APB5 reset register.", + "byte_offset": 2620, + "fieldset": "APB5RSTSR" + }, + { + "name": "DIVENSR", + "description": "RCC Divider enable register.", + "byte_offset": 2624, + "fieldset": "DIVENSR" + }, + { + "name": "BUSENSR", + "description": "RCC bus enable register.", + "byte_offset": 2628, + "fieldset": "BUSENSR" + }, + { + "name": "MISCENSR", + "description": "RCC miscellaneous enable register.", + "byte_offset": 2632, + "fieldset": "MISCENSR" + }, + { + "name": "MEMENSR", + "description": "RCC memory enable register.", + "byte_offset": 2636, + "fieldset": "MEMENSR" + }, + { + "name": "AHB1ENSR", + "description": "RCC AHB1 enable register.", + "byte_offset": 2640, + "fieldset": "AHB1ENSR" + }, + { + "name": "AHB2ENSR", + "description": "RCC AHB2 enable register.", + "byte_offset": 2644, + "fieldset": "AHB2ENSR" + }, + { + "name": "AHB3ENSR", + "description": "RCC AHB3 enable register.", + "byte_offset": 2648, + "fieldset": "AHB3ENSR" + }, + { + "name": "AHB4ENSR", + "description": "RCC AHB4 enable register.", + "byte_offset": 2652, + "fieldset": "AHB4ENSR" + }, + { + "name": "AHB5ENSR", + "description": "RCC AHB5 enable register.", + "byte_offset": 2656, + "fieldset": "AHB5ENSR" + }, + { + "name": "APB1LENSR", + "description": "RCC APB1L enable register.", + "byte_offset": 2660, + "fieldset": "APB1LENSR" + }, + { + "name": "APB1HENSR", + "description": "RCC APB1H enable register.", + "byte_offset": 2664, + "fieldset": "APB1HENSR" + }, + { + "name": "APB2ENSR", + "description": "RCC APB2 enable register.", + "byte_offset": 2668, + "fieldset": "APB2ENSR" + }, + { + "name": "APB3ENSR", + "description": "RCC APB3 enable register.", + "byte_offset": 2672, + "fieldset": "APB3ENSR" + }, + { + "name": "APB4LENSR", + "description": "RCC APB4L enable register.", + "byte_offset": 2676, + "fieldset": "APB4LENSR" + }, + { + "name": "APB4HENSR", + "description": "RCC APB4H enable register.", + "byte_offset": 2680, + "fieldset": "APB4HENSR" + }, + { + "name": "APB5ENSR", + "description": "RCC APB5 enable register.", + "byte_offset": 2684, + "fieldset": "APB5ENSR" + }, + { + "name": "DIVLPENSR", + "description": "RCC divider Sleep enable register.", + "byte_offset": 2688, + "fieldset": "DIVLPENSR" + }, + { + "name": "BUSLPENSR", + "description": "RCC bus Sleep enable register.", + "byte_offset": 2692, + "fieldset": "BUSLPENSR" + }, + { + "name": "MISCLPENSR", + "description": "RCC miscellaneous Sleep enable register.", + "byte_offset": 2696, + "fieldset": "MISCLPENSR" + }, + { + "name": "MEMLPENSR", + "description": "RCC memory sleep enable register.", + "byte_offset": 2700, + "fieldset": "MEMLPENSR" + }, + { + "name": "AHB1LPENSR", + "description": "RCC AHB1 Sleep enable register.", + "byte_offset": 2704, + "fieldset": "AHB1LPENSR" + }, + { + "name": "AHB2LPENSR", + "description": "RCC AHB2 Sleep enable register.", + "byte_offset": 2708, + "fieldset": "AHB2LPENSR" + }, + { + "name": "AHB3LPENSR", + "description": "RCC AHB3 Sleep enable register.", + "byte_offset": 2712, + "fieldset": "AHB3LPENSR" + }, + { + "name": "AHB4LPENSR", + "description": "RCC AHB4 Sleep enable register.", + "byte_offset": 2716, + "fieldset": "AHB4LPENSR" + }, + { + "name": "AHB5LPENSR", + "description": "RCC AHB5 Sleep enable register.", + "byte_offset": 2720, + "fieldset": "AHB5LPENSR" + }, + { + "name": "APB1LLPENSR", + "description": "RCC APB1L Sleep enable register.", + "byte_offset": 2724, + "fieldset": "APB1LLPENSR" + }, + { + "name": "APB1HLPENSR", + "description": "RCC APB1H Sleep enable register.", + "byte_offset": 2728, + "fieldset": "APB1HLPENSR" + }, + { + "name": "APB2LPENSR", + "description": "RCC APB2 Sleep enable register.", + "byte_offset": 2732, + "fieldset": "APB2LPENSR" + }, + { + "name": "APB3LPENSR", + "description": "RCC APB3 Sleep enable register.", + "byte_offset": 2736, + "fieldset": "APB3LPENSR" + }, + { + "name": "APB4LLPENSR", + "description": "RCC APB4L Sleep enable register.", + "byte_offset": 2740, + "fieldset": "APB4LLPENSR" + }, + { + "name": "APB4HLPENSR", + "description": "RCC APB4H Sleep enable register.", + "byte_offset": 2744, + "fieldset": "APB4HLPENSR" + }, + { + "name": "APB5LPENSR", + "description": "RCC APB5 Sleep enable register.", + "byte_offset": 2748, + "fieldset": "APB5LPENSR" + }, + { + "name": "PRIVCFGSR0", + "description": "RCC oscillator privilege configuration register0.", + "byte_offset": 3972, + "fieldset": "PRIVCFGSR0" + }, + { + "name": "PUBCFGSR0", + "description": "RCC oscillator public configuration register0.", + "byte_offset": 3980, + "fieldset": "PUBCFGSR0" + }, + { + "name": "PRIVCFGSR1", + "description": "RCC PLL privilege configuration register1.", + "byte_offset": 3988, + "fieldset": "PRIVCFGSR1" + }, + { + "name": "PUBCFGSR1", + "description": "RCC PLL public configuration register1.", + "byte_offset": 3996, + "fieldset": "PUBCFGSR1" + }, + { + "name": "PRIVCFGSR2", + "description": "RCC divider privilege configuration register2.", + "byte_offset": 4004, + "fieldset": "PRIVCFGSR2" + }, + { + "name": "PUBCFGSR2", + "description": "RCC divider public configuration register2.", + "byte_offset": 4012, + "fieldset": "PUBCFGSR2" + }, + { + "name": "SECCFGSR3", + "description": "RCC system secure configuration register3.", + "byte_offset": 4016, + "fieldset": "SECCFGSR3" + }, + { + "name": "PRIVCFGSR3", + "description": "RCC system privilege configuration register3.", + "byte_offset": 4020, + "fieldset": "PRIVCFGSR3" + }, + { + "name": "LOCKCFGSR3", + "description": "RCC system lock configuration register3.", + "byte_offset": 4024, + "fieldset": "LOCKCFGSR3" + }, + { + "name": "PUBCFGSR3", + "description": "RCC system public configuration register3.", + "byte_offset": 4028, + "fieldset": "PUBCFGSR3" + }, + { + "name": "PRIVCFGSR4", + "description": "RCC privilege configuration register4.", + "byte_offset": 4036, + "fieldset": "PRIVCFGSR4" + }, + { + "name": "PUBCFGSR4", + "description": "RCC public configuration register4.", + "byte_offset": 4044, + "fieldset": "PUBCFGSR4" + }, + { + "name": "PUBCFGSR5", + "description": "RCC public configuration register4.", + "byte_offset": 4048, + "fieldset": "PUBCFGSR5" + }, + { + "name": "CCR", + "description": "RCC control Clear register.", + "byte_offset": 4096, + "fieldset": "CCR" + }, + { + "name": "STOPCCR", + "description": "RCC StopCCR configuration register.", + "byte_offset": 4104, + "fieldset": "STOPCCR" + }, + { + "name": "BUSRSTCR", + "description": "RCC bus reset register.", + "byte_offset": 4612, + "fieldset": "BUSRSTCR" + }, + { + "name": "MISCRSTCR", + "description": "RCC miscellaneous reset register.", + "byte_offset": 4616, + "fieldset": "MISCRSTCR" + }, + { + "name": "MEMRSTCR", + "description": "RCC memory reset register.", + "byte_offset": 4620, + "fieldset": "MEMRSTCR" + }, + { + "name": "AHB1RSTCR", + "description": "RCC AHB1 reset register.", + "byte_offset": 4624, + "fieldset": "AHB1RSTCR" + }, + { + "name": "AHB2RSTCR", + "description": "RCC AHB2 Reset register.", + "byte_offset": 4628, + "fieldset": "AHB2RSTCR" + }, + { + "name": "AHB3RSTCR", + "description": "RCC AHB3 reset register.", + "byte_offset": 4632, + "fieldset": "AHB3RSTCR" + }, + { + "name": "AHB4RSTCR", + "description": "RCC AHB4 reset register.", + "byte_offset": 4636, + "fieldset": "AHB4RSTCR" + }, + { + "name": "AHB5RSTCR", + "description": "RCC AHB5 reset register.", + "byte_offset": 4640, + "fieldset": "AHB5RSTCR" + }, + { + "name": "APB1LRSTCR", + "description": "RCC APB1L reset register.", + "byte_offset": 4644, + "fieldset": "APB1LRSTCR" + }, + { + "name": "APB1HRSTCR", + "description": "RCC APB1H reset register.", + "byte_offset": 4648, + "fieldset": "APB1HRSTCR" + }, + { + "name": "APB2RSTCR", + "description": "RCC APB2 reset register.", + "byte_offset": 4652, + "fieldset": "APB2RSTCR" + }, + { + "name": "APB4LRSTCR", + "description": "RCC APB4L reset register.", + "byte_offset": 4660, + "fieldset": "APB4LRSTCR" + }, + { + "name": "APB4HRSTCR", + "description": "RCC APB4H reset register.", + "byte_offset": 4664, + "fieldset": "APB4HRSTCR" + }, + { + "name": "APB5RSTCR", + "description": "RCC APB5 reset register.", + "byte_offset": 4668, + "fieldset": "APB5RSTCR" + }, + { + "name": "DIVENCR", + "description": "RCC divider enable register.", + "byte_offset": 4672, + "fieldset": "DIVENCR" + }, + { + "name": "BUSENCR", + "description": "RCC bus enable register.", + "byte_offset": 4676, + "fieldset": "BUSENCR" + }, + { + "name": "MISCENCR", + "description": "RCC miscellaneous enable register.", + "byte_offset": 4680, + "fieldset": "MISCENCR" + }, + { + "name": "MEMENCR", + "description": "RCC memory enable register.", + "byte_offset": 4684, + "fieldset": "MEMENCR" + }, + { + "name": "AHB1ENCR", + "description": "RCC AHB1 enable register.", + "byte_offset": 4688, + "fieldset": "AHB1ENCR" + }, + { + "name": "AHB2ENCR", + "description": "RCC AHB2 enable register.", + "byte_offset": 4692, + "fieldset": "AHB2ENCR" + }, + { + "name": "AHB3ENCR", + "description": "RCC AHB3 enable register.", + "byte_offset": 4696, + "fieldset": "AHB3ENCR" + }, + { + "name": "AHB4ENCR", + "description": "RCC AHB4 enable register.", + "byte_offset": 4700, + "fieldset": "AHB4ENCR" + }, + { + "name": "AHB5ENCR", + "description": "RCC AHB5 enable register.", + "byte_offset": 4704, + "fieldset": "AHB5ENCR" + }, + { + "name": "APB1LENCR", + "description": "RCC APB1L enable register.", + "byte_offset": 4708, + "fieldset": "APB1LENCR" + }, + { + "name": "APB1HENCR", + "description": "RCC APB1H enable register.", + "byte_offset": 4712, + "fieldset": "APB1HENCR" + }, + { + "name": "APB2ENCR", + "description": "RCC APB2 enable register.", + "byte_offset": 4716, + "fieldset": "APB2ENCR" + }, + { + "name": "APB3ENCR", + "description": "RCC APB3 enable register.", + "byte_offset": 4720, + "fieldset": "APB3ENCR" + }, + { + "name": "APB4LENCR", + "description": "RCC APB4L enable register.", + "byte_offset": 4724, + "fieldset": "APB4LENCR" + }, + { + "name": "APB4HENCR", + "description": "RCC APB4H enable register.", + "byte_offset": 4728, + "fieldset": "APB4HENCR" + }, + { + "name": "APB5ENCR", + "description": "RCC APB5 enable register.", + "byte_offset": 4732, + "fieldset": "APB5ENCR" + }, + { + "name": "DIVLPENCR", + "description": "RCC divider Sleep enable register.", + "byte_offset": 4736, + "fieldset": "DIVLPENCR" + }, + { + "name": "BUSLPENCR", + "description": "RCC bus Sleep enable register.", + "byte_offset": 4740, + "fieldset": "BUSLPENCR" + }, + { + "name": "MISCLPENCR", + "description": "RCC miscellaneous Sleep enable register.", + "byte_offset": 4744, + "fieldset": "MISCLPENCR" + }, + { + "name": "MEMLPENCR", + "description": "RCC memory Sleep enable register.", + "byte_offset": 4748, + "fieldset": "MEMLPENCR" + }, + { + "name": "AHB1LPENCR", + "description": "RCC AHB1 Sleep enable register.", + "byte_offset": 4752, + "fieldset": "AHB1LPENCR" + }, + { + "name": "AHB2LPENCR", + "description": "RCC AHB2 Sleep enable register.", + "byte_offset": 4756, + "fieldset": "AHB2LPENCR" + }, + { + "name": "AHB3LPENCR", + "description": "RCC AHB3 Sleep enable register.", + "byte_offset": 4760, + "fieldset": "AHB3LPENCR" + }, + { + "name": "AHB4LPENCR", + "description": "RCC AHB4 Sleep enable register.", + "byte_offset": 4764, + "fieldset": "AHB4LPENCR" + }, + { + "name": "AHB5LPENCR", + "description": "RCC AHB5 Sleep enable register.", + "byte_offset": 4768, + "fieldset": "AHB5LPENCR" + }, + { + "name": "APB1LLPENCR", + "description": "RCC APB1L Sleep enable register.", + "byte_offset": 4772, + "fieldset": "APB1LLPENCR" + }, + { + "name": "APB1HLPENCR", + "description": "RCC APB1H Sleep enable register.", + "byte_offset": 4776, + "fieldset": "APB1HLPENCR" + }, + { + "name": "APB2LPENCR", + "description": "RCC APB2 Sleep enable register.", + "byte_offset": 4780, + "fieldset": "APB2LPENCR" + }, + { + "name": "APB3LPENCR", + "description": "RCC APB3 Sleep enable register.", + "byte_offset": 4784, + "fieldset": "APB3LPENCR" + }, + { + "name": "APB4LLPENCR", + "description": "RCC APB4L Sleep enable register.", + "byte_offset": 4788, + "fieldset": "APB4LLPENCR" + }, + { + "name": "APB4HLPENCR", + "description": "RCC APB4H Sleep enable register.", + "byte_offset": 4792, + "fieldset": "APB4HLPENCR" + }, + { + "name": "APB5LPENCR", + "description": "RCC APB5 Sleep enable register.", + "byte_offset": 4796, + "fieldset": "APB5LPENCR" + }, + { + "name": "PRIVCFGCR0", + "description": "RCC oscillator privilege configuration register0.", + "byte_offset": 6020, + "fieldset": "PRIVCFGCR0" + }, + { + "name": "PUBCFGCR0", + "description": "RCC oscillator public configuration register0.", + "byte_offset": 6028, + "fieldset": "PUBCFGCR0" + }, + { + "name": "PRIVCFGCR1", + "description": "RCC PLL privilege configuration register1.", + "byte_offset": 6036, + "fieldset": "PRIVCFGCR1" + }, + { + "name": "PUBCFGCR1", + "description": "RCC PLL public configuration register1.", + "byte_offset": 6044, + "fieldset": "PUBCFGCR1" + }, + { + "name": "PRIVCFGCR2", + "description": "RCC divider privilege configuration register2.", + "byte_offset": 6052, + "fieldset": "PRIVCFGCR2" + }, + { + "name": "PUBCFGCR2", + "description": "RCC divider public configuration register2.", + "byte_offset": 6060, + "fieldset": "PUBCFGCR2" + }, + { + "name": "PRIVCFGCR3", + "description": "RCC system privilege configuration register3.", + "byte_offset": 6068, + "fieldset": "PRIVCFGCR3" + }, + { + "name": "PUBCFGCR3", + "description": "RCC system public configuration register3.", + "byte_offset": 6076, + "fieldset": "PUBCFGCR3" + }, + { + "name": "PRIVCFGCR4", + "description": "RCC privilege configuration register4.", + "byte_offset": 6084, + "fieldset": "PRIVCFGCR4" + }, + { + "name": "PUBCFGCR4", + "description": "RCC public configuration register4.", + "byte_offset": 6092, + "fieldset": "PUBCFGCR4" + }, + { + "name": "PUBCFGCR5", + "description": "RCC public configuration register4.", + "byte_offset": 6096, + "fieldset": "PUBCFGCR5" + } + ] + }, + "fieldset/AHB1ENCR": { + "description": "RCC AHB1 enable register.", + "fields": [ + { + "name": "GPDMA1ENC", + "description": "GPDMA1 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADC12ENC", + "description": "ADC12 enable.", + "bit_offset": 5, + "bit_size": 1 + } + ] + }, + "fieldset/AHB1ENR": { + "description": "RCC AHB1 enable register.", + "fields": [ + { + "name": "GPDMA1EN", + "description": "GPDMA1 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADC12EN", + "description": "ADC12 enable.", + "bit_offset": 5, + "bit_size": 1 + } + ] + }, + "fieldset/AHB1ENSR": { + "description": "RCC AHB1 enable register.", + "fields": [ + { + "name": "GPDMA1ENS", + "description": "GPDMA1 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADC12ENS", + "description": "ADC12 enable.", + "bit_offset": 5, + "bit_size": 1 + } + ] + }, + "fieldset/AHB1LPENCR": { + "description": "RCC AHB1 Sleep enable register.", + "fields": [ + { + "name": "GPDMA1LPENC", + "description": "GPDMA1 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADC12LPENC", + "description": "ADC12 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + } + ] + }, + "fieldset/AHB1LPENR": { + "description": "RCC AHB1 Sleep enable register.", + "fields": [ + { + "name": "GPDMA1LPEN", + "description": "GPDMA1 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADC12LPEN", + "description": "ADC12 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + } + ] + }, + "fieldset/AHB1LPENSR": { + "description": "RCC AHB1 Sleep enable register.", + "fields": [ + { + "name": "GPDMA1LPENS", + "description": "GPDMA1 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADC12LPENS", + "description": "ADC12 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + } + ] + }, + "fieldset/AHB1RSTCR": { + "description": "RCC AHB1 reset register.", + "fields": [ + { + "name": "GPDMA1RSTC", + "description": "GPDMA1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADC12RSTC", + "description": "ADC12 reset.", + "bit_offset": 5, + "bit_size": 1 + } + ] + }, + "fieldset/AHB1RSTR": { + "description": "RCC AHB1 Reset register.", + "fields": [ + { + "name": "GPDMA1RST", + "description": "GPDMA1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADC12RST", + "description": "ADC12 reset.", + "bit_offset": 5, + "bit_size": 1 + } + ] + }, + "fieldset/AHB1RSTSR": { + "description": "RCC AHB1 reset register.", + "fields": [ + { + "name": "GPDMA1RSTS", + "description": "GPDMA1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADC12RSTS", + "description": "ADC12 reset.", + "bit_offset": 5, + "bit_size": 1 + } + ] + }, + "fieldset/AHB2ENCR": { + "description": "RCC AHB2 enable register.", + "fields": [ + { + "name": "RAMCFGENC", + "description": "RAMCFG enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "MDF1ENC", + "description": "MDF1 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ADF1ENC", + "description": "ADF1 enable.", + "bit_offset": 17, + "bit_size": 1 + } + ] + }, + "fieldset/AHB2ENR": { + "description": "RCC AHB2 enable register.", + "fields": [ + { + "name": "RAMCFGEN", + "description": "RAMCFG enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "MDF1EN", + "description": "MDF1 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ADF1EN", + "description": "ADF enable.", + "bit_offset": 17, + "bit_size": 1 + } + ] + }, + "fieldset/AHB2ENSR": { + "description": "RCC AHB2 enable register.", + "fields": [ + { + "name": "RAMCFGENS", + "description": "RAMCFG enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "MDF1ENS", + "description": "MDF1 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ADF1ENS", + "description": "ADF1 enable.", + "bit_offset": 17, + "bit_size": 1 + } + ] + }, + "fieldset/AHB2LPENCR": { + "description": "RCC AHB2 Sleep enable register.", + "fields": [ + { + "name": "RAMCFGLPENC", + "description": "RAMCFG sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "MDF1LPENC", + "description": "MDF1 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ADF1LPENC", + "description": "ADF1 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + } + ] + }, + "fieldset/AHB2LPENR": { + "description": "RCC AHB2 Sleep enable register.", + "fields": [ + { + "name": "RAMCFGLPEN", + "description": "RAMCFG sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "MDF1LPEN", + "description": "MDF1 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ADF1LPEN", + "description": "ADF1 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + } + ] + }, + "fieldset/AHB2LPENSR": { + "description": "RCC AHB2 Sleep enable register.", + "fields": [ + { + "name": "RAMCFGLPENS", + "description": "RAMCFG sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "MDF1LPENS", + "description": "MDF1 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ADF1LPENS", + "description": "ADF1 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + } + ] + }, + "fieldset/AHB2RSTCR": { + "description": "RCC AHB2 Reset register.", + "fields": [ + { + "name": "RAMCFGRSTC", + "description": "RAMCFG reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "MDF1RSTC", + "description": "MDF1 reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ADF1RSTC", + "description": "ADF1 reset.", + "bit_offset": 17, + "bit_size": 1 + } + ] + }, + "fieldset/AHB2RSTR": { + "description": "RCC AHB2 reset register.", + "fields": [ + { + "name": "RAMCFGRST", + "description": "RAMCFG reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "MDF1RST", + "description": "MDF1 reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ADF1RST", + "description": "ADF1 reset.", + "bit_offset": 17, + "bit_size": 1 + } + ] + }, + "fieldset/AHB2RSTSR": { + "description": "RCC AHB2 reset register.", + "fields": [ + { + "name": "RAMCFGRSTS", + "description": "RAMCFG reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "MDF1RSTS", + "description": "MDF1 reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "ADF1RSTS", + "description": "ADF1 reset.", + "bit_offset": 17, + "bit_size": 1 + } + ] + }, + "fieldset/AHB3ENCR": { + "description": "RCC AHB3 enable register.", + "fields": [ + { + "name": "RNGENC", + "description": "RNG enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "HASHENC", + "description": "HASH enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CRYPENC", + "description": "CRYP enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "SAESENC", + "description": "SAES enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PKAENC", + "description": "PKA enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "RIFSCENC", + "description": "RIFSC enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IACENC", + "description": "IAC enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "RISAFENC", + "description": "RISAF enable.", + "bit_offset": 14, + "bit_size": 1 + } + ] + }, + "fieldset/AHB3ENR": { + "description": "RCC AHB3 enable register.", + "fields": [ + { + "name": "RNGEN", + "description": "RNG enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "HASHEN", + "description": "HASH enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CRYPEN", + "description": "CRYP enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "SAESEN", + "description": "SAES enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PKAEN", + "description": "PKA enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "RIFSCEN", + "description": "RIFSC enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IACEN", + "description": "IAC enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "RISAFEN", + "description": "RISAF enable.", + "bit_offset": 14, + "bit_size": 1 + } + ] + }, + "fieldset/AHB3ENSR": { + "description": "RCC AHB3 enable register.", + "fields": [ + { + "name": "RNGENS", + "description": "RNG enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "HASHENS", + "description": "HASH enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CRYPENS", + "description": "CRYP enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "SAESENS", + "description": "SAES enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PKAENS", + "description": "PKA enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "RIFSCENS", + "description": "RIFSC enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IACENS", + "description": "IAC enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "RISAFENS", + "description": "RISAF enable.", + "bit_offset": 14, + "bit_size": 1 + } + ] + }, + "fieldset/AHB3LPENCR": { + "description": "RCC AHB3 Sleep enable register.", + "fields": [ + { + "name": "RNGLPENC", + "description": "RNG sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "HASHLPENC", + "description": "HASH sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CRYPLPENC", + "description": "CRYP sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "SAESLPENC", + "description": "SAES sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PKALPENC", + "description": "PKA sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "RIFSCLPENC", + "description": "RIFSC sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IACLPENC", + "description": "IAC sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "RISAFLPENC", + "description": "RISAF sleep enable.", + "bit_offset": 14, + "bit_size": 1 + } + ] + }, + "fieldset/AHB3LPENR": { + "description": "RCC AHB3 Sleep enable register.", + "fields": [ + { + "name": "RNGLPEN", + "description": "RNG sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "HASHLPEN", + "description": "HASH sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CRYPLPEN", + "description": "CRYP sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "SAESLPEN", + "description": "SAES sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PKALPEN", + "description": "PKA sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "RIFSCLPEN", + "description": "RIFSC sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IACLPEN", + "description": "IAC sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "RISAFLPEN", + "description": "RISAF sleep enable.", + "bit_offset": 14, + "bit_size": 1 + } + ] + }, + "fieldset/AHB3LPENSR": { + "description": "RCC AHB3 Sleep enable register.", + "fields": [ + { + "name": "RNGLPENS", + "description": "RNG sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "HASHLPENS", + "description": "HASH sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CRYPLPENS", + "description": "CRYP sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "SAESLPENS", + "description": "SAES sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PKALPENS", + "description": "PKA sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "RIFSCLPENS", + "description": "RIFSC sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IACLPENS", + "description": "IAC sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "RISAFLPENS", + "description": "RISAF sleep enable.", + "bit_offset": 14, + "bit_size": 1 + } + ] + }, + "fieldset/AHB3RSTCR": { + "description": "RCC AHB3 reset register.", + "fields": [ + { + "name": "RNGRSTC", + "description": "RNG reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "HASHRSTC", + "description": "HASH reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CRYPRSTC", + "description": "CRYP reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "SAESRSTC", + "description": "SAES reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PKARSTC", + "description": "PKA reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IACRSTC", + "description": "IAC reset.", + "bit_offset": 10, + "bit_size": 1 + } + ] + }, + "fieldset/AHB3RSTR": { + "description": "RCC AHB3 reset register.", + "fields": [ + { + "name": "RNGRST", + "description": "RNG reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "HASHRST", + "description": "HASH reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CRYPRST", + "description": "CRYP reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "SAESRST", + "description": "SAES reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PKARST", + "description": "PKA reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IACRST", + "description": "IAC reset.", + "bit_offset": 10, + "bit_size": 1 + } + ] + }, + "fieldset/AHB3RSTSR": { + "description": "RCC AHB3 reset register.", + "fields": [ + { + "name": "RNGRSTS", + "description": "RNG reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "HASHRSTS", + "description": "HASH reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CRYPRSTS", + "description": "CRYP reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "SAESRSTS", + "description": "SAES reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PKARSTS", + "description": "PKA reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IACRSTS", + "description": "IAC reset.", + "bit_offset": 10, + "bit_size": 1 + } + ] + }, + "fieldset/AHB4ENCR": { + "description": "RCC AHB4 enable register.", + "fields": [ + { + "name": "GPIOAENC", + "description": "GPIOA enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "GPIOBENC", + "description": "GPIOB enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GPIOCENC", + "description": "GPIOC enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GPIODENC", + "description": "GPIOD enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "GPIOEENC", + "description": "GPIOE enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "GPIOFENC", + "description": "GPIOF enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "GPIOGENC", + "description": "GPIOG enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "GPIOHENC", + "description": "GPIOH enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GPIONENC", + "description": "GPION enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GPIOOENC", + "description": "GPIOO enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "GPIOPENC", + "description": "GPIOP enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "GPIOQENC", + "description": "GPIOQ enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PWRENC", + "description": "PWR enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "CRCENC", + "description": "CRC enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/AHB4ENR": { + "description": "RCC AHB4 enable register.", + "fields": [ + { + "name": "GPIOAEN", + "description": "GPIOA enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "GPIOBEN", + "description": "GPIOB enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GPIOCEN", + "description": "GPIOC enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GPIODEN", + "description": "GPIOD enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "GPIOEEN", + "description": "GPIOE enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "GPIOFEN", + "description": "GPIOF enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "GPIOGEN", + "description": "GPIOG enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "GPIOHEN", + "description": "GPIOH enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GPIONEN", + "description": "GPION enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GPIOOEN", + "description": "GPIOO enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "GPIOPEN", + "description": "GPIOP enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "GPIOQEN", + "description": "GPIOQ enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PWREN", + "description": "PWR enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "CRCEN", + "description": "CRC enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/AHB4ENSR": { + "description": "RCC AHB4 enable register.", + "fields": [ + { + "name": "GPIOAENS", + "description": "GPIOA enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "GPIOBENS", + "description": "GPIOB enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GPIOCENS", + "description": "GPIOC enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GPIODENS", + "description": "GPIOD enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "GPIOEENS", + "description": "GPIOE enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "GPIOFENS", + "description": "GPIOF enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "GPIOGENS", + "description": "GPIOG enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "GPIOHENS", + "description": "GPIOH enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GPIONENS", + "description": "GPION enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GPIOOENS", + "description": "GPIOO enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "GPIOPENS", + "description": "GPIOP enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "GPIOQENS", + "description": "GPIOQ enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PWRENS", + "description": "PWR enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "CRCENS", + "description": "CRC enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/AHB4LPENCR": { + "description": "RCC AHB4 Sleep enable register.", + "fields": [ + { + "name": "GPIOALPENC", + "description": "GPIOA sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "GPIOBLPENC", + "description": "GPIOB sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GPIOCLPENC", + "description": "GPIOC sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GPIODLPENC", + "description": "GPIOD sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "GPIOELPENC", + "description": "GPIOE sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "GPIOFLPENC", + "description": "GPIOF sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "GPIOGLPENC", + "description": "GPIOG sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "GPIOHLPENC", + "description": "GPIOH sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GPIONLPENC", + "description": "GPION sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GPIOOLPENC", + "description": "GPIOO sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "GPIOPLPENC", + "description": "GPIOP sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "GPIOQLPENC", + "description": "GPIOQ sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PWRLPENC", + "description": "PWR sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "CRCLPENC", + "description": "CRC sleep enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/AHB4LPENR": { + "description": "RCC AHB4 Sleep enable register.", + "fields": [ + { + "name": "GPIOALPEN", + "description": "GPIOA sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "GPIOBLPEN", + "description": "GPIOB sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GPIOCLPEN", + "description": "GPIOC sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GPIODLPEN", + "description": "GPIOD sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "GPIOELPEN", + "description": "GPIOE sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "GPIOFLPEN", + "description": "GPIOF sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "GPIOGLPEN", + "description": "GPIOG sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "GPIOHLPEN", + "description": "GPIOH sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GPIONLPEN", + "description": "GPION sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GPIOOLPEN", + "description": "GPIOO sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "GPIOPLPEN", + "description": "GPIOP sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "GPIOQLPEN", + "description": "GPIOQ sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PWRLPEN", + "description": "PWR sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "CRCLPEN", + "description": "CRC sleep enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/AHB4LPENSR": { + "description": "RCC AHB4 Sleep enable register.", + "fields": [ + { + "name": "GPIOALPENS", + "description": "GPIOA sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "GPIOBLPENS", + "description": "GPIOB sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GPIOCLPENS", + "description": "GPIOC sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GPIODLPENS", + "description": "GPIOD sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "GPIOELPENS", + "description": "GPIOE sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "GPIOFLPENS", + "description": "GPIOF sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "GPIOGLPENS", + "description": "GPIOG sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "GPIOHLPENS", + "description": "GPIOH sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GPIONLPENS", + "description": "GPION sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GPIOOLPENS", + "description": "GPIOO sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "GPIOPLPENS", + "description": "GPIOP sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "GPIOQLPENS", + "description": "GPIOQ sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PWRLPENS", + "description": "PWR sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "CRCLPENS", + "description": "CRC sleep enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/AHB4RSTCR": { + "description": "RCC AHB4 reset register.", + "fields": [ + { + "name": "GPIOARSTC", + "description": "GPIOA reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "GPIOBRSTC", + "description": "GPIOB reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GPIOCRSTC", + "description": "GPIOC reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GPIODRSTC", + "description": "GPIOD reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "GPIOERSTC", + "description": "GPIOE reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "GPIOFRSTC", + "description": "GPIOF reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "GPIOGRSTC", + "description": "GPIOG reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "GPIOHRSTC", + "description": "GPIOH reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GPIONRSTC", + "description": "GPION reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GPIOORSTC", + "description": "GPIOO reset.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "GPIOPRSTC", + "description": "GPIOP reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "GPIOQRSTC", + "description": "GPIOQ reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PWRRSTC", + "description": "PWR reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "CRCRSTC", + "description": "CRC reset.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/AHB4RSTR": { + "description": "RCC AHB4 reset register.", + "fields": [ + { + "name": "GPIOARST", + "description": "GPIOA reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "GPIOBRST", + "description": "GPIOB reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GPIOCRST", + "description": "GPIOC reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GPIODRST", + "description": "GPIOD reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "GPIOERST", + "description": "GPIOE reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "GPIOFRST", + "description": "GPIOF reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "GPIOGRST", + "description": "GPIOG reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "GPIOHRST", + "description": "GPIOH reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GPIONRST", + "description": "GPION reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GPIOORST", + "description": "GPIOO reset.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "GPIOPRST", + "description": "GPIOP reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "GPIOQRST", + "description": "GPIOQ reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PWRRST", + "description": "PWR reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "CRCRST", + "description": "CRC reset.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/AHB4RSTSR": { + "description": "RCC AHB4 reset register.", + "fields": [ + { + "name": "GPIOARSTS", + "description": "GPIOA reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "GPIOBRSTS", + "description": "GPIOB reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "GPIOCRSTS", + "description": "GPIOC reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GPIODRSTS", + "description": "GPIOD reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "GPIOERSTS", + "description": "GPIOE reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "GPIOFRSTS", + "description": "GPIOF reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "GPIOGRSTS", + "description": "GPIOG reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "GPIOHRSTS", + "description": "GPIOH reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "GPIONRSTS", + "description": "GPION reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "GPIOORSTS", + "description": "GPIOO reset.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "GPIOPRSTS", + "description": "GPIOP reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "GPIOQRSTS", + "description": "GPIOQ reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "PWRRSTS", + "description": "PWR reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "CRCRSTS", + "description": "CRC reset.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/AHB5ENCR": { + "description": "RCC AHB5 enable register.", + "fields": [ + { + "name": "HPDMA1ENC", + "description": "HPDMA1 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMA2DENC", + "description": "DMA2D enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "JPEGENC", + "description": "JPEG enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FMCENC", + "description": "FMC enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPI1ENC", + "description": "XSPI1 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "PSSIENC", + "description": "PSSI enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SDMMC2ENC", + "description": "SDMMC2 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC1ENC", + "description": "SDMMC1 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "XSPI2ENC", + "description": "XSPI2 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "XSPIMENC", + "description": "XSPIM enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "MCE1ENC", + "description": "MCE1 enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "MCE2ENC", + "description": "MCE2 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "MCE3ENC", + "description": "MCE3 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "XSPI3ENC", + "description": "XSPI3 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "MCE4ENC", + "description": "MCE4 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "GFXMMUENC", + "description": "GFXMMU enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "GPUENC", + "description": "GPU enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ETH1MACENC", + "description": "ETH1MAC enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ETH1TXENC", + "description": "ETH1TX enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ETH1RXENC", + "description": "ETH1RX enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ETH1ENC", + "description": "ETH1 enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "OTG1ENC", + "description": "OTG1 enable.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "OTGPHY1ENC", + "description": "OTGPHY1 enable.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "OTGPHY2ENC", + "description": "OTGPHY2 enable.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "OTG2ENC", + "description": "OTG2 enable.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "NPUCACHEENC", + "description": "NPUCACHE enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "NPUENC", + "description": "NPU enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/AHB5ENR": { + "description": "RCC AHB5 enable register.", + "fields": [ + { + "name": "HPDMA1EN", + "description": "HPDMA1 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMA2DEN", + "description": "DMA2D enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "JPEGEN", + "description": "JPEG enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FMCEN", + "description": "FMC enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPI1EN", + "description": "XSPI1 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "PSSIEN", + "description": "PSSI enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SDMMC2EN", + "description": "SDMMC2 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC1EN", + "description": "SDMMC1 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "XSPI2EN", + "description": "XSPI2 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "XSPIMEN", + "description": "XSPIM enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "MCE1EN", + "description": "MCE1 enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "MCE2EN", + "description": "MCE2 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "MCE3EN", + "description": "MCE3 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "XSPI3EN", + "description": "XSPI3 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "MCE4EN", + "description": "MCE4 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "GFXMMUEN", + "description": "GFXMMU enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "GPUEN", + "description": "GPU enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ETH1MACEN", + "description": "ETH1MAC enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ETH1TXEN", + "description": "ETH1TX enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ETH1RXEN", + "description": "ETH1RX enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ETH1EN", + "description": "ETH1 enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "OTG1EN", + "description": "OTG1 enable.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "OTGPHY1EN", + "description": "OTGPHY1 enable.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "OTGPHY2EN", + "description": "OTGPHY2 enable.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "OTG2EN", + "description": "OTG2 enable.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "NPUCACHEEN", + "description": "NPUCACHE enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "NPUEN", + "description": "NPU enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/AHB5ENSR": { + "description": "RCC AHB5 enable register.", + "fields": [ + { + "name": "HPDMA1ENS", + "description": "HPDMA1 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMA2DENS", + "description": "DMA2D enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "JPEGENS", + "description": "JPEG enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FMCENS", + "description": "FMC enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPI1ENS", + "description": "XSPI1 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "PSSIENS", + "description": "PSSI enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SDMMC2ENS", + "description": "SDMMC2 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC1ENS", + "description": "SDMMC1 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "XSPI2ENS", + "description": "XSPI2 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "XSPIMENS", + "description": "XSPIM enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "MCE1ENS", + "description": "MCE1 enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "MCE2ENS", + "description": "MCE2 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "MCE3ENS", + "description": "MCE3 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "XSPI3ENS", + "description": "XSPI3 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "MCE4ENS", + "description": "MCE4 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "GFXMMUENS", + "description": "GFXMMU enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "GPUENS", + "description": "GPU enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ETH1MACENS", + "description": "ETH1MAC enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ETH1TXENS", + "description": "ETH1TX enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ETH1RXENS", + "description": "ETH1RX enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ETH1ENS", + "description": "ETH1 enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "OTG1ENS", + "description": "OTG1 enable.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "OTGPHY1ENS", + "description": "OTGPHY1 enable.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "OTGPHY2ENS", + "description": "OTGPHY2 enable.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "OTG2ENS", + "description": "OTG2 enable.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "NPUCACHEENS", + "description": "NPUCACHE enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "NPUENS", + "description": "NPU enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/AHB5LPENCR": { + "description": "RCC AHB5 Sleep enable register.", + "fields": [ + { + "name": "HPDMA1LPENC", + "description": "HPDMA1 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMA2DLPENC", + "description": "DMA2D sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "JPEGLPENC", + "description": "JPEG sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FMCLPENC", + "description": "FMC sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPI1LPENC", + "description": "XSPI1 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "PSSILPENC", + "description": "PSSI sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SDMMC2LPENC", + "description": "SDMMC2 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC1LPENC", + "description": "SDMMC1 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "XSPI2LPENC", + "description": "XSPI2 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "XSPIMLPENC", + "description": "XSPIM sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "MCE1LPENC", + "description": "MCE1 sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "MCE2LPENC", + "description": "MCE2 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "MCE3LPENC", + "description": "MCE3 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "XSPI3LPENC", + "description": "XSPI3 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "MCE4LPENC", + "description": "MCE4 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "GFXMMULPENC", + "description": "GFXMMU sleep enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "GPULPENC", + "description": "GPU sleep enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ETH1MACLPENC", + "description": "ETH1MAC sleep enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ETH1TXLPENC", + "description": "ETH1TX sleep enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ETH1RXLPENC", + "description": "ETH1RX sleep enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ETH1LPENC", + "description": "ETH1 sleep enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "OTG1LPENC", + "description": "OTG1 sleep enable.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "OTGPHY1LPENC", + "description": "OTGPHY1 sleep enable.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "OTGPHY2LPENC", + "description": "OTGPHY2 sleep enable.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "OTG2LPENC", + "description": "OTG2 sleep enable.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "NPUCACHELPENC", + "description": "NPUCACHE sleep enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "NPULPENC", + "description": "NPU sleep enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/AHB5LPENR": { + "description": "RCC AHB5 Sleep enable register.", + "fields": [ + { + "name": "HPDMA1LPEN", + "description": "HPDMA1 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMA2DLPEN", + "description": "DMA2D sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "JPEGLPEN", + "description": "JPEG sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FMCLPEN", + "description": "FMC sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPI1LPEN", + "description": "XSPI1 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "PSSILPEN", + "description": "PSSI sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SDMMC2LPEN", + "description": "SDMMC2 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC1LPEN", + "description": "SDMMC1 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "XSPI2LPEN", + "description": "XSPI2 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "XSPIMLPEN", + "description": "XSPIM sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "MCE1LPEN", + "description": "MCE1 sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "MCE2LPEN", + "description": "MCE2 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "MCE3LPEN", + "description": "MCE3 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "XSPI3LPEN", + "description": "XSPI3 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "MCE4LPEN", + "description": "MCE4 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "GFXMMULPEN", + "description": "GFXMMU sleep enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "GPULPEN", + "description": "GPU sleep enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ETH1MACLPEN", + "description": "ETH1MAC sleep enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ETH1TXLPEN", + "description": "ETH1TX sleep enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ETH1RXLPEN", + "description": "ETH1RX sleep enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ETH1LPEN", + "description": "ETH1 sleep enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "OTG1LPEN", + "description": "OTG1 sleep enable.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "OTGPHY1LPEN", + "description": "OTGPHY1 sleep enable.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "OTGPHY2LPEN", + "description": "OTGPHY2 sleep enable.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "OTG2LPEN", + "description": "OTG2 sleep enable.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "NPUCACHELPEN", + "description": "NPUCACHE sleep enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "NPULPEN", + "description": "NPU sleep enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/AHB5LPENSR": { + "description": "RCC AHB5 Sleep enable register.", + "fields": [ + { + "name": "HPDMA1LPENS", + "description": "HPDMA1 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMA2DLPENS", + "description": "DMA2D sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "JPEGLPENS", + "description": "JPEG sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FMCLPENS", + "description": "FMC sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPI1LPENS", + "description": "XSPI1 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "PSSILPENS", + "description": "PSSI sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SDMMC2LPENS", + "description": "SDMMC2 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC1LPENS", + "description": "SDMMC1 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "XSPI2LPENS", + "description": "XSPI2 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "XSPIMLPENS", + "description": "XSPIM sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "MCE1LPENS", + "description": "MCE1 sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "MCE2LPENS", + "description": "MCE2 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "MCE3LPENS", + "description": "MCE3 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "XSPI3LPENS", + "description": "XSPI3 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "MCE4LPENS", + "description": "MCE4 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "GFXMMULPENS", + "description": "GFXMMU sleep enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "GPULPENS", + "description": "GPU sleep enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ETH1MACLPENS", + "description": "ETH1MAC sleep enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "ETH1TXLPENS", + "description": "ETH1TX sleep enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ETH1RXLPENS", + "description": "ETH1RX sleep enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ETH1LPENS", + "description": "ETH1 sleep enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "OTG1LPENS", + "description": "OTG1 sleep enable.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "OTGPHY1LPENS", + "description": "OTGPHY1 sleep enable.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "OTGPHY2LPENS", + "description": "OTGPHY2 sleep enable.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "OTG2LPENS", + "description": "OTG2 sleep enable.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "NPUCACHELPENS", + "description": "NPUCACHE sleep enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "NPULPENS", + "description": "NPU sleep enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/AHB5RSTCR": { + "description": "RCC AHB5 reset register.", + "fields": [ + { + "name": "HPDMA1RSTC", + "description": "HPDMA1 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMA2DRSTC", + "description": "DMA2D reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "JPEGRSTC", + "description": "JPEG reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FMCRSTC", + "description": "FMC reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPI1RSTC", + "description": "XSPI1 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "PSSIRSTC", + "description": "PSSI reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SDMMC2RSTC", + "description": "SDMMC2 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC1RSTC", + "description": "SDMMC1 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "XSPI2RSTC", + "description": "XSPI2 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "XSPIMRSTC", + "description": "XSPIM reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "XSPI3RSTC", + "description": "XSPI3 reset.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "MCE4RSTC", + "description": "MCE4 reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "GFXMMURSTC", + "description": "GFXMMU reset.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "GPURSTC", + "description": "GPU reset.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SYSCFGOTGHSPHY1RSTC", + "description": "SYSCFGOTGHSPHY1 reset.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SYSCFGOTGHSPHY2RSTC", + "description": "SYSCFGOTGHSPHY2 reset.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ETH1RSTC", + "description": "ETH1 reset.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "OTG1RSTC", + "description": "OTG1 reset.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "OTGPHY1RSTC", + "description": "OTGPHY1 reset.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "OTGPHY2RSTC", + "description": "OTGPHY2 reset.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "OTG2RSTC", + "description": "OTG2 reset.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "NPUCACHERSTC", + "description": "NPUCACHE reset.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "NPURSTC", + "description": "NPU reset.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/AHB5RSTR": { + "description": "RCC AHB5 reset register.", + "fields": [ + { + "name": "HPDMA1RST", + "description": "HPDMA1 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMA2DRST", + "description": "DMA2D reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "JPEGRST", + "description": "JPEG reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FMCRST", + "description": "FMC reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPI1RST", + "description": "XSPI1 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "PSSIRST", + "description": "PSSI reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SDMMC2RST", + "description": "SDMMC2 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC1RST", + "description": "SDMMC1 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "XSPI2RST", + "description": "XSPI2 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "XSPIMRST", + "description": "XSPIM reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "XSPI3RST", + "description": "XSPI3 reset.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "MCE4RST", + "description": "MCE4 reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "GFXMMURST", + "description": "GFXMMU reset.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "GPURST", + "description": "GPU reset.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SYSCFGOTGHSPHY1RST", + "description": "SYSCFGOTGHSPHY1 reset.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SYSCFGOTGHSPHY2RST", + "description": "SYSCFGOTGHSPHY2 reset.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ETH1RST", + "description": "ETH1 reset.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "OTG1RST", + "description": "OTG1 reset.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "OTGPHY1RST", + "description": "OTGPHY1 reset.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "OTGPHY2RST", + "description": "OTGPHY2 reset.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "OTG2RST", + "description": "OTG2 reset.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "NPUCACHERST", + "description": "NPUCACHE reset.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "NPURST", + "description": "NPU reset.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/AHB5RSTSR": { + "description": "RCC AHB5 reset register.", + "fields": [ + { + "name": "HPDMA1RSTS", + "description": "HPDMA1 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMA2DRSTS", + "description": "DMA2D reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "JPEGRSTS", + "description": "JPEG reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "FMCRSTS", + "description": "FMC reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPI1RSTS", + "description": "XSPI1 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "PSSIRSTS", + "description": "PSSI reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "SDMMC2RSTS", + "description": "SDMMC2 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC1RSTS", + "description": "SDMMC1 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "XSPI2RSTS", + "description": "XSPI2 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "XSPIMRSTS", + "description": "XSPIM reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "XSPI3RSTS", + "description": "XSPI3 reset.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "MCE4RSTS", + "description": "MCE4 reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "GFXMMURSTS", + "description": "GFXMMU reset.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "GPURSTS", + "description": "GPU reset.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SYSCFGOTGHSPHY1RSTS", + "description": "SYSCFGOTGHSPHY1 reset.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SYSCFGOTGHSPHY2RSTS", + "description": "SYSCFGOTGHSPHY2 reset.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "ETH1RSTS", + "description": "ETH1 reset.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "OTG1RSTS", + "description": "OTG1 reset.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "OTGPHY1RSTS", + "description": "OTGPHY1 reset.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "OTGPHY2RSTS", + "description": "OTGPHY2 reset.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "OTG2RSTS", + "description": "OTG2 reset.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "NPUCACHERSTS", + "description": "NPUCACHE reset.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "NPURSTS", + "description": "NPU reset.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB1HENCR": { + "description": "RCC APB1H enable register.", + "fields": [ + { + "name": "MDIOSENC", + "description": "MDIOS enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FDCANENC", + "description": "FDCAN enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "UCPD1ENC", + "description": "UCPD1 enable.", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/APB1HENR": { + "description": "RCC APB1H enable register.", + "fields": [ + { + "name": "MDIOSEN", + "description": "MDIOS enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FDCANEN", + "description": "FDCAN enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "UCPD1EN", + "description": "UCPD1 enable.", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/APB1HENSR": { + "description": "RCC APB1H enable register.", + "fields": [ + { + "name": "MDIOSENS", + "description": "MDIOS enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FDCANENS", + "description": "FDCAN enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "UCPD1ENS", + "description": "UCPD1 enable.", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/APB1HLPENCR": { + "description": "RCC APB1H Sleep enable register.", + "fields": [ + { + "name": "MDIOSLPENC", + "description": "MDIOS sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FDCANLPENC", + "description": "FDCAN sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "UCPD1LPENC", + "description": "UCPD1 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/APB1HLPENR": { + "description": "RCC APB1H Sleep enable register.", + "fields": [ + { + "name": "MDIOSLPEN", + "description": "MDIOS sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FDCANLPEN", + "description": "FDCAN sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "UCPD1LPEN", + "description": "UCPD1 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/APB1HLPENSR": { + "description": "RCC APB1H Sleep enable register.", + "fields": [ + { + "name": "MDIOSLPENS", + "description": "MDIOS sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FDCANLPENS", + "description": "FDCAN sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "UCPD1LPENS", + "description": "UCPD1 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/APB1HRSTCR": { + "description": "RCC APB1H reset register.", + "fields": [ + { + "name": "MDIOSRSTC", + "description": "MDIOS reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FDCANRSTC", + "description": "FDCAN reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "UCPD1RSTC", + "description": "UCPD1 reset.", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/APB1HRSTR": { + "description": "RCC APB1H reset register.", + "fields": [ + { + "name": "MDIOSRST", + "description": "MDIOS reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FDCANRST", + "description": "FDCAN reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "UCPD1RST", + "description": "UCPD1 reset.", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/APB1HRSTSR": { + "description": "RCC APB1H reset register.", + "fields": [ + { + "name": "MDIOSRSTS", + "description": "MDIOS reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "FDCANRSTS", + "description": "FDCAN reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "UCPD1RSTS", + "description": "UCPD1 reset.", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/APB1LENCR": { + "description": "RCC APB1L enable register.", + "fields": [ + { + "name": "TIM2ENC", + "description": "TIM2 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM3ENC", + "description": "TIM3 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "TIM4ENC", + "description": "TIM4 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "TIM5ENC", + "description": "TIM5 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TIM6ENC", + "description": "TIM6 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TIM7ENC", + "description": "TIM7 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "TIM12ENC", + "description": "TIM12 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "TIM13ENC", + "description": "TIM13 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "TIM14ENC", + "description": "TIM14 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPTIM1ENC", + "description": "LPTIM1 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "TIM10ENC", + "description": "TIM10 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "TIM11ENC", + "description": "TIM11 enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SPI2ENC", + "description": "SPI2 enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "SPI3ENC", + "description": "SPI3 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "SPDIFRX1ENC", + "description": "SPDIFRX1 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "USART2ENC", + "description": "USART2 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "USART3ENC", + "description": "USART3 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "UART4ENC", + "description": "UART4 enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "UART5ENC", + "description": "UART5 enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "I2C1ENC", + "description": "I2C1 enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "I2C2ENC", + "description": "I2C2 enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "I2C3ENC", + "description": "I2C3 enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "I3C1ENC", + "description": "I3C1 enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "I3C2ENC", + "description": "I3C2 enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "UART7ENC", + "description": "UART7 enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "UART8ENC", + "description": "UART8 enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB1LENR": { + "description": "RCC APB1L enable register.", + "fields": [ + { + "name": "TIM2EN", + "description": "TIM2 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM3EN", + "description": "TIM3 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "TIM4EN", + "description": "TIM4 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "TIM5EN", + "description": "TIM5 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TIM6EN", + "description": "TIM6 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TIM7EN", + "description": "TIM7 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "TIM12EN", + "description": "TIM12 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "TIM13EN", + "description": "TIM13 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "TIM14EN", + "description": "TIM14 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPTIM1EN", + "description": "LPTIM1 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "WWDGEN", + "description": "WWDG enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "TIM10EN", + "description": "TIM10 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "TIM11EN", + "description": "TIM11 enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SPI2EN", + "description": "SPI2 enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "SPI3EN", + "description": "SPI3 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "SPDIFRX1EN", + "description": "SPDIFRX1 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "USART2EN", + "description": "USART2 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "USART3EN", + "description": "USART3 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "UART4EN", + "description": "UART4 enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "UART5EN", + "description": "UART5 enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "I2C1EN", + "description": "I2C1 enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "I2C2EN", + "description": "I2C2 enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "I2C3EN", + "description": "I2C3 enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "I3C1EN", + "description": "I3C1 enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "I3C2EN", + "description": "I3C2 enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "UART7EN", + "description": "UART7 enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "UART8EN", + "description": "UART8 enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB1LENSR": { + "description": "RCC APB1L enable register.", + "fields": [ + { + "name": "TIM2ENS", + "description": "TIM2 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM3ENS", + "description": "TIM3 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "TIM4ENS", + "description": "TIM4 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "TIM5ENS", + "description": "TIM5 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TIM6ENS", + "description": "TIM6 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TIM7ENS", + "description": "TIM7 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "TIM12ENS", + "description": "TIM12 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "TIM13ENS", + "description": "TIM13 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "TIM14ENS", + "description": "TIM14 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPTIM1ENS", + "description": "LPTIM1 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "WWDGENS", + "description": "WWDG enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "TIM10ENS", + "description": "TIM10 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "TIM11ENS", + "description": "TIM11 enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SPI2ENS", + "description": "SPI2 enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "SPI3ENS", + "description": "SPI3 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "SPDIFRX1ENS", + "description": "SPDIFRX1 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "USART2ENS", + "description": "USART2 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "USART3ENS", + "description": "USART3 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "UART4ENS", + "description": "UART4 enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "UART5ENS", + "description": "UART5 enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "I2C1ENS", + "description": "I2C1 enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "I2C2ENS", + "description": "I2C2 enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "I2C3ENS", + "description": "I2C3 enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "I3C1ENS", + "description": "I3C1 enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "I3C2ENS", + "description": "I3C2 enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "UART7ENS", + "description": "UART7 enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "UART8ENS", + "description": "UART8 enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB1LLPENCR": { + "description": "RCC APB1L Sleep enable register.", + "fields": [ + { + "name": "TIM2LPENC", + "description": "TIM2 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM3LPENC", + "description": "TIM3 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "TIM4LPENC", + "description": "TIM4 sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "TIM5LPENC", + "description": "TIM5 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TIM6LPENC", + "description": "TIM6 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TIM7LPENC", + "description": "TIM7 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "TIM12LPENC", + "description": "TIM12 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "TIM13LPENC", + "description": "TIM13 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "TIM14LPENC", + "description": "TIM14 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPTIM1LPENC", + "description": "LPTIM1 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "WWDGLPENC", + "description": "WWDG sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "TIM10LPENC", + "description": "TIM10 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "TIM11LPENC", + "description": "TIM11 sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SPI2LPENC", + "description": "SPI2 sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "SPI3LPENC", + "description": "SPI3 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "SPDIFRX1LPENC", + "description": "SPDIFRX1 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "USART2LPENC", + "description": "USART2 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "USART3LPENC", + "description": "USART3 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "UART4LPENC", + "description": "UART4 sleep enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "UART5LPENC", + "description": "UART5 sleep enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "I2C1LPENC", + "description": "I2C1 sleep enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "I2C2LPENC", + "description": "I2C2 sleep enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "I2C3LPENC", + "description": "I2C3 sleep enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "I3C1LPENC", + "description": "I3C1 sleep enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "I3C2LPENC", + "description": "I3C2 sleep enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "UART7LPENC", + "description": "UART7 sleep enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "UART8LPENC", + "description": "UART8 sleep enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB1LLPENR": { + "description": "RCC APB1L Sleep enable register.", + "fields": [ + { + "name": "TIM2LPEN", + "description": "TIM2 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM3LPEN", + "description": "TIM3 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "TIM4LPEN", + "description": "TIM4 sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "TIM5LPEN", + "description": "TIM5 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TIM6LPEN", + "description": "TIM6 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TIM7LPEN", + "description": "TIM7 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "TIM12LPEN", + "description": "TIM12 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "TIM13LPEN", + "description": "TIM13 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "TIM14LPEN", + "description": "TIM14 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPTIM1LPEN", + "description": "LPTIM1 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "WWDGLPEN", + "description": "WWDG sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "TIM10LPEN", + "description": "TIM10 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "TIM11LPEN", + "description": "TIM11 sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SPI2LPEN", + "description": "SPI2 sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "SPI3LPEN", + "description": "SPI3 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "SPDIFRX1LPEN", + "description": "SPDIFRX1 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "USART2LPEN", + "description": "USART2 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "USART3LPEN", + "description": "USART3 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "UART4LPEN", + "description": "UART4 sleep enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "UART5LPEN", + "description": "UART5 sleep enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "I2C1LPEN", + "description": "I2C1 sleep enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "I2C2LPEN", + "description": "I2C2 sleep enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "I2C3LPEN", + "description": "I2C3 sleep enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "I3C1LPEN", + "description": "I3C1 sleep enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "I3C2LPEN", + "description": "I3C2 sleep enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "UART7LPEN", + "description": "UART7 sleep enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "UART8LPEN", + "description": "UART8 sleep enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB1LLPENSR": { + "description": "RCC APB1L Sleep enable register.", + "fields": [ + { + "name": "TIM2LPENS", + "description": "TIM2 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM3LPENS", + "description": "TIM3 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "TIM4LPENS", + "description": "TIM4 sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "TIM5LPENS", + "description": "TIM5 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TIM6LPENS", + "description": "TIM6 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TIM7LPENS", + "description": "TIM7 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "TIM12LPENS", + "description": "TIM12 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "TIM13LPENS", + "description": "TIM13 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "TIM14LPENS", + "description": "TIM14 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPTIM1LPENS", + "description": "LPTIM1 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "WWDGLPENS", + "description": "WWDG sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "TIM10LPENS", + "description": "TIM10 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "TIM11LPENS", + "description": "TIM11 sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SPI2LPENS", + "description": "SPI2 sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "SPI3LPENS", + "description": "SPI3 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "SPDIFRX1LPENS", + "description": "SPDIFRX1 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "USART2LPENS", + "description": "USART2 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "USART3LPENS", + "description": "USART3 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "UART4LPENS", + "description": "UART4 sleep enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "UART5LPENS", + "description": "UART5 sleep enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "I2C1LPENS", + "description": "I2C1 sleep enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "I2C2LPENS", + "description": "I2C2 sleep enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "I2C3LPENS", + "description": "I2C3 sleep enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "I3C1LPENS", + "description": "I3C1 sleep enable.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "I3C2LPENS", + "description": "I3C2 sleep enable.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "UART7LPENS", + "description": "UART7 sleep enable.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "UART8LPENS", + "description": "UART8 sleep enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB1LRSTCR": { + "description": "RCC APB1L reset register.", + "fields": [ + { + "name": "TIM2RSTC", + "description": "TIM2 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM3RSTC", + "description": "TIM3 reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "TIM4RSTC", + "description": "TIM4 reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "TIM5RSTC", + "description": "TIM5 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TIM6RSTC", + "description": "TIM6 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TIM7RSTC", + "description": "TIM7 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "TIM12RSTC", + "description": "TIM12 reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "TIM13RSTC", + "description": "TIM13 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "TIM14RSTC", + "description": "TIM14 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPTIM1RSTC", + "description": "LPTIM1 reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "WWDGRSTC", + "description": "WWDG reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "TIM10RSTC", + "description": "TIM10 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "TIM11RSTC", + "description": "TIM11 reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SPI2RSTC", + "description": "SPI2 reset.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "SPI3RSTC", + "description": "SPI3 reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "SPDIFRX1RSTC", + "description": "SPDIFRX1 reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "USART2RSTC", + "description": "USART2 reset.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "USART3RSTC", + "description": "USART3 reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "UART4RSTC", + "description": "UART4 reset.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "UART5RSTC", + "description": "UART5 reset.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "I2C1RSTC", + "description": "I2C1 reset.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "I2C2RSTC", + "description": "I2C2 reset.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "I2C3RSTC", + "description": "I2C3 reset.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "I3C1RSTC", + "description": "I3C1 reset.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "I3C2RSTC", + "description": "I3C2 reset.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "UART7RSTC", + "description": "UART7 reset.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "UART8RSTC", + "description": "UART8 reset.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB1LRSTR": { + "description": "RCC APB1L reset register.", + "fields": [ + { + "name": "TIM2RST", + "description": "TIM2 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM3RST", + "description": "TIM3 reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "TIM4RST", + "description": "TIM4 reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "TIM5RST", + "description": "TIM5 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TIM6RST", + "description": "TIM6 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TIM7RST", + "description": "TIM7 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "TIM12RST", + "description": "TIM12 reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "TIM13RST", + "description": "TIM13 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "TIM14RST", + "description": "TIM14 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPTIM1RST", + "description": "LPTIM1 reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "WWDGRST", + "description": "WWDG reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "TIM10RST", + "description": "TIM10 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "TIM11RST", + "description": "TIM11 reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SPI2RST", + "description": "SPI2 reset.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "SPI3RST", + "description": "SPI3 reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "SPDIFRX1RST", + "description": "SPDIFRX1 reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "USART2RST", + "description": "USART2 reset.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "USART3RST", + "description": "USART3 reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "UART4RST", + "description": "UART4 reset.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "UART5RST", + "description": "UART5 reset.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "I2C1RST", + "description": "I2C1 reset.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "I2C2RST", + "description": "I2C2 reset.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "I2C3RST", + "description": "I2C3 reset.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "I3C1RST", + "description": "I3C1 reset.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "I3C2RST", + "description": "I3C2 reset.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "UART7RST", + "description": "UART7 reset.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "UART8RST", + "description": "UART8 reset.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB1LRSTSR": { + "description": "RCC APB1L reset register.", + "fields": [ + { + "name": "TIM2RSTS", + "description": "TIM2 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM3RSTS", + "description": "TIM3 reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "TIM4RSTS", + "description": "TIM4 reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "TIM5RSTS", + "description": "TIM5 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TIM6RSTS", + "description": "TIM6 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "TIM7RSTS", + "description": "TIM7 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "TIM12RSTS", + "description": "TIM12 reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "TIM13RSTS", + "description": "TIM13 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "TIM14RSTS", + "description": "TIM14 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "LPTIM1RSTS", + "description": "LPTIM1 reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "WWDGRSTS", + "description": "WWDG reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "TIM10RSTS", + "description": "TIM10 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "TIM11RSTS", + "description": "TIM11 reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SPI2RSTS", + "description": "SPI2 reset.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "SPI3RSTS", + "description": "SPI3 reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "SPDIFRX1RSTS", + "description": "SPDIFRX1 reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "USART2RSTS", + "description": "USART2 reset.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "USART3RSTS", + "description": "USART3 reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "UART4RSTS", + "description": "UART4 reset.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "UART5RSTS", + "description": "UART5 reset.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "I2C1RSTS", + "description": "I2C1 reset.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "I2C2RSTS", + "description": "I2C2 reset.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "I2C3RSTS", + "description": "I2C3 reset.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "I3C1RSTS", + "description": "I3C1 reset.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "I3C2RSTS", + "description": "I3C2 reset.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "UART7RSTS", + "description": "UART7 reset.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "UART8RSTS", + "description": "UART8 reset.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB2ENCR": { + "description": "RCC APB2 enable register.", + "fields": [ + { + "name": "TIM1ENC", + "description": "TIM1 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM8ENC", + "description": "TIM8 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "USART1ENC", + "description": "USART1 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "USART6ENC", + "description": "USART6 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "UART9ENC", + "description": "UART9 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "USART10ENC", + "description": "USART10 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SPI1ENC", + "description": "SPI1 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "SPI4ENC", + "description": "SPI4 enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "TIM18ENC", + "description": "TIM18 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "TIM15ENC", + "description": "TIM15 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "TIM16ENC", + "description": "TIM16 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "TIM17ENC", + "description": "TIM17 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "TIM9ENC", + "description": "TIM9 enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "SPI5ENC", + "description": "SPI5 enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SAI1ENC", + "description": "SAI1 enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SAI2ENC", + "description": "SAI2 enable.", + "bit_offset": 22, + "bit_size": 1 + } + ] + }, + "fieldset/APB2ENR": { + "description": "RCC APB2 enable register.", + "fields": [ + { + "name": "TIM1EN", + "description": "TIM1 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM8EN", + "description": "TIM8 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "USART1EN", + "description": "USART1 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "USART6EN", + "description": "USART6 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "UART9EN", + "description": "UART9 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "USART10EN", + "description": "USART10 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SPI1EN", + "description": "SPI1 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "SPI4EN", + "description": "SPI4 enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "TIM18EN", + "description": "TIM18 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "TIM15EN", + "description": "TIM15 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "TIM16EN", + "description": "TIM16 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "TIM17EN", + "description": "TIM17 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "TIM9EN", + "description": "TIM9 enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "SPI5EN", + "description": "SPI5 enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SAI1EN", + "description": "SAI1 enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SAI2EN", + "description": "SAI2 enable.", + "bit_offset": 22, + "bit_size": 1 + } + ] + }, + "fieldset/APB2ENSR": { + "description": "RCC APB2 enable register.", + "fields": [ + { + "name": "TIM1ENS", + "description": "TIM1 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM8ENS", + "description": "TIM8 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "USART1ENS", + "description": "USART1 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "USART6ENS", + "description": "USART6 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "UART9ENS", + "description": "UART9 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "USART10ENS", + "description": "USART10 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SPI1ENS", + "description": "SPI1 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "SPI4ENS", + "description": "SPI4 enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "TIM18ENS", + "description": "TIM18 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "TIM15ENS", + "description": "TIM15 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "TIM16ENS", + "description": "TIM16 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "TIM17ENS", + "description": "TIM17 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "TIM9ENS", + "description": "TIM9 enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "SPI5ENS", + "description": "SPI5 enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SAI1ENS", + "description": "SAI1 enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SAI2ENS", + "description": "SAI2 enable.", + "bit_offset": 22, + "bit_size": 1 + } + ] + }, + "fieldset/APB2LPENCR": { + "description": "RCC APB2 Sleep enable register.", + "fields": [ + { + "name": "TIM1LPENC", + "description": "TIM1 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM8LPENC", + "description": "TIM8 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "USART1LPENC", + "description": "USART1 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "USART6LPENC", + "description": "USART6 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "UART9LPENC", + "description": "UART9 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "USART10LPENC", + "description": "USART10 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SPI1LPENC", + "description": "SPI1 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "SPI4LPENC", + "description": "SPI4 sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "TIM18LPENC", + "description": "TIM18 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "TIM15LPENC", + "description": "TIM15 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "TIM16LPENC", + "description": "TIM16 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "TIM17LPENC", + "description": "TIM17 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "TIM9LPENC", + "description": "TIM9 sleep enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "SPI5LPENC", + "description": "SPI5 sleep enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SAI1LPENC", + "description": "SAI1 sleep enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SAI2LPENC", + "description": "SAI2 sleep enable.", + "bit_offset": 22, + "bit_size": 1 + } + ] + }, + "fieldset/APB2LPENR": { + "description": "RCC APB2 Sleep enable register.", + "fields": [ + { + "name": "TIM1LPEN", + "description": "TIM1 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM8LPEN", + "description": "TIM8 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "USART1LPEN", + "description": "USART1 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "USART6LPEN", + "description": "USART6 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "UART9LPEN", + "description": "UART9 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "USART10LPEN", + "description": "USART10 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SPI1LPEN", + "description": "SPI1 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "SPI4LPEN", + "description": "SPI4 sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "TIM18LPEN", + "description": "TIM18 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "TIM15LPEN", + "description": "TIM15 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "TIM16LPEN", + "description": "TIM16 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "TIM17LPEN", + "description": "TIM17 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "TIM9LPEN", + "description": "TIM9 sleep enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "SPI5LPEN", + "description": "SPI5 sleep enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SAI1LPEN", + "description": "SAI1 sleep enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SAI2LPEN", + "description": "SAI2 sleep enable.", + "bit_offset": 22, + "bit_size": 1 + } + ] + }, + "fieldset/APB2LPENSR": { + "description": "RCC APB2 Sleep enable register.", + "fields": [ + { + "name": "TIM1LPENS", + "description": "TIM1 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM8LPENS", + "description": "TIM8 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "USART1LPENS", + "description": "USART1 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "USART6LPENS", + "description": "USART6 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "UART9LPENS", + "description": "UART9 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "USART10LPENS", + "description": "USART10 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SPI1LPENS", + "description": "SPI1 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "SPI4LPENS", + "description": "SPI4 sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "TIM18LPENS", + "description": "TIM18 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "TIM15LPENS", + "description": "TIM15 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "TIM16LPENS", + "description": "TIM16 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "TIM17LPENS", + "description": "TIM17 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "TIM9LPENS", + "description": "TIM9 sleep enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "SPI5LPENS", + "description": "SPI5 sleep enable.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SAI1LPENS", + "description": "SAI1 sleep enable.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SAI2LPENS", + "description": "SAI2 sleep enable.", + "bit_offset": 22, + "bit_size": 1 + } + ] + }, + "fieldset/APB2RSTCR": { + "description": "RCC APB2 reset register.", + "fields": [ + { + "name": "TIM1RSTC", + "description": "TIM1 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM8RSTC", + "description": "TIM8 reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "USART1RSTC", + "description": "USART1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "USART6RSTC", + "description": "USART6 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "UART9RSTC", + "description": "UART9 reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "USART10RSTC", + "description": "USART10 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SPI1RSTC", + "description": "SPI1 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "SPI4RSTC", + "description": "SPI4 reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "TIM18RSTC", + "description": "TIM18 reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "TIM15RSTC", + "description": "TIM15 reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "TIM16RSTC", + "description": "TIM16 reset.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "TIM17RSTC", + "description": "TIM17 reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "TIM9RSTC", + "description": "TIM9 reset.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "SPI5RSTC", + "description": "SPI5 reset.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SAI1RSTC", + "description": "SAI1 reset.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SAI2RSTC", + "description": "SAI2 reset.", + "bit_offset": 22, + "bit_size": 1 + } + ] + }, + "fieldset/APB2RSTR": { + "description": "RCC APB2 reset register.", + "fields": [ + { + "name": "TIM1RST", + "description": "TIM1 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM8RST", + "description": "TIM8 reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "USART1RST", + "description": "USART1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "USART6RST", + "description": "USART6 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "UART9RST", + "description": "UART9 reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "USART10RST", + "description": "USART10 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SPI1RST", + "description": "SPI1 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "SPI4RST", + "description": "SPI4 reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "TIM18RST", + "description": "TIM18 reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "TIM15RST", + "description": "TIM15 reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "TIM16RST", + "description": "TIM16 reset.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "TIM17RST", + "description": "TIM17 reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "TIM9RST", + "description": "TIM9 reset.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "SPI5RST", + "description": "SPI5 reset.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SAI1RST", + "description": "SAI1 reset.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SAI2RST", + "description": "SAI2 reset.", + "bit_offset": 22, + "bit_size": 1 + } + ] + }, + "fieldset/APB2RSTSR": { + "description": "RCC APB2 reset register.", + "fields": [ + { + "name": "TIM1RSTS", + "description": "TIM1 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "TIM8RSTS", + "description": "TIM8 reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "USART1RSTS", + "description": "USART1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "USART6RSTS", + "description": "USART6 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "UART9RSTS", + "description": "UART9 reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "USART10RSTS", + "description": "USART10 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SPI1RSTS", + "description": "SPI1 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "SPI4RSTS", + "description": "SPI4 reset.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "TIM18RSTS", + "description": "TIM18 reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "TIM15RSTS", + "description": "TIM15 reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "TIM16RSTS", + "description": "TIM16 reset.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "TIM17RSTS", + "description": "TIM17 reset.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "TIM9RSTS", + "description": "TIM9 reset.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "SPI5RSTS", + "description": "SPI5 reset.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SAI1RSTS", + "description": "SAI1 reset.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SAI2RSTS", + "description": "SAI2 reset.", + "bit_offset": 22, + "bit_size": 1 + } + ] + }, + "fieldset/APB3ENCR": { + "description": "RCC APB3 enable register.", + "fields": [ + { + "name": "DFTENC", + "description": "DFT enable.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/APB3ENR": { + "description": "RCC APB3 enable register.", + "fields": [ + { + "name": "DFTEN", + "description": "DFT enable.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/APB3ENSR": { + "description": "RCC APB3 enable register.", + "fields": [ + { + "name": "DFTENS", + "description": "DFT enable.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/APB3LPENCR": { + "description": "RCC APB3 Sleep enable register.", + "fields": [ + { + "name": "DFTLPENC", + "description": "DFT sleep enable.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/APB3LPENR": { + "description": "RCC APB3 Sleep enable register.", + "fields": [ + { + "name": "DFTLPEN", + "description": "DFT sleep enable.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/APB3LPENSR": { + "description": "RCC APB3 Sleep enable register.", + "fields": [ + { + "name": "DFTLPENS", + "description": "DFT sleep enable.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/APB4HENCR": { + "description": "RCC APB4H enable register.", + "fields": [ + { + "name": "SYSCFGENC", + "description": "SYSCFG enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BSECENC", + "description": "BSEC enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DTSENC", + "description": "DTS enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSPERFMENC", + "description": "BUSPERFM enable.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/APB4HENR": { + "description": "RCC APB4H enable register.", + "fields": [ + { + "name": "SYSCFGEN", + "description": "SYSCFG enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BSECEN", + "description": "BSEC enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DTSEN", + "description": "DTS enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSPERFMEN", + "description": "BUSPERFM enable.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/APB4HENSR": { + "description": "RCC APB4H enable register.", + "fields": [ + { + "name": "SYSCFGENS", + "description": "SYSCFG enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BSECENS", + "description": "BSEC enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DTSENS", + "description": "DTS enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSPERFMENS", + "description": "BUSPERFM enable.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/APB4HLPENCR": { + "description": "RCC APB4H Sleep enable register.", + "fields": [ + { + "name": "SYSCFGLPENC", + "description": "SYSCFG sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BSECLPENC", + "description": "BSEC sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DTSLPENC", + "description": "DTS sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSPERFMLPENC", + "description": "BUSPERFM sleep enable.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/APB4HLPENR": { + "description": "RCC APB4H Sleep enable register.", + "fields": [ + { + "name": "SYSCFGLPEN", + "description": "SYSCFG sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BSECLPEN", + "description": "BSEC sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DTSLPEN", + "description": "DTS sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSPERFMLPEN", + "description": "BUSPERFM sleep enable.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/APB4HLPENSR": { + "description": "RCC APB4H Sleep enable register.", + "fields": [ + { + "name": "SYSCFGLPENS", + "description": "SYSCFG sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "BSECLPENS", + "description": "BSEC sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DTSLPENS", + "description": "DTS sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSPERFMLPENS", + "description": "BUSPERFM sleep enable.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/APB4HRSTCR": { + "description": "RCC APB4H reset register.", + "fields": [ + { + "name": "SYSCFGRSTC", + "description": "SYSCFG reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DTSRSTC", + "description": "DTS reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSPERFMRSTC", + "description": "BUSPERFM reset.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/APB4HRSTR": { + "description": "RCC APB4H reset register.", + "fields": [ + { + "name": "SYSCFGRST", + "description": "SYSCFG reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DTSRST", + "description": "DTS reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSPERFMRST", + "description": "BUSPERFM reset.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/APB4HRSTSR": { + "description": "RCC APB4H reset register.", + "fields": [ + { + "name": "SYSCFGRSTS", + "description": "SYSCFG reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DTSRSTS", + "description": "DTS reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "BUSPERFMRSTS", + "description": "BUSPERFM reset.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/APB4LENCR": { + "description": "RCC APB4L enable register.", + "fields": [ + { + "name": "HDPENC", + "description": "HDP enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPUART1ENC", + "description": "LPUART1 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "SPI6ENC", + "description": "SPI6 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "I2C4ENC", + "description": "I2C4 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "LPTIM2ENC", + "description": "LPTIM2 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPTIM3ENC", + "description": "LPTIM3 enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPTIM4ENC", + "description": "LPTIM4 enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPTIM5ENC", + "description": "LPTIM5 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "VREFBUFENC", + "description": "VREFBUF enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "RTCENC", + "description": "RTC enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "R2GRETENC", + "description": "R2GRET enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "R2GNPUENC", + "description": "R2GNPU enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SERFENC", + "description": "SERF enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB4LENR": { + "description": "RCC APB4L enable register.", + "fields": [ + { + "name": "HDPEN", + "description": "HDP enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPUART1EN", + "description": "LPUART1 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "SPI6EN", + "description": "SPI6 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "I2C4EN", + "description": "I2C4 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "LPTIM2EN", + "description": "LPTIM2 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPTIM3EN", + "description": "LPTIM3 enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPTIM4EN", + "description": "LPTIM4 enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPTIM5EN", + "description": "LPTIM5 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "VREFBUFEN", + "description": "VREFBUF enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "RTCEN", + "description": "RTC enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "R2GRETEN", + "description": "R2GRET enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "R2GNPUEN", + "description": "R2GNPU enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SERFEN", + "description": "SERF enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB4LENSR": { + "description": "RCC APB4L enable register.", + "fields": [ + { + "name": "HDPENS", + "description": "HDP enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPUART1ENS", + "description": "LPUART1 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "SPI6ENS", + "description": "SPI6 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "I2C4ENS", + "description": "I2C4 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "LPTIM2ENS", + "description": "LPTIM2 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPTIM3ENS", + "description": "LPTIM3 enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPTIM4ENS", + "description": "LPTIM4 enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPTIM5ENS", + "description": "LPTIM5 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "VREFBUFENS", + "description": "VREFBUF enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "RTCENS", + "description": "RTC enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "R2GRETENS", + "description": "R2GRET enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "R2GNPUENS", + "description": "R2GNPU enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SERFENS", + "description": "SERF enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB4LLPENCR": { + "description": "RCC APB4L Sleep enable register.", + "fields": [ + { + "name": "HDPLPENC", + "description": "HDP sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPUART1LPENC", + "description": "LPUART1 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "SPI6LPENC", + "description": "SPI6 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "I2C4LPENC", + "description": "I2C4 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "LPTIM2LPENC", + "description": "LPTIM2 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPTIM3LPENC", + "description": "LPTIM3 sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPTIM4LPENC", + "description": "LPTIM4 sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPTIM5LPENC", + "description": "LPTIM5 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "VREFBUFLPENC", + "description": "VREFBUF sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "RTCLPENC", + "description": "RTC sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "RTCAPBLPENC", + "description": "RTCAPB sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "R2GRETLPENC", + "description": "R2GRET sleep enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "R2GNPULPENC", + "description": "R2GNPU sleep enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SERFLPENC", + "description": "SERF sleep enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB4LLPENR": { + "description": "RCC APB4L Sleep enable register.", + "fields": [ + { + "name": "HDPLPEN", + "description": "HDP sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPUART1LPEN", + "description": "LPUART1 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "SPI6LPEN", + "description": "SPI6 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "I2C4LPEN", + "description": "I2C4 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "LPTIM2LPEN", + "description": "LPTIM2 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPTIM3LPEN", + "description": "LPTIM3 sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPTIM4LPEN", + "description": "LPTIM4 sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPTIM5LPEN", + "description": "LPTIM5 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "VREFBUFLPEN", + "description": "VREFBUF sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "RTCLPEN", + "description": "RTC sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "RTCAPBLPEN", + "description": "RTCAPB sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "R2GRETLPEN", + "description": "R2GRET sleep enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "R2GNPULPEN", + "description": "R2GNPU sleep enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SERFLPEN", + "description": "SERF sleep enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB4LLPENSR": { + "description": "RCC APB4L Sleep enable register.", + "fields": [ + { + "name": "HDPLPENS", + "description": "HDP sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPUART1LPENS", + "description": "LPUART1 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "SPI6LPENS", + "description": "SPI6 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "I2C4LPENS", + "description": "I2C4 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "LPTIM2LPENS", + "description": "LPTIM2 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPTIM3LPENS", + "description": "LPTIM3 sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPTIM4LPENS", + "description": "LPTIM4 sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPTIM5LPENS", + "description": "LPTIM5 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "VREFBUFLPENS", + "description": "VREFBUF sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "RTCLPENS", + "description": "RTC sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "RTCAPBLPENS", + "description": "RTCAPB sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "R2GRETLPENS", + "description": "R2GRET sleep enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "R2GNPULPENS", + "description": "R2GNPU sleep enable.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SERFLPENS", + "description": "SERF sleep enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB4LRSTCR": { + "description": "RCC APB4L reset register.", + "fields": [ + { + "name": "HDPRSTC", + "description": "HDP reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPUART1RSTC", + "description": "LPUART1 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "SPI6RSTC", + "description": "SPI6 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "I2C4RSTC", + "description": "I2C4 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "LPTIM2RSTC", + "description": "LPTIM2 reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPTIM3RSTC", + "description": "LPTIM3 reset.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPTIM4RSTC", + "description": "LPTIM4 reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPTIM5RSTC", + "description": "LPTIM5 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "VREFBUFRSTC", + "description": "VREFBUF reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "RTCRSTC", + "description": "RTC reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "R2GRETRSTC", + "description": "R2GRET reset.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "R2GNPURSTC", + "description": "R2GNPU reset.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SERFRSTC", + "description": "SERF reset.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB4LRSTR": { + "description": "RCC APB4L reset register.", + "fields": [ + { + "name": "HDPRST", + "description": "HDP reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPUART1RST", + "description": "LPUART1 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "SPI6RST", + "description": "SPI6 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "I2C4RST", + "description": "I2C4 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "LPTIM2RST", + "description": "LPTIM2 reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPTIM3RST", + "description": "LPTIM3 reset.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPTIM4RST", + "description": "LPTIM4 reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPTIM5RST", + "description": "LPTIM5 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "VREFBUFRST", + "description": "VREFBUF reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "RTCRST", + "description": "RTC reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "R2GRETRST", + "description": "R2GRET reset.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "R2GNPURST", + "description": "R2GNPU reset.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SERFRST", + "description": "SERF reset.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB4LRSTSR": { + "description": "RCC APB4L reset register.", + "fields": [ + { + "name": "HDPRSTS", + "description": "HDP reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "LPUART1RSTS", + "description": "LPUART1 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "SPI6RSTS", + "description": "SPI6 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "I2C4RSTS", + "description": "I2C4 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "LPTIM2RSTS", + "description": "LPTIM2 reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LPTIM3RSTS", + "description": "LPTIM3 reset.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LPTIM4RSTS", + "description": "LPTIM4 reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LPTIM5RSTS", + "description": "LPTIM5 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "VREFBUFRSTS", + "description": "VREFBUF reset.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "RTCRSTS", + "description": "RTC reset.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "R2GRETRSTS", + "description": "R2GRET reset.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "R2GNPURSTS", + "description": "R2GNPU reset.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SERFRSTS", + "description": "SERF reset.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB5ENCR": { + "description": "RCC APB5 enable register.", + "fields": [ + { + "name": "LTDCENC", + "description": "LTDC enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DCMIPPENC", + "description": "DCMIPP enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GFXTIMENC", + "description": "GFXTIM enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "VENCENC", + "description": "VENC enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CSIENC", + "description": "CSI enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/APB5ENR": { + "description": "RCC APB5 enable register.", + "fields": [ + { + "name": "LTDCEN", + "description": "LTDC enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DCMIPPEN", + "description": "DCMIPP enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GFXTIMEN", + "description": "GFXTIM enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "VENCEN", + "description": "VENC enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CSIEN", + "description": "CSI enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/APB5ENSR": { + "description": "RCC APB5 enable register.", + "fields": [ + { + "name": "LTDCENS", + "description": "LTDC enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DCMIPPENS", + "description": "DCMIPP enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GFXTIMENS", + "description": "GFXTIM enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "VENCENS", + "description": "VENC enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CSIENS", + "description": "CSI enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/APB5LPENCR": { + "description": "RCC APB5 Sleep enable register.", + "fields": [ + { + "name": "LTDCLPENC", + "description": "LTDC sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DCMIPPLPENC", + "description": "DCMIPP sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GFXTIMLPENC", + "description": "GFXTIM sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "VENCLPENC", + "description": "VENC sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CSILPENC", + "description": "CSI sleep enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/APB5LPENR": { + "description": "RCC APB5 Sleep enable register.", + "fields": [ + { + "name": "LTDCLPEN", + "description": "LTDC sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DCMIPPLPEN", + "description": "DCMIPP sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GFXTIMLPEN", + "description": "GFXTIM sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "VENCLPEN", + "description": "VENC sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CSILPEN", + "description": "CSI sleep enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/APB5LPENSR": { + "description": "RCC APB5 Sleep enable register.", + "fields": [ + { + "name": "LTDCLPENS", + "description": "LTDC sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DCMIPPLPENS", + "description": "DCMIPP sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GFXTIMLPENS", + "description": "GFXTIM sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "VENCLPENS", + "description": "VENC sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CSILPENS", + "description": "CSI sleep enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/APB5RSTCR": { + "description": "RCC APB5 reset register.", + "fields": [ + { + "name": "LTDCRSTC", + "description": "LTDC reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DCMIPPRSTC", + "description": "DCMIPP reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GFXTIMRSTC", + "description": "GFXTIM reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "VENCRSTC", + "description": "VENC reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CSIRSTC", + "description": "CSI reset.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/APB5RSTR": { + "description": "RCC APB5 reset register.", + "fields": [ + { + "name": "LTDCRST", + "description": "LTDC reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DCMIPPRST", + "description": "DCMIPP reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GFXTIMRST", + "description": "GFXTIM reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "VENCRST", + "description": "VENC reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CSIRST", + "description": "CSI reset.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/APB5RSTSR": { + "description": "RCC APB5 reset register.", + "fields": [ + { + "name": "LTDCRSTS", + "description": "LTDC reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DCMIPPRSTS", + "description": "DCMIPP reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "GFXTIMRSTS", + "description": "GFXTIM reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "VENCRSTS", + "description": "VENC reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CSIRSTS", + "description": "CSI reset.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/BDCR": { + "description": "RCC backup domain protection register.", + "fields": [ + { + "name": "VSWRST", + "description": "VSW domain software reset.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/BUSENCR": { + "description": "RCC bus enable register.", + "fields": [ + { + "name": "ACLKNENC", + "description": "ACLKN enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACLKNCENC", + "description": "ACLKNC enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AHBMENC", + "description": "AHBM enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1ENC", + "description": "AHB1 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2ENC", + "description": "AHB2 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3ENC", + "description": "AHB3 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4ENC", + "description": "AHB4 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5ENC", + "description": "AHB5 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1ENC", + "description": "APB1 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2ENC", + "description": "APB2 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3ENC", + "description": "APB3 enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4ENC", + "description": "APB4 enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5ENC", + "description": "APB5 enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/BUSENR": { + "description": "RCC SoC buses enable register.", + "fields": [ + { + "name": "ACLKNEN", + "description": "ACLKN enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACLKNCEN", + "description": "ACLKNC enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AHBMEN", + "description": "AHBM enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1EN", + "description": "AHB1 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2EN", + "description": "AHB2 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3EN", + "description": "AHB3 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4EN", + "description": "AHB4 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5EN", + "description": "AHB5 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1EN", + "description": "APB1 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2EN", + "description": "APB2 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3EN", + "description": "APB3 enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4EN", + "description": "APB4 enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5EN", + "description": "APB5 enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/BUSENSR": { + "description": "RCC bus enable register.", + "fields": [ + { + "name": "ACLKNENS", + "description": "ACLKN enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACLKNCENS", + "description": "ACLKNC enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AHBMENS", + "description": "AHBM enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1ENS", + "description": "AHB1 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2ENS", + "description": "AHB2 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3ENS", + "description": "AHB3 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4ENS", + "description": "AHB4 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5ENS", + "description": "AHB5 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1ENS", + "description": "APB1 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2ENS", + "description": "APB2 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3ENS", + "description": "APB3 enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4ENS", + "description": "APB4 enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5ENS", + "description": "APB5 enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/BUSLPENCR": { + "description": "RCC bus Sleep enable register.", + "fields": [ + { + "name": "ACLKNLPENC", + "description": "ACLKN sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACLKNCLPENC", + "description": "ACLKNC sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AHBMLPENC", + "description": "AHBM sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1LPENC", + "description": "AHB1 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2LPENC", + "description": "AHB2 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3LPENC", + "description": "AHB3 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4LPENC", + "description": "AHB4 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5LPENC", + "description": "AHB5 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1LPENC", + "description": "APB1 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2LPENC", + "description": "APB2 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3LPENC", + "description": "APB3 sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4LPENC", + "description": "APB4 sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5LPENC", + "description": "APB5 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/BUSLPENR": { + "description": "RCC SoC buses Sleep enable register.", + "fields": [ + { + "name": "ACLKNLPEN", + "description": "ACLKN sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACLKNCLPEN", + "description": "ACLKNC sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AHBMLPEN", + "description": "AHBM sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1LPEN", + "description": "AHB1 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2LPEN", + "description": "AHB2 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3LPEN", + "description": "AHB3 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4LPEN", + "description": "AHB4 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5LPEN", + "description": "AHB5 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1LPEN", + "description": "APB1 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2LPEN", + "description": "APB2 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3LPEN", + "description": "APB3 sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4LPEN", + "description": "APB4 sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5LPEN", + "description": "APB5 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/BUSLPENSR": { + "description": "RCC bus Sleep enable register.", + "fields": [ + { + "name": "ACLKNLPENS", + "description": "ACLKN sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACLKNCLPENS", + "description": "ACLKNC sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AHBMLPENS", + "description": "AHBM sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1LPENS", + "description": "AHB1 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2LPENS", + "description": "AHB2 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3LPENS", + "description": "AHB3 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4LPENS", + "description": "AHB4 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5LPENS", + "description": "AHB5 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1LPENS", + "description": "APB1 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2LPENS", + "description": "APB2 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3LPENS", + "description": "APB3 sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4LPENS", + "description": "APB4 sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5LPENS", + "description": "APB5 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/BUSRSTCR": { + "description": "RCC bus reset register.", + "fields": [ + { + "name": "ACLKNRSTC", + "description": "ACLKN reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AHBMRSTC", + "description": "AHBM reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1RSTC", + "description": "AHB1 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2RSTC", + "description": "AHB2 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3RSTC", + "description": "AHB3 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4RSTC", + "description": "AHB4 reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5RSTC", + "description": "AHB5 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1RSTC", + "description": "APB1 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2RSTC", + "description": "APB2 reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3RSTC", + "description": "APB3 reset.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4RSTC", + "description": "APB4 reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5RSTC", + "description": "APB5 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "NOCRSTC", + "description": "NOC reset.", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/BUSRSTR": { + "description": "RCC SoC buses reset register.", + "fields": [ + { + "name": "ACLKNRST", + "description": "ACLKN reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AHBMRST", + "description": "AHBM reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1RST", + "description": "AHB1 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2RST", + "description": "AHB2 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3RST", + "description": "AHB3 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4RST", + "description": "AHB4 reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5RST", + "description": "AHB5 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1RST", + "description": "APB1 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2RST", + "description": "APB2 reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3RST", + "description": "APB3 reset.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4RST", + "description": "APB4 reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5RST", + "description": "APB5 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "NOCRST", + "description": "NOC reset.", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/BUSRSTSR": { + "description": "RCC bus reset set register.", + "fields": [ + { + "name": "ACLKNRSTS", + "description": "ACLKN reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AHBMRSTS", + "description": "AHBM reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1RSTS", + "description": "AHB1 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2RSTS", + "description": "AHB2 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3RSTS", + "description": "AHB3 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4RSTS", + "description": "AHB4 reset.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5RSTS", + "description": "AHB5 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1RSTS", + "description": "APB1 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2RSTS", + "description": "APB2 reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3RSTS", + "description": "APB3 reset.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4RSTS", + "description": "APB4 reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5RSTS", + "description": "APB5 reset.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "NOCRSTS", + "description": "NOC reset.", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/CCIPR1": { + "description": "RCC clock configuration for independent peripheral register1.", + "fields": [ + { + "name": "ADF1SEL", + "description": "Source selection for the ADF1 kernel clock.", + "bit_offset": 0, + "bit_size": 3, + "enum": "ADFSEL" + }, + { + "name": "ADC12SEL", + "description": "Source selection for the ADC12 kernel clock.", + "bit_offset": 4, + "bit_size": 3, + "enum": "ADCSEL" + }, + { + "name": "ADCPRE", + "description": "ADC12 Prog clock divider selection (for clock ck_icn_p_adf1).", + "bit_offset": 8, + "bit_size": 8, + "enum": "ADCPRE" + }, + { + "name": "DCMIPPSEL", + "description": "Source selection for the DCMIPP kernel clock.", + "bit_offset": 20, + "bit_size": 2, + "enum": "DCMIPPSEL" + } + ] + }, + "fieldset/CCIPR12": { + "description": "RCC clock configuration for independent peripheral register12.", + "fields": [ + { + "name": "LPTIM1SEL", + "description": "Source selection for the LPTIM1 kernel clock.", + "bit_offset": 8, + "bit_size": 3, + "enum": "LPTIMSEL" + }, + { + "name": "LPTIM2SEL", + "description": "Source selection for the LPTIM2 kernel clock.", + "bit_offset": 12, + "bit_size": 3, + "enum": "LPTIMSEL" + }, + { + "name": "LPTIM3SEL", + "description": "Source selection for the LPTIM3 kernel clock.", + "bit_offset": 16, + "bit_size": 3, + "enum": "LPTIMSEL" + }, + { + "name": "LPTIM4SEL", + "description": "Source selection for the LPTIM4 kernel clock.", + "bit_offset": 20, + "bit_size": 3, + "enum": "LPTIMSEL" + }, + { + "name": "LPTIM5SEL", + "description": "Source selection for the LPTIM5 kernel clock.", + "bit_offset": 24, + "bit_size": 3, + "enum": "LPTIMSEL" + } + ] + }, + "fieldset/CCIPR13": { + "description": "RCC clock configuration for independent peripheral register13.", + "fields": [ + { + "name": "USART1SEL", + "description": "Source selection for the USART1 kernel clock.", + "bit_offset": 0, + "bit_size": 3, + "enum": "USARTSEL" + }, + { + "name": "USART2SEL", + "description": "Source selection for the USART2 kernel clock.", + "bit_offset": 4, + "bit_size": 3, + "enum": "USARTSEL" + }, + { + "name": "USART3SEL", + "description": "Source selection for the USART3 kernel clock.", + "bit_offset": 8, + "bit_size": 3, + "enum": "USARTSEL" + }, + { + "name": "UART4SEL", + "description": "Source selection for the UART4 kernel clock.", + "bit_offset": 12, + "bit_size": 3, + "enum": "UARTSEL" + }, + { + "name": "UART5SEL", + "description": "Source selection for the UART5 kernel clock.", + "bit_offset": 16, + "bit_size": 3, + "enum": "UARTSEL" + }, + { + "name": "USART6SEL", + "description": "Source selection for the USART6 kernel clock.", + "bit_offset": 20, + "bit_size": 3, + "enum": "USARTSEL" + }, + { + "name": "UART7SEL", + "description": "Source selection for the UART7 kernel clock.", + "bit_offset": 24, + "bit_size": 3, + "enum": "UARTSEL" + }, + { + "name": "UART8SEL", + "description": "Source selection for the UART8 kernel clock.", + "bit_offset": 28, + "bit_size": 3, + "enum": "UARTSEL" + } + ] + }, + "fieldset/CCIPR14": { + "description": "RCC clock configuration for independent peripheral register14.", + "fields": [ + { + "name": "UART9SEL", + "description": "Source selection for the UART9 kernel clock.", + "bit_offset": 0, + "bit_size": 3, + "enum": "UARTSEL" + }, + { + "name": "USART10SEL", + "description": "Source selection for the USART10 kernel clock.", + "bit_offset": 4, + "bit_size": 3, + "enum": "USARTSEL" + }, + { + "name": "LPUART1SEL", + "description": "Source selection for the LPUART1 kernel clock.", + "bit_offset": 8, + "bit_size": 3, + "enum": "LPUARTSEL" + } + ] + }, + "fieldset/CCIPR2": { + "description": "RCC clock configuration for independent peripheral register 2.", + "fields": [ + { + "name": "ETH1PTPSEL", + "description": "Source selection for the ETH1 kernel clock.", + "bit_offset": 0, + "bit_size": 2, + "enum": "ETHPTPSEL" + }, + { + "name": "ETH1PTPDIV", + "description": "ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp).", + "bit_offset": 4, + "bit_size": 4, + "enum": "ETHPTPDIV" + }, + { + "name": "ETH1PWRDOWNACK", + "description": "Set and reset by software.", + "bit_offset": 8, + "bit_size": 1, + "enum": "ETHPWRDOWNACK" + }, + { + "name": "ETH1CLKSEL", + "description": "Source selection for the ETH1 kernel clock.", + "bit_offset": 12, + "bit_size": 2, + "enum": "ETHCLKSEL" + }, + { + "name": "ETH1SEL", + "description": "Set and reset by software.", + "bit_offset": 16, + "bit_size": 3 + }, + { + "name": "ETH1REFCLKSEL", + "description": "Set and reset by software.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "ETH1GTXCLKSEL", + "description": "Set and reset by software.", + "bit_offset": 24, + "bit_size": 1, + "enum": "ETHGTXCLKSEL" + } + ] + }, + "fieldset/CCIPR3": { + "description": "RCC clock configuration for independent peripheral register3.", + "fields": [ + { + "name": "FDCANSEL", + "description": "Source selection for the FDCAN kernel clock.", + "bit_offset": 0, + "bit_size": 2, + "enum": "FDCANSEL" + }, + { + "name": "FMCSEL", + "description": "Source selection for the FMC kernel clock.", + "bit_offset": 4, + "bit_size": 2, + "enum": "FMCSEL" + }, + { + "name": "DFTSEL", + "description": "Source selection for the DFT kernel clock.", + "bit_offset": 8, + "bit_size": 1, + "enum": "DFTSEL" + } + ] + }, + "fieldset/CCIPR4": { + "description": "RCC clock configuration for independent peripheral register4.", + "fields": [ + { + "name": "I2C1SEL", + "description": "Source selection for the I2C1 kernel clock.", + "bit_offset": 0, + "bit_size": 3, + "enum": "I2C1SEL" + }, + { + "name": "I2C2SEL", + "description": "Source selection for the I2C2 kernel clock.", + "bit_offset": 4, + "bit_size": 3, + "enum": "I2C2SEL" + }, + { + "name": "I2C3SEL", + "description": "Source selection for the I2C3 kernel clock.", + "bit_offset": 8, + "bit_size": 3, + "enum": "I2C3SEL" + }, + { + "name": "I2C4SEL", + "description": "Source selection for the I2C4 kernel clock.", + "bit_offset": 12, + "bit_size": 3, + "enum": "I2C4SEL" + }, + { + "name": "I3C1SEL", + "description": "Source selection for the I3C1 kernel clock.", + "bit_offset": 16, + "bit_size": 3, + "enum": "I3C1SEL" + }, + { + "name": "I3C2SEL", + "description": "Source selection for the I3C2 kernel clock.", + "bit_offset": 20, + "bit_size": 3, + "enum": "I3C2SEL" + }, + { + "name": "LTDCSEL", + "description": "Source selection for the LTDC kernel clock.", + "bit_offset": 24, + "bit_size": 2, + "enum": "LTDCSEL" + } + ] + }, + "fieldset/CCIPR5": { + "description": "RCC lock configuration for independent peripheral register5.", + "fields": [ + { + "name": "MCO1SEL", + "description": "Source selection for the MCO1 kernel clock.", + "bit_offset": 0, + "bit_size": 3, + "enum": "MCOSEL" + }, + { + "name": "MCO1PRE", + "description": "MCO1 Prog clock divider selection (for clock ck_icn_p_mce3).", + "bit_offset": 4, + "bit_size": 4, + "enum": "MCOPRE" + }, + { + "name": "MCO2SEL", + "description": "Source selection for the MCO2 kernel clock.", + "bit_offset": 8, + "bit_size": 3, + "enum": "MCOSEL" + }, + { + "name": "MCO2PRE", + "description": "MCO2 Prog clock divider selection (for clock ck_icn_p_mce4).", + "bit_offset": 12, + "bit_size": 4, + "enum": "MCOPRE" + }, + { + "name": "MDF1SEL", + "description": "Source selection for the MDF1 kernel clock.", + "bit_offset": 16, + "bit_size": 3, + "enum": "MDFSEL" + } + ] + }, + "fieldset/CCIPR6": { + "description": "RCC clock configuration for independent peripheral register6.", + "fields": [ + { + "name": "XSPI1SEL", + "description": "Source selection for the XSPI1 kernel clock.", + "bit_offset": 0, + "bit_size": 2, + "enum": "XSPISEL" + }, + { + "name": "XSPI2SEL", + "description": "Source selection for the XSPI2 kernel clock.", + "bit_offset": 4, + "bit_size": 2, + "enum": "XSPISEL" + }, + { + "name": "XSPI3SEL", + "description": "Source selection for the XSPI3 kernel clock.", + "bit_offset": 8, + "bit_size": 2, + "enum": "XSPISEL" + }, + { + "name": "OTGPHY1SEL", + "description": "Source selection for the OTGPHY1 kernel clock.", + "bit_offset": 12, + "bit_size": 2, + "enum": "OTGPHYSEL" + }, + { + "name": "OTGPHY1CKREFSEL", + "description": "Set and reset by software.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "OTGPHY2SEL", + "description": "Source selection for the OTGPHY2 kernel clock.", + "bit_offset": 20, + "bit_size": 2, + "enum": "OTGPHYSEL" + }, + { + "name": "OTGPHY2CKREFSEL", + "description": "Set and reset by software.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CCIPR7": { + "description": "RCC clock configuration for independent peripheral register7.", + "fields": [ + { + "name": "PERSEL", + "description": "Source selection for the PER kernel clock.", + "bit_offset": 0, + "bit_size": 3, + "enum": "PERSEL" + }, + { + "name": "PSSISEL", + "description": "Source selection for the PSSI kernel clock.", + "bit_offset": 4, + "bit_size": 2, + "enum": "PSSISEL" + }, + { + "name": "RTCSEL", + "description": "Source selection for the RTC kernel clock.", + "bit_offset": 8, + "bit_size": 2, + "enum": "RTCSEL" + }, + { + "name": "RTCPRE", + "description": "RTC Prog clock divider selection (for clock ck_icn_p_risaf).", + "bit_offset": 12, + "bit_size": 6, + "enum": "RTCPRE" + }, + { + "name": "SAI1SEL", + "description": "Source selection for the SAI1 kernel clock.", + "bit_offset": 20, + "bit_size": 3, + "enum": "SAISEL" + }, + { + "name": "SAI2SEL", + "description": "Source selection for the SAI2 kernel clock.", + "bit_offset": 24, + "bit_size": 3, + "enum": "SAISEL" + } + ] + }, + "fieldset/CCIPR8": { + "description": "RCC clock configuration for independent peripheral register8.", + "fields": [ + { + "name": "SDMMC1SEL", + "description": "Source selection for the SDMMC1 kernel clock.", + "bit_offset": 0, + "bit_size": 2, + "enum": "SDMMCSEL" + }, + { + "name": "SDMMC2SEL", + "description": "Source selection for the SDMMC2 kernel clock.", + "bit_offset": 4, + "bit_size": 2, + "enum": "SDMMCSEL" + } + ] + }, + "fieldset/CCIPR9": { + "description": "RCC clock configuration for independent peripheral register9.", + "fields": [ + { + "name": "SPDIFRX1SEL", + "description": "Source selection for the SPDIFRX1 kernel clock.", + "bit_offset": 0, + "bit_size": 3, + "enum": "SPDIFRXSEL" + }, + { + "name": "SPI1SEL", + "description": "Source selection for the SPI1 kernel clock.", + "bit_offset": 4, + "bit_size": 3, + "enum": "SPISEL1" + }, + { + "name": "SPI2SEL", + "description": "Source selection for the SPI2 kernel clock.", + "bit_offset": 8, + "bit_size": 3, + "enum": "SPISEL23" + }, + { + "name": "SPI3SEL", + "description": "Source selection for the SPI3 kernel clock.", + "bit_offset": 12, + "bit_size": 3, + "enum": "SPISEL23" + }, + { + "name": "SPI4SEL", + "description": "Source selection for the SPI4 kernel clock.", + "bit_offset": 16, + "bit_size": 3, + "enum": "SPISEL45" + }, + { + "name": "SPI5SEL", + "description": "Source selection for the SPI5 kernel clock.", + "bit_offset": 20, + "bit_size": 3, + "enum": "SPISEL45" + }, + { + "name": "SPI6SEL", + "description": "Source selection for the SPI6 kernel clock.", + "bit_offset": 24, + "bit_size": 3, + "enum": "SPISEL6" + } + ] + }, + "fieldset/CCR": { + "description": "RCC control Clear register.", + "fields": [ + { + "name": "LSIONC", + "description": "LSI oscillator enable in Run/Sleep mode.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "LSEONC", + "description": "LSE oscillator enable in Run/Sleep mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MSIONC", + "description": "MSI oscillator enable in Run/Sleep mode.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "HSIONC", + "description": "HSI oscillator enable in Run/Sleep mode.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "HSEONC", + "description": "HSE oscillator enable in Run/Sleep mode.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PLLONC", + "description": "PLL1 oscillator enable in Run/Sleep mode.", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } + } + ] + }, + "fieldset/CFGR1": { + "description": "RCC configuration register 1.", + "fields": [ + { + "name": "STOPWUCK", + "description": "System clock selection after a wake up from system Stop.", + "bit_offset": 0, + "bit_size": 1, + "enum": "STOPWUCK" + }, + { + "name": "CPUSW", + "description": "CPU clock switch selection.", + "bit_offset": 16, + "bit_size": 2, + "enum": "CPUSW" + }, + { + "name": "CPUSWS", + "description": "CPU clock switch status.", + "bit_offset": 20, + "bit_size": 2, + "enum": "CPUSWS" + }, + { + "name": "SYSSW", + "description": "System clock switch selection.", + "bit_offset": 24, + "bit_size": 2, + "enum": "SYSSW" + }, + { + "name": "SYSSWS", + "description": "System clock switch status.", + "bit_offset": 28, + "bit_size": 2, + "enum": "SYSSWS" + } + ] + }, + "fieldset/CFGR2": { + "description": "RCC configuration register 2.", + "fields": [ + { + "name": "PPRE1", + "description": "CPU domain APB1 prescaler.", + "bit_offset": 0, + "bit_size": 3, + "enum": "PPRE" + }, + { + "name": "PPRE2", + "description": "CPU domain APB2 prescaler.", + "bit_offset": 4, + "bit_size": 3, + "enum": "PPRE" + }, + { + "name": "PPRE4", + "description": "CPU domain APB4 prescaler.", + "bit_offset": 12, + "bit_size": 3, + "enum": "PPRE" + }, + { + "name": "PPRE5", + "description": "CPU domain APB5 prescaler.", + "bit_offset": 16, + "bit_size": 3, + "enum": "PPRE" + }, + { + "name": "HPRE", + "description": "AHB clock prescaler.", + "bit_offset": 20, + "bit_size": 3, + "enum": "HPRE" + }, + { + "name": "TIMPRE", + "description": "Timers clocks prescaler selection.", + "bit_offset": 24, + "bit_size": 2, + "enum": "TIMPRE" + } + ] + }, + "fieldset/CICR": { + "description": "RCC clock-source interrupt Clear register.", + "fields": [ + { + "name": "LSIRDYC", + "description": "LSI ready interrupt clear.", + "bit_offset": 0, + "bit_size": 1, + "enum": "LSIRDYC" + }, + { + "name": "LSERDYC", + "description": "LSE ready interrupt clear.", + "bit_offset": 1, + "bit_size": 1, + "enum": "LSERDYC" + }, + { + "name": "MSIRDYC", + "description": "MSI ready interrupt clear.", + "bit_offset": 2, + "bit_size": 1, + "enum": "MSIRDYC" + }, + { + "name": "HSIRDYC", + "description": "HSI ready interrupt clear.", + "bit_offset": 3, + "bit_size": 1, + "enum": "HSIRDYC" + }, + { + "name": "HSERDYC", + "description": "HSE ready interrupt clear.", + "bit_offset": 4, + "bit_size": 1, + "enum": "HSERDYC" + }, + { + "name": "PLLRDYC", + "description": "PLL1 ready interrupt clear.", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + }, + "enum": "PLLRDYC" + }, + { + "name": "LSECSSC", + "description": "LSE ready interrupt clear.", + "bit_offset": 16, + "bit_size": 1, + "enum": "LSECSSC" + }, + { + "name": "HSECSSC", + "description": "HSE ready interrupt clear.", + "bit_offset": 17, + "bit_size": 1, + "enum": "HSECSSC" + }, + { + "name": "WKUPFC", + "description": "CPU Wakeup ready interrupt clear.", + "bit_offset": 24, + "bit_size": 1, + "enum": "WKUPFC" + } + ] + }, + "fieldset/CIER": { + "description": "RCC clock-source interrupt enable register.", + "fields": [ + { + "name": "LSIRDYIE", + "description": "LSI ready interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "enum": "LSIRDYIE" + }, + { + "name": "LSERDYIE", + "description": "LSE ready interrupt enable.", + "bit_offset": 1, + "bit_size": 1, + "enum": "LSERDYIE" + }, + { + "name": "MSIRDYIE", + "description": "MSI ready interrupt enable.", + "bit_offset": 2, + "bit_size": 1, + "enum": "MSIRDYIE" + }, + { + "name": "HSIRDYIE", + "description": "HSI ready interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "enum": "HSIRDYIE" + }, + { + "name": "HSERDYIE", + "description": "HSE ready interrupt enable.", + "bit_offset": 4, + "bit_size": 1, + "enum": "HSERDYIE" + }, + { + "name": "PLLRDYIE", + "description": "PLL1 ready interrupt enable.", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + }, + "enum": "PLLRDYIE" + }, + { + "name": "LSECSSIE", + "description": "LSE clock security system (CSS) interrupt enable.", + "bit_offset": 16, + "bit_size": 1, + "enum": "LSECSSIE" + }, + { + "name": "HSECSSIE", + "description": "HSE clock security system (CSS) interrupt enable.", + "bit_offset": 17, + "bit_size": 1, + "enum": "HSECSSIE" + }, + { + "name": "WKUPIE", + "description": "CPU wakeup from Stop interrupt enable.", + "bit_offset": 24, + "bit_size": 1, + "enum": "WKUPIE" + } + ] + }, + "fieldset/CIFR": { + "description": "RCC clock-source interrupt flag register.", + "fields": [ + { + "name": "LSIRDYF", + "description": "LSI ready interrupt flag.", + "bit_offset": 0, + "bit_size": 1, + "enum": "LSIRDYF" + }, + { + "name": "LSERDYF", + "description": "LSE ready interrupt flag.", + "bit_offset": 1, + "bit_size": 1, + "enum": "LSERDYF" + }, + { + "name": "MSIRDYF", + "description": "MSI ready interrupt flag.", + "bit_offset": 2, + "bit_size": 1, + "enum": "MSIRDYF" + }, + { + "name": "HSIRDYF", + "description": "HSI ready interrupt flag.", + "bit_offset": 3, + "bit_size": 1, + "enum": "HSIRDYF" + }, + { + "name": "HSERDYF", + "description": "HSE ready interrupt flag.", + "bit_offset": 4, + "bit_size": 1, + "enum": "HSERDYF" + }, + { + "name": "PLLRDYF", + "description": "PLL1 ready interrupt flag.", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + }, + "enum": "PLLRDYF" + }, + { + "name": "LSECSSF", + "description": "LSE ready interrupt flag.", + "bit_offset": 16, + "bit_size": 1, + "enum": "LSECSSF" + }, + { + "name": "HSECSSF", + "description": "HSE ready interrupt flag.", + "bit_offset": 17, + "bit_size": 1, + "enum": "HSECSSF" + }, + { + "name": "WKUPF", + "description": "CPU wakeup from Stop interrupt flag.", + "bit_offset": 24, + "bit_size": 1, + "enum": "WKUPF" + } + ] + }, + "fieldset/CKPROTR": { + "description": "RCC clock protection register.", + "fields": [ + { + "name": "XSPI3SELS", + "description": "XSPI3 clock selection current status.", + "bit_offset": 16, + "bit_size": 2, + "enum": "XSPISELS" + }, + { + "name": "XSPI2SELS", + "description": "XSPI2 clock selection current status.", + "bit_offset": 20, + "bit_size": 2, + "enum": "XSPISELS" + }, + { + "name": "XSPI1SELS", + "description": "XSPI1 clock selection current status.", + "bit_offset": 24, + "bit_size": 2, + "enum": "XSPISELS" + }, + { + "name": "FMCSELS", + "description": "FMC clock selection current status.", + "bit_offset": 28, + "bit_size": 2, + "enum": "FMCSELS" + } + ] + }, + "fieldset/CR": { + "description": "RCC control register.", + "fields": [ + { + "name": "LSION", + "description": "LSI oscillator enable in Run/Sleep mode.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "LSEON", + "description": "LSE oscillator enable in Run/Sleep mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MSION", + "description": "MSI oscillator enable in Run/Sleep mode.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "HSION", + "description": "HSI oscillator enable in Run/Sleep mode.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "HSEON", + "description": "HSE oscillator enable in Run/Sleep mode.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PLLON", + "description": "PLL1 enable in Run/Sleep mode.", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } + } + ] + }, + "fieldset/CSR": { + "description": "RCC control set register.", + "fields": [ + { + "name": "LSIONS", + "description": "LSI oscillator enable in Run/Sleep mode.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "LSEONS", + "description": "LSE oscillator enable in Run/Sleep mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MSIONS", + "description": "MSI oscillator enable in Run/Sleep mode.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "HSIONS", + "description": "HSI oscillator enable in Run/Sleep mode.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "HSEONS", + "description": "HSE oscillator enable in Run/Sleep mode.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "PLLONS", + "description": "PLL1 oscillator enable in Run/Sleep mode.", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } + } + ] + }, + "fieldset/DIVENCR": { + "description": "RCC divider enable register.", + "fields": [ + { + "name": "IC1ENC", + "description": "IC1 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "IC2ENC", + "description": "IC2 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "IC3ENC", + "description": "IC3 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "IC4ENC", + "description": "IC4 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "IC5ENC", + "description": "IC5 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "IC6ENC", + "description": "IC6 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "IC7ENC", + "description": "IC7 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "IC8ENC", + "description": "IC8 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "IC9ENC", + "description": "IC9 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IC10ENC", + "description": "IC10 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IC11ENC", + "description": "IC11 enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "IC12ENC", + "description": "IC12 enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "IC13ENC", + "description": "IC13 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "IC14ENC", + "description": "IC14 enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "IC15ENC", + "description": "IC15 enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IC16ENC", + "description": "IC16 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "IC17ENC", + "description": "IC17 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IC18ENC", + "description": "IC18 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IC19ENC", + "description": "IC19 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "IC20ENC", + "description": "IC20 enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/DIVENR": { + "description": "RCC IC dividers enable register.", + "fields": [ + { + "name": "IC1EN", + "description": "IC1 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "IC2EN", + "description": "IC2 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "IC3EN", + "description": "IC3 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "IC4EN", + "description": "IC4 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "IC5EN", + "description": "IC5 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "IC6EN", + "description": "IC6 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "IC7EN", + "description": "IC7 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "IC8EN", + "description": "IC8 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "IC9EN", + "description": "IC9 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IC10EN", + "description": "IC10 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IC11EN", + "description": "IC11 enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "IC12EN", + "description": "IC12 enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "IC13EN", + "description": "IC13 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "IC14EN", + "description": "IC14 enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "IC15EN", + "description": "IC15 enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IC16EN", + "description": "IC16 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "IC17EN", + "description": "IC17 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IC18EN", + "description": "IC18 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IC19EN", + "description": "IC19 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "IC20EN", + "description": "IC20 enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/DIVENSR": { + "description": "RCC Divider enable register.", + "fields": [ + { + "name": "IC1ENS", + "description": "IC1 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "IC2ENS", + "description": "IC2 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "IC3ENS", + "description": "IC3 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "IC4ENS", + "description": "IC4 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "IC5ENS", + "description": "IC5 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "IC6ENS", + "description": "IC6 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "IC7ENS", + "description": "IC7 enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "IC8ENS", + "description": "IC8 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "IC9ENS", + "description": "IC9 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IC10ENS", + "description": "IC10 enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IC11ENS", + "description": "IC11 enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "IC12ENS", + "description": "IC12 enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "IC13ENS", + "description": "IC13 enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "IC14ENS", + "description": "IC14 enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "IC15ENS", + "description": "IC15 enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IC16ENS", + "description": "IC16 enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "IC17ENS", + "description": "IC17 enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IC18ENS", + "description": "IC18 enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IC19ENS", + "description": "IC19 enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "IC20ENS", + "description": "IC20 enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/DIVLPENCR": { + "description": "RCC divider Sleep enable register.", + "fields": [ + { + "name": "IC1LPENC", + "description": "IC1 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "IC2LPENC", + "description": "IC2 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "IC3LPENC", + "description": "IC3 sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "IC4LPENC", + "description": "IC4 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "IC5LPENC", + "description": "IC5 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "IC6LPENC", + "description": "IC6 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "IC7LPENC", + "description": "IC7 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "IC8LPENC", + "description": "IC8 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "IC9LPENC", + "description": "IC9 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IC10LPENC", + "description": "IC10 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IC11LPENC", + "description": "IC11 sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "IC12LPENC", + "description": "IC12 sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "IC13LPENC", + "description": "IC13 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "IC14LPENC", + "description": "IC14 sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "IC15LPENC", + "description": "IC15 sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IC16LPENC", + "description": "IC16 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "IC17LPENC", + "description": "IC17 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IC18LPENC", + "description": "IC18 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IC19LPENC", + "description": "IC19 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "IC20LPENC", + "description": "IC20 sleep enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/DIVLPENR": { + "description": "RCC dividers Sleep enable register.", + "fields": [ + { + "name": "IC1LPEN", + "description": "IC1 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "IC2LPEN", + "description": "IC2 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "IC3LPEN", + "description": "IC3 sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "IC4LPEN", + "description": "IC4 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "IC5LPEN", + "description": "IC5 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "IC6LPEN", + "description": "IC6 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "IC7LPEN", + "description": "IC7 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "IC8LPEN", + "description": "IC8 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "IC9LPEN", + "description": "IC9 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IC10LPEN", + "description": "IC10 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IC11LPEN", + "description": "IC11 sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "IC12LPEN", + "description": "IC12 sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "IC13LPEN", + "description": "IC13 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "IC14LPEN", + "description": "IC14 sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "IC15LPEN", + "description": "IC15 sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IC16LPEN", + "description": "IC16 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "IC17LPEN", + "description": "IC17 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IC18LPEN", + "description": "IC18 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IC19LPEN", + "description": "IC19 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "IC20LPEN", + "description": "IC20 sleep enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/DIVLPENSR": { + "description": "RCC divider Sleep enable register.", + "fields": [ + { + "name": "IC1LPENS", + "description": "IC1 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "IC2LPENS", + "description": "IC2 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "IC3LPENS", + "description": "IC3 sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "IC4LPENS", + "description": "IC4 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "IC5LPENS", + "description": "IC5 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "IC6LPENS", + "description": "IC6 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "IC7LPENS", + "description": "IC7 sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "IC8LPENS", + "description": "IC8 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "IC9LPENS", + "description": "IC9 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IC10LPENS", + "description": "IC10 sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IC11LPENS", + "description": "IC11 sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "IC12LPENS", + "description": "IC12 sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "IC13LPENS", + "description": "IC13 sleep enable.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "IC14LPENS", + "description": "IC14 sleep enable.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "IC15LPENS", + "description": "IC15 sleep enable.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IC16LPENS", + "description": "IC16 sleep enable.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "IC17LPENS", + "description": "IC17 sleep enable.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IC18LPENS", + "description": "IC18 sleep enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IC19LPENS", + "description": "IC19 sleep enable.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "IC20LPENS", + "description": "IC20 sleep enable.", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/HSECFGR": { + "description": "RCC HSE configuration register.", + "fields": [ + { + "name": "HSEDIV2BYP", + "description": "HSE div2 oscillator clock in Bypass mode.", + "bit_offset": 6, + "bit_size": 1, + "enum": "HSEDIVBYP" + }, + { + "name": "HSECSSON", + "description": "HSE clock security system (CSS) enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "HSECSSRA", + "description": "HSE clock security system (CSS) re-arm function.", + "bit_offset": 8, + "bit_size": 1, + "enum": "HSECSSRA" + }, + { + "name": "HSECSSD", + "description": "HSE clock security system (CSS) failure detection.", + "bit_offset": 9, + "bit_size": 1, + "enum": "HSECSSD" + }, + { + "name": "HSECSSBYP", + "description": "HSE clock security system (CSS) bypass enable.", + "bit_offset": 10, + "bit_size": 1, + "enum": "HSECSSBYP" + }, + { + "name": "HSECSSBPRE", + "description": "HSE clock security system (CSS) bypass divider.", + "bit_offset": 11, + "bit_size": 4, + "enum": "HSECSSBPRE" + }, + { + "name": "HSEBYP", + "description": "HSE clock bypass.", + "bit_offset": 15, + "bit_size": 1, + "enum": "HSEBYP" + }, + { + "name": "HSEEXT", + "description": "HSE clock type in Bypass mode.", + "bit_offset": 16, + "bit_size": 1, + "enum": "HSEEXT" + }, + { + "name": "HSEGFON", + "description": "HSE clock glitch filter enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "HSEDRV", + "description": "HSE oscillator driving capability.", + "bit_offset": 18, + "bit_size": 2, + "enum": "HSEDRV" + } + ] + }, + "fieldset/HSICFGR": { + "description": "RCC HSI configuration register.", + "fields": [ + { + "name": "HSIDIV", + "description": "HSI clock divider.", + "bit_offset": 7, + "bit_size": 2, + "enum": "HSIDIV" + }, + { + "name": "HSITRIM", + "description": "HSI clock trimming.", + "bit_offset": 16, + "bit_size": 7, + "enum": "HSITRIM" + }, + { + "name": "HSICAL", + "description": "HSI clock calibration.", + "bit_offset": 23, + "bit_size": 9 + } + ] + }, + "fieldset/HSIMCR": { + "description": "RCC HSI monitor control register.", + "fields": [ + { + "name": "HSIREF", + "description": "HSI clock cycle counter reference value.", + "bit_offset": 0, + "bit_size": 11 + }, + { + "name": "HSIDEV", + "description": "HSI clock count deviation value.", + "bit_offset": 16, + "bit_size": 6 + }, + { + "name": "HSIMONEN", + "description": "HSI clock period monitor enable.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HSIMSR": { + "description": "RCC HSI monitor status register.", + "fields": [ + { + "name": "HSIVAL", + "description": "HSI clock cycle counter measured value.", + "bit_offset": 0, + "bit_size": 11 + } + ] + }, + "fieldset/HWRSR": { + "description": "RCC reset status register for hardware.", + "fields": [ + { + "name": "RMVF", + "description": "Remove reset flag.", + "bit_offset": 16, + "bit_size": 1, + "enum": "HWRSR_RMVF" + }, + { + "name": "LCKRSTF", + "description": "CPU lockup reset flag.", + "bit_offset": 17, + "bit_size": 1, + "enum": "HWRSR_LCKRSTF" + }, + { + "name": "BORRSTF", + "description": "BOR flag.", + "bit_offset": 21, + "bit_size": 1, + "enum": "HWRSR_BORRSTF" + }, + { + "name": "PINRSTF", + "description": "Pin reset flag (NRST).", + "bit_offset": 22, + "bit_size": 1, + "enum": "HWRSR_PINRSTF" + }, + { + "name": "PORRSTF", + "description": "POR/PDR flag.", + "bit_offset": 23, + "bit_size": 1, + "enum": "HWRSR_PORRSTF" + }, + { + "name": "SFTRSTF", + "description": "Software system reset flag (1).", + "bit_offset": 24, + "bit_size": 1, + "enum": "HWRSR_SFTRSTF" + }, + { + "name": "IWDGRSTF", + "description": "Independent Watchdog reset flag.", + "bit_offset": 26, + "bit_size": 1, + "enum": "HWRSR_IWDGRSTF" + }, + { + "name": "WWDGRSTF", + "description": "Window watchdog reset flag.", + "bit_offset": 28, + "bit_size": 1, + "enum": "HWRSR_WWDGRSTF" + }, + { + "name": "LPWRRSTF", + "description": "Illegal Stop or Standby flag.", + "bit_offset": 30, + "bit_size": 1, + "enum": "HWRSR_LPWRRSTF" + } + ] + }, + "fieldset/IC10CFGR": { + "description": "RCC IC10 configuration register.", + "fields": [ + { + "name": "IC10INT", + "description": "Divider IC10 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC10INT" + }, + { + "name": "IC10SEL", + "description": "Divider IC10 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC10SEL" + } + ] + }, + "fieldset/IC11CFGR": { + "description": "RCC IC11 configuration register.", + "fields": [ + { + "name": "IC11INT", + "description": "Divider IC11 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC11INT" + }, + { + "name": "IC11SEL", + "description": "Divider IC11 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC11SEL" + } + ] + }, + "fieldset/IC12CFGR": { + "description": "RCC IC12 configuration register.", + "fields": [ + { + "name": "IC12INT", + "description": "Divider IC12 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC12INT" + }, + { + "name": "IC12SEL", + "description": "Divider IC12 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC12SEL" + } + ] + }, + "fieldset/IC13CFGR": { + "description": "RCC IC13 configuration register.", + "fields": [ + { + "name": "IC13INT", + "description": "Divider IC13 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC13INT" + }, + { + "name": "IC13SEL", + "description": "Divider IC13 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC13SEL" + } + ] + }, + "fieldset/IC14CFGR": { + "description": "RCC IC14 configuration register.", + "fields": [ + { + "name": "IC14INT", + "description": "Divider IC14 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC14INT" + }, + { + "name": "IC14SEL", + "description": "Divider IC14 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC14SEL" + } + ] + }, + "fieldset/IC15CFGR": { + "description": "RCC IC15 configuration register.", + "fields": [ + { + "name": "IC15INT", + "description": "Divider IC15 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC15INT" + }, + { + "name": "IC15SEL", + "description": "Divider IC15 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC15SEL" + } + ] + }, + "fieldset/IC16CFGR": { + "description": "RCC IC16 configuration register.", + "fields": [ + { + "name": "IC16INT", + "description": "Divider IC16 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC16INT" + }, + { + "name": "IC16SEL", + "description": "Divider IC16 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC16SEL" + } + ] + }, + "fieldset/IC17CFGR": { + "description": "RCC IC17 configuration register.", + "fields": [ + { + "name": "IC17INT", + "description": "Divider IC17 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC17INT" + }, + { + "name": "IC17SEL", + "description": "Divider IC17 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC17SEL" + } + ] + }, + "fieldset/IC18CFGR": { + "description": "RCC IC18 configuration register.", + "fields": [ + { + "name": "IC18INT", + "description": "Divider IC18 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC18INT" + }, + { + "name": "IC18SEL", + "description": "Divider IC18 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC18SEL" + } + ] + }, + "fieldset/IC19CFGR": { + "description": "RCC IC19 configuration register.", + "fields": [ + { + "name": "IC19INT", + "description": "Divider IC19 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC19INT" + }, + { + "name": "IC19SEL", + "description": "Divider IC19 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC19SEL" + } + ] + }, + "fieldset/IC1CFGR": { + "description": "RCC IC1 configuration register.", + "fields": [ + { + "name": "IC1INT", + "description": "Divider IC1 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC1INT" + }, + { + "name": "IC1SEL", + "description": "Divider IC1 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC1SEL" + } + ] + }, + "fieldset/IC20CFGR": { + "description": "RCC IC20 configuration register.", + "fields": [ + { + "name": "IC20INT", + "description": "Divider IC20 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC20INT" + }, + { + "name": "IC20SEL", + "description": "Divider IC20 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC20SEL" + } + ] + }, + "fieldset/IC2CFGR": { + "description": "RCC IC2 configuration register.", + "fields": [ + { + "name": "IC2INT", + "description": "Divider IC2 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC2INT" + }, + { + "name": "IC2SEL", + "description": "Divider IC2 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC2SEL" + } + ] + }, + "fieldset/IC3CFGR": { + "description": "RCC IC3 configuration register.", + "fields": [ + { + "name": "IC3INT", + "description": "Divider IC3 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC3INT" + }, + { + "name": "IC3SEL", + "description": "Divider IC3 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC3SEL" + } + ] + }, + "fieldset/IC4CFGR": { + "description": "RCC IC4 configuration register.", + "fields": [ + { + "name": "IC4INT", + "description": "Divider IC4 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC4INT" + }, + { + "name": "IC4SEL", + "description": "Divider IC4 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC4SEL" + } + ] + }, + "fieldset/IC5CFGR": { + "description": "RCC IC5 configuration register.", + "fields": [ + { + "name": "IC5INT", + "description": "Divider IC5 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC5INT" + }, + { + "name": "IC5SEL", + "description": "Divider IC5 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC5SEL" + } + ] + }, + "fieldset/IC6CFGR": { + "description": "RCC IC6 configuration register.", + "fields": [ + { + "name": "IC6INT", + "description": "Divider IC6 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC6INT" + }, + { + "name": "IC6SEL", + "description": "Divider IC6 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC6SEL" + } + ] + }, + "fieldset/IC7CFGR": { + "description": "RCC IC7 configuration register.", + "fields": [ + { + "name": "IC7INT", + "description": "Divider IC7 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC7INT" + }, + { + "name": "IC7SEL", + "description": "Divider IC7 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC7SEL" + } + ] + }, + "fieldset/IC8CFGR": { + "description": "RCC IC8 configuration register.", + "fields": [ + { + "name": "IC8INT", + "description": "Divider IC8 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC8INT" + }, + { + "name": "IC8SEL", + "description": "Divider IC8 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC8SEL" + } + ] + }, + "fieldset/IC9CFGR": { + "description": "RCC IC9 configuration register.", + "fields": [ + { + "name": "IC9INT", + "description": "Divider IC9 integer division factor.", + "bit_offset": 16, + "bit_size": 8, + "enum": "IC9INT" + }, + { + "name": "IC9SEL", + "description": "Divider IC9 Source Selection.", + "bit_offset": 28, + "bit_size": 2, + "enum": "IC9SEL" + } + ] + }, + "fieldset/LOCKCFGR0": { + "description": "RCC oscillator lock configuration register0.", + "fields": [ + { + "name": "LSILOCK", + "description": "Defines the lock protection of the LSI oscillator configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "LSILOCK" + }, + { + "name": "LSELOCK", + "description": "Defines the lock protection of the LSE oscillator configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "LSELOCK" + }, + { + "name": "MSILOCK", + "description": "Defines the lock protection of the MSI oscillator configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "MSILOCK" + }, + { + "name": "HSILOCK", + "description": "Defines the lock protection of the HSI oscillator configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "HSILOCK" + }, + { + "name": "HSELOCK", + "description": "Defines the lock protection of the HSE oscillator configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "HSELOCK" + } + ] + }, + "fieldset/LOCKCFGR1": { + "description": "RCC PLL lock configuration register1.", + "fields": [ + { + "name": "PLLLOCK", + "description": "Defines the lock protection of the PLL1 PLL configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + }, + "enum": "PLLLOCK" + } + ] + }, + "fieldset/LOCKCFGR2": { + "description": "RCC divider lock configuration register2.", + "fields": [ + { + "name": "IC1LOCK", + "description": "Defines the lock protection of the IC1 divider configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC2LOCK", + "description": "Defines the lock protection of the IC2 divider configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC3LOCK", + "description": "Defines the lock protection of the IC3 divider configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC4LOCK", + "description": "Defines the lock protection of the IC4 divider configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC5LOCK", + "description": "Defines the lock protection of the IC5 divider configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC6LOCK", + "description": "Defines the lock protection of the IC6 divider configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC7LOCK", + "description": "Defines the lock protection of the IC7 divider configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC8LOCK", + "description": "Defines the lock protection of the IC8 divider configuration bits.", + "bit_offset": 7, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC9LOCK", + "description": "Defines the lock protection of the IC9 divider configuration bits.", + "bit_offset": 8, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC10LOCK", + "description": "Defines the lock protection of the IC10 divider configuration bits.", + "bit_offset": 9, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC11LOCK", + "description": "Defines the lock protection of the IC11 divider configuration bits.", + "bit_offset": 10, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC12LOCK", + "description": "Defines the lock protection of the IC12 divider configuration bits.", + "bit_offset": 11, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC13LOCK", + "description": "Defines the lock protection of the IC13 divider configuration bits.", + "bit_offset": 12, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC14LOCK", + "description": "Defines the lock protection of the IC14 divider configuration bits.", + "bit_offset": 13, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC15LOCK", + "description": "Defines the lock protection of the IC15 divider configuration bits.", + "bit_offset": 14, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC16LOCK", + "description": "Defines the lock protection of the IC16 divider configuration bits.", + "bit_offset": 15, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC17LOCK", + "description": "Defines the lock protection of the IC17 divider configuration bits.", + "bit_offset": 16, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC18LOCK", + "description": "Defines the lock protection of the IC18 divider configuration bits.", + "bit_offset": 17, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC19LOCK", + "description": "Defines the lock protection of the IC19 divider configuration bits.", + "bit_offset": 18, + "bit_size": 1, + "enum": "ICLOCK" + }, + { + "name": "IC20LOCK", + "description": "Defines the lock protection of the IC20 divider configuration bits.", + "bit_offset": 19, + "bit_size": 1, + "enum": "ICLOCK" + } + ] + }, + "fieldset/LOCKCFGR3": { + "description": "RCC system lock configuration register3.", + "fields": [ + { + "name": "MODLOCK", + "description": "Defines the lock protection of the MOD system configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "MODLOCK" + }, + { + "name": "SYSLOCK", + "description": "Defines the lock protection of the SYS system configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "SYSLOCK" + }, + { + "name": "BUSLOCK", + "description": "Defines the lock protection of the BUS system configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "BUSLOCK" + }, + { + "name": "PERLOCK", + "description": "Defines the lock protection of the PER system configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "PERLOCK" + }, + { + "name": "INTLOCK", + "description": "Defines the lock protection of the INT system configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "INTLOCK" + }, + { + "name": "RSTLOCK", + "description": "Defines the lock protection of the RST system configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "RSTLOCK" + }, + { + "name": "DFTLOCK", + "description": "Defines the lock protection of the DFT system configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "DFTLOCK" + } + ] + }, + "fieldset/LOCKCFGR4": { + "description": "RCC bus lock configuration register4.", + "fields": [ + { + "name": "ACLKNLOCK", + "description": "Defines the lock protection of the ACLKN bus configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ACLKNLOCK" + }, + { + "name": "ACLKNCLOCK", + "description": "Defines the lock protection of the ACLKNC bus configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "ACLKNCLOCK" + }, + { + "name": "AHBMLOCK", + "description": "Defines the lock protection of the AHBM bus configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "AHBMLOCK" + }, + { + "name": "AHB1LOCK", + "description": "Defines the lock protection of the AHB1 bus configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "AHBLOCK" + }, + { + "name": "AHB2LOCK", + "description": "Defines the lock protection of the AHB2 bus configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "AHBLOCK" + }, + { + "name": "AHB3LOCK", + "description": "Defines the lock protection of the AHB3 bus configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "AHBLOCK" + }, + { + "name": "AHB4LOCK", + "description": "Defines the lock protection of the AHB4 bus configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "AHBLOCK" + }, + { + "name": "AHB5LOCK", + "description": "Defines the lock protection of the AHB5 bus configuration bits.", + "bit_offset": 7, + "bit_size": 1, + "enum": "AHBLOCK" + }, + { + "name": "APB1LOCK", + "description": "Defines the lock protection of the APB1 bus configuration bits.", + "bit_offset": 8, + "bit_size": 1, + "enum": "APBLOCK" + }, + { + "name": "APB2LOCK", + "description": "Defines the lock protection of the APB2 bus configuration bits.", + "bit_offset": 9, + "bit_size": 1, + "enum": "APBLOCK" + }, + { + "name": "APB3LOCK", + "description": "Defines the lock protection of the APB3 bus configuration bits.", + "bit_offset": 10, + "bit_size": 1, + "enum": "APBLOCK" + }, + { + "name": "APB4LOCK", + "description": "Defines the lock protection of the APB4 bus configuration bits.", + "bit_offset": 11, + "bit_size": 1, + "enum": "APBLOCK" + }, + { + "name": "APB5LOCK", + "description": "Defines the lock protection of the APB5 bus configuration bits.", + "bit_offset": 12, + "bit_size": 1, + "enum": "APBLOCK" + }, + { + "name": "NOCLOCK", + "description": "Defines the lock protection of the NOC bus configuration bits.", + "bit_offset": 13, + "bit_size": 1, + "enum": "NOCLOCK" + } + ] + }, + "fieldset/LOCKCFGSR3": { + "description": "RCC system lock configuration register3.", + "fields": [ + { + "name": "MODLOCKS", + "description": "Defines the lock protection of the MOD configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SYSLOCKS", + "description": "Defines the lock protection of the SYS configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BUSLOCKS", + "description": "Defines the lock protection of the BUS configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PERLOCKS", + "description": "Defines the lock protection of the PER configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "INTLOCKS", + "description": "Defines the lock protection of the INT configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "RSTLOCKS", + "description": "Defines the lock protection of the RST configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DFTLOCKS", + "description": "Defines the lock protection of the DFT configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/LSECFGR": { + "description": "RCC LSE configuration register.", + "fields": [ + { + "name": "LSECSSON", + "description": "LSE clock security system (CSS) enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "LSECSSRA", + "description": "LSE clock security system (CSS) re-arm function.", + "bit_offset": 8, + "bit_size": 1, + "enum": "LSECSSRA" + }, + { + "name": "LSECSSD", + "description": "LSE clock security system (CSS) failure detection.", + "bit_offset": 9, + "bit_size": 1, + "enum": "LSECSSD" + }, + { + "name": "LSEBYP", + "description": "LSE clock bypass.", + "bit_offset": 15, + "bit_size": 1, + "enum": "LSEBYP" + }, + { + "name": "LSEEXT", + "description": "LSE clock type in Bypass mode.", + "bit_offset": 16, + "bit_size": 1, + "enum": "LSEEXT" + }, + { + "name": "LSEGFON", + "description": "LSE clock glitch filter enable.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "LSEDRV", + "description": "LSE oscillator driving capability.", + "bit_offset": 18, + "bit_size": 2, + "enum": "LSEDRV" + } + ] + }, + "fieldset/MEMENCR": { + "description": "RCC memory enable register.", + "fields": [ + { + "name": "AXISRAM3ENC", + "description": "AXISRAM3 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AXISRAM4ENC", + "description": "AXISRAM4 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AXISRAM5ENC", + "description": "AXISRAM5 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AXISRAM6ENC", + "description": "AXISRAM6 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHBSRAM1ENC", + "description": "AHBSRAM1 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHBSRAM2ENC", + "description": "AHBSRAM2 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "BKPSRAMENC", + "description": "BKPSRAM enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AXISRAM1ENC", + "description": "AXISRAM1 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AXISRAM2ENC", + "description": "AXISRAM2 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FLEXRAMENC", + "description": "FLEXRAM enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "NPUCACHERAMENC", + "description": "NPUCACHERAM enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "VENCRAMENC", + "description": "VENCRAM enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "BOOTROMENC", + "description": "BOOTROM enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/MEMENR": { + "description": "RCC memory enable register.", + "fields": [ + { + "name": "AXISRAM3EN", + "description": "AXISRAM3 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AXISRAM4EN", + "description": "AXISRAM4 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AXISRAM5EN", + "description": "AXISRAM5 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AXISRAM6EN", + "description": "AXISRAM6 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHBSRAM1EN", + "description": "AHBSRAM1 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHBSRAM2EN", + "description": "AHBSRAM2 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "BKPSRAMEN", + "description": "BKPSRAM enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AXISRAM1EN", + "description": "AXISRAM1 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AXISRAM2EN", + "description": "AXISRAM2 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FLEXRAMEN", + "description": "FLEXRAM enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "NPUCACHERAMEN", + "description": "NPUCACHERAM enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "VENCRAMEN", + "description": "VENCRAM enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "BOOTROMEN", + "description": "BOOTROM enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/MEMENSR": { + "description": "RCC memory enable register.", + "fields": [ + { + "name": "AXISRAM3ENS", + "description": "AXISRAM3 enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AXISRAM4ENS", + "description": "AXISRAM4 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AXISRAM5ENS", + "description": "AXISRAM5 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AXISRAM6ENS", + "description": "AXISRAM6 enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHBSRAM1ENS", + "description": "AHBSRAM1 enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHBSRAM2ENS", + "description": "AHBSRAM2 enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "BKPSRAMENS", + "description": "BKPSRAM enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AXISRAM1ENS", + "description": "AXISRAM1 enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AXISRAM2ENS", + "description": "AXISRAM2 enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FLEXRAMENS", + "description": "FLEXRAM enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "NPUCACHERAMENS", + "description": "NPUCACHERAM enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "VENCRAMENS", + "description": "VENCRAM enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "BOOTROMENS", + "description": "BOOTROM enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/MEMLPENCR": { + "description": "RCC memory Sleep enable register.", + "fields": [ + { + "name": "AXISRAM3LPENC", + "description": "AXISRAM3 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AXISRAM4LPENC", + "description": "AXISRAM4 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AXISRAM5LPENC", + "description": "AXISRAM5 sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AXISRAM6LPENC", + "description": "AXISRAM6 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHBSRAM1LPENC", + "description": "AHBSRAM1 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHBSRAM2LPENC", + "description": "AHBSRAM2 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "BKPSRAMLPENC", + "description": "BKPSRAM sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AXISRAM1LPENC", + "description": "AXISRAM1 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AXISRAM2LPENC", + "description": "AXISRAM2 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FLEXRAMLPENC", + "description": "FLEXRAM sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "NPUCACHERAMLPENC", + "description": "NPUCACHERAM sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "VENCRAMLPENC", + "description": "VENCRAM sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "BOOTROMLPENC", + "description": "BOOTROM sleep enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/MEMLPENR": { + "description": "RCC memory Sleep enable register.", + "fields": [ + { + "name": "AXISRAM3LPEN", + "description": "AXISRAM3 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AXISRAM4LPEN", + "description": "AXISRAM4 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AXISRAM5LPEN", + "description": "AXISRAM5 sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AXISRAM6LPEN", + "description": "AXISRAM6 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHBSRAM1LPEN", + "description": "AHBSRAM1 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHBSRAM2LPEN", + "description": "AHBSRAM2 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "BKPSRAMLPEN", + "description": "BKPSRAM sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AXISRAM1LPEN", + "description": "AXISRAM1 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AXISRAM2LPEN", + "description": "AXISRAM2 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FLEXRAMLPEN", + "description": "FLEXRAM sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "NPUCACHERAMLPEN", + "description": "NPUCACHERAM sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "VENCRAMLPEN", + "description": "VENCRAM sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "BOOTROMLPEN", + "description": "BOOTROM sleep enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/MEMLPENSR": { + "description": "RCC memory sleep enable register.", + "fields": [ + { + "name": "AXISRAM3LPENS", + "description": "AXISRAM3 sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AXISRAM4LPENS", + "description": "AXISRAM4 sleep enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AXISRAM5LPENS", + "description": "AXISRAM5 sleep enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AXISRAM6LPENS", + "description": "AXISRAM6 sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHBSRAM1LPENS", + "description": "AHBSRAM1 sleep enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHBSRAM2LPENS", + "description": "AHBSRAM2 sleep enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "BKPSRAMLPENS", + "description": "BKPSRAM sleep enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AXISRAM1LPENS", + "description": "AXISRAM1 sleep enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AXISRAM2LPENS", + "description": "AXISRAM2 sleep enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FLEXRAMLPENS", + "description": "FLEXRAM sleep enable.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "NPUCACHERAMLPENS", + "description": "NPUCACHERAM sleep enable.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "VENCRAMLPENS", + "description": "VENCRAM sleep enable.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "BOOTROMLPENS", + "description": "BOOTROM sleep enable.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/MEMRSTCR": { + "description": "RCC memory reset register.", + "fields": [ + { + "name": "AXISRAM3RSTC", + "description": "AXISRAM3 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AXISRAM4RSTC", + "description": "AXISRAM4 reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AXISRAM5RSTC", + "description": "AXISRAM5 reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AXISRAM6RSTC", + "description": "AXISRAM6 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHBSRAM1RSTC", + "description": "AHBSRAM1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHBSRAM2RSTC", + "description": "AHBSRAM2 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AXISRAM1RSTC", + "description": "AXISRAM1 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AXISRAM2RSTC", + "description": "AXISRAM2 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FLEXRAMRSTC", + "description": "FLEXRAM reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "NPUCACHERAMRSTC", + "description": "NPUCACHERAM reset.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "VENCRAMRSTC", + "description": "VENCRAM reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "BOOTROMRSTC", + "description": "BOOTROM reset.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/MEMRSTR": { + "description": "RCC memories reset register.", + "fields": [ + { + "name": "AXISRAM3RST", + "description": "AXISRAM3 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AXISRAM4RST", + "description": "AXISRAM4reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AXISRAM5RST", + "description": "AXISRAM5 reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AXISRAM6RST", + "description": "AXISRAM6 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHBSRAM1RST", + "description": "AHBSRAM1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHBSRAM2RST", + "description": "AHBSRAM2 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AXISRAM1RST", + "description": "AXISRAM1 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AXISRAM2RST", + "description": "AXISRAM2 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FLEXRAMRST", + "description": "FLEXRAM reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "NPUCACHERAMRST", + "description": "NPUCACHERAM reset.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "VENCRAMRST", + "description": "VENCRAM reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "BOOTROMRST", + "description": "BOOTROM reset.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/MEMRSTSR": { + "description": "RCC memory reset register.", + "fields": [ + { + "name": "AXISRAM3RSTS", + "description": "AXISRAM3 reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AXISRAM4RSTS", + "description": "AXISRAM4 reset.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AXISRAM5RSTS", + "description": "AXISRAM5 reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AXISRAM6RSTS", + "description": "AXISRAM6 reset.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHBSRAM1RSTS", + "description": "AHBSRAM1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHBSRAM2RSTS", + "description": "AHBSRAM2 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AXISRAM1RSTS", + "description": "AXISRAM1 reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AXISRAM2RSTS", + "description": "AXISRAM2 reset.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FLEXRAMRSTS", + "description": "FLEXRAM reset.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "NPUCACHERAMRSTS", + "description": "NPUCACHERAM reset.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "VENCRAMRSTS", + "description": "VENCRAM reset.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "BOOTROMRSTS", + "description": "BOOTROM reset.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/MISCENCR": { + "description": "RCC miscellaneous enable register.", + "fields": [ + { + "name": "DBGENC", + "description": "DBG enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MCO1ENC", + "description": "MCO1 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MCO2ENC", + "description": "MCO2 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "XSPIPHYCOMPENC", + "description": "XSPIPHYCOMP enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PERENC", + "description": "PER enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/MISCENR": { + "description": "RCC miscellaneous configuration enable register.", + "fields": [ + { + "name": "DBGEN", + "description": "DBG enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MCO1EN", + "description": "MCO1 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MCO2EN", + "description": "MCO2 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "XSPIPHYCOMPEN", + "description": "XSPIPHYCOMP enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PEREN", + "description": "PER enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/MISCENSR": { + "description": "RCC miscellaneous enable register.", + "fields": [ + { + "name": "DBGENS", + "description": "DBG enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MCO1ENS", + "description": "MCO1 enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MCO2ENS", + "description": "MCO2 enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "XSPIPHYCOMPENS", + "description": "XSPIPHYCOMP enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PERENS", + "description": "PER enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/MISCLPENCR": { + "description": "RCC miscellaneous Sleep enable register.", + "fields": [ + { + "name": "DBGLPENC", + "description": "DBG sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "XSPIPHYCOMPLPENC", + "description": "XSPIPHYCOMP sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PERLPENC", + "description": "PER sleep enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/MISCLPENR": { + "description": "RCC miscellaneous configurations Sleep enable register.", + "fields": [ + { + "name": "DBGLPEN", + "description": "DBG sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "XSPIPHYCOMPLPEN", + "description": "XSPIPHYCOMP sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PERLPEN", + "description": "PER sleep enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/MISCLPENSR": { + "description": "RCC miscellaneous Sleep enable register.", + "fields": [ + { + "name": "DBGLPENS", + "description": "DBG sleep enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "XSPIPHYCOMPLPENS", + "description": "XSPIPHYCOMP sleep enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "PERLPENS", + "description": "PER sleep enable.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/MISCRSTCR": { + "description": "RCC miscellaneous reset register.", + "fields": [ + { + "name": "DBGRSTC", + "description": "DBG reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "XSPIPHY1RSTC", + "description": "XSPIPHY1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPIPHY2RSTC", + "description": "XSPIPHY2 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "SDMMC1DLLRSTC", + "description": "SDMMC1DLL reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC2DLLRSTC", + "description": "SDMMC2DLL reset.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/MISCRSTR": { + "description": "RCC miscellaneous configurations reset register.", + "fields": [ + { + "name": "DBGRST", + "description": "DBG reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "XSPIPHY1RST", + "description": "XSPIPHY1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPIPHY2RST", + "description": "XSPIPHY2 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "SDMMC1DLLRST", + "description": "SDMMC1DLL reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC2DLLRST", + "description": "SDMMC2DLL reset.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/MISCRSTSR": { + "description": "RCC miscellaneous reset register.", + "fields": [ + { + "name": "DBGRSTS", + "description": "DBG reset.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "XSPIPHY1RSTS", + "description": "XSPIPHY1 reset.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "XSPIPHY2RSTS", + "description": "XSPIPHY2 reset.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "SDMMC1DLLRSTS", + "description": "SDMMC1DLL reset.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "SDMMC2DLLRSTS", + "description": "SDMMC2DLL reset.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/MSICFGR": { + "description": "RCC MSI configuration register.", + "fields": [ + { + "name": "MSIFREQSEL", + "description": "MSI oscillator frequency select.", + "bit_offset": 9, + "bit_size": 1, + "enum": "MSIFREQSEL" + }, + { + "name": "MSITRIM", + "description": "MSI clock trimming.", + "bit_offset": 16, + "bit_size": 5 + }, + { + "name": "MSICAL", + "description": "MSI clock calibration.", + "bit_offset": 23, + "bit_size": 8 + } + ] + }, + "fieldset/PLL1CFGR1": { + "description": "RCC PLL1 configuration register 1.", + "fields": [ + { + "name": "PLLDIVN", + "description": "PLL1 Integer part for the VCO multiplication factor.", + "bit_offset": 8, + "bit_size": 12, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLDIVM", + "description": "PLL1 reference input clock divide frequency ratio.", + "bit_offset": 20, + "bit_size": 6, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLDIVM" + }, + { + "name": "PLLBYP", + "description": "PLL1 bypass.", + "bit_offset": 27, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLBYP" + }, + { + "name": "PLLSEL", + "description": "PLL1 source selection of the reference clock.", + "bit_offset": 28, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLSEL" + } + ] + }, + "fieldset/PLL1CFGR2": { + "description": "RCC PLL1 configuration register 2.", + "fields": [ + { + "name": "PLLDIVNFRAC", + "description": "PLL1 Fractional part of the VCO multiplication factor.", + "bit_offset": 0, + "bit_size": 24, + "array": { + "len": 1, + "stride": 0 + } + } + ] + }, + "fieldset/PLL1CFGR3": { + "description": "RCC PLL1 configuration register 3.", + "fields": [ + { + "name": "PLLMODSSRST", + "description": "PLL1 Modulation Spread Spectrum reset.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLDACEN", + "description": "PLL1 noise canceling DAC enable in fractional mode.", + "bit_offset": 1, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSSDIS", + "description": "PLL1 Modulation Spread-Spectrum Disable.", + "bit_offset": 2, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLMODSSDIS" + }, + { + "name": "PLLMODDSEN", + "description": "PLL1 Modulation Spread-Spectrum (and Fractional Divide) enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSPRDW", + "description": "PLL1 Modulation Spread-Spectrum Down.", + "bit_offset": 4, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLMODSPRDW" + }, + { + "name": "PLLMODDIV", + "description": "PLL1 Modulation Division frequency adjustment.", + "bit_offset": 8, + "bit_size": 4, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSPR", + "description": "PLL1 Modulation Spread depth adjustment.", + "bit_offset": 16, + "bit_size": 5, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLPDIV2", + "description": "PLL1 VCO frequency divider level 2.", + "bit_offset": 24, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLPDIV" + }, + { + "name": "PLLPDIV1", + "description": "PLL1 VCO frequency divider level 1.", + "bit_offset": 27, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLPDIV" + }, + { + "name": "PLLPDIVEN", + "description": "PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable.", + "bit_offset": 30, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + } + ] + }, + "fieldset/PLL2CFGR1": { + "description": "RCC PLL2 configuration register 1.", + "fields": [ + { + "name": "PLLDIVN", + "description": "PLL2 Integer part for the VCO multiplication factor.", + "bit_offset": 8, + "bit_size": 12, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLDIVM", + "description": "PLL2 reference input clock divide frequency ratio.", + "bit_offset": 20, + "bit_size": 6, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLDIVM" + }, + { + "name": "PLLBYP", + "description": "PLL2 bypass.", + "bit_offset": 27, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLBYP" + }, + { + "name": "PLLSEL", + "description": "PLL2 source selection of the reference clock.", + "bit_offset": 28, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLSEL" + } + ] + }, + "fieldset/PLL2CFGR2": { + "description": "RCC PLL2 configuration register 2.", + "fields": [ + { + "name": "PLLDIVNFRAC", + "description": "PLL2 Fractional part of the VCO multiplication factor.", + "bit_offset": 0, + "bit_size": 24, + "array": { + "len": 1, + "stride": 0 + } + } + ] + }, + "fieldset/PLL2CFGR3": { + "description": "RCC PLL2 configuration register 3.", + "fields": [ + { + "name": "PLLMODSSRST", + "description": "PLL2 Modulation Spread Spectrum reset.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLDACEN", + "description": "PLL2 noise canceling DAC enable in fractional mode.", + "bit_offset": 1, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSSDIS", + "description": "PLL2 Modulation Spread-Spectrum Disable.", + "bit_offset": 2, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLMODSSDIS" + }, + { + "name": "PLLMODDSEN", + "description": "PLL2 Modulation Spread-Spectrum (and Fractional Divide) enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSPRDW", + "description": "PLL2 Modulation Down Spread.", + "bit_offset": 4, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLMODSPRDW" + }, + { + "name": "PLLMODDIV", + "description": "PLL2 Modulation Division frequency adjustment.", + "bit_offset": 8, + "bit_size": 4, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSPR", + "description": "PLL2 Modulation Spread depth adjustment.", + "bit_offset": 16, + "bit_size": 5, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLPDIV2", + "description": "PLL2 VCO frequency divider level 2.", + "bit_offset": 24, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLPDIV" + }, + { + "name": "PLLPDIV1", + "description": "PLL2 VCO frequency divider level 1.", + "bit_offset": 27, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLPDIV" + }, + { + "name": "PLLPDIVEN", + "description": "PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable.", + "bit_offset": 30, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + } + ] + }, + "fieldset/PLL3CFGR1": { + "description": "RCC PLL3 configuration register 1.", + "fields": [ + { + "name": "PLLDIVN", + "description": "PLL3 Integer part for the VCO multiplication factor.", + "bit_offset": 8, + "bit_size": 12, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLDIVM", + "description": "PLL3 reference input clock divide frequency ratio.", + "bit_offset": 20, + "bit_size": 6, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLDIVM" + }, + { + "name": "PLLBYP", + "description": "PLL3 bypass.", + "bit_offset": 27, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLBYP" + }, + { + "name": "PLLSEL", + "description": "PLL3 source selection of the reference clock.", + "bit_offset": 28, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLSEL" + } + ] + }, + "fieldset/PLL3CFGR2": { + "description": "RCC PLL3 configuration register 2.", + "fields": [ + { + "name": "PLLDIVNFRAC", + "description": "PLL3 Fractional part of the VCO multiplication factor.", + "bit_offset": 0, + "bit_size": 24, + "array": { + "len": 1, + "stride": 0 + } + } + ] + }, + "fieldset/PLL3CFGR3": { + "description": "RCC PLL3 configuration register 3.", + "fields": [ + { + "name": "PLLMODSSRST", + "description": "PLL3 Modulation Spread Spectrum reset.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLDACEN", + "description": "PLL3 noise canceling DAC enable in fractional mode.", + "bit_offset": 1, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSSDIS", + "description": "PLL3 Modulation Spread-Spectrum Disable.", + "bit_offset": 2, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLMODSSDIS" + }, + { + "name": "PLLMODDSEN", + "description": "PLL3 Modulation Spread-Spectrum (and Fractional Divide) enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSPRDW", + "description": "PLL3 Modulation Down Spread.", + "bit_offset": 4, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLMODSPRDW" + }, + { + "name": "PLLMODDIV", + "description": "PLL3 Modulation Division frequency adjustment.", + "bit_offset": 8, + "bit_size": 4, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSPR", + "description": "PLL3 Modulation Spread depth adjustment.", + "bit_offset": 16, + "bit_size": 5, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLPDIV2", + "description": "PLL3 VCO frequency divider level 2.", + "bit_offset": 24, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLPDIV" + }, + { + "name": "PLLPDIV1", + "description": "PLL3 VCO frequency divider level 1.", + "bit_offset": 27, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLPDIV" + }, + { + "name": "PLLPDIVEN", + "description": "PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable.", + "bit_offset": 30, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + } + ] + }, + "fieldset/PLL4CFGR1": { + "description": "RCC PLL4 configuration register 1.", + "fields": [ + { + "name": "PLLDIVN", + "description": "PLL4 Integer part for the VCO multiplication factor.", + "bit_offset": 8, + "bit_size": 12, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLDIVM", + "description": "PLL4 reference input clock divide frequency ratio.", + "bit_offset": 20, + "bit_size": 6, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLDIVM" + }, + { + "name": "PLLBYP", + "description": "PLL4 bypass.", + "bit_offset": 27, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLBYP" + }, + { + "name": "PLLSEL", + "description": "PLL4 source selection of the reference clock.", + "bit_offset": 28, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLSEL" + } + ] + }, + "fieldset/PLL4CFGR2": { + "description": "RCC PLL4 configuration register 2.", + "fields": [ + { + "name": "PLLDIVNFRAC", + "description": "PLL4 Fractional part of the VCO multiplication factor.", + "bit_offset": 0, + "bit_size": 24, + "array": { + "len": 1, + "stride": 0 + } + } + ] + }, + "fieldset/PLL4CFGR3": { + "description": "RCC PLL4 configuration register 3.", + "fields": [ + { + "name": "PLLMODSSRST", + "description": "PLL4 Modulation Spread Spectrum reset.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLDACEN", + "description": "PLL4 noise canceling DAC enable in fractional mode.", + "bit_offset": 1, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSSDIS", + "description": "PLL4 Modulation Spread-Spectrum Disable.", + "bit_offset": 2, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLMODSSDIS" + }, + { + "name": "PLLMODDSEN", + "description": "PLL4 Modulation Spread-Spectrum (and Fractional Divide) enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSPRDW", + "description": "PLL4 Modulation Down Spread.", + "bit_offset": 4, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLMODSPRDW" + }, + { + "name": "PLLMODDIV", + "description": "PLL4 Modulation Division frequency adjustment.", + "bit_offset": 8, + "bit_size": 4, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLMODSPR", + "description": "PLL4 Modulation Spread depth adjustment.", + "bit_offset": 16, + "bit_size": 5, + "array": { + "len": 1, + "stride": 0 + } + }, + { + "name": "PLLPDIV2", + "description": "PLL4 VCO frequency divider level 2.", + "bit_offset": 24, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLPDIV" + }, + { + "name": "PLLPDIV1", + "description": "PLL4 VCO frequency divider level 1.", + "bit_offset": 27, + "bit_size": 3, + "array": { + "len": 1, + "stride": 0 + }, + "enum": "PLLPDIV" + }, + { + "name": "PLLPDIVEN", + "description": "PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable.", + "bit_offset": 30, + "bit_size": 1, + "array": { + "len": 1, + "stride": 0 + } + } + ] + }, + "fieldset/PRIVCFGCR0": { + "description": "RCC oscillator privilege configuration register0.", + "fields": [ + { + "name": "LSIPVC", + "description": "Defines the privilege protection of the LSI configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "LSEPVC", + "description": "Defines the privilege protection of the LSE configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MSIPVC", + "description": "Defines the privilege protection of the MSI configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "HSIPVC", + "description": "Defines the privilege protection of the HSI configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "HSEPVC", + "description": "Defines the privilege protection of the HSE configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/PRIVCFGCR1": { + "description": "RCC PLL privilege configuration register1.", + "fields": [ + { + "name": "PLLPVC", + "description": "Defines the privilege protection of the PLL1 configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } + } + ] + }, + "fieldset/PRIVCFGCR2": { + "description": "RCC divider privilege configuration register2.", + "fields": [ + { + "name": "IC1PVC", + "description": "Defines the privilege protection of the IC1 configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "IC2PVC", + "description": "Defines the privilege protection of the IC2 configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "IC3PVC", + "description": "Defines the privilege protection of the IC3 configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "IC4PVC", + "description": "Defines the privilege protection of the IC4 configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "IC5PVC", + "description": "Defines the privilege protection of the IC5 configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "IC6PVC", + "description": "Defines the privilege protection of the IC6 configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "IC7PVC", + "description": "Defines the privilege protection of the IC7 configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "IC8PVC", + "description": "Defines the privilege protection of the IC8 configuration bits (enable, ready, divider).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "IC9PVC", + "description": "Defines the privilege protection of the IC9 configuration bits (enable, ready, divider).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IC10PVC", + "description": "Defines the privilege protection of the IC10 configuration bits (enable, ready, divider).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IC11PVC", + "description": "Defines the privilege protection of the IC11 configuration bits (enable, ready, divider).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "IC12PVC", + "description": "Defines the privilege protection of the IC12 configuration bits (enable, ready, divider).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "IC13PVC", + "description": "Defines the privilege protection of the IC13 configuration bits (enable, ready, divider).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "IC14PVC", + "description": "Defines the privilege protection of the IC14 configuration bits (enable, ready, divider).", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "IC15PVC", + "description": "Defines the privilege protection of the IC15 configuration bits (enable, ready, divider).", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IC16PVC", + "description": "Defines the privilege protection of the IC16 configuration bits (enable, ready, divider).", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "IC17PVC", + "description": "Defines the privilege protection of the IC17 configuration bits (enable, ready, divider).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IC18PVC", + "description": "Defines the privilege protection of the IC18 configuration bits (enable, ready, divider).", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IC19PVC", + "description": "Defines the privilege protection of the IC19 configuration bits (enable, ready, divider).", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "IC20PVC", + "description": "Defines the privilege protection of the IC20 configuration bits (enable, ready, divider).", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/PRIVCFGCR3": { + "description": "RCC system privilege configuration register3.", + "fields": [ + { + "name": "MODPVC", + "description": "Defines the privilege protection of the MOD configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SYSPVC", + "description": "Defines the privilege protection of the SYS configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BUSPVC", + "description": "Defines the privilege protection of the BUS configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PERPVC", + "description": "Defines the privilege protection of the PER configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "INTPVC", + "description": "Defines the privilege protection of the INT configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "RSTPVC", + "description": "Defines the privilege protection of the RST configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DFTPVC", + "description": "Defines the privilege protection of the DFT configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/PRIVCFGCR4": { + "description": "RCC privilege configuration register4.", + "fields": [ + { + "name": "ACLKNPVC", + "description": "Defines the privilege protection of the ACLKN configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACLKNCPVC", + "description": "Defines the privilege protection of the ACLKNC configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AHBMPVC", + "description": "Defines the privilege protection of the AHBM configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1PVC", + "description": "Defines the privilege protection of the AHB1 configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2PVC", + "description": "Defines the privilege protection of the AHB2 configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3PVC", + "description": "Defines the privilege protection of the AHB3 configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4PVC", + "description": "Defines the privilege protection of the AHB4 configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5PVC", + "description": "Defines the privilege protection of the AHB5 configuration bits (enable, ready, divider).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1PVC", + "description": "Defines the privilege protection of the APB1 configuration bits (enable, ready, divider).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2PVC", + "description": "Defines the privilege protection of the APB2 configuration bits (enable, ready, divider).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3PVC", + "description": "Defines the privilege protection of the APB3 configuration bits (enable, ready, divider).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4PVC", + "description": "Defines the privilege protection of the APB4 configuration bits (enable, ready, divider).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5PVC", + "description": "Defines the privilege protection of the APB5 configuration bits (enable, ready, divider).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "NOCPVC", + "description": "Defines the privilege protection of the NOC configuration bits (enable, ready, divider).", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/PRIVCFGR0": { + "description": "RCC oscillator privilege configuration register0.", + "fields": [ + { + "name": "LSIPV", + "description": "Defines the privilege protection of the LSI oscillator configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "LSIPV" + }, + { + "name": "LSEPV", + "description": "Defines the privilege protection of the LSE oscillator configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "LSEPV" + }, + { + "name": "MSIPV", + "description": "Defines the privilege protection of the MSI oscillator configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "MSIPV" + }, + { + "name": "HSIPV", + "description": "Defines the privilege protection of the HSI oscillator configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "HSIPV" + }, + { + "name": "HSEPV", + "description": "Defines the privilege protection of the HSE oscillator configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "HSEPV" + } + ] + }, + "fieldset/PRIVCFGR1": { + "description": "RCC PLL privilege configuration register1.", + "fields": [ + { + "name": "PLLPV", + "description": "Defines the privilege protection of the PLL1 PLL configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + }, + "enum": "PLLPV" + } + ] + }, + "fieldset/PRIVCFGR2": { + "description": "RCC divider privilege configuration register2.", + "fields": [ + { + "name": "IC1PV", + "description": "Defines the privilege protection of the IC1 divider configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC2PV", + "description": "Defines the privilege protection of the IC2 divider configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC3PV", + "description": "Defines the privilege protection of the IC3 divider configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC4PV", + "description": "Defines the privilege protection of the IC4 divider configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC5PV", + "description": "Defines the privilege protection of the IC5 divider configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC6PV", + "description": "Defines the privilege protection of the IC6 divider configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC7PV", + "description": "Defines the privilege protection of the IC7 divider configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC8PV", + "description": "Defines the privilege protection of the IC8 divider configuration bits.", + "bit_offset": 7, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC9PV", + "description": "Defines the privilege protection of the IC9 divider configuration bits.", + "bit_offset": 8, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC10PV", + "description": "Defines the privilege protection of the IC10 divider configuration bits.", + "bit_offset": 9, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC11PV", + "description": "Defines the privilege protection of the IC11 divider configuration bits.", + "bit_offset": 10, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC12PV", + "description": "Defines the privilege protection of the IC12 divider configuration bits.", + "bit_offset": 11, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC13PV", + "description": "Defines the privilege protection of the IC13 divider configuration bits.", + "bit_offset": 12, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC14PV", + "description": "Defines the privilege protection of the IC14 divider configuration bits.", + "bit_offset": 13, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC15PV", + "description": "Defines the privilege protection of the IC15 divider configuration bits.", + "bit_offset": 14, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC16PV", + "description": "Defines the privilege protection of the IC16 divider configuration bits.", + "bit_offset": 15, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC17PV", + "description": "Defines the privilege protection of the IC17 divider configuration bits.", + "bit_offset": 16, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC18PV", + "description": "Defines the privilege protection of the IC18 divider configuration bits.", + "bit_offset": 17, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC19PV", + "description": "Defines the privilege protection of the IC19 divider configuration bits.", + "bit_offset": 18, + "bit_size": 1, + "enum": "ICPV" + }, + { + "name": "IC20PV", + "description": "Defines the privilege protection of the IC20 divider configuration bits.", + "bit_offset": 19, + "bit_size": 1, + "enum": "ICPV" + } + ] + }, + "fieldset/PRIVCFGR3": { + "description": "RCC system privilege configuration register3.", + "fields": [ + { + "name": "MODPV", + "description": "Defines the privilege protection of the MOD system configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "MODPV" + }, + { + "name": "SYSPV", + "description": "Defines the privilege protection of the SYS system configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "SYSPV" + }, + { + "name": "BUSPV", + "description": "Defines the privilege protection of the BUS system configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "BUSPV" + }, + { + "name": "PERPV", + "description": "Defines the privilege protection of the PER system configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "PERPV" + }, + { + "name": "INTPV", + "description": "Defines the privilege protection of the INT system configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "INTPV" + }, + { + "name": "RSTPV", + "description": "Defines the privilege protection of the RST system configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "RSTPV" + }, + { + "name": "DFTPV", + "description": "Defines the privilege protection of the DFT system configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "DFTPV" + } + ] + }, + "fieldset/PRIVCFGR4": { + "description": "RCC bus privilege configuration register4.", + "fields": [ + { + "name": "ACLKNPV", + "description": "Defines the privilege protection of the ACLKN bus configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ACLKNPV" + }, + { + "name": "ACLKNCPV", + "description": "Defines the privilege protection of the ACLKNC bus configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "ACLKNCPV" + }, + { + "name": "AHBMPV", + "description": "Defines the privilege protection of the AHBM bus configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "AHBMPV" + }, + { + "name": "AHB1PV", + "description": "Defines the privilege protection of the AHB1 bus configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "AHBPV" + }, + { + "name": "AHB2PV", + "description": "Defines the privilege protection of the AHB2 bus configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "AHBPV" + }, + { + "name": "AHB3PV", + "description": "Defines the privilege protection of the AHB3 bus configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "AHBPV" + }, + { + "name": "AHB4PV", + "description": "Defines the privilege protection of the AHB4 bus configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "AHBPV" + }, + { + "name": "AHB5PV", + "description": "Defines the privilege protection of the AHB5 bus configuration bits.", + "bit_offset": 7, + "bit_size": 1, + "enum": "AHBPV" + }, + { + "name": "APB1PV", + "description": "Defines the privilege protection of the APB1 bus configuration bits.", + "bit_offset": 8, + "bit_size": 1, + "enum": "APBPV" + }, + { + "name": "APB2PV", + "description": "Defines the privilege protection of the APB2 bus configuration bits.", + "bit_offset": 9, + "bit_size": 1, + "enum": "APBPV" + }, + { + "name": "APB3PV", + "description": "Defines the privilege protection of the APB3 bus configuration bits.", + "bit_offset": 10, + "bit_size": 1, + "enum": "APBPV" + }, + { + "name": "APB4PV", + "description": "Defines the privilege protection of the APB4 bus configuration bits.", + "bit_offset": 11, + "bit_size": 1, + "enum": "APBPV" + }, + { + "name": "APB5PV", + "description": "Defines the privilege protection of the APB5 bus configuration bits.", + "bit_offset": 12, + "bit_size": 1, + "enum": "APBPV" + }, + { + "name": "NOCPV", + "description": "Defines the privilege protection of the NOC bus configuration bits.", + "bit_offset": 13, + "bit_size": 1, + "enum": "NOCPV" + } + ] + }, + "fieldset/PRIVCFGSR0": { + "description": "RCC oscillator privilege configuration register0.", + "fields": [ + { + "name": "LSIPVS", + "description": "Defines the privilege protection of the LSI configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "LSEPVS", + "description": "Defines the privilege protection of the LSE configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MSIPVS", + "description": "Defines the privilege protection of the MSI configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "HSIPVS", + "description": "Defines the privilege protection of the HSI configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "HSEPVS", + "description": "Defines the privilege protection of the HSE configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/PRIVCFGSR1": { + "description": "RCC PLL privilege configuration register1.", + "fields": [ + { + "name": "PLLPVS", + "description": "Defines the privilege protection of the PLL1 configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } + } + ] + }, + "fieldset/PRIVCFGSR2": { + "description": "RCC divider privilege configuration register2.", + "fields": [ + { + "name": "IC1PVS", + "description": "Defines the privilege protection of the IC1 configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "IC2PVS", + "description": "Defines the privilege protection of the IC2 configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "IC3PVS", + "description": "Defines the privilege protection of the IC3 configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "IC4PVS", + "description": "Defines the privilege protection of the IC4 configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "IC5PVS", + "description": "Defines the privilege protection of the IC5 configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "IC6PVS", + "description": "Defines the privilege protection of the IC6 configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "IC7PVS", + "description": "Defines the privilege protection of the IC7 configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "IC8PVS", + "description": "Defines the privilege protection of the IC8 configuration bits (enable, ready, divider).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "IC9PVS", + "description": "Defines the privilege protection of the IC9 configuration bits (enable, ready, divider).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IC10PVS", + "description": "Defines the privilege protection of the IC10 configuration bits (enable, ready, divider).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IC11PVS", + "description": "Defines the privilege protection of the IC11 configuration bits (enable, ready, divider).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "IC12PVS", + "description": "Defines the privilege protection of the IC12 configuration bits (enable, ready, divider).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "IC13PVS", + "description": "Defines the privilege protection of the IC13 configuration bits (enable, ready, divider).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "IC14PVS", + "description": "Defines the privilege protection of the IC14 configuration bits (enable, ready, divider).", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "IC15PVS", + "description": "Defines the privilege protection of the IC15 configuration bits (enable, ready, divider).", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IC16PVS", + "description": "Defines the privilege protection of the IC16 configuration bits (enable, ready, divider).", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "IC17PVS", + "description": "Defines the privilege protection of the IC17 configuration bits (enable, ready, divider).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IC18PVS", + "description": "Defines the privilege protection of the IC18 configuration bits (enable, ready, divider).", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IC19PVS", + "description": "Defines the privilege protection of the IC19 configuration bits (enable, ready, divider).", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "IC20PVS", + "description": "Defines the privilege protection of the IC20 configuration bits (enable, ready, divider).", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/PRIVCFGSR3": { + "description": "RCC system privilege configuration register3.", + "fields": [ + { + "name": "MODPVS", + "description": "Defines the privilege protection of the MOD configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SYSPVS", + "description": "Defines the privilege protection of the SYS configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BUSPVS", + "description": "Defines the privilege protection of the BUS configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PERPVS", + "description": "Defines the privilege protection of the PER configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "INTPVS", + "description": "Defines the privilege protection of the INT configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "RSTPVS", + "description": "Defines the privilege protection of the RST configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DFTPVS", + "description": "Defines the privilege protection of the DFT configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/PRIVCFGSR4": { + "description": "RCC privilege configuration register4.", + "fields": [ + { + "name": "ACLKNPVS", + "description": "Defines the privilege protection of the ACLKN configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACLKNCPVS", + "description": "Defines the privilege protection of the ACLKNC configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AHBMPVS", + "description": "Defines the privilege protection of the AHBM configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1PVS", + "description": "Defines the privilege protection of the AHB1 configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2PVS", + "description": "Defines the privilege protection of the AHB2 configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3PVS", + "description": "Defines the privilege protection of the AHB3 configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4PVS", + "description": "Defines the privilege protection of the AHB4 configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5PVS", + "description": "Defines the privilege protection of the AHB5 configuration bits (enable, ready, divider).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1PVS", + "description": "Defines the privilege protection of the APB1 configuration bits (enable, ready, divider).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2PVS", + "description": "Defines the privilege protection of the APB2 configuration bits (enable, ready, divider).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3PVS", + "description": "Defines the privilege protection of the APB3 configuration bits (enable, ready, divider).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4PVS", + "description": "Defines the privilege protection of the APB4 configuration bits (enable, ready, divider).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5PVS", + "description": "Defines the privilege protection of the APB5 configuration bits (enable, ready, divider).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "NOCPVS", + "description": "Defines the privilege protection of the NOC configuration bits (enable, ready, divider).", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/PUBCFGCR0": { + "description": "RCC oscillator public configuration register0.", + "fields": [ + { + "name": "LSIPUBC", + "description": "Defines the public protection of the LSI configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "LSEPUBC", + "description": "Defines the public protection of the LSE configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MSIPUBC", + "description": "Defines the public protection of the MSI configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "HSIPUBC", + "description": "Defines the public protection of the HSI configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "HSEPUBC", + "description": "Defines the public protection of the HSE configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/PUBCFGCR1": { + "description": "RCC PLL public configuration register1.", + "fields": [ + { + "name": "PLLPUBC", + "description": "Defines the public protection of the PLL1 configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } + } + ] + }, + "fieldset/PUBCFGCR2": { + "description": "RCC divider public configuration register2.", + "fields": [ + { + "name": "IC1PUBC", + "description": "Defines the public protection of the IC1 configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "IC2PUBC", + "description": "Defines the public protection of the IC2 configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "IC3PUBC", + "description": "Defines the public protection of the IC3 configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "IC4PUBC", + "description": "Defines the public protection of the IC4 configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "IC5PUBC", + "description": "Defines the public protection of the IC5 configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "IC6PUBC", + "description": "Defines the public protection of the IC6 configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "IC7PUBC", + "description": "Defines the public protection of the IC7 configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "IC8PUBC", + "description": "Defines the public protection of the IC8 configuration bits (enable, ready, divider).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "IC9PUBC", + "description": "Defines the public protection of the IC9 configuration bits (enable, ready, divider).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IC10PUBC", + "description": "Defines the public protection of the IC10 configuration bits (enable, ready, divider).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IC11PUBC", + "description": "Defines the public protection of the IC11 configuration bits (enable, ready, divider).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "IC12PUBC", + "description": "Defines the public protection of the IC12 configuration bits (enable, ready, divider).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "IC13PUBC", + "description": "Defines the public protection of the IC13 configuration bits (enable, ready, divider).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "IC14PUBC", + "description": "Defines the public protection of the IC14 configuration bits (enable, ready, divider).", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "IC15PUBC", + "description": "Defines the public protection of the IC15 configuration bits (enable, ready, divider).", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IC16PUBC", + "description": "Defines the public protection of the IC16 configuration bits (enable, ready, divider).", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "IC17PUBC", + "description": "Defines the public protection of the IC17 configuration bits (enable, ready, divider).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IC18PUBC", + "description": "Defines the public protection of the IC18 configuration bits (enable, ready, divider).", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IC19PUBC", + "description": "Defines the public protection of the IC19 configuration bits (enable, ready, divider).", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "IC20PUBC", + "description": "Defines the public protection of the IC20 configuration bits (enable, ready, divider).", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/PUBCFGCR3": { + "description": "RCC system public configuration register3.", + "fields": [ + { + "name": "MODPUBC", + "description": "Defines the public protection of the MOD configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SYSPUBC", + "description": "Defines the public protection of the SYS configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BUSPUBC", + "description": "Defines the public protection of the BUS configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PERPUBC", + "description": "Defines the public protection of the PER configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "INTPUBC", + "description": "Defines the public protection of the INT configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "RSTPUBC", + "description": "Defines the public protection of the RST configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DFTPUBC", + "description": "Defines the public protection of the DFT configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/PUBCFGCR4": { + "description": "RCC public configuration register4.", + "fields": [ + { + "name": "ACLKNPUBC", + "description": "Defines the public protection of the ACLKN configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACLKNCPUBC", + "description": "Defines the public protection of the ACLKNC configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AHBMPUBC", + "description": "Defines the public protection of the AHBM configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1PUBC", + "description": "Defines the public protection of the AHB1 configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2PUBC", + "description": "Defines the public protection of the AHB2 configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3PUBC", + "description": "Defines the public protection of the AHB3 configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4PUBC", + "description": "Defines the public protection of the AHB4 configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5PUBC", + "description": "Defines the public protection of the AHB5 configuration bits (enable, ready, divider).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1PUBC", + "description": "Defines the public protection of the APB1 configuration bits (enable, ready, divider).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2PUBC", + "description": "Defines the public protection of the APB2 configuration bits (enable, ready, divider).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3PUBC", + "description": "Defines the public protection of the APB3 configuration bits (enable, ready, divider).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4PUBC", + "description": "Defines the public protection of the APB4 configuration bits (enable, ready, divider).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5PUBC", + "description": "Defines the public protection of the APB5 configuration bits (enable, ready, divider).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "NOCPUBC", + "description": "Defines the public protection of the NOC configuration bits (enable, ready, divider).", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/PUBCFGCR5": { + "description": "RCC public configuration register4.", + "fields": [ + { + "name": "AXISRAM3PUBC", + "description": "Defines the public protection of the AXISRAM3 configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AXISRAM4PUBC", + "description": "Defines the public protection of the AXISRAM4 configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AXISRAM5PUBC", + "description": "Defines the public protection of the AXISRAM5 configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AXISRAM6PUBC", + "description": "Defines the public protection of the AXISRAM6 configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHBSRAM1PUBC", + "description": "Defines the public protection of the AHBSRAM1 configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHBSRAM2PUBC", + "description": "Defines the public protection of the AHBSRAM2 configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "BKPSRAMPUBC", + "description": "Defines the public protection of the BKPSRAM configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AXISRAM1PUBC", + "description": "Defines the public protection of the AXISRAM1 configuration bits (enable, ready, divider).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AXISRAM2PUBC", + "description": "Defines the public protection of the AXISRAM2 configuration bits (enable, ready, divider).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FLEXRAMPUBC", + "description": "Defines the public protection of the FLEXRAM configuration bits (enable, ready, divider).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "CACHEAXIRAMPUBC", + "description": "Defines the public protection of the NPUCACHERAM configuration bits (enable, ready, divider).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "VENCRAMPUBC", + "description": "Defines the public protection of the VENCRAM configuration bits (enable, ready, divider).", + "bit_offset": 11, + "bit_size": 1 + } + ] + }, + "fieldset/PUBCFGR0": { + "description": "RCC oscillator public configuration register0.", + "fields": [ + { + "name": "LSIPUB", + "description": "Defines the public protection of the LSI oscillator configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "LSIPUB" + }, + { + "name": "LSEPUB", + "description": "Defines the public protection of the LSE oscillator configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "LSEPUB" + }, + { + "name": "MSIPUB", + "description": "Defines the public protection of the MSI oscillator configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "MSIPUB" + }, + { + "name": "HSIPUB", + "description": "Defines the public protection of the HSI oscillator configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "HSIPUB" + }, + { + "name": "HSEPUB", + "description": "Defines the public protection of the HSE oscillator configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "HSEPUB" + } + ] + }, + "fieldset/PUBCFGR1": { + "description": "RCC PLL public configuration register1.", + "fields": [ + { + "name": "PLLPUB", + "description": "Defines the public protection of the PLL1 PLL configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + }, + "enum": "PLLPUB" + } + ] + }, + "fieldset/PUBCFGR2": { + "description": "RCC divider public configuration register2.", + "fields": [ + { + "name": "IC1PUB", + "description": "Defines the public protection of the IC1 divider configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC2PUB", + "description": "Defines the public protection of the IC2 divider configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC3PUB", + "description": "Defines the public protection of the IC3 divider configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC4PUB", + "description": "Defines the public protection of the IC4 divider configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC5PUB", + "description": "Defines the public protection of the IC5 divider configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC6PUB", + "description": "Defines the public protection of the IC6 divider configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC7PUB", + "description": "Defines the public protection of the IC7 divider configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC8PUB", + "description": "Defines the public protection of the IC8 divider configuration bits.", + "bit_offset": 7, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC9PUB", + "description": "Defines the public protection of the IC9 divider configuration bits.", + "bit_offset": 8, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC10PUB", + "description": "Defines the public protection of the IC10 divider configuration bits.", + "bit_offset": 9, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC11PUB", + "description": "Defines the public protection of the IC11 divider configuration bits.", + "bit_offset": 10, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC12PUB", + "description": "Defines the public protection of the IC12 divider configuration bits.", + "bit_offset": 11, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC13PUB", + "description": "Defines the public protection of the IC13 divider configuration bits.", + "bit_offset": 12, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC14PUB", + "description": "Defines the public protection of the IC14 divider configuration bits.", + "bit_offset": 13, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC15PUB", + "description": "Defines the public protection of the IC15 divider configuration bits.", + "bit_offset": 14, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC16PUB", + "description": "Defines the public protection of the IC16 divider configuration bits.", + "bit_offset": 15, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC17PUB", + "description": "Defines the public protection of the IC17 divider configuration bits.", + "bit_offset": 16, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC18PUB", + "description": "Defines the public protection of the IC18 divider configuration bits.", + "bit_offset": 17, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC19PUB", + "description": "Defines the public protection of the IC19 divider configuration bits.", + "bit_offset": 18, + "bit_size": 1, + "enum": "ICPUB" + }, + { + "name": "IC20PUB", + "description": "Defines the public protection of the IC20 divider configuration bits.", + "bit_offset": 19, + "bit_size": 1, + "enum": "ICPUB" + } + ] + }, + "fieldset/PUBCFGR3": { + "description": "RCC system public configuration register3.", + "fields": [ + { + "name": "MODPUB", + "description": "Defines the public protection of the MOD system configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "MODPUB" + }, + { + "name": "SYSPUB", + "description": "Defines the public protection of the SYS system configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "SYSPUB" + }, + { + "name": "BUSPUB", + "description": "Defines the public protection of the BUS system configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "BUSPUB" + }, + { + "name": "PERPUB", + "description": "Defines the public protection of the PER system configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "PERPUB" + }, + { + "name": "INTPUB", + "description": "Defines the public protection of the INT system configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "INTPUB" + }, + { + "name": "RSTPUB", + "description": "Defines the public protection of the RST system configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "RSTPUB" + }, + { + "name": "DFTPUB", + "description": "Defines the public protection of the DFT system configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "DFTPUB" + } + ] + }, + "fieldset/PUBCFGR4": { + "description": "RCC bus public configuration register4.", + "fields": [ + { + "name": "ACLKNPUB", + "description": "Defines the public protection of the ACLKN bus configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ACLKNPUB" + }, + { + "name": "ACLKNCPUB", + "description": "Defines the public protection of the ACLKNC bus configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "ACLKNCPUB" + }, + { + "name": "AHBMPUB", + "description": "Defines the public protection of the AHBM bus configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "AHBMPUB" + }, + { + "name": "AHB1PUB", + "description": "Defines the public protection of the AHB1 bus configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "AHBPUB" + }, + { + "name": "AHB2PUB", + "description": "Defines the public protection of the AHB2 bus configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "AHBPUB" + }, + { + "name": "AHB3PUB", + "description": "Defines the public protection of the AHB3 bus configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "AHBPUB" + }, + { + "name": "AHB4PUB", + "description": "Defines the public protection of the AHB4 bus configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "AHBPUB" + }, + { + "name": "AHB5PUB", + "description": "Defines the public protection of the AHB5 bus configuration bits.", + "bit_offset": 7, + "bit_size": 1, + "enum": "AHBPUB" + }, + { + "name": "APB1PUB", + "description": "Defines the public protection of the APB1 bus configuration bits.", + "bit_offset": 8, + "bit_size": 1, + "enum": "APBPUB" + }, + { + "name": "APB2PUB", + "description": "Defines the public protection of the APB2 bus configuration bits.", + "bit_offset": 9, + "bit_size": 1, + "enum": "APBPUB" + }, + { + "name": "APB3PUB", + "description": "Defines the public protection of the APB3 bus configuration bits.", + "bit_offset": 10, + "bit_size": 1, + "enum": "APBPUB" + }, + { + "name": "APB4PUB", + "description": "Defines the public protection of the APB4 bus configuration bits.", + "bit_offset": 11, + "bit_size": 1, + "enum": "APBPUB" + }, + { + "name": "APB5PUB", + "description": "Defines the public protection of the APB5 bus configuration bits.", + "bit_offset": 12, + "bit_size": 1, + "enum": "APBPUB" + }, + { + "name": "NOCPUB", + "description": "Defines the public protection of the NOC bus configuration bits.", + "bit_offset": 13, + "bit_size": 1, + "enum": "NOCPUB" + } + ] + }, + "fieldset/PUBCFGR5": { + "description": "RCC bus public configuration register4.", + "fields": [ + { + "name": "AXISRAM3PUB", + "description": "Defines the public protection of the AXISRAM3 bus configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "AXISRAMPUB" + }, + { + "name": "AXISRAM4PUB", + "description": "Defines the public protection of the AXISRAM4 bus configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "AXISRAMPUB" + }, + { + "name": "AXISRAM5PUB", + "description": "Defines the public protection of the AXISRAM5 bus configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "AXISRAMPUB" + }, + { + "name": "AXISRAM6PUB", + "description": "Defines the public protection of the AXISRAM6 bus configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "AXISRAMPUB" + }, + { + "name": "AHBSRAM1PUB", + "description": "Defines the public protection of the AHBSRAM1 bus configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "AHBSRAMPUB" + }, + { + "name": "AHBSRAM2PUB", + "description": "Defines the public protection of the AHBSRAM2 bus configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "AHBSRAMPUB" + }, + { + "name": "BKPSRAMPUB", + "description": "Defines the public protection of the BKPSRAM bus configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "BKPSRAMPUB" + }, + { + "name": "AXISRAM1PUB", + "description": "Defines the public protection of the AXISRAM1 bus configuration bits.", + "bit_offset": 7, + "bit_size": 1, + "enum": "AXISRAMPUB" + }, + { + "name": "AXISRAM2PUB", + "description": "Defines the public protection of the AXISRAM2 bus configuration bits.", + "bit_offset": 8, + "bit_size": 1, + "enum": "AXISRAMPUB" + }, + { + "name": "FLEXRAMPUB", + "description": "Defines the public protection of the FLEXRAM bus configuration bits.", + "bit_offset": 9, + "bit_size": 1, + "enum": "FLEXRAMPUB" + }, + { + "name": "NPUCACHERAMPUB", + "description": "Defines the public protection of the NPUCACHERAM bus configuration bits.", + "bit_offset": 10, + "bit_size": 1, + "enum": "NPUCACHERAMPUB" + }, + { + "name": "VENCRAMPUB", + "description": "Defines the public protection of the VENCRAM bus configuration bits.", + "bit_offset": 11, + "bit_size": 1, + "enum": "VENCRAMPUB" + } + ] + }, + "fieldset/PUBCFGSR0": { + "description": "RCC oscillator public configuration register0.", + "fields": [ + { + "name": "LSIPUBS", + "description": "Defines the public protection of the LSI configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "LSEPUBS", + "description": "Defines the public protection of the LSE configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MSIPUBS", + "description": "Defines the public protection of the MSI configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "HSIPUBS", + "description": "Defines the public protection of the HSI configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "HSEPUBS", + "description": "Defines the public protection of the HSE configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/PUBCFGSR1": { + "description": "RCC PLL public configuration register1.", + "fields": [ + { + "name": "PLLPUBS", + "description": "Defines the public protection of the PLL1 configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } + } + ] + }, + "fieldset/PUBCFGSR2": { + "description": "RCC divider public configuration register2.", + "fields": [ + { + "name": "IC1PUBS", + "description": "Defines the public protection of the IC1 configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "IC2PUBS", + "description": "Defines the public protection of the IC2 configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "IC3PUBS", + "description": "Defines the public protection of the IC3 configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "IC4PUBS", + "description": "Defines the public protection of the IC4 configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "IC5PUBS", + "description": "Defines the public protection of the IC5 configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "IC6PUBS", + "description": "Defines the public protection of the IC6 configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "IC7PUBS", + "description": "Defines the public protection of the IC7 configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "IC8PUBS", + "description": "Defines the public protection of the IC8 configuration bits (enable, ready, divider).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "IC9PUBS", + "description": "Defines the public protection of the IC9 configuration bits (enable, ready, divider).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "IC10PUBS", + "description": "Defines the public protection of the IC10 configuration bits (enable, ready, divider).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "IC11PUBS", + "description": "Defines the public protection of the IC11 configuration bits (enable, ready, divider).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "IC12PUBS", + "description": "Defines the public protection of the IC12 configuration bits (enable, ready, divider).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "IC13PUBS", + "description": "Defines the public protection of the IC13 configuration bits (enable, ready, divider).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "IC14PUBS", + "description": "Defines the public protection of the IC14 configuration bits (enable, ready, divider).", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "IC15PUBS", + "description": "Defines the public protection of the IC15 configuration bits (enable, ready, divider).", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "IC16PUBS", + "description": "Defines the public protection of the IC16 configuration bits (enable, ready, divider).", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "IC17PUBS", + "description": "Defines the public protection of the IC17 configuration bits (enable, ready, divider).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "IC18PUBS", + "description": "Defines the public protection of the IC18 configuration bits (enable, ready, divider).", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "IC19PUBS", + "description": "Defines the public protection of the IC19 configuration bits (enable, ready, divider).", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "IC20PUBS", + "description": "Defines the public protection of the IC20 configuration bits (enable, ready, divider).", + "bit_offset": 19, + "bit_size": 1 + } + ] + }, + "fieldset/PUBCFGSR3": { + "description": "RCC system public configuration register3.", + "fields": [ + { + "name": "MODPUBS", + "description": "Defines the public protection of the MOD configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SYSPUBS", + "description": "Defines the public protection of the SYS configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BUSPUBS", + "description": "Defines the public protection of the BUS configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PERPUBS", + "description": "Defines the public protection of the PER configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "INTPUBS", + "description": "Defines the public protection of the INT configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "RSTPUBS", + "description": "Defines the public protection of the RST configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DFTPUBS", + "description": "Defines the public protection of the DFT configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/PUBCFGSR4": { + "description": "RCC public configuration register4.", + "fields": [ + { + "name": "ACLKNPUBS", + "description": "Defines the public protection of the ACLKN configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ACLKNCPUBS", + "description": "Defines the public protection of the ACLKNC configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AHBMPUBS", + "description": "Defines the public protection of the AHBM configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AHB1PUBS", + "description": "Defines the public protection of the AHB1 configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHB2PUBS", + "description": "Defines the public protection of the AHB2 configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHB3PUBS", + "description": "Defines the public protection of the AHB3 configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AHB4PUBS", + "description": "Defines the public protection of the AHB4 configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AHB5PUBS", + "description": "Defines the public protection of the AHB5 configuration bits (enable, ready, divider).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "APB1PUBS", + "description": "Defines the public protection of the APB1 configuration bits (enable, ready, divider).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "APB2PUBS", + "description": "Defines the public protection of the APB2 configuration bits (enable, ready, divider).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "APB3PUBS", + "description": "Defines the public protection of the APB3 configuration bits (enable, ready, divider).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "APB4PUBS", + "description": "Defines the public protection of the APB4 configuration bits (enable, ready, divider).", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "APB5PUBS", + "description": "Defines the public protection of the APB5 configuration bits (enable, ready, divider).", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "NOCPUBS", + "description": "Defines the public protection of the NOC configuration bits (enable, ready, divider).", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/PUBCFGSR5": { + "description": "RCC public configuration register4.", + "fields": [ + { + "name": "AXISRAM3PUBS", + "description": "Defines the public protection of the AXISRAM3 configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AXISRAM4PUBS", + "description": "Defines the public protection of the AXISRAM4 configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AXISRAM5PUBS", + "description": "Defines the public protection of the AXISRAM5 configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AXISRAM6PUBS", + "description": "Defines the public protection of the AXISRAM6 configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AHBSRAM1PUBS", + "description": "Defines the public protection of the AHBSRAM1 configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AHBSRAM2PUBS", + "description": "Defines the public protection of the AHBSRAM2 configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "BKPSRAMPUBS", + "description": "Defines the public protection of the BKPSRAM configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AXISRAM1PUBS", + "description": "Defines the public protection of the AXISRAM1 configuration bits (enable, ready, divider).", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AXISRAM2PUBS", + "description": "Defines the public protection of the AXISRAM2 configuration bits (enable, ready, divider).", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "FLEXRAMPUBS", + "description": "Defines the public protection of the FLEXRAM configuration bits (enable, ready, divider).", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "NPUCACHERAMPUBS", + "description": "Defines the public protection of the NPUCACHERAM configuration bits (enable, ready, divider).", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "VENCRAMPUBS", + "description": "Defines the public protection of the VENCRAM configuration bits (enable, ready, divider).", + "bit_offset": 11, + "bit_size": 1 + } + ] + }, + "fieldset/RDCR": { + "description": "RCC APB5 Sleep enable register.", + "fields": [ + { + "name": "MRD", + "description": "BOOTROM sleep enable.", + "bit_offset": 16, + "bit_size": 5, + "enum": "MRD" + }, + { + "name": "EADLY", + "description": "BOOTROM sleep enable.", + "bit_offset": 24, + "bit_size": 4, + "enum": "EADLY" + } + ] + }, + "fieldset/RSR": { + "description": "RCC reset register.", + "fields": [ + { + "name": "RMVF", + "description": "Remove reset flag.", + "bit_offset": 16, + "bit_size": 1, + "enum": "RSR_RMVF" + }, + { + "name": "LCKRSTF", + "description": "CPU lockup reset flag.", + "bit_offset": 17, + "bit_size": 1, + "enum": "RSR_LCKRSTF" + }, + { + "name": "BORRSTF", + "description": "BOR flag.", + "bit_offset": 21, + "bit_size": 1, + "enum": "RSR_BORRSTF" + }, + { + "name": "PINRSTF", + "description": "Pin reset flag (NRST).", + "bit_offset": 22, + "bit_size": 1, + "enum": "RSR_PINRSTF" + }, + { + "name": "PORRSTF", + "description": "POR/PDR flag.", + "bit_offset": 23, + "bit_size": 1, + "enum": "RSR_PORRSTF" + }, + { + "name": "SFTRSTF", + "description": "Software System reset flag (1).", + "bit_offset": 24, + "bit_size": 1, + "enum": "RSR_SFTRSTF" + }, + { + "name": "IWDGRSTF", + "description": "Independent Watchdog reset flag.", + "bit_offset": 26, + "bit_size": 1, + "enum": "RSR_IWDGRSTF" + }, + { + "name": "WWDGRSTF", + "description": "Window Watchdog reset flag.", + "bit_offset": 28, + "bit_size": 1, + "enum": "RSR_WWDGRSTF" + }, + { + "name": "LPWRRSTF", + "description": "Illegal Stop or Standby flag.", + "bit_offset": 30, + "bit_size": 1, + "enum": "RSR_LPWRRSTF" + } + ] + }, + "fieldset/SECCFGR0": { + "description": "RCC oscillator secure configuration register0.", + "fields": [ + { + "name": "LSISEC", + "description": "Defines the secure protection of the LSI oscillator configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "LSISEC" + }, + { + "name": "LSESEC", + "description": "Defines the secure protection of the LSE oscillator configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "LSESEC" + }, + { + "name": "MSISEC", + "description": "Defines the secure protection of the MSI oscillator configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "MSISEC" + }, + { + "name": "HSISEC", + "description": "Defines the secure protection of the HSI oscillator configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "HSISEC" + }, + { + "name": "HSESEC", + "description": "Defines the secure protection of the HSE oscillator configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "HSESEC" + } + ] + }, + "fieldset/SECCFGR1": { + "description": "RCC PLL secure configuration register1.", + "fields": [ + { + "name": "PLLSEC", + "description": "Defines the secure protection of the PLL1 PLL configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + }, + "enum": "PLLSEC" + } + ] + }, + "fieldset/SECCFGR2": { + "description": "RCC divider secure configuration register2.", + "fields": [ + { + "name": "IC1SEC", + "description": "Defines the secure protection of the IC1 divider configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC2SEC", + "description": "Defines the secure protection of the IC2 divider configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC3SEC", + "description": "Defines the secure protection of the IC3 divider configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC4SEC", + "description": "Defines the secure protection of the IC4 divider configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC5SEC", + "description": "Defines the secure protection of the IC5 divider configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC6SEC", + "description": "Defines the secure protection of the IC6 divider configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC7SEC", + "description": "Defines the secure protection of the IC7 divider configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC8SEC", + "description": "Defines the secure protection of the IC8 divider configuration bits.", + "bit_offset": 7, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC9SEC", + "description": "Defines the secure protection of the IC9 divider configuration bits.", + "bit_offset": 8, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC10SEC", + "description": "Defines the secure protection of the IC10 divider configuration bits.", + "bit_offset": 9, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC11SEC", + "description": "Defines the secure protection of the IC11 divider configuration bits.", + "bit_offset": 10, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC12SEC", + "description": "Defines the secure protection of the IC12 divider configuration bits.", + "bit_offset": 11, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC13SEC", + "description": "Defines the secure protection of the IC13 divider configuration bits.", + "bit_offset": 12, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC14SEC", + "description": "Defines the secure protection of the IC14 divider configuration bits.", + "bit_offset": 13, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC15SEC", + "description": "Defines the secure protection of the IC15 divider configuration bits.", + "bit_offset": 14, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC16SEC", + "description": "Defines the secure protection of the IC16 divider configuration bits.", + "bit_offset": 15, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC17SEC", + "description": "Defines the secure protection of the IC17 divider configuration bits.", + "bit_offset": 16, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC18SEC", + "description": "Defines the secure protection of the IC18 divider configuration bits.", + "bit_offset": 17, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC19SEC", + "description": "Defines the secure protection of the IC19 divider configuration bits.", + "bit_offset": 18, + "bit_size": 1, + "enum": "ICSEC" + }, + { + "name": "IC20SEC", + "description": "Defines the secure protection of the IC20 divider configuration bits.", + "bit_offset": 19, + "bit_size": 1, + "enum": "ICSEC" + } + ] + }, + "fieldset/SECCFGR3": { + "description": "RCC system secure configuration register3.", + "fields": [ + { + "name": "MODSEC", + "description": "Defines the secure protection of the MOD system configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "MODSEC" + }, + { + "name": "SYSSEC", + "description": "Defines the secure protection of the SYS system configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "SYSSEC" + }, + { + "name": "BUSSEC", + "description": "Defines the secure protection of the BUS system configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "BUSSEC" + }, + { + "name": "PERSEC", + "description": "Defines the secure protection of the PER system configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "PERSEC" + }, + { + "name": "INTSEC", + "description": "Defines the secure protection of the INT system configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "INTSEC" + }, + { + "name": "RSTSEC", + "description": "Defines the secure protection of the RST system configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "RSTSEC" + }, + { + "name": "DFTSEC", + "description": "Defines the secure protection of the DFT system configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "DFTSEC" + } + ] + }, + "fieldset/SECCFGR4": { + "description": "RCC bus secure configuration register4.", + "fields": [ + { + "name": "ACLKNSEC", + "description": "Defines the secure protection of the ACLKN bus configuration bits.", + "bit_offset": 0, + "bit_size": 1, + "enum": "ACLKNSEC" + }, + { + "name": "ACLKNCSEC", + "description": "Defines the secure protection of the ACLKNC bus configuration bits.", + "bit_offset": 1, + "bit_size": 1, + "enum": "ACLKNCSEC" + }, + { + "name": "AHBMSEC", + "description": "Defines the secure protection of the AHBM bus configuration bits.", + "bit_offset": 2, + "bit_size": 1, + "enum": "AHBMSEC" + }, + { + "name": "AHB1SEC", + "description": "Defines the secure protection of the AHB1 bus configuration bits.", + "bit_offset": 3, + "bit_size": 1, + "enum": "AHBSEC" + }, + { + "name": "AHB2SEC", + "description": "Defines the secure protection of the AHB2 bus configuration bits.", + "bit_offset": 4, + "bit_size": 1, + "enum": "AHBSEC" + }, + { + "name": "AHB3SEC", + "description": "Defines the secure protection of the AHB3 bus configuration bits.", + "bit_offset": 5, + "bit_size": 1, + "enum": "AHBSEC" + }, + { + "name": "AHB4SEC", + "description": "Defines the secure protection of the AHB4 bus configuration bits.", + "bit_offset": 6, + "bit_size": 1, + "enum": "AHBSEC" + }, + { + "name": "AHB5SEC", + "description": "Defines the secure protection of the AHB5 bus configuration bits.", + "bit_offset": 7, + "bit_size": 1, + "enum": "AHBSEC" + }, + { + "name": "APB1SEC", + "description": "Defines the secure protection of the APB1 bus configuration bits.", + "bit_offset": 8, + "bit_size": 1, + "enum": "APBSEC" + }, + { + "name": "APB2SEC", + "description": "Defines the secure protection of the APB2 bus configuration bits.", + "bit_offset": 9, + "bit_size": 1, + "enum": "APBSEC" + }, + { + "name": "APB3SEC", + "description": "Defines the secure protection of the APB3 bus configuration bits.", + "bit_offset": 10, + "bit_size": 1, + "enum": "APBSEC" + }, + { + "name": "APB4SEC", + "description": "Defines the secure protection of the APB4 bus configuration bits.", + "bit_offset": 11, + "bit_size": 1, + "enum": "APBSEC" + }, + { + "name": "APB5SEC", + "description": "Defines the secure protection of the APB5 bus configuration bits.", + "bit_offset": 12, + "bit_size": 1, + "enum": "APBSEC" + }, + { + "name": "NOCSEC", + "description": "Defines the secure protection of the NOC bus configuration bits.", + "bit_offset": 13, + "bit_size": 1, + "enum": "NOCSEC" + } + ] + }, + "fieldset/SECCFGSR3": { + "description": "RCC system secure configuration register3.", + "fields": [ + { + "name": "MODSECS", + "description": "Defines the secure protection of the MOD configuration bits (enable, ready, divider).", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SYSSECS", + "description": "Defines the secure protection of the SYS configuration bits (enable, ready, divider).", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "BUSSECS", + "description": "Defines the secure protection of the BUS configuration bits (enable, ready, divider).", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "PERSECS", + "description": "Defines the secure protection of the PER configuration bits (enable, ready, divider).", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "INTSECS", + "description": "Defines the secure protection of the INT configuration bits (enable, ready, divider).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "RSTSECS", + "description": "Defines the secure protection of the RST configuration bits (enable, ready, divider).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DFTSECS", + "description": "Defines the secure protection of the DFT configuration bits (enable, ready, divider).", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/SR": { + "description": "RCC status register.", + "fields": [ + { + "name": "LSIRDY", + "description": "LSI clock ready flag.", + "bit_offset": 0, + "bit_size": 1, + "enum": "LSIRDY" + }, + { + "name": "LSERDY", + "description": "LSE clock ready flag.", + "bit_offset": 1, + "bit_size": 1, + "enum": "LSERDY" + }, + { + "name": "MSIRDY", + "description": "MSI clock ready flag.", + "bit_offset": 2, + "bit_size": 1, + "enum": "MSIRDY" + }, + { + "name": "HSIRDY", + "description": "HSI clock ready flag.", + "bit_offset": 3, + "bit_size": 1, + "enum": "HSIRDY" + }, + { + "name": "HSERDY", + "description": "HSE clock ready flag.", + "bit_offset": 4, + "bit_size": 1, + "enum": "HSERDY" + }, + { + "name": "PLLRDY", + "description": "PLL1 clock ready flag.", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + }, + "enum": "PLLRDY" + } + ] + }, + "fieldset/STOPCCR": { + "description": "RCC StopCCR configuration register.", + "fields": [ + { + "name": "LSISTOPENC", + "description": "LSI oscillator enable in Run/Sleep mode.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "LSESTOPENC", + "description": "LSE oscillator enable in Run/Sleep mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MSISTOPENC", + "description": "MSI oscillator enable in Run/Sleep mode.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "HSISTOPENC", + "description": "HSI oscillator enable in Run/Sleep mode.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/STOPCR": { + "description": "RCC Stop mode control register.", + "fields": [ + { + "name": "LSISTOPEN", + "description": "LSI oscillator enable in Stop mode.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "LSESTOPEN", + "description": "LSE oscillator enable in Stop mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "MSISTOPEN", + "description": "MSI oscillator enable in Stop mode.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "HSISTOPEN", + "description": "HSI oscillator enable in Stop mode.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/STOPCSR": { + "description": "RCC Stop configuration register.", + "fields": [ + { + "name": "MSISTOPENS", + "description": "MSISTOPENS.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "HSISTOPENS", + "description": "HSISTOPENS.", + "bit_offset": 1, + "bit_size": 1 + } + ] + }, + "enum/ACLKNCLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "ACLKNC configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "B_0x1", + "description": "ACLKNC configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/ACLKNCPUB": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "ACLKNC configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "B_0x1", + "description": "ACLKNC configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/ACLKNCPV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "ACLKNC configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "B_0x1", + "description": "ACLKNC configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/ACLKNCSEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "ACLKNC configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "B_0x1", + "description": "ACLKNC configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/ACLKNLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "ACLKN configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "B_0x1", + "description": "ACLKN configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/ACLKNPUB": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "ACLKN configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "B_0x1", + "description": "ACLKN configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/ACLKNPV": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "ACLKN configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "B_0x1", + "description": "ACLKN configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/ACLKNSEC": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "ACLKN configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "B_0x1", + "description": "ACLKN configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/ADCPRE": { + "bit_size": 8, + "variants": [ + { + "name": "B_0x0", + "description": "ck_icn_p_adf1 is divided by 1.", + "value": 0 + }, + { + "name": "B_0x1", + "description": "ck_icn_p_adf1 is divided by 2.", + "value": 1 + }, + { + "name": "B_0x2", + "description": "ck_icn_p_adf1 is divided by 3.", + "value": 2 + }, + { + "name": "B_0x3", + "description": "ck_icn_p_adf1 is divided by 4.", + "value": 3 + } + ] + }, + "enum/ADCSEL": { + "bit_size": 3, + "variants": [ + { + "name": "HCLK1", + "description": "hclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC7", + "description": "ic7_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC8", + "description": "ic8_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + }, + { + "name": "I2S_CKIN", + "description": "I2S_CKIN selected as reference clock.", + "value": 6 + }, + { + "name": "TIMG", + "description": "timg_ck selected as reference clock.", + "value": 7 + } + ] + }, + "enum/ADFSEL": { + "bit_size": 3, + "variants": [ + { + "name": "HCLK2", + "description": "hclk2 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC7", + "description": "ic7_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC8", + "description": "ic8_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + }, + { + "name": "I2S_CKIN", + "description": "I2S_CKIN selected as reference clock.", + "value": 6 + }, + { + "name": "TIMG", + "description": "timg_ck selected as reference clock.", + "value": 7 + } + ] + }, + "enum/AHBLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "AHB1 configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "AHB1 configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/AHBMLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "AHBM configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "AHBM configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/AHBMPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "AHBM configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "AHBM configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/AHBMPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIV", + "description": "AHBM configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIV", + "description": "AHBM configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/AHBMSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "AHBM configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "AHBM configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/AHBPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "AHB1 configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "AHB1 configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/AHBPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIV", + "description": "AHB1 configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIV", + "description": "AHB1 configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/AHBSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "AHB1 configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "AHB1 configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/AHBSRAMPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "AHBSRAM1 configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "AHBSRAM1 configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/APBLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "APB1 configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "APB1 configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/APBPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "APB1 configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "APB1 configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/APBPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIV", + "description": "APB1 configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIV", + "description": "APB1 configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/APBSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "APB1 configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "APB1 configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/AXISRAMPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "AXISRAM1 configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "AXISRAM1 configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/BKPSRAMPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "BKPSRAM configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "BKPSRAM configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/BUSLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "BUS configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "BUS configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/BUSPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "BUS configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "BUS configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/BUSPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIV", + "description": "BUS configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIV", + "description": "BUS configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/BUSSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "BUS configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "BUS configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/CPUSW": { + "bit_size": 2, + "variants": [ + { + "name": "HSI", + "description": "hsi_ck selected as system clock (default after reset).", + "value": 0 + }, + { + "name": "MSI", + "description": "msi_ck selected as system clock.", + "value": 1 + }, + { + "name": "HSE", + "description": "hse_ck selected as system clock.", + "value": 2 + }, + { + "name": "IC1", + "description": "ic1_ck selected as system clock.", + "value": 3 + } + ] + }, + "enum/CPUSWS": { + "bit_size": 2, + "variants": [ + { + "name": "HSI", + "description": "hsi_ck selected as system clock (default after reset).", + "value": 0 + }, + { + "name": "MSI", + "description": "msi_ck selected as system clock.", + "value": 1 + }, + { + "name": "HSE", + "description": "hse_ck selected as system clock.", + "value": 2 + }, + { + "name": "IC1", + "description": "ic1_ck selected as system clock.", + "value": 3 + } + ] + }, + "enum/DCMIPPSEL": { + "bit_size": 2, + "variants": [ + { + "name": "PCLK5", + "description": "pclk5 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC17", + "description": "ic17_ck selected as reference clock.", + "value": 2 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 3 + } + ] + }, + "enum/DFTLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "DFT configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "DFT configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/DFTPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "DFT configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "DFT configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/DFTPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIV", + "description": "DFT configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIV", + "description": "DFT configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/DFTSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "DFT configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "DFT configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/DFTSEL": { + "bit_size": 1, + "variants": [ + { + "name": "JTAG_TCK", + "description": "jtag_tck selected as reference clock (default after reset).", + "value": 0 + }, + { + "name": "PCLK3", + "description": "pclk3 selected as reference clock.", + "value": 1 + } + ] + }, + "enum/EADLY": { + "bit_size": 4, + "variants": [ + { + "name": "BYPASS", + "description": "sysrstn low pulse duration is guaranteed by the pulse stretcher of the PAD. The RPCTL is bypassed (default after reset).", + "value": 0 + }, + { + "name": "1MS", + "description": "The guaranteed sysrstn low pulse duration is about 1 ms (1 x 32 lsi_ck cycles).", + "value": 1 + }, + { + "name": "2MS", + "description": "The guaranteed sysrstn low pulse duration is about 2 ms (2 x 32 lsi_ck cycles).", + "value": 2 + } + ] + }, + "enum/ETHCLKSEL": { + "bit_size": 2, + "variants": [ + { + "name": "HCLKE", + "description": "hclke selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC12", + "description": "ic12_ck selected as reference clock.", + "value": 2 + }, + { + "name": "HSE", + "description": "hse_ck selected as reference clock.", + "value": 3 + } + ] + }, + "enum/ETHGTXCLKSEL": { + "bit_size": 1, + "variants": [ + { + "name": "MII", + "description": "MII.", + "value": 0 + }, + { + "name": "RGMII", + "description": "RGMII.", + "value": 1 + } + ] + }, + "enum/ETHPTPDIV": { + "bit_size": 4, + "variants": [ + { + "name": "DIV1", + "description": "ck_ker_eth1ptp is divided by 1.", + "value": 0 + }, + { + "name": "DIV2", + "description": "ck_ker_eth1ptp is divided by 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "ck_ker_eth1ptp is divided by 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "ck_ker_eth1ptp is divided by 4.", + "value": 3 + }, + { + "name": "DIV16", + "description": "ck_ker_eth1ptp is divided by 16.", + "value": 15 + } + ] + }, + "enum/ETHPTPSEL": { + "bit_size": 2, + "variants": [ + { + "name": "HCLKE", + "description": "hclke selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC13", + "description": "ic13_ck selected as reference clock.", + "value": 2 + }, + { + "name": "HSE", + "description": "hse_ck selected as reference clock.", + "value": 3 + } + ] + }, + "enum/ETHPWRDOWNACK": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_ACK", + "description": "Power-down sequence start not yet acknowledged.", + "value": 0 + }, + { + "name": "ACK", + "description": "Power-down sequence start acknowledged.", + "value": 1 + } + ] + }, + "enum/FDCANSEL": { + "bit_size": 2, + "variants": [ + { + "name": "PCLK1", + "description": "pclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC19", + "description": "ic19_ck selected as reference clock.", + "value": 2 + }, + { + "name": "HSE", + "description": "hse_ck selected as reference clock.", + "value": 3 + } + ] + }, + "enum/FLEXRAMPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "FLEXRAM configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "FLEXRAM configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/FMCSEL": { + "bit_size": 2, + "variants": [ + { + "name": "HCLK5", + "description": "hclk5 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC3", + "description": "ic3_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC4", + "description": "ic4_ck selected as reference clock.", + "value": 3 + } + ] + }, + "enum/FMCSELS": { + "bit_size": 2, + "variants": [ + { + "name": "HCLK5", + "description": "hclk5 selected as FMC clock (default after reset).", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as FMC clock.", + "value": 1 + }, + { + "name": "IC3", + "description": "ic3_ck selected as FMC clock.", + "value": 2 + }, + { + "name": "IC4", + "description": "ic4_ck selected as FMC clock.", + "value": 3 + } + ] + }, + "enum/HPRE": { + "bit_size": 3, + "variants": [ + { + "name": "DIV1", + "description": "sys_bus2_ck= sys_bus_ck.", + "value": 0 + }, + { + "name": "DIV2", + "description": "sys_bus2_ck = sys_bus_ck / 2 (default after reset).", + "value": 1 + }, + { + "name": "DIV4", + "description": "sys_bus2_ck= sys_bus_ck / 4.", + "value": 2 + }, + { + "name": "DIV8", + "description": "sys_bus2_ck = sys_bus_ck / 8.", + "value": 3 + }, + { + "name": "DIV16", + "description": "sys_bus2_ck = sys_bus_ck / 16.", + "value": 4 + }, + { + "name": "DIV32", + "description": "sys_bus2_ck = sys_bus_ck / 32.", + "value": 5 + }, + { + "name": "DIV64", + "description": "sys_bus2_ck = sys_bus_ck / 64.", + "value": 6 + }, + { + "name": "DIV128", + "description": "sys_bus2_ck = sys_bus_ck / 128.", + "value": 7 + } + ] + }, + "enum/HSEBYP": { + "bit_size": 1, + "variants": [ + { + "name": "NO_BYPASS", + "description": "HSE oscillator not bypassed (default after reset).", + "value": 0 + }, + { + "name": "BYPASS", + "description": "HSE oscillator bypassed with an external clock.", + "value": 1 + } + ] + }, + "enum/HSECSSBPRE": { + "bit_size": 4, + "variants": [ + { + "name": "DIV1", + "description": "HSI clock is divided by 1.", + "value": 0 + }, + { + "name": "DIV2", + "description": "HSI clock is divided by 2 (default after reset).", + "value": 1 + }, + { + "name": "DIV3", + "description": "HSI clock is divided by 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "HSI clock is divided by 4.", + "value": 3 + }, + { + "name": "DIV15", + "description": "HSI clock is divided by 15.", + "value": 15 + } + ] + }, + "enum/HSECSSBYP": { + "bit_size": 1, + "variants": [ + { + "name": "NO_BYPASS", + "description": "clock Security System Bypass of the HSE oscillator is OFF (default after reset).", + "value": 0 + }, + { + "name": "BYPASS", + "description": "clock Security System Bypass on the HSE oscillator is ON.", + "value": 1 + } + ] + }, + "enum/HSECSSC": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_MODIFIED", + "description": "HSECSSF not modified (default after reset).", + "value": 0 + }, + { + "name": "CLEARED", + "description": "HSECSSF cleared.", + "value": 1 + } + ] + }, + "enum/HSECSSD": { + "bit_size": 1, + "variants": [ + { + "name": "NO_FAILURE", + "description": "No failure detected on the oscillator (default after reset).", + "value": 0 + }, + { + "name": "FAILURE", + "description": "Failure detected on the oscillator.", + "value": 1 + } + ] + }, + "enum/HSECSSF": { + "bit_size": 1, + "variants": [ + { + "name": "NO_CLOCK_READY", + "description": "no clock ready interrupt caused by the HSE (default after reset).", + "value": 0 + }, + { + "name": "CLOCK_READY", + "description": "clock ready interrupt caused by the HSE.", + "value": 1 + } + ] + }, + "enum/HSECSSIE": { + "bit_size": 1, + "variants": [ + { + "name": "DISABLED", + "description": "HSE CSS interrupt disabled.", + "value": 0 + }, + { + "name": "ENABLED", + "description": "HSE CSS interrupt enabled (default after reset).", + "value": 1 + } + ] + }, + "enum/HSECSSRA": { + "bit_size": 1, + "variants": [ + { + "name": "NO_RE_ARM", + "description": "Writing 0 has no effect (default after reset).", + "value": 0 + }, + { + "name": "RE_ARM", + "description": "Writing 1 generates a re-arm pulse for the HSECSS function.", + "value": 1 + } + ] + }, + "enum/HSEDIVBYP": { + "bit_size": 1, + "variants": [ + { + "name": "DIV2", + "description": "HSE: hse_div2_osc_ck = hse_osc_ck/2 (default after reset).", + "value": 0 + }, + { + "name": "DIV1", + "description": "HSE: hse_div2_osc_ck = hse_osc_ck.", + "value": 1 + } + ] + }, + "enum/HSEDRV": { + "bit_size": 2, + "variants": [ + { + "name": "LOWEST", + "description": "Lowest drive (default after reset).", + "value": 0 + }, + { + "name": "LOW", + "description": "Medium low drive.", + "value": 1 + }, + { + "name": "HIGH", + "description": "Medium high drive.", + "value": 2 + }, + { + "name": "HIGHEST", + "description": "Highest drive.", + "value": 3 + } + ] + }, + "enum/HSEEXT": { + "bit_size": 1, + "variants": [ + { + "name": "ANALOG", + "description": "HSE in analog mode (default after reset).", + "value": 0 + }, + { + "name": "DIGITAL", + "description": "HSE in digital mode.", + "value": 1 + } + ] + }, + "enum/HSELOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "HSE configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "HSE configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/HSEPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "HSE configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "HSE configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/HSEPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIV", + "description": "HSE configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIV", + "description": "HSE configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/HSERDY": { + "bit_size": 1, + "variants": [ + { + "name": "No_RDY", + "description": "HSE is not ready (default after reset).", + "value": 0 + }, + { + "name": "RDY", + "description": "HSE is ready.", + "value": 1 + } + ] + }, + "enum/HSERDYC": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_MODIFIED", + "description": "HSERDYF not modified (default after reset).", + "value": 0 + }, + { + "name": "CLEARED", + "description": "HSERDYF cleared.", + "value": 1 + } + ] + }, + "enum/HSERDYF": { + "bit_size": 1, + "variants": [ + { + "name": "NO_CLOCK_READY", + "description": "no clock ready interrupt caused by the HSE (default after reset).", + "value": 0 + }, + { + "name": "CLOCK_READY", + "description": "clock ready interrupt caused by the HSE.", + "value": 1 + } + ] + }, + "enum/HSERDYIE": { + "bit_size": 1, + "variants": [ + { + "name": "DISABLED", + "description": "HSE ready interrupt disabled (default after reset).", + "value": 0 + }, + { + "name": "ENABLED", + "description": "HSE ready interrupt enabled.", + "value": 1 + } + ] + }, + "enum/HSESEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "HSE configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "HSE configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/HSIDIV": { + "bit_size": 2, + "variants": [ + { + "name": "DIV1", + "description": "hsi_ck = hsi_osc_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "hsi_ck = hsi_osc_ck / 2.", + "value": 1 + } + ] + }, + "enum/HSILOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "HSI configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "HSI configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/HSIPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "HSI configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "HSI configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/HSIPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIV", + "description": "HSI configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIV", + "description": "HSI configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/HSIRDY": { + "bit_size": 1, + "variants": [ + { + "name": "NO_RDY", + "description": "HSI is not ready.", + "value": 0 + }, + { + "name": "RDY", + "description": "HSI is ready (default after reset).", + "value": 1 + } + ] + }, + "enum/HSIRDYC": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_MODIFIED", + "description": "HSIRDYF not modified (default after reset).", + "value": 0 + }, + { + "name": "CLEARED", + "description": "HSIRDYF cleared.", + "value": 1 + } + ] + }, + "enum/HSIRDYF": { + "bit_size": 1, + "variants": [ + { + "name": "NO_CLOCK_READY", + "description": "no clock ready interrupt caused by the HSI (default after reset).", + "value": 0 + }, + { + "name": "CLOCK_READY", + "description": "clock ready interrupt caused by the HSI.", + "value": 1 + } + ] + }, + "enum/HSIRDYIE": { + "bit_size": 1, + "variants": [ + { + "name": "DISABLED", + "description": "HSI ready interrupt disabled (default after reset).", + "value": 0 + }, + { + "name": "ENABLED", + "description": "HSI ready interrupt enabled.", + "value": 1 + } + ] + }, + "enum/HSISEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "HSI configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "HSI configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/HSITRIM": { + "bit_size": 7, + "variants": [ + { + "name": "ZERO", + "description": "bsec_hsi_cal[8:0] (default after reset).", + "value": 0 + }, + { + "name": "PLUS_62", + "description": "bsec_hsi_cal[8:0] + 62.", + "value": 62 + }, + { + "name": "PLUS_63", + "description": "bsec_hsi_cal[8:0] + 63.", + "value": 63 + }, + { + "name": "MINUS_64", + "description": "bsec_hsi_cal[8:0] - 64.", + "value": 64 + }, + { + "name": "MINUS_63", + "description": "bsec_hsi_cal[8:0] - 63.", + "value": 65 + } + ] + }, + "enum/HWRSR_BORRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_OCCURRED", + "description": "no BOR occurred.", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "BOR occurred (default after power-on reset).", + "value": 1 + } + ] + }, + "enum/HWRSR_IWDGRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_OCCURRED", + "description": "no Independent Watchdog Reset occurred (default after power-on reset).", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "Independent Watchdog Reset occurred.", + "value": 1 + } + ] + }, + "enum/HWRSR_LCKRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_OCCURRED", + "description": "No reset from CPU lockup occurred.", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "Reset from CPU lockup occurred.", + "value": 1 + } + ] + }, + "enum/HWRSR_LPWRRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_OCCURRED", + "description": "no illegal reset occurred (default after power-on reset).", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "illegal Stop or Standby reset occurred.", + "value": 1 + } + ] + }, + "enum/HWRSR_PINRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_OCCURRED", + "description": "no reset from pin occurred.", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "Reset from Pin occurred (default after power-on reset).", + "value": 1 + } + ] + }, + "enum/HWRSR_PORRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_OCCURRED", + "description": "no POR/PDR reset occurred.", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "POR/PDR reset occurred (default after power-on reset).", + "value": 1 + } + ] + }, + "enum/HWRSR_RMVF": { + "bit_size": 1, + "variants": [ + { + "name": "NO_CLEAR", + "description": "clear of the reset flags not activated (default after power-on reset).", + "value": 0 + }, + { + "name": "CLEAR", + "description": "clear the value of the reset flags.", + "value": 1 + } + ] + }, + "enum/HWRSR_SFTRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_OCCURRED", + "description": "no Software System reset occurred (default after power-on reset).", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "a Software System reset has been generated by the CPU.", + "value": 1 + } + ] + }, + "enum/HWRSR_WWDGRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "B_0x0", + "description": "no Window Watchdog Reset occurred from WWDG (default after power-on reset).", + "value": 0 + }, + { + "name": "B_0x1", + "description": "Window Watchdog Reset occurred from WWDG.", + "value": 1 + } + ] + }, + "enum/I2C1SEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK1", + "description": "pclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC10", + "description": "ic10_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC15", + "description": "ic15_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + } + ] + }, + "enum/I2C2SEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK1", + "description": "pclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC10", + "description": "ic10_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC15", + "description": "ic15_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + } + ] + }, + "enum/I2C3SEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK1", + "description": "pclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC10", + "description": "ic10_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC15", + "description": "ic15_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + } + ] + }, + "enum/I2C4SEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK1", + "description": "pclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC10", + "description": "ic10_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC15", + "description": "ic15_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + } + ] + }, + "enum/I3C1SEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK1", + "description": "pclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC10", + "description": "ic10_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC15", + "description": "ic15_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + } + ] + }, + "enum/I3C2SEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK1", + "description": "pclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC10", + "description": "ic10_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC15", + "description": "ic15_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + } + ] + }, + "enum/IC10INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC10 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC10 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC10 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC10 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC10 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC10SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected (default after reset).", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC11INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC11 = pllx_ck.", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC11 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC11 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC11 = pllx_ck / 4 (default after reset).", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC11 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC11SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected (default after reset).", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC12INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC12 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC12 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC12 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC12 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC12 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC12SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC13INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC13 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC13 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC13 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC13 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC13 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC13SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC14INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC14 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC14 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC14 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC14 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC14 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC14SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC15INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC15 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC15 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC15 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC15 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC15 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC15SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC16INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV2", + "description": "IC16 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC16 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC16 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC16 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC16SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC17INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC17 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC17 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC17 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC17 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC17 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC17SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC18INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC18 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC18 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC18 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC18 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC18 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC18SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC19INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC19 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC19 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC19 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC19 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC19 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC19SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC1INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC1 = pllx_ck.", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC1 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC1 = pllx_ck / 3 (default after reset).", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC1 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC1 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC1SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected (default after reset).", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC20INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC20 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC20 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC20 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC20 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC20 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC20SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC2INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC2 = pllx_ck.", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC2 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC2 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC2 = pllx_ck / 4 (default after reset).", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC2 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC2SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected (default after reset).", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC3INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC3 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC3 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC3 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC3 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC3 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC3SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected (default after reset).", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC4INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC4 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC4 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC4 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC4 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC4 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC4SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected (default after reset).", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC5INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC5 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC5 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC5 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC5 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC5 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC5SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected (default after reset).", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC6INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC6 = pllx_ck.", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC6 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC6 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC6 = pllx_ck / 4 (default after reset).", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC6 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC6SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected (default after reset).", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected.", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC7INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC7 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC7 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC7 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC7 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC7 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC7SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected (default after reset).", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC8INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC8 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC8 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC8 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC8 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC8 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC8SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected (default after reset).", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/IC9INT": { + "bit_size": 8, + "variants": [ + { + "name": "DIV1", + "description": "IC9 = pllx_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "IC9 = pllx_ck / 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "IC9 = pllx_ck / 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "IC9 = pllx_ck / 4.", + "value": 3 + }, + { + "name": "DIV256", + "description": "IC9 = pllx_ck / 256.", + "value": 255 + } + ] + }, + "enum/IC9SEL": { + "bit_size": 2, + "variants": [ + { + "name": "PLL1", + "description": "pll1_ck is selected.", + "value": 0 + }, + { + "name": "PLL2", + "description": "pll2_ck is selected (default after reset).", + "value": 1 + }, + { + "name": "HSI_OSC_DIV4", + "description": "hsi_ck = hsi_osc_ck / 4.", + "value": 2 + }, + { + "name": "HSI_OSC_DIV8", + "description": "hsi_ck = hsi_osc_ck / 8.", + "value": 3 + } + ] + }, + "enum/ICLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "IC10 configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "IC10 configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/ICPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "IC10 configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "IC10 configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/ICPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIVILEGE", + "description": "IC10 configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIVILEGE", + "description": "IC10 configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/ICSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "IC10 configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "IC10 configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/INTLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "INT configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "INT configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/INTPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "INT configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "INT configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/INTPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIVILEGE", + "description": "INT configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIVILEGE", + "description": "INT configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/INTSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "INT configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "INT configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/LPTIMSEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK1", + "description": "pclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC15", + "description": "ic15_ck selected as reference clock.", + "value": 2 + }, + { + "name": "LSE", + "description": "lse_ck selected as reference clock.", + "value": 3 + }, + { + "name": "LSI", + "description": "lsi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "TIMG", + "description": "timg_ck selected as reference clock.", + "value": 5 + } + ] + }, + "enum/LPUARTSEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK4", + "description": "pclk4 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC9", + "description": "ic9_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC14", + "description": "ic14_ck selected as reference clock.", + "value": 3 + }, + { + "name": "LSE", + "description": "lse_ck selected as reference clock.", + "value": 4 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 5 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 6 + } + ] + }, + "enum/LSEBYP": { + "bit_size": 1, + "variants": [ + { + "name": "NO_BYPASS", + "description": "LSE oscillator not bypassed (default after reset).", + "value": 0 + }, + { + "name": "BYPASS", + "description": "LSE oscillator bypassed with an external clock.", + "value": 1 + } + ] + }, + "enum/LSECSSC": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_MODIFIED", + "description": "LSECSSF not modified (default after reset).", + "value": 0 + }, + { + "name": "CLEARED", + "description": "LSECSSF cleared.", + "value": 1 + } + ] + }, + "enum/LSECSSD": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_DETECTED", + "description": "No failure detected on the oscillator (default after reset).", + "value": 0 + }, + { + "name": "DETECTED", + "description": "Failure detected on the oscillator.", + "value": 1 + } + ] + }, + "enum/LSECSSF": { + "bit_size": 1, + "variants": [ + { + "name": "NO_READY", + "description": "no clock ready interrupt caused by the LSE (default after reset).", + "value": 0 + }, + { + "name": "READY", + "description": "clock ready interrupt caused by the LSE.", + "value": 1 + } + ] + }, + "enum/LSECSSIE": { + "bit_size": 1, + "variants": [ + { + "name": "DISABLED", + "description": "LSE CSS interrupt disabled (default after reset).", + "value": 0 + }, + { + "name": "ENABLED", + "description": "LSE CSS interrupt enabled.", + "value": 1 + } + ] + }, + "enum/LSECSSRA": { + "bit_size": 1, + "variants": [ + { + "name": "NO_EFFECT", + "description": "Writing 0 has no effect (default after reset).", + "value": 0 + }, + { + "name": "RE_ARM", + "description": "Writing 1 generates a re-arm pulse for the LSECSS function.", + "value": 1 + } + ] + }, + "enum/LSEDRV": { + "bit_size": 2, + "variants": [ + { + "name": "LOWEST", + "description": "Lowest drive (default after reset).", + "value": 0 + }, + { + "name": "MEDIUM_LOW", + "description": "Medium low drive.", + "value": 1 + }, + { + "name": "MEDIUM_HIGH", + "description": "Medium high drive.", + "value": 2 + }, + { + "name": "HIGHEST", + "description": "Highest drive.", + "value": 3 + } + ] + }, + "enum/LSEEXT": { + "bit_size": 1, + "variants": [ + { + "name": "ANALOG", + "description": "LSE in analog mode (default after reset).", + "value": 0 + }, + { + "name": "DIGITAL", + "description": "LSE in digital mode.", + "value": 1 + } + ] + }, + "enum/LSELOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "LSE configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "LSE configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/LSEPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "LSE configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "LSE configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/LSEPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIVILEGE", + "description": "LSE configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIVILAGE", + "description": "LSE configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/LSERDY": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_READY", + "description": "LSE is not ready (default after reset).", + "value": 0 + }, + { + "name": "READY", + "description": "LSE is ready.", + "value": 1 + } + ] + }, + "enum/LSERDYC": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_MODIFIED", + "description": "LSERDYF not modified (default after reset).", + "value": 0 + }, + { + "name": "CLEARED", + "description": "LSERDYF cleared.", + "value": 1 + } + ] + }, + "enum/LSERDYF": { + "bit_size": 1, + "variants": [ + { + "name": "NO_READY", + "description": "no clock ready interrupt caused by the LSE (default after reset).", + "value": 0 + }, + { + "name": "READY", + "description": "clock ready interrupt caused by the LSE.", + "value": 1 + } + ] + }, + "enum/LSERDYIE": { + "bit_size": 1, + "variants": [ + { + "name": "DISABLED", + "description": "LSE ready interrupt disabled (default after reset).", + "value": 0 + }, + { + "name": "ENABLED", + "description": "LSE ready interrupt enabled.", + "value": 1 + } + ] + }, + "enum/LSESEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "LSE configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "LSE configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/LSILOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "LSI configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "LSI configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/LSIPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "LSI configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "LSI configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/LSIPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIVILEGE", + "description": "LSI configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIVILEGE", + "description": "LSI configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/LSIRDY": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_READY", + "description": "LSI is not ready (default after reset).", + "value": 0 + }, + { + "name": "READY", + "description": "LSI is ready.", + "value": 1 + } + ] + }, + "enum/LSIRDYC": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_MODIFIED", + "description": "LSIRDYF not modified (default after reset).", + "value": 0 + }, + { + "name": "CLEARED", + "description": "LSIRDYF cleared.", + "value": 1 + } + ] + }, + "enum/LSIRDYF": { + "bit_size": 1, + "variants": [ + { + "name": "NO_INTERRUPT", + "description": "no clock ready interrupt caused by the LSI (default after reset).", + "value": 0 + }, + { + "name": "INTERRUPT", + "description": "clock ready interrupt caused by the LSI.", + "value": 1 + } + ] + }, + "enum/LSIRDYIE": { + "bit_size": 1, + "variants": [ + { + "name": "DISABLED", + "description": "LSI ready interrupt disabled (default after reset).", + "value": 0 + }, + { + "name": "ENABLED", + "description": "LSI ready interrupt enabled.", + "value": 1 + } + ] + }, + "enum/LSISEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "LSI configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "LSI configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/LTDCSEL": { + "bit_size": 2, + "variants": [ + { + "name": "PCLK5", + "description": "pclk5 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC16", + "description": "ic16_ck selected as reference clock.", + "value": 2 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 3 + } + ] + }, + "enum/MCOPRE": { + "bit_size": 4, + "variants": [ + { + "name": "DIV1", + "description": "ck_icn_p_mce3 is divided by 1.", + "value": 0 + }, + { + "name": "DIV2", + "description": "ck_icn_p_mce3 is divided by 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "ck_icn_p_mce3 is divided by 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "ck_icn_p_mce3 is divided by 4.", + "value": 3 + }, + { + "name": "DIV16", + "description": "ck_icn_p_mce3 is divided by 16.", + "value": 15 + } + ] + }, + "enum/MCOSEL": { + "bit_size": 3, + "variants": [ + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock (default after reset).", + "value": 0 + }, + { + "name": "LSE", + "description": "lse_ck selected as reference clock.", + "value": 1 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 2 + }, + { + "name": "LSI", + "description": "lsi_ck selected as reference clock.", + "value": 3 + }, + { + "name": "HSE", + "description": "hse_ck selected as reference clock.", + "value": 4 + }, + { + "name": "IC5", + "description": "ic5_ck selected as reference clock.", + "value": 5 + }, + { + "name": "IC10", + "description": "ic10_ck selected as reference clock.", + "value": 6 + }, + { + "name": "SYSA", + "description": "sysa_ck selected as reference clock.", + "value": 7 + } + ] + }, + "enum/MDFSEL": { + "bit_size": 3, + "variants": [ + { + "name": "HCLK2", + "description": "hclk2 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC7", + "description": "ic7_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC8", + "description": "ic8_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + }, + { + "name": "I2S_CKIN", + "description": "I2S_CKIN selected as reference clock.", + "value": 6 + }, + { + "name": "TIMG", + "description": "timg_ck selected as reference clock.", + "value": 7 + } + ] + }, + "enum/MODLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "MOD configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "MOD configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/MODPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "MOD configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "MOD configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/MODPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIVILEGE", + "description": "MOD configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIVILEGE", + "description": "MOD configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/MODSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "MOD configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "MOD configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/MRD": { + "bit_size": 5, + "variants": [ + { + "name": "NO_DELAY", + "description": "No extra delay added by the BOOTROM.", + "value": 0 + }, + { + "name": "100US", + "description": "100 us.", + "value": 1 + }, + { + "name": "200US", + "description": "200 us.", + "value": 2 + }, + { + "name": "500US", + "description": "500 us.", + "value": 3 + }, + { + "name": "1MS", + "description": "1 ms.", + "value": 4 + }, + { + "name": "2MS", + "description": "2 ms.", + "value": 5 + }, + { + "name": "5MS", + "description": "5 ms (default after reset).", + "value": 6 + }, + { + "name": "10MS", + "description": "10 ms.", + "value": 7 + }, + { + "name": "20MS", + "description": "20 ms.", + "value": 8 + }, + { + "name": "50MS", + "description": "50 ms.", + "value": 9 + }, + { + "name": "100MS", + "description": "100 ms.", + "value": 10 + }, + { + "name": "200MS", + "description": "200 ms.", + "value": 11 + }, + { + "name": "500MS", + "description": "500 ms.", + "value": 12 + }, + { + "name": "1S", + "description": "1 s.", + "value": 13 + }, + { + "name": "2S", + "description": "2 s.", + "value": 14 + }, + { + "name": "3S", + "description": "5 s.", + "value": 15 + } + ] + }, + "enum/MSIFREQSEL": { + "bit_size": 1, + "variants": [ + { + "name": "4MHZ", + "description": "MSI oscillator frequency is 4 MHz (default after backup domain reset).", + "value": 0 + }, + { + "name": "16MHZ", + "description": "MSI oscillator frequency is 16 MHz.", + "value": 1 + } + ] + }, + "enum/MSILOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "MSI configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "MSI configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/MSIPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUB", + "description": "MSI configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUB", + "description": "MSI configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/MSIPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIVILEGE", + "description": "MSI configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIVILEGE", + "description": "MSI configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/MSIRDY": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_READY", + "description": "MSI is not ready (default after reset).", + "value": 0 + }, + { + "name": "READY", + "description": "MSI is ready.", + "value": 1 + } + ] + }, + "enum/MSIRDYC": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_MODIFIED", + "description": "MSIRDYF not modified (default after reset).", + "value": 0 + }, + { + "name": "CLEARED", + "description": "MSIRDYF cleared.", + "value": 1 + } + ] + }, + "enum/MSIRDYF": { + "bit_size": 1, + "variants": [ + { + "name": "NO_INTERRUPT", + "description": "no clock ready interrupt caused by the MSI (default after reset).", + "value": 0 + }, + { + "name": "INTERRUPT", + "description": "clock ready interrupt caused by the MSI.", + "value": 1 + } + ] + }, + "enum/MSIRDYIE": { + "bit_size": 1, + "variants": [ + { + "name": "DISABLED", + "description": "MSI ready interrupt disabled (default after reset).", + "value": 0 + }, + { + "name": "ENABLED", + "description": "MSI ready interrupt enabled.", + "value": 1 + } + ] + }, + "enum/MSISEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "MSI configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "MSI configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/NOCLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "NOC configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "NOC configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/NOCPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "NOC configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "NOC configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/NOCPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIVILEGE", + "description": "NOC configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIVILEGE", + "description": "NOC configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/NOCSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "NOC configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "NOC configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/NPUCACHERAMPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "NPUCACHERAM configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "NPUCACHERAM configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/OTGPHYSEL": { + "bit_size": 2, + "variants": [ + { + "name": "HSE", + "description": "hse_ck selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC15", + "description": "ic15_ck selected as reference clock.", + "value": 2 + }, + { + "name": "HSE_DIV2_OSC", + "description": "hse_div2_osc_ck selected as reference clock.", + "value": 3 + } + ] + }, + "enum/PERLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "PER configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "PER configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/PERPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "PER configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "PER configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/PERPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIVILEGE", + "description": "PER configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIVILEGE", + "description": "PER configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/PERSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "PER configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "PER configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/PERSEL": { + "bit_size": 3, + "variants": [ + { + "name": "HSI", + "description": "hsi_ck selected as reference clock.", + "value": 0 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 1 + }, + { + "name": "HSE", + "description": "hse_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC19", + "description": "ic19_ck selected as reference clock.", + "value": 3 + }, + { + "name": "IC5", + "description": "ic5_ck selected as reference clock.", + "value": 4 + }, + { + "name": "IC10", + "description": "ic10_ck selected as reference clock.", + "value": 5 + }, + { + "name": "IC15", + "description": "ic15_ck selected as reference clock.", + "value": 6 + }, + { + "name": "IC20", + "description": "ic20_ck selected as reference clock.", + "value": 7 + } + ] + }, + "enum/PLLBYP": { + "bit_size": 1, + "variants": [ + { + "name": "VCO_POSTDIV", + "description": "PLL output is driven by the VCO, via the optional POSTDIV division.", + "value": 0 + }, + { + "name": "BYPASS", + "description": "PLL output is bypassed and driven by the PLL reference clock (default after reset).", + "value": 1 + } + ] + }, + "enum/PLLDIVM": { + "bit_size": 6, + "variants": [ + { + "name": "NOT_APPLICABLE", + "description": "Not applicable when PLL is enabled.", + "value": 0 + }, + { + "name": "DIV1", + "description": "reference clock is divided by 1 (min value).", + "value": 1 + }, + { + "name": "DIV2", + "description": "reference clock is divided by 2.", + "value": 2 + }, + { + "name": "DIV63", + "description": "reference clock is divided by 63.", + "value": 63 + } + ] + }, + "enum/PLLLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "PLL1 configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "PLL1 configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/PLLMODSPRDW": { + "bit_size": 1, + "variants": [ + { + "name": "CENTER_SPREAD", + "description": "Center-spread modulation selected (default after reset).", + "value": 0 + }, + { + "name": "DOWN_SPREAD", + "description": "Down-spread modulation selected.", + "value": 1 + } + ] + }, + "enum/PLLMODSSDIS": { + "bit_size": 1, + "variants": [ + { + "name": "MODULATION_SPREAD_SPECTRUM", + "description": "Modulation Spread-Spectrum is active (and Fractional Divide inactive).", + "value": 0 + }, + { + "name": "FRACTIONAL_DIVIDE", + "description": "Fractional Divide is active (and the Modulation Spread-Spectrum inactive) (default after reset).", + "value": 1 + } + ] + }, + "enum/PLLPDIV": { + "bit_size": 3, + "variants": [ + { + "name": "NOT_APPLICABLE", + "description": "Not applicable.", + "value": 0 + }, + { + "name": "DIV1", + "description": "VCO output is divided by 1 (minimum value) (default after reset).", + "value": 1 + }, + { + "name": "DIV7", + "description": "VCO output is divided by 7.", + "value": 7 + } + ] + }, + "enum/PLLPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "PLL1 configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "PLL1 configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/PLLPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIVILEGE", + "description": "PLL1 configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIVILEGE", + "description": "PLL1 configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/PLLRDY": { + "bit_size": 1, + "variants": [ + { + "name": "UNLOCKED", + "description": "PLL1 unlocked (default after reset).", + "value": 0 + }, + { + "name": "LOCKED", + "description": "PLL1 locked.", + "value": 1 + } + ] + }, + "enum/PLLRDYC": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_MODIFIED", + "description": "PLL1RDYF not modified (default after reset).", + "value": 0 + }, + { + "name": "CLEARED", + "description": "PLL1RDYF cleared.", + "value": 1 + } + ] + }, + "enum/PLLRDYF": { + "bit_size": 1, + "variants": [ + { + "name": "NO_INTERRUPT", + "description": "no clock ready interrupt caused by the PLL1 (default after reset).", + "value": 0 + }, + { + "name": "INTERRUPT", + "description": "clock ready interrupt caused by the PLL1.", + "value": 1 + } + ] + }, + "enum/PLLRDYIE": { + "bit_size": 1, + "variants": [ + { + "name": "DISABLED", + "description": "PLL1 lock interrupt disabled (default after reset).", + "value": 0 + }, + { + "name": "ENABLED", + "description": "PLL1 lock interrupt enabled.", + "value": 1 + } + ] + }, + "enum/PLLSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "PLL1 configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "PLL1 configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/PLLSEL": { + "bit_size": 3, + "variants": [ + { + "name": "HSI", + "description": "hsi_ck selected as reference clock.", + "value": 0 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 1 + }, + { + "name": "HSE", + "description": "hse_ck selected as reference clock.", + "value": 2 + }, + { + "name": "I2S_CKIN", + "description": "I2S_CKIN selected as reference clock.", + "value": 3 + } + ] + }, + "enum/PPRE": { + "bit_size": 3, + "variants": [ + { + "name": "DIV1", + "description": "rcc_pclk1 = sys_bus2_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "rcc_pclk1 = sys_bus2_ck / 2.", + "value": 1 + }, + { + "name": "DIV4", + "description": "rcc_pclk1 = sys_bus2_ck / 4.", + "value": 2 + }, + { + "name": "DIV8", + "description": "rcc_pclk1 = sys_bus2_ck / 8.", + "value": 3 + }, + { + "name": "DIV16", + "description": "rcc_pclk1 = sys_bus2_ck / 16.", + "value": 4 + }, + { + "name": "DIV32", + "description": "rcc_pclk1 = sys_bus2_ck / 32.", + "value": 5 + }, + { + "name": "DIV64", + "description": "rcc_pclk1 = sys_bus2_ck / 64.", + "value": 6 + }, + { + "name": "DIV128", + "description": "rcc_pclk1 = sys_bus2_ck / 128.", + "value": 7 + } + ] + }, + "enum/PSSISEL": { + "bit_size": 2, + "variants": [ + { + "name": "HCLK5", + "description": "hclk5 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC20", + "description": "ic20_ck selected as reference clock.", + "value": 2 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 3 + } + ] + }, + "enum/RSR_BORRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "ABSENCE", + "description": "no BOR occurred.", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "BOR occurred (default after power-on reset).", + "value": 1 + } + ] + }, + "enum/RSR_IWDGRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "ABSENCE", + "description": "no Independent Watchdog reset occurred (default after power-on reset).", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "Independent Watchdog reset occurred.", + "value": 1 + } + ] + }, + "enum/RSR_LCKRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "ABSENCE", + "description": "No reset from CPU lockup occurred.", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "Reset from CPU lockup occurred.", + "value": 1 + } + ] + }, + "enum/RSR_LPWRRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "ABSENCE", + "description": "no illegal reset occurred (default after power-on reset).", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "illegal Stop or Standby reset occurred.", + "value": 1 + } + ] + }, + "enum/RSR_PINRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "ABSENCE", + "description": "no reset from Pin occurred.", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "Reset from Pin occurred (default after power-on reset).", + "value": 1 + } + ] + }, + "enum/RSR_PORRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "ABSENCE", + "description": "no POR/PDR reset occurred.", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "POR/PDR reset occurred (default after power-on reset).", + "value": 1 + } + ] + }, + "enum/RSR_RMVF": { + "bit_size": 1, + "variants": [ + { + "name": "NO_CLEAR", + "description": "clear of the reset flags not activated (default after power-on reset).", + "value": 0 + }, + { + "name": "CLEAR", + "description": "clear the value of the reset flags.", + "value": 1 + } + ] + }, + "enum/RSR_SFTRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "ABSENCE", + "description": "no Software System reset occurred (default after power-on reset).", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "a Software System reset has been generated by the CPU.", + "value": 1 + } + ] + }, + "enum/RSR_WWDGRSTF": { + "bit_size": 1, + "variants": [ + { + "name": "ABSENCE", + "description": "no Window Watchdog reset occurred from WWDG (default after power-on reset).", + "value": 0 + }, + { + "name": "OCCURRED", + "description": "Window Watchdog reset occurred from WWDG.", + "value": 1 + } + ] + }, + "enum/RSTLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "RST configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "RST configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/RSTPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "RST configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "RST configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/RSTPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIVILEGE", + "description": "RST configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIVILEGE", + "description": "RST configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/RSTSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "RST configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "RST configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/RTCPRE": { + "bit_size": 6, + "variants": [ + { + "name": "DIV1", + "description": "ck_icn_p_risaf is divided by 1.", + "value": 0 + }, + { + "name": "DIV2", + "description": "ck_icn_p_risaf is divided by 2.", + "value": 1 + }, + { + "name": "DIV3", + "description": "ck_icn_p_risaf is divided by 3.", + "value": 2 + }, + { + "name": "DIV4", + "description": "ck_icn_p_risaf is divided by 4.", + "value": 3 + }, + { + "name": "DIV64", + "description": "ck_icn_p_risaf is divided by 64.", + "value": 63 + } + ] + }, + "enum/RTCSEL": { + "bit_size": 2, + "variants": [ + { + "name": "LSE", + "description": "lse_ck selected as reference clock.", + "value": 1 + }, + { + "name": "LSI", + "description": "lsi_ck selected as reference clock.", + "value": 2 + }, + { + "name": "HSE_RTC", + "description": "hse_rtc_ck selected as reference clock.", + "value": 3 + } + ] + }, + "enum/SAISEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK2", + "description": "pclk2 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC7", + "description": "ic7_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC8", + "description": "ic8_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + }, + { + "name": "I2S_CKIN", + "description": "I2S_CKIN selected as reference clock.", + "value": 6 + }, + { + "name": "SPDIF_SYMB", + "description": "spdif_symb_ck selected as reference clock.", + "value": 7 + } + ] + }, + "enum/SDMMCSEL": { + "bit_size": 2, + "variants": [ + { + "name": "HCLKU", + "description": "hclku selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC4", + "description": "ic4_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC5", + "description": "ic5_ck selected as reference clock.", + "value": 3 + } + ] + }, + "enum/SPDIFRXSEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK1", + "description": "pclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC7", + "description": "ic7_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC8", + "description": "ic8_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + }, + { + "name": "I2S_CKIN", + "description": "I2S_CKIN selected as reference clock.", + "value": 6 + } + ] + }, + "enum/SPISEL1": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK2", + "description": "pclk2 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC8", + "description": "ic8_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC9", + "description": "ic9_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + }, + { + "name": "I2S_CKIN", + "description": "I2S_CKIN selected as reference clock.", + "value": 6 + } + ] + }, + "enum/SPISEL23": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK1", + "description": "pclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC8", + "description": "ic8_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC9", + "description": "ic9_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + }, + { + "name": "I2S_CKIN", + "description": "I2S_CKIN selected as reference clock.", + "value": 6 + } + ] + }, + "enum/SPISEL45": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK2", + "description": "pclk2 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC9", + "description": "ic9_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC14", + "description": "ic14_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + }, + { + "name": "I2S_CKIN", + "description": "I2S_CKIN selected as reference clock.", + "value": 6 + } + ] + }, + "enum/SPISEL6": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK4", + "description": "pclk2 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC8", + "description": "ic8_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC9", + "description": "ic9_ck selected as reference clock.", + "value": 3 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 4 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 5 + }, + { + "name": "I2S_CKIN", + "description": "I2S_CKIN selected as reference clock.", + "value": 6 + } + ] + }, + "enum/STOPWUCK": { + "bit_size": 1, + "variants": [ + { + "name": "HSI", + "description": "HSI selected as wake up clock from system Stop (default after reset).", + "value": 0 + }, + { + "name": "CSI", + "description": "CSI selected as wake up clock from system Stop.", + "value": 1 + } + ] + }, + "enum/SYSLOCK": { + "bit_size": 1, + "variants": [ + { + "name": "NON_LOCK", + "description": "SYS configuration bits are accessible by non-lock software only (default after reset).", + "value": 0 + }, + { + "name": "LOCK", + "description": "SYS configuration bits are accessible by lock software only.", + "value": 1 + } + ] + }, + "enum/SYSPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "SYS configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "SYS configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/SYSPV": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PRIVILEGE", + "description": "SYS configuration bits are accessible by non-privilege software only (default after reset).", + "value": 0 + }, + { + "name": "PRIVILEGE", + "description": "SYS configuration bits are accessible by privilege software only.", + "value": 1 + } + ] + }, + "enum/SYSSEC": { + "bit_size": 1, + "variants": [ + { + "name": "NON_SECURE", + "description": "SYS configuration bits are accessible by non-secure software only (default after reset).", + "value": 0 + }, + { + "name": "SECURE", + "description": "SYS configuration bits are accessible by secure software only.", + "value": 1 + } + ] + }, + "enum/SYSSW": { + "bit_size": 2, + "variants": [ + { + "name": "HSI", + "description": "hsi_ck selected as system clock (default after reset).", + "value": 0 + }, + { + "name": "MSI", + "description": "msi_ck selected as system clock.", + "value": 1 + }, + { + "name": "HSE", + "description": "hse_ck selected as system clock.", + "value": 2 + }, + { + "name": "IC2", + "description": "ic2_ck selected as system clock.", + "value": 3 + } + ] + }, + "enum/SYSSWS": { + "bit_size": 2, + "variants": [ + { + "name": "HSI", + "description": "hsi_ck selected as system clock (default after reset).", + "value": 0 + }, + { + "name": "MSI", + "description": "msi_ck selected as system clock.", + "value": 1 + }, + { + "name": "HSE", + "description": "hse_ck selected as system clock.", + "value": 2 + }, + { + "name": "IC2", + "description": "ic2_ck selected as system clock.", + "value": 3 + } + ] + }, + "enum/TIMPRE": { + "bit_size": 2, + "variants": [ + { + "name": "DIV1", + "description": "timg_ck = sys_bus_ck (default after reset).", + "value": 0 + }, + { + "name": "DIV2", + "description": "timg_ck = sys_bus_ck / 2.", + "value": 1 + }, + { + "name": "DIV4", + "description": "timg_ck = sys_bus_ck / 4.", + "value": 2 + } + ] + }, + "enum/UARTSEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK1", + "description": "pclk1 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC9", + "description": "ic9_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC14", + "description": "ic14_ck selected as reference clock.", + "value": 3 + }, + { + "name": "LSE", + "description": "lse_ck selected as reference clock.", + "value": 4 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 5 + }, + { + "name": "HSI", + "description": "hsi_div_ck selected as reference clock.", + "value": 6 + } + ] + }, + "enum/USARTSEL": { + "bit_size": 3, + "variants": [ + { + "name": "PCLK2", + "description": "pclk2 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC9", + "description": "ic9_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC14", + "description": "ic14_ck selected as reference clock.", + "value": 3 + }, + { + "name": "LSE", + "description": "lse_ck selected as reference clock.", + "value": 4 + }, + { + "name": "MSI", + "description": "msi_ck selected as reference clock.", + "value": 5 + }, + { + "name": "HSI_DIV", + "description": "hsi_div_ck selected as reference clock.", + "value": 6 + } + ] + }, + "enum/VENCRAMPUB": { + "bit_size": 1, + "variants": [ + { + "name": "NON_PUBLIC", + "description": "VENCRAM configuration bits are accessible by non-public software only (default after reset).", + "value": 0 + }, + { + "name": "PUBLIC", + "description": "VENCRAM configuration bits are accessible by public software only.", + "value": 1 + } + ] + }, + "enum/WKUPF": { + "bit_size": 1, + "variants": [ + { + "name": "NO_INTERRUPT", + "description": "no wakeup interrupt caused by the PWR (default after reset).", + "value": 0 + }, + { + "name": "INTERRUPT", + "description": "wakeup interrupt caused by the PWR.", + "value": 1 + } + ] + }, + "enum/WKUPFC": { + "bit_size": 1, + "variants": [ + { + "name": "NOT_MODIFIED", + "description": "WKUPF not modified (default after reset).", + "value": 0 + }, + { + "name": "CLEARED", + "description": "WKUPF cleared.", + "value": 1 + } + ] + }, + "enum/WKUPIE": { + "bit_size": 1, + "variants": [ + { + "name": "DISABLED", + "description": "Wakeup interrupt disabled (default after reset).", + "value": 0 + }, + { + "name": "ENABLED", + "description": "Wakeup interrupt enabled.", + "value": 1 + } + ] + }, + "enum/XSPISEL": { + "bit_size": 2, + "variants": [ + { + "name": "HCLK5", + "description": "hclk5 selected as reference clock.", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as reference clock.", + "value": 1 + }, + { + "name": "IC3", + "description": "ic3_ck selected as reference clock.", + "value": 2 + }, + { + "name": "IC4", + "description": "ic4_ck selected as reference clock.", + "value": 3 + } + ] + }, + "enum/XSPISELS": { + "bit_size": 2, + "variants": [ + { + "name": "HCLK5", + "description": "hclk5 selected as XSPI1 clock (default after reset).", + "value": 0 + }, + { + "name": "PER", + "description": "per_ck selected as XSPI1 clock.", + "value": 1 + }, + { + "name": "IC3", + "description": "ic3_ck selected as XSPI1 clock.", + "value": 2 + }, + { + "name": "IC4", + "description": "ic4_ck selected as XSPI1 clock.", + "value": 3 + } + ] + } +} \ No newline at end of file