diff --git a/data/chips/STM32H503CB.json b/data/chips/STM32H503CB.json index fbefc3c..0be03e5 100644 --- a/data/chips/STM32H503CB.json +++ b/data/chips/STM32H503CB.json @@ -1255,8 +1255,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1415,8 +1415,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32H503EB.json b/data/chips/STM32H503EB.json index a181494..80a7df7 100644 --- a/data/chips/STM32H503EB.json +++ b/data/chips/STM32H503EB.json @@ -1143,8 +1143,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1268,8 +1268,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32H503KB.json b/data/chips/STM32H503KB.json index 2646762..4b0e41b 100644 --- a/data/chips/STM32H503KB.json +++ b/data/chips/STM32H503KB.json @@ -1192,8 +1192,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1337,8 +1337,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32H503RB.json b/data/chips/STM32H503RB.json index a7abe33..ef4943c 100644 --- a/data/chips/STM32H503RB.json +++ b/data/chips/STM32H503RB.json @@ -1405,8 +1405,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1575,8 +1575,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index 19e7bf8..f3a2ca5 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -2659,8 +2659,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2804,8 +2804,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2929,8 +2929,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3069,8 +3069,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3127,8 +3127,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3257,8 +3257,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index 8091019..5fd3c51 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -2670,8 +2670,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2815,8 +2815,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2940,8 +2940,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3080,8 +3080,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3138,8 +3138,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3268,8 +3268,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index 23a5abc..9800688 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -2688,8 +2688,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2833,8 +2833,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2958,8 +2958,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3098,8 +3098,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3156,8 +3156,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3286,8 +3286,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index ba0c379..7d9d607 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -2699,8 +2699,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2844,8 +2844,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2969,8 +2969,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3109,8 +3109,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3167,8 +3167,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3297,8 +3297,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index 781f923..9b4d002 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -1765,8 +1765,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1860,8 +1860,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1975,8 +1975,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2085,8 +2085,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2123,8 +2123,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2193,8 +2193,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index d6f922a..d360af4 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -1776,8 +1776,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1871,8 +1871,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1986,8 +1986,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2096,8 +2096,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2134,8 +2134,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2204,8 +2204,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index ebde387..275bb47 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -2195,8 +2195,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2300,8 +2300,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2420,8 +2420,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2530,8 +2530,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2578,8 +2578,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2648,8 +2648,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index f619f19..105236c 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -2206,8 +2206,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2311,8 +2311,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2431,8 +2431,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2541,8 +2541,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2589,8 +2589,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2659,8 +2659,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index 44536a8..8128163 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -2469,8 +2469,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2599,8 +2599,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2719,8 +2719,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2859,8 +2859,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2917,8 +2917,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3047,8 +3047,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index 3337199..73b13de 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -2480,8 +2480,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2610,8 +2610,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2730,8 +2730,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2870,8 +2870,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2928,8 +2928,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3058,8 +3058,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index a591b7d..a7a04b9 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -2932,8 +2932,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3077,8 +3077,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3202,8 +3202,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3342,8 +3342,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3400,8 +3400,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3530,8 +3530,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index 6092598..c9aba64 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -2962,8 +2962,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3107,8 +3107,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3232,8 +3232,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3372,8 +3372,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3430,8 +3430,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3560,8 +3560,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 88f8d00..1433b65 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -2966,8 +2966,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3111,8 +3111,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3236,8 +3236,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3376,8 +3376,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3434,8 +3434,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3564,8 +3564,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index 9f26c10..73dc92d 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -2985,8 +2985,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3130,8 +3130,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3255,8 +3255,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3395,8 +3395,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3453,8 +3453,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3583,8 +3583,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index e93d8fd..deda488 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -2149,8 +2149,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2234,8 +2234,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2324,8 +2324,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2434,8 +2434,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2472,8 +2472,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2542,8 +2542,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index 445c61b..a3dc5f2 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -1983,8 +1983,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2078,8 +2078,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2193,8 +2193,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2303,8 +2303,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2341,8 +2341,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2411,8 +2411,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index de93dd1..db121c4 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -1994,8 +1994,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2089,8 +2089,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2204,8 +2204,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2314,8 +2314,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2352,8 +2352,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2422,8 +2422,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index 8597be5..dc00ca1 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -2418,8 +2418,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2523,8 +2523,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2643,8 +2643,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2753,8 +2753,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2801,8 +2801,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2871,8 +2871,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index cf791fb..86e06c5 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -2443,8 +2443,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2548,8 +2548,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2673,8 +2673,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2783,8 +2783,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2831,8 +2831,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2901,8 +2901,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index 59c3032..969fb9e 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -2717,8 +2717,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2847,8 +2847,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2967,8 +2967,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3107,8 +3107,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3165,8 +3165,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3295,8 +3295,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index 4a54094..9586e4e 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -2757,8 +2757,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2892,8 +2892,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3017,8 +3017,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3157,8 +3157,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3215,8 +3215,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3345,8 +3345,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 6d8bd7b..a33ed64 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -3021,8 +3021,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3166,8 +3166,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3291,8 +3291,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3431,8 +3431,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3489,8 +3489,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3619,8 +3619,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index 9494755..e771eda 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -3044,8 +3044,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3189,8 +3189,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3314,8 +3314,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3454,8 +3454,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3512,8 +3512,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3642,8 +3642,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index 8a03d19..6f49ddb 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -2208,8 +2208,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2293,8 +2293,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2383,8 +2383,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2493,8 +2493,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2531,8 +2531,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2601,8 +2601,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index 3386f3b..10c5d4f 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -2053,8 +2053,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2148,8 +2148,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2263,8 +2263,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2373,8 +2373,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2411,8 +2411,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2481,8 +2481,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index 69a5bb5..5b102c5 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -2502,8 +2502,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2607,8 +2607,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2732,8 +2732,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2842,8 +2842,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2890,8 +2890,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2960,8 +2960,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index c3105bb..548553e 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -2816,8 +2816,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2951,8 +2951,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3076,8 +3076,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3216,8 +3216,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3274,8 +3274,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3404,8 +3404,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2h5", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/registers/lptim_v2h5.json b/data/registers/lptim_v2h5.json new file mode 100644 index 0000000..20e48b9 --- /dev/null +++ b/data/registers/lptim_v2h5.json @@ -0,0 +1,1120 @@ +{ + "block/IC": { + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR_IC" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR_IC" + }, + { + "name": "DIER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "DIER_IC" + } + ] + }, + "block/LPTIM_ADV": { + "extends": "LPTIM_BASIC", + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "InputCapture", + "byte_offset": 0, + "block": "IC" + }, + { + "name": "OutputCompare", + "byte_offset": 0, + "block": "OC_ADV" + }, + { + "name": "CCR", + "description": "LPTIM compare register 1.", + "array": { + "len": 2, + "stride": 32 + }, + "byte_offset": 20, + "fieldset": "CCR" + }, + { + "name": "CCMR_IC", + "description": "LPTIM capture/compare mode register 1.", + "byte_offset": 44, + "fieldset": "CCMR_IC" + }, + { + "name": "CCMR_OC", + "description": "LPTIM capture/compare mode register 1.", + "byte_offset": 44, + "fieldset": "CCMR_OC" + } + ] + }, + "block/LPTIM_BASIC": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "OutputCompare", + "byte_offset": 0, + "block": "OC_BASIC" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CCR", + "description": "LPTIM compare register 1.", + "array": { + "len": 1, + "stride": 32 + }, + "byte_offset": 20, + "fieldset": "CCR" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "CFGR2", + "description": "LPTIM configuration register 2.", + "byte_offset": 36, + "fieldset": "CFGR2" + }, + { + "name": "RCR", + "description": "LPTIM repetition register.", + "byte_offset": 40, + "fieldset": "RCR" + } + ] + }, + "block/OC_ADV": { + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR_OC_ADV" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR_OC_ADV" + }, + { + "name": "DIER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "DIER_OC_ADV" + } + ] + }, + "block/OC_BASIC": { + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR_OC_BASIC" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR_OC_BASIC" + }, + { + "name": "DIER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "DIER_OC_BASIC" + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CCMR_IC": { + "extends": "CCMR_partial", + "description": "LPTIM input capture mode register 1.", + "fields": [ + { + "name": "CCP", + "description": "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.", + "bit_offset": 2, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "CCP_IC" + } + ] + }, + "fieldset/CCMR_OC": { + "extends": "CCMR_partial", + "description": "LPTIM output compare mode register 1.", + "fields": [ + { + "name": "CCP", + "description": "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.", + "bit_offset": 2, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "CCP_OC" + } + ] + }, + "fieldset/CCMR_partial": { + "description": "internal use only - common fields between CCMR input mode and output mode", + "fields": [ + { + "name": "CCSEL", + "description": "Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "CCSEL" + }, + { + "name": "CCE", + "description": "Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not.", + "bit_offset": 1, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + }, + { + "name": "ICPSC", + "description": "Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).", + "bit_offset": 8, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "Filter" + }, + { + "name": "ICF", + "description": "Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 12, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "Filter" + } + ] + }, + "fieldset/CCR": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CCR", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "CKSEL" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": 13, + "bit_size": 3 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR2": { + "description": "LPTIM configuration register 2.", + "fields": [ + { + "name": "INSEL", + "description": "LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to.", + "bit_offset": 0, + "bit_size": 2, + "array": { + "len": 2, + "stride": 4 + } + }, + { + "name": "ICSEL", + "description": "LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to.", + "bit_offset": 16, + "bit_size": 2, + "array": { + "len": 2, + "stride": 4 + } + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "COUNTRST", + "description": "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "RSTARE", + "description": "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/DIER_IC": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UEIE", + "description": "Update event interrupt enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKIE", + "description": "Repetition register update OK interrupt Enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "CCOIE", + "description": "Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 12, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, + { + "name": "CCDE", + "description": "Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 16, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "UEDE", + "description": "Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 23, + "bit_size": 1 + } + ] + }, + "fieldset/DIER_OC_ADV": { + "extends": "DIER_OC_BASIC", + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + } + ] + }, + "fieldset/DIER_OC_BASIC": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UEIE", + "description": "Update event interrupt enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKIE", + "description": "Repetition register update OK interrupt Enable.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/ICR_IC": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UECF", + "description": "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKCF", + "description": "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "CCOCF", + "description": "Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 12, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, + { + "name": "DIEROKCF", + "description": "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/ICR_OC_ADV": { + "extends": "ICR_OC_BASIC", + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + } + ] + }, + "fieldset/ICR_OC_BASIC": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UECF", + "description": "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKCF", + "description": "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "DIEROKCF", + "description": "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/ISR_IC": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "capture 1 interrupt flag If channel CC1 is configured as input: CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UE", + "description": "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOK", + "description": "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "CCOF", + "description": "Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 12, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, + { + "name": "DIEROK", + "description": "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/ISR_OC_ADV": { + "extends": "ISR_OC_BASIC", + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + } + ] + }, + "fieldset/ISR_OC_BASIC": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UE", + "description": "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOK", + "description": "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "DIEROK", + "description": "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/RCR": { + "description": "LPTIM repetition register.", + "fields": [ + { + "name": "REP", + "description": "Repetition register value REP is the repetition value for the LPTIM.", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "enum/CCP_IC": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "value": 0 + }, + { + "name": "Falling", + "value": 1 + }, + { + "name": "Both", + "value": 3 + } + ] + }, + "enum/CCP_OC": { + "bit_size": 2, + "variants": [ + { + "name": "ActiveHigh", + "value": 0 + }, + { + "name": "ActiveLow", + "value": 1 + } + ] + }, + "enum/CCSEL": { + "bit_size": 1, + "variants": [ + { + "name": "OutputCompare", + "description": "channel is configured in output PWM mode", + "value": 0 + }, + { + "name": "InputCapture", + "description": "channel is configured in input capture mode", + "value": 1 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/CKSEL": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "LPTIM is clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + } +} \ No newline at end of file