diff --git a/data/chips/STM32U031C6.json b/data/chips/STM32U031C6.json index 590d02d..409932c 100644 --- a/data/chips/STM32U031C6.json +++ b/data/chips/STM32U031C6.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,11 +119,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -184,6 +199,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -200,6 +220,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1279,6 +1304,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2261,6 +2291,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031C8.json b/data/chips/STM32U031C8.json index e3e122f..2620760 100644 --- a/data/chips/STM32U031C8.json +++ b/data/chips/STM32U031C8.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,11 +119,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -184,6 +199,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -200,6 +220,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1279,6 +1304,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2261,6 +2291,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031F4.json b/data/chips/STM32U031F4.json index 117db70..098cce9 100644 --- a/data/chips/STM32U031F4.json +++ b/data/chips/STM32U031F4.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -171,6 +186,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -187,6 +207,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1165,6 +1190,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2019,6 +2049,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031F6.json b/data/chips/STM32U031F6.json index 27768d4..a423cbe 100644 --- a/data/chips/STM32U031F6.json +++ b/data/chips/STM32U031F6.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -171,6 +186,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -187,6 +207,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1165,6 +1190,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2019,6 +2049,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031F8.json b/data/chips/STM32U031F8.json index 95cc607..e68c338 100644 --- a/data/chips/STM32U031F8.json +++ b/data/chips/STM32U031F8.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -171,6 +186,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -187,6 +207,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1165,6 +1190,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2019,6 +2049,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031G6.json b/data/chips/STM32U031G6.json index 1843d8a..3686791 100644 --- a/data/chips/STM32U031G6.json +++ b/data/chips/STM32U031G6.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -171,6 +186,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -187,6 +207,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1120,6 +1145,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -1954,6 +1984,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031G8.json b/data/chips/STM32U031G8.json index 01dd54d..1625758 100644 --- a/data/chips/STM32U031G8.json +++ b/data/chips/STM32U031G8.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -171,6 +186,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -187,6 +207,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1120,6 +1145,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -1954,6 +1984,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031K4.json b/data/chips/STM32U031K4.json index 594b714..9e7c1e6 100644 --- a/data/chips/STM32U031K4.json +++ b/data/chips/STM32U031K4.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -171,6 +186,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -187,6 +207,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1150,6 +1175,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2019,6 +2049,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031K6.json b/data/chips/STM32U031K6.json index 3e9f997..ae3de90 100644 --- a/data/chips/STM32U031K6.json +++ b/data/chips/STM32U031K6.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -171,6 +186,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -187,6 +207,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1150,6 +1175,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2019,6 +2049,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031K8.json b/data/chips/STM32U031K8.json index 1173b29..eb8e685 100644 --- a/data/chips/STM32U031K8.json +++ b/data/chips/STM32U031K8.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -171,6 +186,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -187,6 +207,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1150,6 +1175,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2019,6 +2049,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031R6.json b/data/chips/STM32U031R6.json index a206148..11dba31 100644 --- a/data/chips/STM32U031R6.json +++ b/data/chips/STM32U031R6.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,11 +143,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -220,6 +235,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -236,6 +256,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1399,6 +1424,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2420,6 +2450,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U031R8.json b/data/chips/STM32U031R8.json index 4f7f5f5..ca30659 100644 --- a/data/chips/STM32U031R8.json +++ b/data/chips/STM32U031R8.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,11 +143,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -220,6 +235,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -236,6 +256,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1399,6 +1424,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2420,6 +2450,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", diff --git a/data/chips/STM32U073C8.json b/data/chips/STM32U073C8.json index 0beee34..1fea783 100644 --- a/data/chips/STM32U073C8.json +++ b/data/chips/STM32U073C8.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,11 +119,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -184,6 +199,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -248,6 +268,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -264,6 +289,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -287,6 +317,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1869,6 +1904,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2917,6 +2957,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3415,6 +3460,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3462,7 +3512,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073CB.json b/data/chips/STM32U073CB.json index 1609657..662f893 100644 --- a/data/chips/STM32U073CB.json +++ b/data/chips/STM32U073CB.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,11 +119,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -184,6 +199,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -248,6 +268,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -264,6 +289,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -287,6 +317,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1869,6 +1904,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2917,6 +2957,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3415,6 +3460,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3462,7 +3512,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073CC.json b/data/chips/STM32U073CC.json index 1e3d8a1..4df5c89 100644 --- a/data/chips/STM32U073CC.json +++ b/data/chips/STM32U073CC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,11 +119,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -184,6 +199,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -248,6 +268,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -264,6 +289,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -287,6 +317,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1869,6 +1904,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2917,6 +2957,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3415,6 +3460,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3462,7 +3512,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073H8.json b/data/chips/STM32U073H8.json index 2b8e23c..35c69b2 100644 --- a/data/chips/STM32U073H8.json +++ b/data/chips/STM32U073H8.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -180,6 +195,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -239,6 +259,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -255,6 +280,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -278,6 +308,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1751,6 +1786,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2720,6 +2760,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3163,6 +3208,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3210,7 +3260,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073HB.json b/data/chips/STM32U073HB.json index e0f5ae2..3ab1242 100644 --- a/data/chips/STM32U073HB.json +++ b/data/chips/STM32U073HB.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -180,6 +195,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -239,6 +259,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -255,6 +280,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -278,6 +308,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1751,6 +1786,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2720,6 +2760,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3163,6 +3208,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3210,7 +3260,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073HC.json b/data/chips/STM32U073HC.json index e996fd2..778a80e 100644 --- a/data/chips/STM32U073HC.json +++ b/data/chips/STM32U073HC.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -180,6 +195,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -239,6 +259,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -255,6 +280,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -278,6 +308,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1751,6 +1786,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2720,6 +2760,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3163,6 +3208,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3210,7 +3260,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073K8.json b/data/chips/STM32U073K8.json index cf03d77..337ebc7 100644 --- a/data/chips/STM32U073K8.json +++ b/data/chips/STM32U073K8.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -171,6 +186,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -230,6 +250,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -246,6 +271,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -269,6 +299,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1655,6 +1690,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2590,6 +2630,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3018,6 +3063,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3065,7 +3115,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073KB.json b/data/chips/STM32U073KB.json index f83bf2d..faa31b7 100644 --- a/data/chips/STM32U073KB.json +++ b/data/chips/STM32U073KB.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -171,6 +186,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -230,6 +250,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -246,6 +271,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -269,6 +299,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1655,6 +1690,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2590,6 +2630,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3018,6 +3063,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3065,7 +3115,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073KC.json b/data/chips/STM32U073KC.json index 94c96ce..f96fae8 100644 --- a/data/chips/STM32U073KC.json +++ b/data/chips/STM32U073KC.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -171,6 +186,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -230,6 +250,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -246,6 +271,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -269,6 +299,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1655,6 +1690,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2590,6 +2630,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3018,6 +3063,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3065,7 +3115,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073M8.json b/data/chips/STM32U073M8.json index 6ce7c9c..f17486c 100644 --- a/data/chips/STM32U073M8.json +++ b/data/chips/STM32U073M8.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,11 +143,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -220,6 +235,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -288,6 +308,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -304,6 +329,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -327,6 +357,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2328,6 +2363,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3470,6 +3510,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -4133,6 +4178,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -4185,7 +4235,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073MB.json b/data/chips/STM32U073MB.json index 6a14049..e24291a 100644 --- a/data/chips/STM32U073MB.json +++ b/data/chips/STM32U073MB.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,11 +143,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -220,6 +235,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -288,6 +308,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -304,6 +329,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -327,6 +357,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2328,6 +2363,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3470,6 +3510,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -4133,6 +4178,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -4185,7 +4235,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073MC.json b/data/chips/STM32U073MC.json index f4560e5..293e91f 100644 --- a/data/chips/STM32U073MC.json +++ b/data/chips/STM32U073MC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,11 +143,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -220,6 +235,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -288,6 +308,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -304,6 +329,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -327,6 +357,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2328,6 +2363,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3470,6 +3510,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -4133,6 +4178,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -4185,7 +4235,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073R8.json b/data/chips/STM32U073R8.json index 958d797..8659cdd 100644 --- a/data/chips/STM32U073R8.json +++ b/data/chips/STM32U073R8.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,11 +143,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -220,6 +235,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -284,6 +304,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -300,6 +325,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -323,6 +353,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2169,6 +2204,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3271,6 +3311,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3859,6 +3904,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3911,7 +3961,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073RB.json b/data/chips/STM32U073RB.json index 51d51ba..0688804 100644 --- a/data/chips/STM32U073RB.json +++ b/data/chips/STM32U073RB.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,11 +143,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -220,6 +235,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -284,6 +304,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -300,6 +325,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -323,6 +353,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2169,6 +2204,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3271,6 +3311,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3859,6 +3904,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3911,7 +3961,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U073RC.json b/data/chips/STM32U073RC.json index 5b6a8de..10e1d97 100644 --- a/data/chips/STM32U073RC.json +++ b/data/chips/STM32U073RC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,11 +143,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -220,6 +235,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -284,6 +304,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -300,6 +325,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -323,6 +353,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2169,6 +2204,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3271,6 +3311,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3859,6 +3904,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3911,7 +3961,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U083CC.json b/data/chips/STM32U083CC.json index e711825..a560dc2 100644 --- a/data/chips/STM32U083CC.json +++ b/data/chips/STM32U083CC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -114,11 +119,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "AES", "address": 1073897472, + "registers": { + "kind": "aes", + "version": "v2", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -147,6 +162,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -212,6 +232,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -276,6 +301,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -292,6 +322,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -315,6 +350,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1897,6 +1937,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2945,6 +2990,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3443,6 +3493,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3490,7 +3545,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U083HC.json b/data/chips/STM32U083HC.json index 74bdd0a..3ada50b 100644 --- a/data/chips/STM32U083HC.json +++ b/data/chips/STM32U083HC.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "AES", "address": 1073897472, + "registers": { + "kind": "aes", + "version": "v2", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -143,6 +158,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -208,6 +228,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -267,6 +292,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -283,6 +313,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -306,6 +341,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1779,6 +1819,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2748,6 +2793,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3191,6 +3241,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3238,7 +3293,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U083KC.json b/data/chips/STM32U083KC.json index 6233ca4..fa198dc 100644 --- a/data/chips/STM32U083KC.json +++ b/data/chips/STM32U083KC.json @@ -37,6 +37,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -110,11 +115,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "AES", "address": 1073897472, + "registers": { + "kind": "aes", + "version": "v2", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -143,6 +158,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -199,6 +219,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -258,6 +283,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -274,6 +304,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -297,6 +332,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -1683,6 +1723,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -2618,6 +2663,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3046,6 +3096,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3093,7 +3148,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U083MC.json b/data/chips/STM32U083MC.json index 39c078a..a888d5f 100644 --- a/data/chips/STM32U083MC.json +++ b/data/chips/STM32U083MC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,11 +143,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "AES", "address": 1073897472, + "registers": { + "kind": "aes", + "version": "v2", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -171,6 +186,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -248,6 +268,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -316,6 +341,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -332,6 +362,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -355,6 +390,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2356,6 +2396,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3498,6 +3543,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -4161,6 +4211,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -4213,7 +4268,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/chips/STM32U083RC.json b/data/chips/STM32U083RC.json index d6f2e54..f102a1f 100644 --- a/data/chips/STM32U083RC.json +++ b/data/chips/STM32U083RC.json @@ -41,6 +41,11 @@ { "name": "ADC1", "address": 1073816576, + "registers": { + "kind": "adc", + "version": "u0", + "block": "ADC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -138,11 +143,21 @@ }, { "name": "ADC_COMMON", - "address": 1073817352 + "address": 1073817352, + "registers": { + "kind": "adccommon", + "version": "v3", + "block": "ADC_COMMON" + } }, { "name": "AES", "address": 1073897472, + "registers": { + "kind": "aes", + "version": "v2", + "block": "AES" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -171,6 +186,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -248,6 +268,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "u0", + "block": "COMP" + }, "pins": [ { "pin": "PA2", @@ -312,6 +337,11 @@ { "name": "CRC", "address": 1073885184, + "registers": { + "kind": "crc", + "version": "v3", + "block": "CRC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -328,6 +358,11 @@ { "name": "CRS", "address": 1073769472, + "registers": { + "kind": "crs", + "version": "v1", + "block": "CRS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -351,6 +386,11 @@ { "name": "DAC1", "address": 1073771520, + "registers": { + "kind": "dac", + "version": "v4", + "block": "DAC" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", @@ -2197,6 +2237,11 @@ { "name": "RNG", "address": 1073893376, + "registers": { + "kind": "rng", + "version": "v3", + "block": "RNG" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3299,6 +3344,11 @@ { "name": "TSC", "address": 1073889280, + "registers": { + "kind": "tsc", + "version": "v2", + "block": "TSC" + }, "rcc": { "bus_clock": "HCLK1", "kernel_clock": "HCLK1", @@ -3887,6 +3937,11 @@ { "name": "USB", "address": 1073765376, + "registers": { + "kind": "usb", + "version": "v4", + "block": "USB" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": { @@ -3939,7 +3994,12 @@ }, { "name": "USBRAM", - "address": 1073780736 + "address": 1073780736, + "registers": { + "kind": "usbram", + "version": "32_1024", + "block": "USBRAM" + } }, { "name": "VREFBUF", diff --git a/data/registers/adc_u0.json b/data/registers/adc_u0.json new file mode 100644 index 0000000..e22db70 --- /dev/null +++ b/data/registers/adc_u0.json @@ -0,0 +1,705 @@ +{ + "block/ADC": { + "description": "Analog to Digital Converter", + "items": [ + { + "name": "ISR", + "description": "ADC interrupt and status register", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "IER", + "description": "ADC interrupt enable register", + "byte_offset": 4, + "fieldset": "IER" + }, + { + "name": "CR", + "description": "ADC control register", + "byte_offset": 8, + "fieldset": "CR" + }, + { + "name": "CFGR1", + "description": "ADC configuration register 1", + "byte_offset": 12, + "fieldset": "CFGR1" + }, + { + "name": "CFGR2", + "description": "ADC configuration register 2", + "byte_offset": 16, + "fieldset": "CFGR2" + }, + { + "name": "SMPR", + "description": "ADC sampling time register", + "byte_offset": 20, + "fieldset": "SMPR" + }, + { + "name": "AWD1TR", + "description": "watchdog threshold register", + "byte_offset": 32, + "fieldset": "AWD1TR" + }, + { + "name": "AWD2TR", + "description": "watchdog threshold register", + "byte_offset": 36, + "fieldset": "AWD2TR" + }, + { + "name": "CHSELR", + "description": "channel selection register", + "byte_offset": 40, + "fieldset": "CHSELR" + }, + { + "name": "CHSELR_1", + "description": "channel selection register CHSELRMOD = 1 in ADC_CFGR1", + "byte_offset": 40, + "fieldset": "CHSELR_1" + }, + { + "name": "AWD3TR", + "description": "watchdog threshold register", + "byte_offset": 44, + "fieldset": "AWD3TR" + }, + { + "name": "DR", + "description": "ADC group regular conversion data register", + "byte_offset": 64, + "access": "Read", + "fieldset": "DR" + }, + { + "name": "AWD2CR", + "description": "ADC analog watchdog 2 configuration register", + "byte_offset": 160, + "fieldset": "AWD2CR" + }, + { + "name": "AWD3CR", + "description": "ADC analog watchdog 3 configuration register", + "byte_offset": 164, + "fieldset": "AWD3CR" + }, + { + "name": "CALFACT", + "description": "ADC calibration factors register", + "byte_offset": 180, + "fieldset": "CALFACT" + }, + { + "name": "CCR", + "description": "ADC common control register", + "byte_offset": 776, + "fieldset": "CCR" + } + ] + }, + "fieldset/AWD1TR": { + "description": "watchdog threshold register", + "fields": [ + { + "name": "LT1", + "description": "ADC analog watchdog 1 threshold low", + "bit_offset": 0, + "bit_size": 12 + }, + { + "name": "HT1", + "description": "ADC analog watchdog 1 threshold high", + "bit_offset": 16, + "bit_size": 12 + } + ] + }, + "fieldset/AWD2CR": { + "description": "ADC analog watchdog 2 configuration register", + "fields": [ + { + "name": "AWD2CH", + "description": "ADC analog watchdog 2 monitored channel selection", + "bit_offset": 0, + "bit_size": 19 + } + ] + }, + "fieldset/AWD2TR": { + "description": "watchdog threshold register", + "fields": [ + { + "name": "LT2", + "description": "ADC analog watchdog 2 threshold low", + "bit_offset": 0, + "bit_size": 12 + }, + { + "name": "HT2", + "description": "ADC analog watchdog 2 threshold high", + "bit_offset": 16, + "bit_size": 12 + } + ] + }, + "fieldset/AWD3CR": { + "description": "ADC analog watchdog 3 configuration register", + "fields": [ + { + "name": "AWD3CH", + "description": "ADC analog watchdog 3 monitored channel selection", + "bit_offset": 0, + "bit_size": 19 + } + ] + }, + "fieldset/AWD3TR": { + "description": "watchdog threshold register", + "fields": [ + { + "name": "LT3", + "description": "ADC analog watchdog 3 threshold high", + "bit_offset": 0, + "bit_size": 12 + }, + { + "name": "HT3", + "description": "ADC analog watchdog 3 threshold high", + "bit_offset": 16, + "bit_size": 12 + } + ] + }, + "fieldset/CALFACT": { + "description": "ADC calibration factors register", + "fields": [ + { + "name": "CALFACT", + "description": "ADC calibration factor in single-ended mode", + "bit_offset": 0, + "bit_size": 7 + } + ] + }, + "fieldset/CCR": { + "description": "ADC common control register", + "fields": [ + { + "name": "PRESC", + "description": "ADC prescaler", + "bit_offset": 18, + "bit_size": 4 + }, + { + "name": "VREFEN", + "description": "VREFINT enable", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "TSEN", + "description": "Temperature sensor enable", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "VBATEN", + "description": "VBAT enable", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR1": { + "description": "ADC configuration register 1", + "fields": [ + { + "name": "DMAEN", + "description": "ADC DMA transfer enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMACFG", + "description": "ADC DMA transfer configuration", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "SCANDIR", + "description": "Scan sequence direction", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "RES", + "description": "ADC data resolution", + "bit_offset": 3, + "bit_size": 2, + "enum": "RES" + }, + { + "name": "ALIGN", + "description": "ADC data alignement", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "EXTSEL", + "description": "ADC group regular external trigger source", + "bit_offset": 6, + "bit_size": 3 + }, + { + "name": "EXTEN", + "description": "ADC group regular external trigger polarity", + "bit_offset": 10, + "bit_size": 2 + }, + { + "name": "OVRMOD", + "description": "ADC group regular overrun configuration", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "CONT", + "description": "ADC group regular continuous conversion mode", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "WAIT", + "description": "Wait conversion mode", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "AUTOFF", + "description": "Auto-off mode", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "DISCEN", + "description": "ADC group regular sequencer discontinuous mode", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "CHSELRMOD", + "description": "Mode selection of the ADC_CHSELR register", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "AWD1SGL", + "description": "ADC analog watchdog 1 monitoring a single channel or all channels", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "AWD1EN", + "description": "ADC analog watchdog 1 enable on scope ADC group regular", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "AWDCH1CH", + "description": "ADC analog watchdog 1 monitored channel selection", + "bit_offset": 26, + "bit_size": 5 + } + ] + }, + "fieldset/CFGR2": { + "description": "ADC configuration register 2", + "fields": [ + { + "name": "OVSE", + "description": "ADC oversampler enable on scope ADC group regular", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "OVSR", + "description": "ADC oversampling ratio", + "bit_offset": 2, + "bit_size": 3 + }, + { + "name": "OVSS", + "description": "ADC oversampling shift", + "bit_offset": 5, + "bit_size": 4 + }, + { + "name": "TOVS", + "description": "ADC oversampling discontinuous mode (triggered mode) for ADC group regular", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LFTRIG", + "description": "Low frequency trigger mode enable", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "CKMODE", + "description": "ADC clock mode", + "bit_offset": 30, + "bit_size": 2 + } + ] + }, + "fieldset/CHSELR": { + "description": "channel selection register", + "fields": [ + { + "name": "CHSEL", + "description": "Channel-x selection", + "bit_offset": 0, + "bit_size": 19 + } + ] + }, + "fieldset/CHSELR_1": { + "description": "channel selection register CHSELRMOD = 1 in ADC_CFGR1", + "fields": [ + { + "name": "SQ1", + "description": "conversion of the sequence", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "SQ2", + "description": "conversion of the sequence", + "bit_offset": 4, + "bit_size": 4 + }, + { + "name": "SQ3", + "description": "conversion of the sequence", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SQ4", + "description": "conversion of the sequence", + "bit_offset": 12, + "bit_size": 4 + }, + { + "name": "SQ5", + "description": "conversion of the sequence", + "bit_offset": 16, + "bit_size": 4 + }, + { + "name": "SQ6", + "description": "conversion of the sequence", + "bit_offset": 20, + "bit_size": 4 + }, + { + "name": "SQ7", + "description": "conversion of the sequence", + "bit_offset": 24, + "bit_size": 4 + }, + { + "name": "SQ8", + "description": "conversion of the sequence", + "bit_offset": 28, + "bit_size": 4 + } + ] + }, + "fieldset/CR": { + "description": "ADC control register", + "fields": [ + { + "name": "ADEN", + "description": "ADC enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ADDIS", + "description": "ADC disable", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ADSTART", + "description": "ADC group regular conversion start", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ADSTP", + "description": "ADC group regular conversion stop", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADVREGEN", + "description": "ADC voltage regulator enable", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ADCAL", + "description": "ADC calibration", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/DR": { + "description": "ADC group regular conversion data register", + "fields": [ + { + "name": "regularDATA", + "description": "ADC group regular conversion data", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/IER": { + "description": "ADC interrupt enable register", + "fields": [ + { + "name": "ADRDYIE", + "description": "ADC ready interrupt", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "EOSMPIE", + "description": "ADC group regular end of sampling interrupt", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EOCIE", + "description": "ADC group regular end of unitary conversion interrupt", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "EOSIE", + "description": "ADC group regular end of sequence conversions interrupt", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "OVRIE", + "description": "ADC group regular overrun interrupt", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AWD1IE", + "description": "ADC analog watchdog 1 interrupt", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AWD2IE", + "description": "ADC analog watchdog 2 interrupt", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AWD3IE", + "description": "ADC analog watchdog 3 interrupt", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "EOCALIE", + "description": "End of calibration interrupt enable", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "CCRDYIE", + "description": "Channel Configuration Ready Interrupt enable", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "ADC interrupt and status register", + "fields": [ + { + "name": "ADRDY", + "description": "ADC ready flag", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "EOSMP", + "description": "ADC group regular end of sampling flag", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EOC", + "description": "ADC group regular end of unitary conversion flag", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "EOS", + "description": "ADC group regular end of sequence conversions flag", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "OVR", + "description": "ADC group regular overrun flag", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AWD1", + "description": "ADC analog watchdog 1 flag", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AWD2", + "description": "ADC analog watchdog 2 flag", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AWD3", + "description": "ADC analog watchdog 3 flag", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "EOCAL", + "description": "End Of Calibration flag", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "CCRDY", + "description": "Channel Configuration Ready flag", + "bit_offset": 13, + "bit_size": 1 + } + ] + }, + "fieldset/SMPR": { + "description": "ADC sampling time register", + "fields": [ + { + "name": "SMP1", + "description": "Sampling time selection", + "bit_offset": 0, + "bit_size": 3, + "enum": "SAMPLE_TIME" + }, + { + "name": "SMP2", + "description": "Sampling time selection", + "bit_offset": 4, + "bit_size": 3, + "enum": "SAMPLE_TIME" + }, + { + "name": "SMPSEL", + "description": "Channel sampling time selection", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 19, + "stride": 0 + } + } + ] + }, + "enum/RES": { + "bit_size": 2, + "variants": [ + { + "name": "Bits12", + "description": "12-bit resolution", + "value": 0 + }, + { + "name": "Bits10", + "description": "10-bit resolution", + "value": 1 + }, + { + "name": "Bits8", + "description": "8-bit resolution", + "value": 2 + }, + { + "name": "Bits6", + "description": "6-bit resolution", + "value": 3 + } + ] + }, + "enum/SAMPLE_TIME": { + "bit_size": 3, + "variants": [ + { + "name": "Cycles1_5", + "description": "1.5 ADC cycles", + "value": 0 + }, + { + "name": "Cycles3_5", + "description": "3.5 ADC cycles", + "value": 1 + }, + { + "name": "Cycles7_5", + "description": "7.5 ADC cycles", + "value": 2 + }, + { + "name": "Cycles12_5", + "description": "12.5 ADC cycles", + "value": 3 + }, + { + "name": "Cycles19_5", + "description": "19.5 ADC cycles", + "value": 4 + }, + { + "name": "Cycles39_5", + "description": "39.5 ADC cycles", + "value": 5 + }, + { + "name": "Cycles79_5", + "description": "79.5 ADC cycles", + "value": 6 + }, + { + "name": "Cycles160_5", + "description": "160.5 ADC cycles", + "value": 7 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/comp_u0.json b/data/registers/comp_u0.json new file mode 100644 index 0000000..660aa77 --- /dev/null +++ b/data/registers/comp_u0.json @@ -0,0 +1,222 @@ +{ + "block/COMP": { + "description": "Comparator.", + "items": [ + { + "name": "CSR", + "description": "Comparator control and status register.", + "byte_offset": 0, + "fieldset": "CSR" + } + ] + }, + "fieldset/CSR": { + "description": "control and status register.", + "fields": [ + { + "name": "EN", + "description": "Enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "INMSEL", + "description": "Input minus selection bits.", + "bit_offset": 4, + "bit_size": 4 + }, + { + "name": "INPSEL", + "description": "Input plus selection bit.", + "bit_offset": 8, + "bit_size": 3 + }, + { + "name": "WINMODE", + "description": "Comparator 1 noninverting input selector for window mode.", + "bit_offset": 14, + "bit_size": 1, + "enum": "WINMODE" + }, + { + "name": "WINOUT", + "description": "Comparator 1 output selector.", + "bit_offset": 14, + "bit_size": 1, + "enum": "WINOUT" + }, + { + "name": "POLARITY", + "description": "Polarity selection bit.", + "bit_offset": 15, + "bit_size": 1, + "enum": "POLARITY" + }, + { + "name": "HYST", + "description": "Hysteresis selection bits.", + "bit_offset": 16, + "bit_size": 2, + "enum": "HYST" + }, + { + "name": "PWRMODE", + "description": "Power Mode.", + "bit_offset": 18, + "bit_size": 2, + "enum": "PWRMODE" + }, + { + "name": "BLANKSEL", + "description": "Blanking source selection bits.", + "bit_offset": 20, + "bit_size": 5, + "enum": "BLANKING" + }, + { + "name": "BRGEN", + "description": "Scaler bridge enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "VALUE", + "description": "Output status bit.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "LOCK", + "description": "Register lock bit.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "enum/BLANKING": { + "bit_size": 5, + "variants": [ + { + "name": "NoBlanking", + "description": "No blanking.", + "value": 0 + }, + { + "name": "TIM1OC4", + "description": "TIM1 OC4 enabled as blanking source", + "value": 1 + }, + { + "name": "TIM1OC5", + "description": "TIM1 OC5 enabled as blanking source", + "value": 2 + }, + { + "name": "TIM2OC3", + "description": "TIM5 OC3 enabled as blanking source", + "value": 4 + }, + { + "name": "TIM3OC3", + "description": "TIM3 OC3 enabled as blanking source", + "value": 8 + }, + { + "name": "TIM15OC2", + "description": "TIM15 OC2 enabled as blanking source", + "value": 16 + } + ] + }, + "enum/HYST": { + "bit_size": 2, + "variants": [ + { + "name": "None", + "value": 0 + }, + { + "name": "Low", + "value": 1 + }, + { + "name": "Medium", + "value": 2 + }, + { + "name": "High", + "value": 3 + } + ] + }, + "enum/POLARITY": { + "bit_size": 1, + "variants": [ + { + "name": "NotInverted", + "description": "Output is not inverted.", + "value": 0 + }, + { + "name": "Inverted", + "description": "Output is inverted.", + "value": 1 + } + ] + }, + "enum/PWRMODE": { + "bit_size": 2, + "variants": [ + { + "name": "HighSpeed", + "description": "High speed / full power.", + "value": 0 + }, + { + "name": "MediumSpeed", + "description": "Medium speed / medium power.", + "value": 1 + }, + { + "name": "LowSpeed", + "description": "Low speed / low power.", + "value": 2 + }, + { + "name": "VeryLowSpeed", + "description": "Very-low speed / ultra-low power.", + "value": 3 + } + ] + }, + "enum/WINMODE": { + "bit_size": 1, + "variants": [ + { + "name": "ThisInpsel", + "description": "Signal selected with INPSEL[2:0] bitfield of this register.", + "value": 0 + }, + { + "name": "OtherInpsel", + "description": "Signal selected with INPSEL[2:0] bitfield of the other register (required for window mode).", + "value": 1 + } + ] + }, + "enum/WINOUT": { + "bit_size": 1, + "variants": [ + { + "name": "COMP1_VALUE", + "description": "Comparator 1 value.", + "value": 0 + }, + { + "name": "COMP1_VALUE XOR COMP2_VALUE", + "description": "Comparator 1 value XOR comparator 2 value (required for window mode).", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/usbram_32_1024.json b/data/registers/usbram_32_1024.json new file mode 100644 index 0000000..4550d45 --- /dev/null +++ b/data/registers/usbram_32_1024.json @@ -0,0 +1,16 @@ +{ + "block/USBRAM": { + "description": "USB Endpoint memory", + "items": [ + { + "name": "MEM", + "description": "USB Endpoint memory", + "array": { + "len": 256, + "stride": 4 + }, + "byte_offset": 0 + } + ] + } +} \ No newline at end of file