diff --git a/data/chips/STM32G431C6.json b/data/chips/STM32G431C6.json index 3dacd0b..d6ce406 100644 --- a/data/chips/STM32G431C6.json +++ b/data/chips/STM32G431C6.json @@ -254,7 +254,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431C8.json b/data/chips/STM32G431C8.json index c6b9c92..ff0e4b8 100644 --- a/data/chips/STM32G431C8.json +++ b/data/chips/STM32G431C8.json @@ -254,7 +254,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431CB.json b/data/chips/STM32G431CB.json index 566b149..fcebfc1 100644 --- a/data/chips/STM32G431CB.json +++ b/data/chips/STM32G431CB.json @@ -258,7 +258,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -337,7 +337,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431K6.json b/data/chips/STM32G431K6.json index f048d7b..1b984cd 100644 --- a/data/chips/STM32G431K6.json +++ b/data/chips/STM32G431K6.json @@ -254,7 +254,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -317,7 +317,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431K8.json b/data/chips/STM32G431K8.json index 348a7e5..b4602f0 100644 --- a/data/chips/STM32G431K8.json +++ b/data/chips/STM32G431K8.json @@ -254,7 +254,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -317,7 +317,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431KB.json b/data/chips/STM32G431KB.json index 5559f18..9f75814 100644 --- a/data/chips/STM32G431KB.json +++ b/data/chips/STM32G431KB.json @@ -254,7 +254,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -317,7 +317,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431M6.json b/data/chips/STM32G431M6.json index f3d96c4..f695ea0 100644 --- a/data/chips/STM32G431M6.json +++ b/data/chips/STM32G431M6.json @@ -250,7 +250,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -345,7 +345,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431M8.json b/data/chips/STM32G431M8.json index 3954997..2f7ae35 100644 --- a/data/chips/STM32G431M8.json +++ b/data/chips/STM32G431M8.json @@ -250,7 +250,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -345,7 +345,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431MB.json b/data/chips/STM32G431MB.json index b55c859..eee7b03 100644 --- a/data/chips/STM32G431MB.json +++ b/data/chips/STM32G431MB.json @@ -250,7 +250,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -345,7 +345,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431R6.json b/data/chips/STM32G431R6.json index 438a0df..d71d190 100644 --- a/data/chips/STM32G431R6.json +++ b/data/chips/STM32G431R6.json @@ -254,7 +254,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -349,7 +349,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431R8.json b/data/chips/STM32G431R8.json index e413c6c..e77cb3c 100644 --- a/data/chips/STM32G431R8.json +++ b/data/chips/STM32G431R8.json @@ -254,7 +254,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -349,7 +349,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431RB.json b/data/chips/STM32G431RB.json index 7a4e960..52cda2e 100644 --- a/data/chips/STM32G431RB.json +++ b/data/chips/STM32G431RB.json @@ -254,7 +254,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -349,7 +349,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431V6.json b/data/chips/STM32G431V6.json index 705160d..186db53 100644 --- a/data/chips/STM32G431V6.json +++ b/data/chips/STM32G431V6.json @@ -250,7 +250,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -345,7 +345,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431V8.json b/data/chips/STM32G431V8.json index 364a463..ec5218a 100644 --- a/data/chips/STM32G431V8.json +++ b/data/chips/STM32G431V8.json @@ -250,7 +250,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -345,7 +345,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G431VB.json b/data/chips/STM32G431VB.json index d50defa..528561e 100644 --- a/data/chips/STM32G431VB.json +++ b/data/chips/STM32G431VB.json @@ -250,7 +250,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -345,7 +345,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G441CB.json b/data/chips/STM32G441CB.json index c10b451..2c34911 100644 --- a/data/chips/STM32G441CB.json +++ b/data/chips/STM32G441CB.json @@ -252,7 +252,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -331,7 +331,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G441KB.json b/data/chips/STM32G441KB.json index e0203a9..35d4f76 100644 --- a/data/chips/STM32G441KB.json +++ b/data/chips/STM32G441KB.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -311,7 +311,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G441MB.json b/data/chips/STM32G441MB.json index 903c4de..09494d7 100644 --- a/data/chips/STM32G441MB.json +++ b/data/chips/STM32G441MB.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G441RB.json b/data/chips/STM32G441RB.json index 9e45a02..171c61e 100644 --- a/data/chips/STM32G441RB.json +++ b/data/chips/STM32G441RB.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -343,7 +343,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G441VB.json b/data/chips/STM32G441VB.json index 3d505e3..e2153e4 100644 --- a/data/chips/STM32G441VB.json +++ b/data/chips/STM32G441VB.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G471CC.json b/data/chips/STM32G471CC.json index 9eb791a..a45fb14 100644 --- a/data/chips/STM32G471CC.json +++ b/data/chips/STM32G471CC.json @@ -49,7 +49,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -128,7 +128,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -211,7 +211,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G471CE.json b/data/chips/STM32G471CE.json index d5b24a7..3e3e8c7 100644 --- a/data/chips/STM32G471CE.json +++ b/data/chips/STM32G471CE.json @@ -49,7 +49,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -128,7 +128,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -211,7 +211,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G471MC.json b/data/chips/STM32G471MC.json index b595e90..89f942b 100644 --- a/data/chips/STM32G471MC.json +++ b/data/chips/STM32G471MC.json @@ -45,7 +45,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -140,7 +140,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -243,7 +243,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G471ME.json b/data/chips/STM32G471ME.json index 34c7e61..33a0187 100644 --- a/data/chips/STM32G471ME.json +++ b/data/chips/STM32G471ME.json @@ -49,7 +49,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -144,7 +144,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -247,7 +247,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G471QC.json b/data/chips/STM32G471QC.json index c6bf810..62cf7df 100644 --- a/data/chips/STM32G471QC.json +++ b/data/chips/STM32G471QC.json @@ -45,7 +45,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -140,7 +140,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -243,7 +243,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G471QE.json b/data/chips/STM32G471QE.json index 399dd40..309bb50 100644 --- a/data/chips/STM32G471QE.json +++ b/data/chips/STM32G471QE.json @@ -45,7 +45,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -140,7 +140,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -243,7 +243,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G471RC.json b/data/chips/STM32G471RC.json index 0fed239..c3b5613 100644 --- a/data/chips/STM32G471RC.json +++ b/data/chips/STM32G471RC.json @@ -45,7 +45,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -140,7 +140,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -243,7 +243,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G471RE.json b/data/chips/STM32G471RE.json index 605bf44..7a5323d 100644 --- a/data/chips/STM32G471RE.json +++ b/data/chips/STM32G471RE.json @@ -45,7 +45,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -140,7 +140,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -243,7 +243,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G471VC.json b/data/chips/STM32G471VC.json index db2c80b..965f9c2 100644 --- a/data/chips/STM32G471VC.json +++ b/data/chips/STM32G471VC.json @@ -53,7 +53,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -148,7 +148,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -251,7 +251,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G471VE.json b/data/chips/STM32G471VE.json index f5b6997..168e698 100644 --- a/data/chips/STM32G471VE.json +++ b/data/chips/STM32G471VE.json @@ -53,7 +53,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -148,7 +148,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -251,7 +251,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473CB.json b/data/chips/STM32G473CB.json index 63f6469..bb7d620 100644 --- a/data/chips/STM32G473CB.json +++ b/data/chips/STM32G473CB.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -327,7 +327,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -410,7 +410,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -461,7 +461,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -512,7 +512,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473CC.json b/data/chips/STM32G473CC.json index 2a53026..00b00ea 100644 --- a/data/chips/STM32G473CC.json +++ b/data/chips/STM32G473CC.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -327,7 +327,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -410,7 +410,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -461,7 +461,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -512,7 +512,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473CE.json b/data/chips/STM32G473CE.json index 35b4f46..06daf68 100644 --- a/data/chips/STM32G473CE.json +++ b/data/chips/STM32G473CE.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -327,7 +327,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -410,7 +410,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -461,7 +461,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -512,7 +512,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473MB.json b/data/chips/STM32G473MB.json index fff2f5b..6e5ada9 100644 --- a/data/chips/STM32G473MB.json +++ b/data/chips/STM32G473MB.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -442,7 +442,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -529,7 +529,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -620,7 +620,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473MC.json b/data/chips/STM32G473MC.json index 74816a6..5bd3a07 100644 --- a/data/chips/STM32G473MC.json +++ b/data/chips/STM32G473MC.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -442,7 +442,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -529,7 +529,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -620,7 +620,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473ME.json b/data/chips/STM32G473ME.json index 76d7753..899d10f 100644 --- a/data/chips/STM32G473ME.json +++ b/data/chips/STM32G473ME.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -343,7 +343,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -446,7 +446,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -533,7 +533,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -624,7 +624,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473PB.json b/data/chips/STM32G473PB.json index ad7f76e..d091437 100644 --- a/data/chips/STM32G473PB.json +++ b/data/chips/STM32G473PB.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -436,7 +436,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -535,7 +535,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -638,7 +638,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473PC.json b/data/chips/STM32G473PC.json index d862623..aac104e 100644 --- a/data/chips/STM32G473PC.json +++ b/data/chips/STM32G473PC.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -436,7 +436,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -535,7 +535,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -638,7 +638,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473PE.json b/data/chips/STM32G473PE.json index 553f40b..531b91c 100644 --- a/data/chips/STM32G473PE.json +++ b/data/chips/STM32G473PE.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -436,7 +436,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -535,7 +535,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -638,7 +638,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473QB.json b/data/chips/STM32G473QB.json index d572352..206b4b5 100644 --- a/data/chips/STM32G473QB.json +++ b/data/chips/STM32G473QB.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -442,7 +442,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -541,7 +541,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -644,7 +644,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473QC.json b/data/chips/STM32G473QC.json index 8e58e6d..94cfa6b 100644 --- a/data/chips/STM32G473QC.json +++ b/data/chips/STM32G473QC.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -442,7 +442,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -541,7 +541,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -644,7 +644,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473QE.json b/data/chips/STM32G473QE.json index bf10b33..4c2df23 100644 --- a/data/chips/STM32G473QE.json +++ b/data/chips/STM32G473QE.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -442,7 +442,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -541,7 +541,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -644,7 +644,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473RB.json b/data/chips/STM32G473RB.json index 3a0b9c2..2c3f6c8 100644 --- a/data/chips/STM32G473RB.json +++ b/data/chips/STM32G473RB.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -442,7 +442,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -493,7 +493,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -544,7 +544,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473RC.json b/data/chips/STM32G473RC.json index bb7980c..e009c55 100644 --- a/data/chips/STM32G473RC.json +++ b/data/chips/STM32G473RC.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -442,7 +442,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -493,7 +493,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -544,7 +544,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473RE.json b/data/chips/STM32G473RE.json index f3637c0..5c807f4 100644 --- a/data/chips/STM32G473RE.json +++ b/data/chips/STM32G473RE.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -442,7 +442,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -493,7 +493,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -544,7 +544,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473VB.json b/data/chips/STM32G473VB.json index 0010229..3db3ccc 100644 --- a/data/chips/STM32G473VB.json +++ b/data/chips/STM32G473VB.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -343,7 +343,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -446,7 +446,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -545,7 +545,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -648,7 +648,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473VC.json b/data/chips/STM32G473VC.json index f0012c2..adcf234 100644 --- a/data/chips/STM32G473VC.json +++ b/data/chips/STM32G473VC.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -343,7 +343,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -446,7 +446,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -545,7 +545,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -648,7 +648,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G473VE.json b/data/chips/STM32G473VE.json index e309988..ab5a44c 100644 --- a/data/chips/STM32G473VE.json +++ b/data/chips/STM32G473VE.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -343,7 +343,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -446,7 +446,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -545,7 +545,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -648,7 +648,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474CB.json b/data/chips/STM32G474CB.json index 29dbaf5..c2fedc1 100644 --- a/data/chips/STM32G474CB.json +++ b/data/chips/STM32G474CB.json @@ -260,7 +260,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -422,7 +422,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -473,7 +473,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -524,7 +524,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474CC.json b/data/chips/STM32G474CC.json index 9a82b73..b81706e 100644 --- a/data/chips/STM32G474CC.json +++ b/data/chips/STM32G474CC.json @@ -260,7 +260,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -422,7 +422,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -473,7 +473,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -524,7 +524,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474CE.json b/data/chips/STM32G474CE.json index 6797cc6..82f74aa 100644 --- a/data/chips/STM32G474CE.json +++ b/data/chips/STM32G474CE.json @@ -260,7 +260,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -422,7 +422,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -473,7 +473,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -524,7 +524,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474MB.json b/data/chips/STM32G474MB.json index ce39b13..93bfd98 100644 --- a/data/chips/STM32G474MB.json +++ b/data/chips/STM32G474MB.json @@ -256,7 +256,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -351,7 +351,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -454,7 +454,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -541,7 +541,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -632,7 +632,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474MC.json b/data/chips/STM32G474MC.json index d2a074e..fbe6f8c 100644 --- a/data/chips/STM32G474MC.json +++ b/data/chips/STM32G474MC.json @@ -256,7 +256,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -351,7 +351,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -454,7 +454,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -541,7 +541,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -632,7 +632,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474ME.json b/data/chips/STM32G474ME.json index f25b552..8587d81 100644 --- a/data/chips/STM32G474ME.json +++ b/data/chips/STM32G474ME.json @@ -260,7 +260,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -355,7 +355,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -458,7 +458,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -545,7 +545,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -636,7 +636,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474PB.json b/data/chips/STM32G474PB.json index dd74ce2..12b7da1 100644 --- a/data/chips/STM32G474PB.json +++ b/data/chips/STM32G474PB.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -436,7 +436,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -535,7 +535,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -638,7 +638,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474PC.json b/data/chips/STM32G474PC.json index 307c93e..c609d7b 100644 --- a/data/chips/STM32G474PC.json +++ b/data/chips/STM32G474PC.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -436,7 +436,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -535,7 +535,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -638,7 +638,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474PE.json b/data/chips/STM32G474PE.json index a0177a3..9372221 100644 --- a/data/chips/STM32G474PE.json +++ b/data/chips/STM32G474PE.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -436,7 +436,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -535,7 +535,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -638,7 +638,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474QB.json b/data/chips/STM32G474QB.json index efef65c..e31f515 100644 --- a/data/chips/STM32G474QB.json +++ b/data/chips/STM32G474QB.json @@ -256,7 +256,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -351,7 +351,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -454,7 +454,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -553,7 +553,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -656,7 +656,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474QC.json b/data/chips/STM32G474QC.json index 7b44b83..9dc4d6d 100644 --- a/data/chips/STM32G474QC.json +++ b/data/chips/STM32G474QC.json @@ -256,7 +256,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -351,7 +351,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -454,7 +454,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -553,7 +553,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -656,7 +656,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474QE.json b/data/chips/STM32G474QE.json index 252132a..a694963 100644 --- a/data/chips/STM32G474QE.json +++ b/data/chips/STM32G474QE.json @@ -256,7 +256,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -351,7 +351,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -454,7 +454,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -553,7 +553,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -656,7 +656,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474RB.json b/data/chips/STM32G474RB.json index 3ba6dfb..ca7e6f4 100644 --- a/data/chips/STM32G474RB.json +++ b/data/chips/STM32G474RB.json @@ -256,7 +256,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -351,7 +351,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -454,7 +454,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -505,7 +505,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -556,7 +556,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474RC.json b/data/chips/STM32G474RC.json index aed4928..204366f 100644 --- a/data/chips/STM32G474RC.json +++ b/data/chips/STM32G474RC.json @@ -256,7 +256,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -351,7 +351,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -454,7 +454,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -505,7 +505,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -556,7 +556,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474RE.json b/data/chips/STM32G474RE.json index a1983e2..81730f5 100644 --- a/data/chips/STM32G474RE.json +++ b/data/chips/STM32G474RE.json @@ -256,7 +256,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -351,7 +351,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -454,7 +454,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -505,7 +505,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -556,7 +556,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474VB.json b/data/chips/STM32G474VB.json index e89cc37..63f560d 100644 --- a/data/chips/STM32G474VB.json +++ b/data/chips/STM32G474VB.json @@ -260,7 +260,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -355,7 +355,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -458,7 +458,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -557,7 +557,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -660,7 +660,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474VC.json b/data/chips/STM32G474VC.json index 096eec7..a92204a 100644 --- a/data/chips/STM32G474VC.json +++ b/data/chips/STM32G474VC.json @@ -260,7 +260,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -355,7 +355,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -458,7 +458,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -557,7 +557,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -660,7 +660,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G474VE.json b/data/chips/STM32G474VE.json index f5b700c..96c0632 100644 --- a/data/chips/STM32G474VE.json +++ b/data/chips/STM32G474VE.json @@ -260,7 +260,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -355,7 +355,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -458,7 +458,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -557,7 +557,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -660,7 +660,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G483CE.json b/data/chips/STM32G483CE.json index 03dcedb..1f9ab02 100644 --- a/data/chips/STM32G483CE.json +++ b/data/chips/STM32G483CE.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -327,7 +327,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -410,7 +410,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -461,7 +461,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -512,7 +512,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G483ME.json b/data/chips/STM32G483ME.json index 619452e..e019daa 100644 --- a/data/chips/STM32G483ME.json +++ b/data/chips/STM32G483ME.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -343,7 +343,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -446,7 +446,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -533,7 +533,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -624,7 +624,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G483PE.json b/data/chips/STM32G483PE.json index 9a687a8..550572a 100644 --- a/data/chips/STM32G483PE.json +++ b/data/chips/STM32G483PE.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -436,7 +436,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -535,7 +535,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -638,7 +638,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G483QE.json b/data/chips/STM32G483QE.json index f1149ec..998ed12 100644 --- a/data/chips/STM32G483QE.json +++ b/data/chips/STM32G483QE.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -442,7 +442,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -541,7 +541,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -644,7 +644,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G483RE.json b/data/chips/STM32G483RE.json index 7693300..fae1551 100644 --- a/data/chips/STM32G483RE.json +++ b/data/chips/STM32G483RE.json @@ -244,7 +244,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -339,7 +339,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -442,7 +442,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -493,7 +493,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -544,7 +544,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G483VE.json b/data/chips/STM32G483VE.json index db4c165..e7a79c1 100644 --- a/data/chips/STM32G483VE.json +++ b/data/chips/STM32G483VE.json @@ -248,7 +248,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -343,7 +343,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -446,7 +446,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -545,7 +545,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -648,7 +648,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G484CE.json b/data/chips/STM32G484CE.json index c9c73b5..7b09890 100644 --- a/data/chips/STM32G484CE.json +++ b/data/chips/STM32G484CE.json @@ -254,7 +254,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -416,7 +416,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -467,7 +467,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -518,7 +518,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G484ME.json b/data/chips/STM32G484ME.json index 00178a1..255737d 100644 --- a/data/chips/STM32G484ME.json +++ b/data/chips/STM32G484ME.json @@ -254,7 +254,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -349,7 +349,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -452,7 +452,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -539,7 +539,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -630,7 +630,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G484PE.json b/data/chips/STM32G484PE.json index 9d8cd23..59c19a0 100644 --- a/data/chips/STM32G484PE.json +++ b/data/chips/STM32G484PE.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -436,7 +436,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -535,7 +535,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -638,7 +638,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G484QE.json b/data/chips/STM32G484QE.json index 9aed428..82460fb 100644 --- a/data/chips/STM32G484QE.json +++ b/data/chips/STM32G484QE.json @@ -250,7 +250,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -345,7 +345,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -448,7 +448,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -547,7 +547,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -650,7 +650,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G484RE.json b/data/chips/STM32G484RE.json index 9662e7e..343ae3d 100644 --- a/data/chips/STM32G484RE.json +++ b/data/chips/STM32G484RE.json @@ -250,7 +250,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -345,7 +345,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -448,7 +448,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -499,7 +499,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -550,7 +550,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G484VE.json b/data/chips/STM32G484VE.json index 40df967..8330663 100644 --- a/data/chips/STM32G484VE.json +++ b/data/chips/STM32G484VE.json @@ -254,7 +254,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -349,7 +349,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -452,7 +452,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -551,7 +551,7 @@ "address": 1342178560, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -654,7 +654,7 @@ "address": 1342178816, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G491CC.json b/data/chips/STM32G491CC.json index 300954d..add68e4 100644 --- a/data/chips/STM32G491CC.json +++ b/data/chips/STM32G491CC.json @@ -242,7 +242,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -321,7 +321,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -404,7 +404,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G491CE.json b/data/chips/STM32G491CE.json index 3fec61a..ae49647 100644 --- a/data/chips/STM32G491CE.json +++ b/data/chips/STM32G491CE.json @@ -242,7 +242,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -321,7 +321,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -404,7 +404,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G491KC.json b/data/chips/STM32G491KC.json index e9ea28e..77a885c 100644 --- a/data/chips/STM32G491KC.json +++ b/data/chips/STM32G491KC.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -301,7 +301,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -368,7 +368,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G491KE.json b/data/chips/STM32G491KE.json index 86f4d65..4a72979 100644 --- a/data/chips/STM32G491KE.json +++ b/data/chips/STM32G491KE.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -301,7 +301,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -368,7 +368,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G491MC.json b/data/chips/STM32G491MC.json index 7463558..0bb4a1a 100644 --- a/data/chips/STM32G491MC.json +++ b/data/chips/STM32G491MC.json @@ -242,7 +242,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -337,7 +337,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -440,7 +440,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G491ME.json b/data/chips/STM32G491ME.json index efb3186..c30acba 100644 --- a/data/chips/STM32G491ME.json +++ b/data/chips/STM32G491ME.json @@ -242,7 +242,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -337,7 +337,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -440,7 +440,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G491RC.json b/data/chips/STM32G491RC.json index 7f028b1..f9ba1c4 100644 --- a/data/chips/STM32G491RC.json +++ b/data/chips/STM32G491RC.json @@ -242,7 +242,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -337,7 +337,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -440,7 +440,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G491RE.json b/data/chips/STM32G491RE.json index 73497d6..2eca149 100644 --- a/data/chips/STM32G491RE.json +++ b/data/chips/STM32G491RE.json @@ -246,7 +246,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -341,7 +341,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -444,7 +444,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G491VC.json b/data/chips/STM32G491VC.json index c98e7a4..824c580 100644 --- a/data/chips/STM32G491VC.json +++ b/data/chips/STM32G491VC.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -436,7 +436,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G491VE.json b/data/chips/STM32G491VE.json index 2b261f5..62f8bf1 100644 --- a/data/chips/STM32G491VE.json +++ b/data/chips/STM32G491VE.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -436,7 +436,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G4A1CE.json b/data/chips/STM32G4A1CE.json index 14f3b6c..b0bdf2e 100644 --- a/data/chips/STM32G4A1CE.json +++ b/data/chips/STM32G4A1CE.json @@ -242,7 +242,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -321,7 +321,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -404,7 +404,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G4A1KE.json b/data/chips/STM32G4A1KE.json index 34fd87a..9c3dff2 100644 --- a/data/chips/STM32G4A1KE.json +++ b/data/chips/STM32G4A1KE.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -301,7 +301,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -368,7 +368,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G4A1ME.json b/data/chips/STM32G4A1ME.json index e45061b..1773558 100644 --- a/data/chips/STM32G4A1ME.json +++ b/data/chips/STM32G4A1ME.json @@ -242,7 +242,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -337,7 +337,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -440,7 +440,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G4A1RE.json b/data/chips/STM32G4A1RE.json index 2374957..a6f4e4b 100644 --- a/data/chips/STM32G4A1RE.json +++ b/data/chips/STM32G4A1RE.json @@ -246,7 +246,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -341,7 +341,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -444,7 +444,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/chips/STM32G4A1VE.json b/data/chips/STM32G4A1VE.json index 613d800..b2e6483 100644 --- a/data/chips/STM32G4A1VE.json +++ b/data/chips/STM32G4A1VE.json @@ -238,7 +238,7 @@ "address": 1342177280, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -333,7 +333,7 @@ "address": 1342177536, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { @@ -436,7 +436,7 @@ "address": 1342178304, "registers": { "kind": "adc", - "version": "v4", + "version": "g4", "block": "ADC" }, "rcc": { diff --git a/data/registers/adc_g4.json b/data/registers/adc_g4.json new file mode 100644 index 0000000..cfe429f --- /dev/null +++ b/data/registers/adc_g4.json @@ -0,0 +1,1245 @@ +{ + "block/ADC": { + "description": "Analog to Digital Converter", + "items": [ + { + "name": "ISR", + "description": "interrupt and status register", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "IER", + "description": "interrupt enable register", + "byte_offset": 4, + "fieldset": "IER" + }, + { + "name": "CR", + "description": "control register", + "byte_offset": 8, + "fieldset": "CR" + }, + { + "name": "CFGR", + "description": "configuration register 1", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CFGR2", + "description": "configuration register 2", + "byte_offset": 16, + "fieldset": "CFGR2" + }, + { + "name": "SMPR", + "description": "sampling time register 1-2", + "array": { + "len": 2, + "stride": 4 + }, + "byte_offset": 20, + "fieldset": "SMPR" + }, + { + "name": "PCSEL", + "description": "pre channel selection register", + "byte_offset": 28, + "fieldset": "PCSEL" + }, + { + "name": "LTR1", + "description": "analog watchdog 1 threshold register", + "byte_offset": 32, + "fieldset": "LTR1" + }, + { + "name": "HTR1", + "description": "analog watchdog 2 threshold register", + "byte_offset": 36, + "fieldset": "HTR1" + }, + { + "name": "SQR1", + "description": "group regular sequencer ranks register 1", + "byte_offset": 48, + "fieldset": "SQR1" + }, + { + "name": "SQR2", + "description": "group regular sequencer ranks register 2", + "byte_offset": 52, + "fieldset": "SQR2" + }, + { + "name": "SQR3", + "description": "group regular sequencer ranks register 3", + "byte_offset": 56, + "fieldset": "SQR3" + }, + { + "name": "SQR4", + "description": "group regular sequencer ranks register 4", + "byte_offset": 60, + "fieldset": "SQR4" + }, + { + "name": "DR", + "description": "group regular conversion data register", + "byte_offset": 64, + "access": "Read", + "fieldset": "DR" + }, + { + "name": "JSQR", + "description": "group injected sequencer register", + "byte_offset": 76, + "fieldset": "JSQR" + }, + { + "name": "OFR", + "description": "offset number 1-4 register", + "array": { + "len": 4, + "stride": 4 + }, + "byte_offset": 96, + "fieldset": "OFR" + }, + { + "name": "JDR", + "description": "group injected sequencer rank 1-4 register", + "array": { + "len": 4, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "JDR" + }, + { + "name": "AWD2CR", + "description": "analog watchdog 2 configuration register", + "byte_offset": 160, + "fieldset": "AWD2CR" + }, + { + "name": "AWD3CR", + "description": "analog watchdog 3 configuration register", + "byte_offset": 164, + "fieldset": "AWD3CR" + }, + { + "name": "LTR2", + "description": "watchdog lower threshold register 2", + "byte_offset": 176, + "fieldset": "LTR2" + }, + { + "name": "HTR2", + "description": "watchdog higher threshold register 2", + "byte_offset": 180, + "fieldset": "HTR2" + }, + { + "name": "LTR3", + "description": "watchdog lower threshold register 3", + "byte_offset": 184, + "fieldset": "LTR3" + }, + { + "name": "HTR3", + "description": "watchdog higher threshold register 3", + "byte_offset": 188, + "fieldset": "HTR3" + }, + { + "name": "DIFSEL", + "description": "channel differential or single-ended mode selection register", + "byte_offset": 192, + "fieldset": "DIFSEL" + }, + { + "name": "CALFACT", + "description": "calibration factors register", + "byte_offset": 196, + "fieldset": "CALFACT" + }, + { + "name": "CALFACT2", + "description": "Calibration Factor register 2", + "byte_offset": 200, + "fieldset": "CALFACT2" + } + ] + }, + "fieldset/AWD2CR": { + "description": "analog watchdog 2 configuration register", + "fields": [ + { + "name": "AWD2CH", + "description": "analog watchdog 2 monitored channel selection", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 20, + "stride": 1 + } + } + ] + }, + "fieldset/AWD3CR": { + "description": "analog watchdog 3 configuration register", + "fields": [ + { + "name": "AWD3CH", + "description": "analog watchdog 3 monitored channel selection", + "bit_offset": 1, + "bit_size": 1, + "array": { + "len": 20, + "stride": 1 + } + } + ] + }, + "fieldset/CALFACT": { + "description": "calibration factors register", + "fields": [ + { + "name": "CALFACT_S", + "description": "calibration factor in single-ended mode", + "bit_offset": 0, + "bit_size": 11 + }, + { + "name": "CALFACT_D", + "description": "calibration factor in differential mode", + "bit_offset": 16, + "bit_size": 11 + } + ] + }, + "fieldset/CALFACT2": { + "description": "Calibration Factor register 2", + "fields": [ + { + "name": "LINCALFACT", + "description": "Linearity Calibration Factor", + "bit_offset": 0, + "bit_size": 30 + } + ] + }, + "fieldset/CFGR": { + "description": "configuration register 1", + "fields": [ + { + "name": "DMNGT", + "description": "DMA transfer enable", + "bit_offset": 0, + "bit_size": 2, + "enum": "DMNGT" + }, + { + "name": "RES", + "description": "data resolution", + "bit_offset": 2, + "bit_size": 3, + "enum": "RES" + }, + { + "name": "EXTSEL", + "description": "group regular external trigger source", + "bit_offset": 5, + "bit_size": 5 + }, + { + "name": "EXTEN", + "description": "group regular external trigger polarity", + "bit_offset": 10, + "bit_size": 2, + "enum": "EXTEN" + }, + { + "name": "OVRMOD", + "description": "group regular overrun configuration", + "bit_offset": 12, + "bit_size": 1, + "enum": "OVRMOD" + }, + { + "name": "CONT", + "description": "group regular continuous conversion mode", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "AUTDLY", + "description": "low power auto wait", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "DISCEN", + "description": "group regular sequencer discontinuous mode", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "DISCNUM", + "description": "group regular sequencer discontinuous number of ranks", + "bit_offset": 17, + "bit_size": 3 + }, + { + "name": "JDISCEN", + "description": "group injected sequencer discontinuous mode", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "JQM", + "description": "group injected contexts queue mode", + "bit_offset": 21, + "bit_size": 1, + "enum": "JQM" + }, + { + "name": "AWD1SGL", + "description": "analog watchdog 1 monitoring a single channel or all channels", + "bit_offset": 22, + "bit_size": 1, + "enum": "AWD1SGL" + }, + { + "name": "AWD1EN", + "description": "analog watchdog 1 enable on scope group regular", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "JAWD1EN", + "description": "analog watchdog 1 enable on scope group injected", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "JAUTO", + "description": "group injected automatic trigger mode", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "AWD1CH", + "description": "analog watchdog 1 monitored channel selection", + "bit_offset": 26, + "bit_size": 5 + }, + { + "name": "JQDIS", + "description": "group injected contexts queue disable", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR2": { + "description": "configuration register 2", + "fields": [ + { + "name": "ROVSE", + "description": "oversampler enable on scope group regular", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "JOVSE", + "description": "oversampler enable on scope group injected", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "OVSS", + "description": "oversampling shift", + "bit_offset": 5, + "bit_size": 4 + }, + { + "name": "TROVS", + "description": "oversampling discontinuous mode (triggered mode) for group regular", + "bit_offset": 9, + "bit_size": 1, + "enum": "TROVS" + }, + { + "name": "ROVSM", + "description": "Regular Oversampling mode", + "bit_offset": 10, + "bit_size": 1, + "enum": "ROVSM" + }, + { + "name": "RSHIFT1", + "description": "Right-shift data after Offset 1 correction", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "RSHIFT2", + "description": "Right-shift data after Offset 2 correction", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "RSHIFT3", + "description": "Right-shift data after Offset 3 correction", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "RSHIFT4", + "description": "Right-shift data after Offset 4 correction", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "OSVR", + "description": "Oversampling ratio", + "bit_offset": 16, + "bit_size": 10 + }, + { + "name": "LSHIFT", + "description": "Left shift factor", + "bit_offset": 28, + "bit_size": 4 + } + ] + }, + "fieldset/CR": { + "description": "control register", + "fields": [ + { + "name": "ADEN", + "description": "enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ADDIS", + "description": "disable", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ADSTART", + "description": "group regular conversion start", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "JADSTART", + "description": "group injected conversion start", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ADSTP", + "description": "group regular conversion stop", + "bit_offset": 4, + "bit_size": 1, + "enum": "ADSTP" + }, + { + "name": "JADSTP", + "description": "group injected conversion stop", + "bit_offset": 5, + "bit_size": 1, + "enum": "ADSTP" + }, + { + "name": "BOOST", + "description": "Boost mode control", + "bit_offset": 8, + "bit_size": 2, + "enum": "BOOST" + }, + { + "name": "ADCALLIN", + "description": "Linearity calibration", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "LINCALRDYW1", + "description": "Linearity calibration ready Word 1", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "LINCALRDYW2", + "description": "Linearity calibration ready Word 2", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "LINCALRDYW3", + "description": "Linearity calibration ready Word 3", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "LINCALRDYW4", + "description": "Linearity calibration ready Word 4", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "LINCALRDYW5", + "description": "Linearity calibration ready Word 5", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "LINCALRDYW6", + "description": "Linearity calibration ready Word 6", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "ADVREGEN", + "description": "voltage regulator enable", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "DEEPPWD", + "description": "deep power down enable", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "ADCALDIF", + "description": "differential mode for calibration", + "bit_offset": 30, + "bit_size": 1, + "enum": "ADCALDIF" + }, + { + "name": "ADCAL", + "description": "calibration", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/DIFSEL": { + "description": "channel differential or single-ended mode selection register", + "fields": [ + { + "name": "DIFSEL", + "description": "channel differential or single-ended mode for channel", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 20, + "stride": 1 + }, + "enum": "DIFSEL" + } + ] + }, + "fieldset/DR": { + "description": "group regular conversion data register", + "fields": [ + { + "name": "RDATA", + "description": "group regular conversion data", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/HTR1": { + "description": "analog watchdog 2 threshold register", + "fields": [ + { + "name": "HTR1", + "description": "analog watchdog 2 threshold low", + "bit_offset": 0, + "bit_size": 26 + } + ] + }, + "fieldset/HTR2": { + "description": "watchdog higher threshold register 2", + "fields": [ + { + "name": "HTR2", + "description": "Analog watchdog 2 higher threshold", + "bit_offset": 0, + "bit_size": 26 + } + ] + }, + "fieldset/HTR3": { + "description": "watchdog higher threshold register 3", + "fields": [ + { + "name": "HTR3", + "description": "Analog watchdog 3 higher threshold", + "bit_offset": 0, + "bit_size": 26 + } + ] + }, + "fieldset/IER": { + "description": "interrupt enable register", + "fields": [ + { + "name": "ADRDYIE", + "description": "ready interrupt", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "EOSMPIE", + "description": "group regular end of sampling interrupt", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EOCIE", + "description": "group regular end of unitary conversion interrupt", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "EOSIE", + "description": "group regular end of sequence conversions interrupt", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "OVRIE", + "description": "group regular overrun interrupt", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "JEOCIE", + "description": "group injected end of unitary conversion interrupt", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "JEOSIE", + "description": "group injected end of sequence conversions interrupt", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AWD1IE", + "description": "analog watchdog 1 interrupt", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AWD2IE", + "description": "analog watchdog 2 interrupt", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AWD3IE", + "description": "analog watchdog 3 interrupt", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "JQOVFIE", + "description": "group injected contexts queue overflow interrupt", + "bit_offset": 10, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "interrupt and status register", + "fields": [ + { + "name": "ADRDY", + "description": "ready flag", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "EOSMP", + "description": "group regular end of sampling flag", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EOC", + "description": "group regular end of unitary conversion flag", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "EOS", + "description": "group regular end of sequence conversions flag", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "OVR", + "description": "group regular overrun flag", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "JEOC", + "description": "group injected end of unitary conversion flag", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "JEOS", + "description": "group injected end of sequence conversions flag", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AWD1", + "description": "analog watchdog 1 flag", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AWD2", + "description": "analog watchdog 2 flag", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AWD3", + "description": "analog watchdog 3 flag", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "JQOVF", + "description": "group injected contexts queue overflow flag", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "LDORDY", + "description": "ADC LDO output voltage ready (not always available)", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/JDR": { + "description": "group injected sequencer rank 1 register", + "fields": [ + { + "name": "JDATA", + "description": "group injected sequencer rank 1 conversion data", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/JSQR": { + "description": "group injected sequencer register", + "fields": [ + { + "name": "JL", + "description": "group injected sequencer scan length", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "JEXTSEL", + "description": "group injected external trigger source", + "bit_offset": 2, + "bit_size": 5 + }, + { + "name": "JEXTEN", + "description": "group injected external trigger polarity", + "bit_offset": 7, + "bit_size": 2, + "enum": "JEXTEN" + }, + { + "name": "JSQ1", + "description": "group injected sequencer rank 1-4", + "bit_offset": 9, + "bit_size": 5, + "array": { + "len": 4, + "stride": 6 + } + } + ] + }, + "fieldset/LTR1": { + "description": "analog watchdog 1 threshold register", + "fields": [ + { + "name": "LTR1", + "description": "analog watchdog 1 threshold low", + "bit_offset": 0, + "bit_size": 26 + } + ] + }, + "fieldset/LTR2": { + "description": "watchdog lower threshold register 2", + "fields": [ + { + "name": "LTR2", + "description": "Analog watchdog 2 lower threshold", + "bit_offset": 0, + "bit_size": 26 + } + ] + }, + "fieldset/LTR3": { + "description": "watchdog lower threshold register 3", + "fields": [ + { + "name": "LTR3", + "description": "Analog watchdog 3 lower threshold", + "bit_offset": 0, + "bit_size": 26 + } + ] + }, + "fieldset/OFR": { + "description": "offset number x register", + "fields": [ + { + "name": "OFFSET1", + "description": "offset number x offset level", + "bit_offset": 0, + "bit_size": 26 + }, + { + "name": "OFFSET1_CH", + "description": "offset number x channel selection", + "bit_offset": 26, + "bit_size": 5 + }, + { + "name": "SSATE", + "description": "Signed saturation enable", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/PCSEL": { + "description": "channel preselection register", + "fields": [ + { + "name": "PCSEL", + "description": "Channel x (VINP[i]) pre selection", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 20, + "stride": 1 + }, + "enum": "PCSEL" + } + ] + }, + "fieldset/SMPR": { + "description": "sampling time register n", + "fields": [ + { + "name": "SMP", + "description": "channel n * 10 + x sampling time", + "bit_offset": 0, + "bit_size": 3, + "array": { + "len": 10, + "stride": 3 + }, + "enum": "SAMPLE_TIME" + } + ] + }, + "fieldset/SQR1": { + "description": "group regular sequencer ranks register 1", + "fields": [ + { + "name": "L", + "description": "L3", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "SQ", + "description": "group regular sequencer rank 1-4", + "bit_offset": 6, + "bit_size": 5, + "array": { + "len": 4, + "stride": 6 + } + } + ] + }, + "fieldset/SQR2": { + "description": "group regular sequencer ranks register 2", + "fields": [ + { + "name": "SQ", + "description": "group regular sequencer rank 5-9", + "bit_offset": 0, + "bit_size": 5, + "array": { + "len": 5, + "stride": 6 + } + } + ] + }, + "fieldset/SQR3": { + "description": "group regular sequencer ranks register 3", + "fields": [ + { + "name": "SQ", + "description": "group regular sequencer rank 10-14", + "bit_offset": 0, + "bit_size": 5, + "array": { + "len": 5, + "stride": 6 + } + } + ] + }, + "fieldset/SQR4": { + "description": "group regular sequencer ranks register 4", + "fields": [ + { + "name": "SQ", + "description": "group regular sequencer rank 15-16", + "bit_offset": 0, + "bit_size": 5, + "array": { + "len": 2, + "stride": 6 + } + } + ] + }, + "enum/ADCALDIF": { + "bit_size": 1, + "variants": [ + { + "name": "SingleEnded", + "description": "Calibration for single-ended mode", + "value": 0 + }, + { + "name": "Differential", + "description": "Calibration for differential mode", + "value": 1 + } + ] + }, + "enum/ADSTP": { + "bit_size": 1, + "variants": [ + { + "name": "Stop", + "description": "Stop conversion of channel", + "value": 1 + } + ] + }, + "enum/AWD1SGL": { + "bit_size": 1, + "variants": [ + { + "name": "All", + "description": "Analog watchdog 1 enabled on all channels", + "value": 0 + }, + { + "name": "Single", + "description": "Analog watchdog 1 enabled on single channel selected in AWD1CH", + "value": 1 + } + ] + }, + "enum/BOOST": { + "bit_size": 2, + "variants": [ + { + "name": "LT6_25", + "description": "Boost mode used when clock ≤ 6.25 MHz", + "value": 0 + }, + { + "name": "LT12_5", + "description": "Boost mode used when 6.25 MHz < clock ≤ 12.5 MHz", + "value": 1 + }, + { + "name": "LT25", + "description": "Boost mode used when 12.5 MHz < clock ≤ 25.0 MHz", + "value": 2 + }, + { + "name": "LT50", + "description": "Boost mode used when 25.0 MHz < clock ≤ 50.0 MHz", + "value": 3 + } + ] + }, + "enum/DIFSEL": { + "bit_size": 1, + "variants": [ + { + "name": "SingleEnded", + "description": "Input channel is configured in single-ended mode", + "value": 0 + }, + { + "name": "Differential", + "description": "Input channel is configured in differential mode", + "value": 1 + } + ] + }, + "enum/DMNGT": { + "bit_size": 2, + "variants": [ + { + "name": "DR", + "description": "Store output data in DR only", + "value": 0 + }, + { + "name": "DMA_OneShot", + "description": "DMA One Shot Mode selected", + "value": 1 + }, + { + "name": "DFSDM", + "description": "DFSDM mode selected", + "value": 2 + }, + { + "name": "DMA_Circular", + "description": "DMA Circular Mode selected", + "value": 3 + } + ] + }, + "enum/EXTEN": { + "bit_size": 2, + "variants": [ + { + "name": "Disabled", + "description": "Trigger detection disabled", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "Trigger detection on the rising edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "Trigger detection on the falling edge", + "value": 2 + }, + { + "name": "BothEdges", + "description": "Trigger detection on both the rising and falling edges", + "value": 3 + } + ] + }, + "enum/JEXTEN": { + "bit_size": 2, + "variants": [ + { + "name": "Disabled", + "description": "Trigger detection disabled", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "Trigger detection on the rising edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "Trigger detection on the falling edge", + "value": 2 + }, + { + "name": "BothEdges", + "description": "Trigger detection on both the rising and falling edges", + "value": 3 + } + ] + }, + "enum/JQM": { + "bit_size": 1, + "variants": [ + { + "name": "Mode0", + "description": "JSQR Mode 0: Queue maintains the last written configuration into JSQR", + "value": 0 + }, + { + "name": "Mode1", + "description": "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence", + "value": 1 + } + ] + }, + "enum/OVRMOD": { + "bit_size": 1, + "variants": [ + { + "name": "Preserve", + "description": "Preserve DR register when an overrun is detected", + "value": 0 + }, + { + "name": "Overwrite", + "description": "Overwrite DR register when an overrun is detected", + "value": 1 + } + ] + }, + "enum/PCSEL": { + "bit_size": 1, + "variants": [ + { + "name": "NotPreselected", + "description": "Input channel x is not pre-selected", + "value": 0 + }, + { + "name": "Preselected", + "description": "Pre-select input channel x", + "value": 1 + } + ] + }, + "enum/RES": { + "bit_size": 3, + "variants": [ + { + "name": "Bits12", + "description": "12-bit resolution", + "value": 0 + }, + { + "name": "Bits10", + "description": "10-bit resolution", + "value": 1 + }, + { + "name": "Bits8", + "description": "8-bit resolution", + "value": 2 + }, + { + "name": "Bits6", + "description": "6-bit resolution", + "value": 3 + } + ] + }, + "enum/ROVSM": { + "bit_size": 1, + "variants": [ + { + "name": "Continued", + "description": "Oversampling is temporary stopped and continued after injection sequence", + "value": 0 + }, + { + "name": "Resumed", + "description": "Oversampling is aborted and resumed from start after injection sequence", + "value": 1 + } + ] + }, + "enum/SAMPLE_TIME": { + "bit_size": 3, + "variants": [ + { + "name": "Cycles2_5", + "description": "2.5 clock cycles", + "value": 0 + }, + { + "name": "Cycles6_5", + "description": "6.5 clock cycles", + "value": 1 + }, + { + "name": "Cycles12_5", + "description": "12.5 clock cycles", + "value": 2 + }, + { + "name": "Cycles24_5", + "description": "24.5 clock cycles", + "value": 3 + }, + { + "name": "Cycles47_5", + "description": "47.5 clock cycles", + "value": 4 + }, + { + "name": "Cycles92_5", + "description": "92.5 clock cycles", + "value": 5 + }, + { + "name": "Cycles247_5", + "description": "247.5 clock cycles", + "value": 6 + }, + { + "name": "Cycles640_5", + "description": "640.5 clock cycles", + "value": 7 + } + ] + }, + "enum/TROVS": { + "bit_size": 1, + "variants": [ + { + "name": "Automatic", + "description": "All oversampled conversions for a channel are run following a trigger", + "value": 0 + }, + { + "name": "Triggered", + "description": "Each oversampled conversion for a channel needs a new trigger", + "value": 1 + } + ] + } +} \ No newline at end of file