diff --git a/data/chips/STM32H503CB.json b/data/chips/STM32H503CB.json index b00bf98..77ea515 100644 --- a/data/chips/STM32H503CB.json +++ b/data/chips/STM32H503CB.json @@ -341,6 +341,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H503EB.json b/data/chips/STM32H503EB.json index 0604b7a..5c81a1a 100644 --- a/data/chips/STM32H503EB.json +++ b/data/chips/STM32H503EB.json @@ -284,6 +284,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H503KB.json b/data/chips/STM32H503KB.json index 5ad20b2..2c801a5 100644 --- a/data/chips/STM32H503KB.json +++ b/data/chips/STM32H503KB.json @@ -333,6 +333,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H503RB.json b/data/chips/STM32H503RB.json index 1a30fb5..5fa61af 100644 --- a/data/chips/STM32H503RB.json +++ b/data/chips/STM32H503RB.json @@ -386,6 +386,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index 223b0f2..dfa7373 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -875,6 +875,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index 1605bbc..ddc0e79 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -886,6 +886,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index bf3e024..f86e31d 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -889,6 +889,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index fba53fa..499d9ef 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -900,6 +900,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index 77b21ea..c7414c9 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -690,6 +690,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index 392df12..02235dc 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -701,6 +701,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index 06978ca..f55fd8a 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -721,6 +721,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index bc8ccdb..8466176 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -732,6 +732,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index 255658f..dcc90aa 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -790,6 +790,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index 95786b1..7c309a4 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -801,6 +801,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index 0fa2c31..22d858c 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -875,6 +875,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index 71c503e..6f866ed 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -900,6 +900,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 700769e..7b25663 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -889,6 +889,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index 52db8cb..924df21 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -908,6 +908,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index 00cd25b..f87fa0c 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -682,6 +682,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index b974f21..8345433 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -690,6 +690,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index 05780f0..67c63f8 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -701,6 +701,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index dcf98a3..d7e035b 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -721,6 +721,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index 99e76f9..400d14f 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -736,6 +736,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index 995b203..5a99db4 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -790,6 +790,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index e8acda2..899f35b 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -810,6 +810,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 35cd9b8..70e6911 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -944,6 +944,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index dae2cff..9274c1f 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -952,6 +952,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index 2a257f1..97f2fc3 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -726,6 +726,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index 3d7d5f7..da3afa6 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -745,6 +745,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index 88a0b96..c92602e 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -780,6 +780,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index 4bc2888..b772f6d 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -854,6 +854,11 @@ { "name": "DTS", "address": 1073777664, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK1", "kernel_clock": "PCLK1", diff --git a/data/chips/STM32H723VE.json b/data/chips/STM32H723VE.json index 6b88f5c..41c1d78 100644 --- a/data/chips/STM32H723VE.json +++ b/data/chips/STM32H723VE.json @@ -1550,6 +1550,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H723VG.json b/data/chips/STM32H723VG.json index 13f0323..8837341 100644 --- a/data/chips/STM32H723VG.json +++ b/data/chips/STM32H723VG.json @@ -1550,6 +1550,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H723ZE.json b/data/chips/STM32H723ZE.json index ea97d94..bf16c4c 100644 --- a/data/chips/STM32H723ZE.json +++ b/data/chips/STM32H723ZE.json @@ -1712,6 +1712,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H723ZG.json b/data/chips/STM32H723ZG.json index 3200e6f..5d0fadf 100644 --- a/data/chips/STM32H723ZG.json +++ b/data/chips/STM32H723ZG.json @@ -1712,6 +1712,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H725AE.json b/data/chips/STM32H725AE.json index 985d6af..09be13e 100644 --- a/data/chips/STM32H725AE.json +++ b/data/chips/STM32H725AE.json @@ -1758,6 +1758,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H725AG.json b/data/chips/STM32H725AG.json index 065559f..9eaa666 100644 --- a/data/chips/STM32H725AG.json +++ b/data/chips/STM32H725AG.json @@ -1764,6 +1764,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H725IE.json b/data/chips/STM32H725IE.json index 90aa732..65c9c4c 100644 --- a/data/chips/STM32H725IE.json +++ b/data/chips/STM32H725IE.json @@ -1803,6 +1803,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H725IG.json b/data/chips/STM32H725IG.json index dd7f1e9..bb72efc 100644 --- a/data/chips/STM32H725IG.json +++ b/data/chips/STM32H725IG.json @@ -1809,6 +1809,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H725RE.json b/data/chips/STM32H725RE.json index 564fc16..3b13509 100644 --- a/data/chips/STM32H725RE.json +++ b/data/chips/STM32H725RE.json @@ -1330,6 +1330,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H725RG.json b/data/chips/STM32H725RG.json index 960dcc4..f119e17 100644 --- a/data/chips/STM32H725RG.json +++ b/data/chips/STM32H725RG.json @@ -1336,6 +1336,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H725VE.json b/data/chips/STM32H725VE.json index 60f0114..fd19cd7 100644 --- a/data/chips/STM32H725VE.json +++ b/data/chips/STM32H725VE.json @@ -1515,6 +1515,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H725VG.json b/data/chips/STM32H725VG.json index 667bfae..63e9e47 100644 --- a/data/chips/STM32H725VG.json +++ b/data/chips/STM32H725VG.json @@ -1525,6 +1525,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H725ZE.json b/data/chips/STM32H725ZE.json index 67eef17..10ae50b 100644 --- a/data/chips/STM32H725ZE.json +++ b/data/chips/STM32H725ZE.json @@ -1624,6 +1624,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H725ZG.json b/data/chips/STM32H725ZG.json index 0312bd2..3069d9a 100644 --- a/data/chips/STM32H725ZG.json +++ b/data/chips/STM32H725ZG.json @@ -1630,6 +1630,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index 9b524ba..c1d1581 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -1803,6 +1803,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index a4590ef..121d3e7 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -1848,6 +1848,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index 22ad249..b29f01e 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -1589,6 +1589,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index 8204227..dfbcd9b 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -1751,6 +1751,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index 34c06c1..5fe8534 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -1589,6 +1589,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index c699301..84ed834 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -1751,6 +1751,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index f461eb0..713aa2d 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -1803,6 +1803,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index 2b2c623..0115143 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -1848,6 +1848,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H735RG.json b/data/chips/STM32H735RG.json index a43d32c..81a69eb 100644 --- a/data/chips/STM32H735RG.json +++ b/data/chips/STM32H735RG.json @@ -1375,6 +1375,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index 4b7346c..0197393 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -1564,6 +1564,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index f7cbc24..e955ac8 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -1669,6 +1669,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index 16b80ac..b8e61d1 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -1782,6 +1782,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index 52add67..9f35a9a 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -1793,6 +1793,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index fe485f0..346b90b 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -1859,6 +1859,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index 05f1718..b6ca876 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -1870,6 +1870,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index a9b3465..1e86d58 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -1841,6 +1841,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index 83d5d44..9b61afa 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -1858,6 +1858,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index c1b7b32..6b7b385 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -1803,6 +1803,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index 4bff280..4217cc6 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -1814,6 +1814,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index 42d4074..ce80683 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -1698,6 +1698,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3RG.json b/data/chips/STM32H7A3RG.json index 7b5de51..20e7534 100644 --- a/data/chips/STM32H7A3RG.json +++ b/data/chips/STM32H7A3RG.json @@ -1472,6 +1472,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3RI.json b/data/chips/STM32H7A3RI.json index ac99cce..75666ac 100644 --- a/data/chips/STM32H7A3RI.json +++ b/data/chips/STM32H7A3RI.json @@ -1483,6 +1483,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index 49e9eb5..6298c33 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -1656,6 +1656,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index a6a33e8..da93ec4 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -1667,6 +1667,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index 4a208d0..4835724 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -1722,6 +1722,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index 8d56785..949bc5b 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -1733,6 +1733,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index 33ef74d..e9b3a4f 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -1815,6 +1815,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index f95f23c..96852f5 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -1884,6 +1884,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index 46837aa..10f1e73 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -1505,6 +1505,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index e34733c..d46065c 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -1677,6 +1677,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index 197df25..95f9839 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -1751,6 +1751,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index 63fa7ed..4752b2d 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -1832,6 +1832,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index ae4c547..e0118f5 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -1909,6 +1909,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index dfb7d10..973e4af 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -1897,6 +1897,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index ceecbf0..49d85e6 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -1853,6 +1853,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index 3a1be90..d2b319f 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -1737,6 +1737,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 4c40136..bc39e54 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -1522,6 +1522,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index c737122..5a042a7 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -1706,6 +1706,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index f5bf6b2..12a5df1 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -1772,6 +1772,11 @@ { "name": "DTS", "address": 1476421632, + "registers": { + "kind": "dts", + "version": "v1", + "block": "DTS" + }, "rcc": { "bus_clock": "PCLK4", "kernel_clock": "PCLK4", diff --git a/data/registers/dts_v1.json b/data/registers/dts_v1.json new file mode 100644 index 0000000..a7b2f96 --- /dev/null +++ b/data/registers/dts_v1.json @@ -0,0 +1,308 @@ +{ + "block/DTS": { + "description": "Digital temperature sensor.", + "items": [ + { + "name": "CFGR1", + "description": "Temperature sensor configuration register 1.", + "byte_offset": 0, + "fieldset": "CFGR1" + }, + { + "name": "T0VALR1", + "description": "Temperature sensor T0 value register 1.", + "byte_offset": 8, + "fieldset": "T0VALR1" + }, + { + "name": "RAMPVALR", + "description": "Temperature sensor ramp value register.", + "byte_offset": 16, + "fieldset": "RAMPVALR" + }, + { + "name": "ITR1", + "description": "Temperature sensor interrupt threshold register 1.", + "byte_offset": 20, + "fieldset": "ITR1" + }, + { + "name": "DR", + "description": "Temperature sensor data register.", + "byte_offset": 28, + "fieldset": "DR" + }, + { + "name": "SR", + "description": "Temperature sensor status register.", + "byte_offset": 32, + "fieldset": "SR" + }, + { + "name": "ITENR", + "description": "Temperature sensor interrupt enable register.", + "byte_offset": 36, + "fieldset": "ITENR" + }, + { + "name": "ICIFR", + "description": "Temperature sensor clear interrupt flag register.", + "byte_offset": 40, + "fieldset": "ICIFR" + }, + { + "name": "OR", + "description": "Temperature sensor option register.", + "byte_offset": 44, + "fieldset": "OR" + } + ] + }, + "fieldset/CFGR1": { + "description": "Temperature sensor configuration register 1.", + "fields": [ + { + "name": "EN", + "description": "Temperature sensor 1 enable bit This bit is set and cleared by software. Note: Once enabled, the temperature sensor is active after a specific delay time. The TS1_RDY flag will be set when the sensor is ready.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "START", + "description": "Start frequency measurement on temperature sensor 1 This bit is set and cleared by software.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "INTRIG_SEL", + "description": "Input trigger selection bit for temperature sensor 1 These bits are set and cleared by software. They select which input triggers a temperature measurement. Refer to Section 19.3.10: Trigger input.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SMP_TIME", + "description": "Sampling time for temperature sensor 1 These bits allow increasing the sampling time to improve measurement precision. When the PCLK clock is selected as reference clock (REFCLK_SEL = 0), the measurement will be performed at TS1_SMP_TIME period of CLK_PTAT. When the LSE is selected as reference clock (REFCLK_SEL =1), the measurement will be performed at TS1_SMP_TIME period of LSE.", + "bit_offset": 16, + "bit_size": 4 + }, + { + "name": "REFCLK_SEL", + "description": "Reference clock selection bit This bit is set and cleared by software. It indicates whether the reference clock is the high speed clock (PCLK) or the low speed clock (LSE).", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "Q_MEAS_OPT", + "description": "Quick measurement option bit This bit is set and cleared by software. It is used to increase the measurement speed by suppressing the calibration step. It is effective only when the LSE clock is used as reference clock (REFCLK_SEL=1).", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "HSREF_CLK_DIV", + "description": "High speed clock division ratio These bits are set and cleared by software. They can be used to define the division ratio for the main clock in order to obtain the internal frequency lower than 1 MHz required for the calibration. They are applicable only for calibration when PCLK is selected as reference clock (REFCLK_SEL=0). ...", + "bit_offset": 24, + "bit_size": 7 + } + ] + }, + "fieldset/DR": { + "description": "Temperature sensor data register.", + "fields": [ + { + "name": "MFREQ", + "description": "Value of the counter output value for temperature sensor 1.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/ICIFR": { + "description": "Temperature sensor clear interrupt flag register.", + "fields": [ + { + "name": "CITEF", + "description": "Interrupt clear flag for end of measurement on temperature sensor 1 Writing 1 to this bit clears the TS1_ITEF flag in the DTS_SR register.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CITLF", + "description": "Interrupt clear flag for low threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_ITLF flag in the DTS_SR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CITHF", + "description": "Interrupt clear flag for high threshold on temperature sensor 1 Writing this bit to 1 clears the TS1_ITHF flag in the DTS_SR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CAITEF", + "description": "Write once bit. Clear the asynchronous IT flag for End Of Measure for thermal sensor 1. Writing 1 clears the TS1_AITEF flag of the DTS_SR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "CAITLF", + "description": "Asynchronous interrupt clear flag for low threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_AITLF flag in the DTS_SR register.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CAITHF", + "description": "Asynchronous interrupt clear flag for high threshold on temperature sensor 1 Writing 1 to this bit clears the TS1_AITHF flag in the DTS_SR register.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/ITENR": { + "description": "Temperature sensor interrupt enable register.", + "fields": [ + { + "name": "ITEEN", + "description": "Interrupt enable flag for end of measurement on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the synchronous interrupt for end of measurement.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ITLEN", + "description": "Interrupt enable flag for low threshold on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the synchronous interrupt when the measure reaches or is below the low threshold.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ITHEN", + "description": "Interrupt enable flag for high threshold on temperature sensor 1, synchronized on PCLK. This bit are set and cleared by software. It enables the interrupt when the measure reaches or is above the high threshold.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AITEEN", + "description": "Asynchronous interrupt enable flag for end of measurement on temperature sensor 1 This bit are set and cleared by software. It enables the asynchronous interrupt for end of measurement (only when REFCLK_SEL = 1).", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AITLEN", + "description": "Asynchronous interrupt enable flag for low threshold on temperature sensor 1. This bit are set and cleared by software. It enables the asynchronous interrupt when the temperature is below the low threshold (only when REFCLK_SEL= 1).", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AITHEN", + "description": "Asynchronous interrupt enable flag on high threshold for temperature sensor 1. This bit are set and cleared by software. It enables the asynchronous interrupt when the temperature is above the high threshold (only when REFCLK_SEL= 1’’).", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/ITR1": { + "description": "Temperature sensor interrupt threshold register 1.", + "fields": [ + { + "name": "LITTHD", + "description": "Low interrupt threshold for temperature sensor 1 These bits are set and cleared by software. They indicate the lowest value than can be reached before raising an interrupt signal.", + "bit_offset": 0, + "bit_size": 16 + }, + { + "name": "HITTHD", + "description": "High interrupt threshold for temperature sensor 1 These bits are set and cleared by software. They indicate the highest value than can be reached before raising an interrupt signal.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/OR": { + "description": "Temperature sensor option register.", + "fields": [ + { + "name": "OP", + "description": "general purpose option bits.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/RAMPVALR": { + "description": "Temperature sensor ramp value register.", + "fields": [ + { + "name": "RAMP_COEFF", + "description": "Engineering value of the ramp coefficient for the temperature sensor 1. This value is expressed in Hz/�C.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/SR": { + "description": "Temperature sensor status register.", + "fields": [ + { + "name": "ITEF", + "description": "Interrupt flag for end of measurement on temperature sensor 1, synchronized on PCLK. This bit is set by hardware when a temperature measure is done. It is cleared by software by writing 1 to the TS2_CITEF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITEFEN bit is set.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ITLF", + "description": "Interrupt flag for low threshold on temperature sensor 1, synchronized on PCLK. This bit is set by hardware when the low threshold is set and reached. It is cleared by software by writing 1 to the TS1_CITLF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITLFEN bit is set.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ITHF", + "description": "Interrupt flag for high threshold on temperature sensor 1, synchronized on PCLK This bit is set by hardware when the high threshold is set and reached. It is cleared by software by writing 1 to the TS1_CITHF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_ITHFEN bit is set.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AITEF", + "description": "Asynchronous interrupt flag for end of measure on temperature sensor 1 This bit is set by hardware when a temperature measure is done. It is cleared by software by writing 1 to the TS1_CAITEF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITEFEN bit is set.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AITLF", + "description": "Asynchronous interrupt flag for low threshold on temperature sensor 1 This bit is set by hardware when the low threshold is reached. It is cleared by software by writing 1 to the TS1_CAITLF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITLFEN bit is set.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AITHF", + "description": "Asynchronous interrupt flag for high threshold on temperature sensor 1 This bit is set by hardware when the high threshold is reached. It is cleared by software by writing 1 to the TS1_CAITHF bit in the DTS_ICIFR register. Note: This bit is active only when the TS1_AITHFEN bit is set.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "RDY", + "description": "Temperature sensor 1 ready flag This bit is set and reset by hardware. It indicates that a measurement is ongoing.", + "bit_offset": 15, + "bit_size": 1 + } + ] + }, + "fieldset/T0VALR1": { + "description": "Temperature sensor T0 value register 1.", + "fields": [ + { + "name": "FMT0", + "description": "Engineering value of the frequency measured at T0 for. temperature sensor 1 This value is expressed in 0.1 kHz.", + "bit_offset": 0, + "bit_size": 16 + }, + { + "name": "T0", + "description": "Engineering value of the T0 temperature for temperature sensor 1. Others: Reserved, must not be used.", + "bit_offset": 16, + "bit_size": 2 + } + ] + } +} \ No newline at end of file