diff --git a/data/chips/STM32G431C6.json b/data/chips/STM32G431C6.json index 28823df..c906dea 100644 --- a/data/chips/STM32G431C6.json +++ b/data/chips/STM32G431C6.json @@ -2024,7 +2024,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431C8.json b/data/chips/STM32G431C8.json index 7ea4ce4..147f42f 100644 --- a/data/chips/STM32G431C8.json +++ b/data/chips/STM32G431C8.json @@ -2024,7 +2024,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431CB.json b/data/chips/STM32G431CB.json index 8ff6f2d..261a177 100644 --- a/data/chips/STM32G431CB.json +++ b/data/chips/STM32G431CB.json @@ -2028,7 +2028,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431K6.json b/data/chips/STM32G431K6.json index ff90919..6c38236 100644 --- a/data/chips/STM32G431K6.json +++ b/data/chips/STM32G431K6.json @@ -1820,7 +1820,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431K8.json b/data/chips/STM32G431K8.json index e57ef3d..ae18ce4 100644 --- a/data/chips/STM32G431K8.json +++ b/data/chips/STM32G431K8.json @@ -1820,7 +1820,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431KB.json b/data/chips/STM32G431KB.json index c588b3e..685c2bf 100644 --- a/data/chips/STM32G431KB.json +++ b/data/chips/STM32G431KB.json @@ -1820,7 +1820,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431M6.json b/data/chips/STM32G431M6.json index 6cff356..22c9ad6 100644 --- a/data/chips/STM32G431M6.json +++ b/data/chips/STM32G431M6.json @@ -2151,7 +2151,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431M8.json b/data/chips/STM32G431M8.json index 6567aa3..8f4f1c6 100644 --- a/data/chips/STM32G431M8.json +++ b/data/chips/STM32G431M8.json @@ -2151,7 +2151,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431MB.json b/data/chips/STM32G431MB.json index 51e526e..1f701e9 100644 --- a/data/chips/STM32G431MB.json +++ b/data/chips/STM32G431MB.json @@ -2151,7 +2151,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431R6.json b/data/chips/STM32G431R6.json index b42a726..02456c6 100644 --- a/data/chips/STM32G431R6.json +++ b/data/chips/STM32G431R6.json @@ -2137,7 +2137,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431R8.json b/data/chips/STM32G431R8.json index 839816b..1835b82 100644 --- a/data/chips/STM32G431R8.json +++ b/data/chips/STM32G431R8.json @@ -2137,7 +2137,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431RB.json b/data/chips/STM32G431RB.json index dfb8bd1..1fbd1ff 100644 --- a/data/chips/STM32G431RB.json +++ b/data/chips/STM32G431RB.json @@ -2137,7 +2137,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431V6.json b/data/chips/STM32G431V6.json index 60aa271..3cbda48 100644 --- a/data/chips/STM32G431V6.json +++ b/data/chips/STM32G431V6.json @@ -2168,7 +2168,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431V8.json b/data/chips/STM32G431V8.json index 763a01f..b7881f4 100644 --- a/data/chips/STM32G431V8.json +++ b/data/chips/STM32G431V8.json @@ -2168,7 +2168,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G431VB.json b/data/chips/STM32G431VB.json index c1d682d..28cc23f 100644 --- a/data/chips/STM32G431VB.json +++ b/data/chips/STM32G431VB.json @@ -2168,7 +2168,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G441CB.json b/data/chips/STM32G441CB.json index 1182a98..8b00835 100644 --- a/data/chips/STM32G441CB.json +++ b/data/chips/STM32G441CB.json @@ -2061,7 +2061,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G441KB.json b/data/chips/STM32G441KB.json index 9ec3d7c..69278d8 100644 --- a/data/chips/STM32G441KB.json +++ b/data/chips/STM32G441KB.json @@ -1853,7 +1853,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G441MB.json b/data/chips/STM32G441MB.json index bce50dc..371d3eb 100644 --- a/data/chips/STM32G441MB.json +++ b/data/chips/STM32G441MB.json @@ -2184,7 +2184,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G441RB.json b/data/chips/STM32G441RB.json index 9aa4558..8e748bd 100644 --- a/data/chips/STM32G441RB.json +++ b/data/chips/STM32G441RB.json @@ -2170,7 +2170,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G441VB.json b/data/chips/STM32G441VB.json index 6cd4e77..8982da9 100644 --- a/data/chips/STM32G441VB.json +++ b/data/chips/STM32G441VB.json @@ -2201,7 +2201,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471CC.json b/data/chips/STM32G471CC.json index 2efff08..064b0b9 100644 --- a/data/chips/STM32G471CC.json +++ b/data/chips/STM32G471CC.json @@ -2095,7 +2095,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471CE.json b/data/chips/STM32G471CE.json index bc755ce..741cb98 100644 --- a/data/chips/STM32G471CE.json +++ b/data/chips/STM32G471CE.json @@ -2095,7 +2095,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471MC.json b/data/chips/STM32G471MC.json index e46ba1a..be3067c 100644 --- a/data/chips/STM32G471MC.json +++ b/data/chips/STM32G471MC.json @@ -2313,7 +2313,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471ME.json b/data/chips/STM32G471ME.json index 0beda81..c3e114d 100644 --- a/data/chips/STM32G471ME.json +++ b/data/chips/STM32G471ME.json @@ -2317,7 +2317,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471QC.json b/data/chips/STM32G471QC.json index 5a17cbf..d6afd7c 100644 --- a/data/chips/STM32G471QC.json +++ b/data/chips/STM32G471QC.json @@ -2477,7 +2477,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471QE.json b/data/chips/STM32G471QE.json index de495b2..16f3675 100644 --- a/data/chips/STM32G471QE.json +++ b/data/chips/STM32G471QE.json @@ -2477,7 +2477,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471RC.json b/data/chips/STM32G471RC.json index 3e3157e..5736e83 100644 --- a/data/chips/STM32G471RC.json +++ b/data/chips/STM32G471RC.json @@ -2224,7 +2224,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471RE.json b/data/chips/STM32G471RE.json index b331949..d6dce89 100644 --- a/data/chips/STM32G471RE.json +++ b/data/chips/STM32G471RE.json @@ -2224,7 +2224,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471VC.json b/data/chips/STM32G471VC.json index b816976..96139b9 100644 --- a/data/chips/STM32G471VC.json +++ b/data/chips/STM32G471VC.json @@ -2385,7 +2385,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G471VE.json b/data/chips/STM32G471VE.json index 06ab6c8..88c00c2 100644 --- a/data/chips/STM32G471VE.json +++ b/data/chips/STM32G471VE.json @@ -2385,7 +2385,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473CB.json b/data/chips/STM32G473CB.json index dba82ce..efccbeb 100644 --- a/data/chips/STM32G473CB.json +++ b/data/chips/STM32G473CB.json @@ -2812,7 +2812,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473CC.json b/data/chips/STM32G473CC.json index 2e0831c..bc147f4 100644 --- a/data/chips/STM32G473CC.json +++ b/data/chips/STM32G473CC.json @@ -2812,7 +2812,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473CE.json b/data/chips/STM32G473CE.json index 89b6799..4d2dfb2 100644 --- a/data/chips/STM32G473CE.json +++ b/data/chips/STM32G473CE.json @@ -2812,7 +2812,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473MB.json b/data/chips/STM32G473MB.json index 74ad31d..cc8f26e 100644 --- a/data/chips/STM32G473MB.json +++ b/data/chips/STM32G473MB.json @@ -3156,7 +3156,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473MC.json b/data/chips/STM32G473MC.json index a9292de..86a518d 100644 --- a/data/chips/STM32G473MC.json +++ b/data/chips/STM32G473MC.json @@ -3156,7 +3156,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473ME.json b/data/chips/STM32G473ME.json index 2f4da32..f11b3a3 100644 --- a/data/chips/STM32G473ME.json +++ b/data/chips/STM32G473ME.json @@ -3160,7 +3160,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473PB.json b/data/chips/STM32G473PB.json index 0ab3fc0..2ff37c0 100644 --- a/data/chips/STM32G473PB.json +++ b/data/chips/STM32G473PB.json @@ -3689,7 +3689,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473PC.json b/data/chips/STM32G473PC.json index 140be87..9e6aa38 100644 --- a/data/chips/STM32G473PC.json +++ b/data/chips/STM32G473PC.json @@ -3689,7 +3689,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473PE.json b/data/chips/STM32G473PE.json index f901343..3fe4a79 100644 --- a/data/chips/STM32G473PE.json +++ b/data/chips/STM32G473PE.json @@ -3689,7 +3689,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473QB.json b/data/chips/STM32G473QB.json index 623ba19..7d4cecf 100644 --- a/data/chips/STM32G473QB.json +++ b/data/chips/STM32G473QB.json @@ -3765,7 +3765,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473QC.json b/data/chips/STM32G473QC.json index 5039bec..4425601 100644 --- a/data/chips/STM32G473QC.json +++ b/data/chips/STM32G473QC.json @@ -3765,7 +3765,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473QE.json b/data/chips/STM32G473QE.json index 40dc310..5698751 100644 --- a/data/chips/STM32G473QE.json +++ b/data/chips/STM32G473QE.json @@ -3765,7 +3765,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473RB.json b/data/chips/STM32G473RB.json index e45df2c..ff6abbc 100644 --- a/data/chips/STM32G473RB.json +++ b/data/chips/STM32G473RB.json @@ -2959,7 +2959,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473RC.json b/data/chips/STM32G473RC.json index 129a223..bc1ab90 100644 --- a/data/chips/STM32G473RC.json +++ b/data/chips/STM32G473RC.json @@ -2959,7 +2959,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473RE.json b/data/chips/STM32G473RE.json index 3857611..b71e425 100644 --- a/data/chips/STM32G473RE.json +++ b/data/chips/STM32G473RE.json @@ -2959,7 +2959,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473VB.json b/data/chips/STM32G473VB.json index 9c4ca3b..6efe182 100644 --- a/data/chips/STM32G473VB.json +++ b/data/chips/STM32G473VB.json @@ -3564,7 +3564,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473VC.json b/data/chips/STM32G473VC.json index 2ab54f6..6436252 100644 --- a/data/chips/STM32G473VC.json +++ b/data/chips/STM32G473VC.json @@ -3564,7 +3564,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G473VE.json b/data/chips/STM32G473VE.json index 85c12de..4a35028 100644 --- a/data/chips/STM32G473VE.json +++ b/data/chips/STM32G473VE.json @@ -3564,7 +3564,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474CB.json b/data/chips/STM32G474CB.json index 40eb094..c9ca00c 100644 --- a/data/chips/STM32G474CB.json +++ b/data/chips/STM32G474CB.json @@ -3058,7 +3058,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474CC.json b/data/chips/STM32G474CC.json index 37ce659..b3faf18 100644 --- a/data/chips/STM32G474CC.json +++ b/data/chips/STM32G474CC.json @@ -3058,7 +3058,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474CE.json b/data/chips/STM32G474CE.json index aed6c3e..a21ba75 100644 --- a/data/chips/STM32G474CE.json +++ b/data/chips/STM32G474CE.json @@ -3058,7 +3058,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474MB.json b/data/chips/STM32G474MB.json index c317b6c..caf0769 100644 --- a/data/chips/STM32G474MB.json +++ b/data/chips/STM32G474MB.json @@ -3432,7 +3432,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474MC.json b/data/chips/STM32G474MC.json index ca0f93e..a02d9be 100644 --- a/data/chips/STM32G474MC.json +++ b/data/chips/STM32G474MC.json @@ -3432,7 +3432,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474ME.json b/data/chips/STM32G474ME.json index 60112dd..8635b95 100644 --- a/data/chips/STM32G474ME.json +++ b/data/chips/STM32G474ME.json @@ -3436,7 +3436,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474PB.json b/data/chips/STM32G474PB.json index 6f594ee..19b1fed 100644 --- a/data/chips/STM32G474PB.json +++ b/data/chips/STM32G474PB.json @@ -3953,7 +3953,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474PC.json b/data/chips/STM32G474PC.json index 6f31d5a..dd595ba 100644 --- a/data/chips/STM32G474PC.json +++ b/data/chips/STM32G474PC.json @@ -3953,7 +3953,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474PE.json b/data/chips/STM32G474PE.json index 1640277..988193a 100644 --- a/data/chips/STM32G474PE.json +++ b/data/chips/STM32G474PE.json @@ -3953,7 +3953,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474QB.json b/data/chips/STM32G474QB.json index eb2428e..b4f4917 100644 --- a/data/chips/STM32G474QB.json +++ b/data/chips/STM32G474QB.json @@ -4041,7 +4041,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474QC.json b/data/chips/STM32G474QC.json index d2c8f35..22dd9d3 100644 --- a/data/chips/STM32G474QC.json +++ b/data/chips/STM32G474QC.json @@ -4041,7 +4041,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474QE.json b/data/chips/STM32G474QE.json index 504dc30..0507f45 100644 --- a/data/chips/STM32G474QE.json +++ b/data/chips/STM32G474QE.json @@ -4041,7 +4041,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474RB.json b/data/chips/STM32G474RB.json index eb49d22..3169699 100644 --- a/data/chips/STM32G474RB.json +++ b/data/chips/STM32G474RB.json @@ -3235,7 +3235,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474RC.json b/data/chips/STM32G474RC.json index 4acb7d5..9d35ade 100644 --- a/data/chips/STM32G474RC.json +++ b/data/chips/STM32G474RC.json @@ -3235,7 +3235,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474RE.json b/data/chips/STM32G474RE.json index 7540bb6..db62679 100644 --- a/data/chips/STM32G474RE.json +++ b/data/chips/STM32G474RE.json @@ -3235,7 +3235,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474VB.json b/data/chips/STM32G474VB.json index d10a997..af9db76 100644 --- a/data/chips/STM32G474VB.json +++ b/data/chips/STM32G474VB.json @@ -3840,7 +3840,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474VC.json b/data/chips/STM32G474VC.json index f7659f3..f55cbd3 100644 --- a/data/chips/STM32G474VC.json +++ b/data/chips/STM32G474VC.json @@ -3840,7 +3840,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G474VE.json b/data/chips/STM32G474VE.json index 0853e8a..1b16019 100644 --- a/data/chips/STM32G474VE.json +++ b/data/chips/STM32G474VE.json @@ -3840,7 +3840,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483CE.json b/data/chips/STM32G483CE.json index aa62782..35debc6 100644 --- a/data/chips/STM32G483CE.json +++ b/data/chips/STM32G483CE.json @@ -2851,7 +2851,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483ME.json b/data/chips/STM32G483ME.json index da30fd9..c1773de 100644 --- a/data/chips/STM32G483ME.json +++ b/data/chips/STM32G483ME.json @@ -3199,7 +3199,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483PE.json b/data/chips/STM32G483PE.json index 15fc71e..883d246 100644 --- a/data/chips/STM32G483PE.json +++ b/data/chips/STM32G483PE.json @@ -3728,7 +3728,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483QE.json b/data/chips/STM32G483QE.json index e3855e5..801bf0c 100644 --- a/data/chips/STM32G483QE.json +++ b/data/chips/STM32G483QE.json @@ -3804,7 +3804,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483RE.json b/data/chips/STM32G483RE.json index 2727541..a8b7922 100644 --- a/data/chips/STM32G483RE.json +++ b/data/chips/STM32G483RE.json @@ -2998,7 +2998,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G483VE.json b/data/chips/STM32G483VE.json index 2aba5d7..82d344e 100644 --- a/data/chips/STM32G483VE.json +++ b/data/chips/STM32G483VE.json @@ -3603,7 +3603,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484CE.json b/data/chips/STM32G484CE.json index 4dc0dd1..e5d0195 100644 --- a/data/chips/STM32G484CE.json +++ b/data/chips/STM32G484CE.json @@ -3091,7 +3091,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484ME.json b/data/chips/STM32G484ME.json index d0afcfd..a7e054d 100644 --- a/data/chips/STM32G484ME.json +++ b/data/chips/STM32G484ME.json @@ -3469,7 +3469,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484PE.json b/data/chips/STM32G484PE.json index b72102f..98eaff9 100644 --- a/data/chips/STM32G484PE.json +++ b/data/chips/STM32G484PE.json @@ -3992,7 +3992,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484QE.json b/data/chips/STM32G484QE.json index 066c5eb..f775ad5 100644 --- a/data/chips/STM32G484QE.json +++ b/data/chips/STM32G484QE.json @@ -4074,7 +4074,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484RE.json b/data/chips/STM32G484RE.json index c06333b..3dde6ea 100644 --- a/data/chips/STM32G484RE.json +++ b/data/chips/STM32G484RE.json @@ -3268,7 +3268,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G484VE.json b/data/chips/STM32G484VE.json index 1b7825c..03ccf39 100644 --- a/data/chips/STM32G484VE.json +++ b/data/chips/STM32G484VE.json @@ -3873,7 +3873,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491CC.json b/data/chips/STM32G491CC.json index 0b585b7..ff66d55 100644 --- a/data/chips/STM32G491CC.json +++ b/data/chips/STM32G491CC.json @@ -2290,7 +2290,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491CE.json b/data/chips/STM32G491CE.json index 2fd3bec..a0b481d 100644 --- a/data/chips/STM32G491CE.json +++ b/data/chips/STM32G491CE.json @@ -2290,7 +2290,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491KC.json b/data/chips/STM32G491KC.json index 2b6a67a..9bc7654 100644 --- a/data/chips/STM32G491KC.json +++ b/data/chips/STM32G491KC.json @@ -2007,7 +2007,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491KE.json b/data/chips/STM32G491KE.json index 37600a3..0807b9b 100644 --- a/data/chips/STM32G491KE.json +++ b/data/chips/STM32G491KE.json @@ -2007,7 +2007,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491MC.json b/data/chips/STM32G491MC.json index 7a23336..48f50a3 100644 --- a/data/chips/STM32G491MC.json +++ b/data/chips/STM32G491MC.json @@ -2506,7 +2506,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491ME.json b/data/chips/STM32G491ME.json index 272a049..2f75bc7 100644 --- a/data/chips/STM32G491ME.json +++ b/data/chips/STM32G491ME.json @@ -2506,7 +2506,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491RC.json b/data/chips/STM32G491RC.json index fcf053e..1c73c11 100644 --- a/data/chips/STM32G491RC.json +++ b/data/chips/STM32G491RC.json @@ -2418,7 +2418,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491RE.json b/data/chips/STM32G491RE.json index b599152..fccac73 100644 --- a/data/chips/STM32G491RE.json +++ b/data/chips/STM32G491RE.json @@ -2422,7 +2422,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491VC.json b/data/chips/STM32G491VC.json index 363056a..cbcc082 100644 --- a/data/chips/STM32G491VC.json +++ b/data/chips/STM32G491VC.json @@ -2570,7 +2570,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G491VE.json b/data/chips/STM32G491VE.json index 91a07c3..779d717 100644 --- a/data/chips/STM32G491VE.json +++ b/data/chips/STM32G491VE.json @@ -2570,7 +2570,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G4A1CE.json b/data/chips/STM32G4A1CE.json index 955cba0..5eab502 100644 --- a/data/chips/STM32G4A1CE.json +++ b/data/chips/STM32G4A1CE.json @@ -2329,7 +2329,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G4A1KE.json b/data/chips/STM32G4A1KE.json index 2f2cc14..d102dd8 100644 --- a/data/chips/STM32G4A1KE.json +++ b/data/chips/STM32G4A1KE.json @@ -2046,7 +2046,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G4A1ME.json b/data/chips/STM32G4A1ME.json index 14b0a4f..fea3b34 100644 --- a/data/chips/STM32G4A1ME.json +++ b/data/chips/STM32G4A1ME.json @@ -2545,7 +2545,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G4A1RE.json b/data/chips/STM32G4A1RE.json index 1f61b2b..82183c2 100644 --- a/data/chips/STM32G4A1RE.json +++ b/data/chips/STM32G4A1RE.json @@ -2461,7 +2461,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32G4A1VE.json b/data/chips/STM32G4A1VE.json index 9b2f3a9..cabc5d1 100644 --- a/data/chips/STM32G4A1VE.json +++ b/data/chips/STM32G4A1VE.json @@ -2609,7 +2609,7 @@ "address": 1073828864, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index c587924..db26fb7 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -4244,6 +4244,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4448,6 +4453,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index 1ce65fa..f8b022c 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -4255,6 +4255,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4459,6 +4464,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index 4b51b69..6504904 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -4288,6 +4288,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4492,6 +4497,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index 5925846..abbc77f 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -4299,6 +4299,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4503,6 +4508,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index 55ee487..d95607f 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -2853,6 +2853,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -2967,6 +2972,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index 9f67f3f..e6d9196 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -2864,6 +2864,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -2978,6 +2983,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index 9d18bc3..06cbaf7 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -3397,6 +3397,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3566,6 +3571,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index a24d42e..b1ee68a 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -3408,6 +3408,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3577,6 +3582,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index e8e8100..b82680c 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -3921,6 +3921,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4125,6 +4130,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index c1d7279..a0c75ed 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -3932,6 +3932,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4136,6 +4141,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index 4363448..2862f91 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -4517,6 +4517,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4721,6 +4726,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index e6934e9..5675314 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -4557,6 +4557,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4761,6 +4766,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 1c56192..19ec099 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -4566,6 +4566,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4770,6 +4775,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index e487c27..7222b7c 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -4585,6 +4585,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4789,6 +4794,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index 72baae3..533db38 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -3192,6 +3192,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3296,6 +3301,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index fe9698e..8216d7a 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -3071,6 +3071,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3185,6 +3190,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index 5158474..7b2f1bd 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -3082,6 +3082,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3196,6 +3201,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index 59ac585..20bfed8 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -3620,6 +3620,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3789,6 +3794,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index 5f98611..2c9606b 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -3650,6 +3650,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3819,6 +3824,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index 966111d..ef2fb17 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -4169,6 +4169,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4373,6 +4378,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index b18cb5b..001bacb 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -4224,6 +4224,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4428,6 +4433,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 0bf4b80..b5b4974 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -4699,6 +4699,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4903,6 +4908,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index 8906394..d1615c8 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -4727,6 +4727,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4931,6 +4936,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index 5b70db4..de63488 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -3334,6 +3334,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3438,6 +3443,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index daaafa0..e7c8a30 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -3224,6 +3224,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3338,6 +3343,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index f33c5eb..dba7be7 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -3792,6 +3792,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3961,6 +3966,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index 1a9d6fc..f077e21 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -4366,6 +4366,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4570,6 +4575,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32H723VE.json b/data/chips/STM32H723VE.json index 1238c3b..1eac80c 100644 --- a/data/chips/STM32H723VE.json +++ b/data/chips/STM32H723VE.json @@ -4436,7 +4436,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4560,7 +4560,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H723VG.json b/data/chips/STM32H723VG.json index 6532a1e..5a20290 100644 --- a/data/chips/STM32H723VG.json +++ b/data/chips/STM32H723VG.json @@ -4436,7 +4436,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4560,7 +4560,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H723ZE.json b/data/chips/STM32H723ZE.json index 4f79c24..c0bf20f 100644 --- a/data/chips/STM32H723ZE.json +++ b/data/chips/STM32H723ZE.json @@ -5072,7 +5072,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5226,7 +5226,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H723ZG.json b/data/chips/STM32H723ZG.json index 7c54230..5154761 100644 --- a/data/chips/STM32H723ZG.json +++ b/data/chips/STM32H723ZG.json @@ -5072,7 +5072,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5226,7 +5226,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725AE.json b/data/chips/STM32H725AE.json index 7c17967..906e5d6 100644 --- a/data/chips/STM32H725AE.json +++ b/data/chips/STM32H725AE.json @@ -5258,7 +5258,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5412,7 +5412,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725AG.json b/data/chips/STM32H725AG.json index cdc2089..a046c99 100644 --- a/data/chips/STM32H725AG.json +++ b/data/chips/STM32H725AG.json @@ -5264,7 +5264,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5418,7 +5418,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725IE.json b/data/chips/STM32H725IE.json index f62213e..fc63ae6 100644 --- a/data/chips/STM32H725IE.json +++ b/data/chips/STM32H725IE.json @@ -5463,7 +5463,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5617,7 +5617,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725IG.json b/data/chips/STM32H725IG.json index c1464fa..932f893 100644 --- a/data/chips/STM32H725IG.json +++ b/data/chips/STM32H725IG.json @@ -5469,7 +5469,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5623,7 +5623,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725RE.json b/data/chips/STM32H725RE.json index 2f8acb0..aaa7eb3 100644 --- a/data/chips/STM32H725RE.json +++ b/data/chips/STM32H725RE.json @@ -3172,7 +3172,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725RG.json b/data/chips/STM32H725RG.json index 57fdf34..ff240a0 100644 --- a/data/chips/STM32H725RG.json +++ b/data/chips/STM32H725RG.json @@ -3178,7 +3178,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725VE.json b/data/chips/STM32H725VE.json index a18bf04..4f5b36d 100644 --- a/data/chips/STM32H725VE.json +++ b/data/chips/STM32H725VE.json @@ -4321,7 +4321,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4445,7 +4445,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725VG.json b/data/chips/STM32H725VG.json index 2252a97..b687215 100644 --- a/data/chips/STM32H725VG.json +++ b/data/chips/STM32H725VG.json @@ -4331,7 +4331,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4455,7 +4455,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725ZE.json b/data/chips/STM32H725ZE.json index 7f5119b..9e1f34e 100644 --- a/data/chips/STM32H725ZE.json +++ b/data/chips/STM32H725ZE.json @@ -4805,7 +4805,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4959,7 +4959,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H725ZG.json b/data/chips/STM32H725ZG.json index 4793121..64462d9 100644 --- a/data/chips/STM32H725ZG.json +++ b/data/chips/STM32H725ZG.json @@ -4811,7 +4811,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4965,7 +4965,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index 440359d..b88d2bb 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -5369,7 +5369,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5523,7 +5523,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index 37d93a2..c39a06c 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -5574,7 +5574,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5728,7 +5728,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index c824ef0..c4d15b2 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -4541,7 +4541,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4665,7 +4665,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index 7277d0b..1be144b 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -5177,7 +5177,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5331,7 +5331,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index 7326119..1d177a0 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -4541,7 +4541,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4665,7 +4665,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index dcce7e7..b11fc5b 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -5177,7 +5177,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5331,7 +5331,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index d37062b..b29de6a 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -5369,7 +5369,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5523,7 +5523,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index 7ac7624..3b9633a 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -5574,7 +5574,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5728,7 +5728,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index ad9c33b..7e52f33 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -4436,7 +4436,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4560,7 +4560,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index 0fd0605..36768f0 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -4916,7 +4916,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5070,7 +5070,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742AG.json b/data/chips/STM32H742AG.json index 0d59c60..91d9eb4 100644 --- a/data/chips/STM32H742AG.json +++ b/data/chips/STM32H742AG.json @@ -4315,7 +4315,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4469,7 +4469,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4615,7 +4615,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4696,7 +4696,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742AI.json b/data/chips/STM32H742AI.json index fcd1ab9..7b90583 100644 --- a/data/chips/STM32H742AI.json +++ b/data/chips/STM32H742AI.json @@ -4326,7 +4326,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4480,7 +4480,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4626,7 +4626,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4707,7 +4707,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742BG.json b/data/chips/STM32H742BG.json index ee5c3aa..8cc576d 100644 --- a/data/chips/STM32H742BG.json +++ b/data/chips/STM32H742BG.json @@ -4468,7 +4468,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4622,7 +4622,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4778,7 +4778,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4859,7 +4859,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742BI.json b/data/chips/STM32H742BI.json index 116add7..10734ba 100644 --- a/data/chips/STM32H742BI.json +++ b/data/chips/STM32H742BI.json @@ -4479,7 +4479,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4633,7 +4633,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4789,7 +4789,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4870,7 +4870,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742IG.json b/data/chips/STM32H742IG.json index 6bfb45f..6938b5b 100644 --- a/data/chips/STM32H742IG.json +++ b/data/chips/STM32H742IG.json @@ -4472,7 +4472,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4626,7 +4626,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4782,7 +4782,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4863,7 +4863,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742II.json b/data/chips/STM32H742II.json index 0270e58..3d4d7e3 100644 --- a/data/chips/STM32H742II.json +++ b/data/chips/STM32H742II.json @@ -4483,7 +4483,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4637,7 +4637,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4793,7 +4793,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4874,7 +4874,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742VG.json b/data/chips/STM32H742VG.json index 8220698..d6dbc58 100644 --- a/data/chips/STM32H742VG.json +++ b/data/chips/STM32H742VG.json @@ -3712,7 +3712,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -3836,7 +3836,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -3947,7 +3947,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4028,7 +4028,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742VI.json b/data/chips/STM32H742VI.json index dd32744..4e6ddae 100644 --- a/data/chips/STM32H742VI.json +++ b/data/chips/STM32H742VI.json @@ -3723,7 +3723,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -3847,7 +3847,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -3958,7 +3958,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4039,7 +4039,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742XG.json b/data/chips/STM32H742XG.json index f2fb070..3cfa002 100644 --- a/data/chips/STM32H742XG.json +++ b/data/chips/STM32H742XG.json @@ -4532,7 +4532,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4686,7 +4686,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4842,7 +4842,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4923,7 +4923,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742XI.json b/data/chips/STM32H742XI.json index c1c59ba..ea88621 100644 --- a/data/chips/STM32H742XI.json +++ b/data/chips/STM32H742XI.json @@ -4543,7 +4543,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4697,7 +4697,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4853,7 +4853,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4934,7 +4934,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742ZG.json b/data/chips/STM32H742ZG.json index d3b99de..52a6794 100644 --- a/data/chips/STM32H742ZG.json +++ b/data/chips/STM32H742ZG.json @@ -4128,7 +4128,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4282,7 +4282,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4408,7 +4408,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4489,7 +4489,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H742ZI.json b/data/chips/STM32H742ZI.json index 9cadf46..a9c7e56 100644 --- a/data/chips/STM32H742ZI.json +++ b/data/chips/STM32H742ZI.json @@ -4139,7 +4139,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4293,7 +4293,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4419,7 +4419,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4500,7 +4500,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743AG.json b/data/chips/STM32H743AG.json index c18c80c..1821177 100644 --- a/data/chips/STM32H743AG.json +++ b/data/chips/STM32H743AG.json @@ -4740,7 +4740,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4894,7 +4894,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5040,7 +5040,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5121,7 +5121,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743AI.json b/data/chips/STM32H743AI.json index 300a233..5e89a3a 100644 --- a/data/chips/STM32H743AI.json +++ b/data/chips/STM32H743AI.json @@ -4751,7 +4751,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4905,7 +4905,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5051,7 +5051,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5132,7 +5132,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743BG.json b/data/chips/STM32H743BG.json index ae85d23..9c99f77 100644 --- a/data/chips/STM32H743BG.json +++ b/data/chips/STM32H743BG.json @@ -5073,7 +5073,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5227,7 +5227,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5383,7 +5383,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5464,7 +5464,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743BI.json b/data/chips/STM32H743BI.json index 4acd0c0..eabc904 100644 --- a/data/chips/STM32H743BI.json +++ b/data/chips/STM32H743BI.json @@ -5084,7 +5084,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5238,7 +5238,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5394,7 +5394,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5475,7 +5475,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743IG.json b/data/chips/STM32H743IG.json index ed65357..63c1189 100644 --- a/data/chips/STM32H743IG.json +++ b/data/chips/STM32H743IG.json @@ -4917,7 +4917,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5071,7 +5071,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5227,7 +5227,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5308,7 +5308,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743II.json b/data/chips/STM32H743II.json index 8179766..82aa028 100644 --- a/data/chips/STM32H743II.json +++ b/data/chips/STM32H743II.json @@ -4928,7 +4928,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5082,7 +5082,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5238,7 +5238,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5319,7 +5319,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743VG.json b/data/chips/STM32H743VG.json index 068a5f8..4885c22 100644 --- a/data/chips/STM32H743VG.json +++ b/data/chips/STM32H743VG.json @@ -3992,7 +3992,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4116,7 +4116,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4227,7 +4227,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4308,7 +4308,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743VI.json b/data/chips/STM32H743VI.json index f0bf842..ff67e75 100644 --- a/data/chips/STM32H743VI.json +++ b/data/chips/STM32H743VI.json @@ -4003,7 +4003,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4127,7 +4127,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4238,7 +4238,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4319,7 +4319,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743XG.json b/data/chips/STM32H743XG.json index 833c39e..385dea2 100644 --- a/data/chips/STM32H743XG.json +++ b/data/chips/STM32H743XG.json @@ -5137,7 +5137,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5291,7 +5291,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5447,7 +5447,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5528,7 +5528,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743XI.json b/data/chips/STM32H743XI.json index 803f622..dc27610 100644 --- a/data/chips/STM32H743XI.json +++ b/data/chips/STM32H743XI.json @@ -5148,7 +5148,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5302,7 +5302,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5458,7 +5458,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5539,7 +5539,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743ZG.json b/data/chips/STM32H743ZG.json index 1ee8513..a7ea107 100644 --- a/data/chips/STM32H743ZG.json +++ b/data/chips/STM32H743ZG.json @@ -4463,7 +4463,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4617,7 +4617,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4743,7 +4743,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4824,7 +4824,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H743ZI.json b/data/chips/STM32H743ZI.json index 74fafd0..35d84b6 100644 --- a/data/chips/STM32H743ZI.json +++ b/data/chips/STM32H743ZI.json @@ -4474,7 +4474,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4628,7 +4628,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4754,7 +4754,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4835,7 +4835,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745BG.json b/data/chips/STM32H745BG.json index fd36149..8be1b79 100644 --- a/data/chips/STM32H745BG.json +++ b/data/chips/STM32H745BG.json @@ -4959,7 +4959,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5113,7 +5113,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5269,7 +5269,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5350,7 +5350,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14767,7 +14767,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14921,7 +14921,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15077,7 +15077,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15158,7 +15158,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745BI.json b/data/chips/STM32H745BI.json index c612937..c2defe2 100644 --- a/data/chips/STM32H745BI.json +++ b/data/chips/STM32H745BI.json @@ -4970,7 +4970,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5124,7 +5124,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5280,7 +5280,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5361,7 +5361,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14778,7 +14778,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14932,7 +14932,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15088,7 +15088,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15169,7 +15169,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745IG.json b/data/chips/STM32H745IG.json index ff4734f..784432b 100644 --- a/data/chips/STM32H745IG.json +++ b/data/chips/STM32H745IG.json @@ -4845,7 +4845,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4999,7 +4999,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5135,7 +5135,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5216,7 +5216,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14395,7 +14395,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14549,7 +14549,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14685,7 +14685,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14766,7 +14766,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745II.json b/data/chips/STM32H745II.json index 8fd8880..6beb85b 100644 --- a/data/chips/STM32H745II.json +++ b/data/chips/STM32H745II.json @@ -4856,7 +4856,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5010,7 +5010,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5146,7 +5146,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5227,7 +5227,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14406,7 +14406,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14560,7 +14560,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14696,7 +14696,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14777,7 +14777,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745XG.json b/data/chips/STM32H745XG.json index 4c5c826..ef70f4c 100644 --- a/data/chips/STM32H745XG.json +++ b/data/chips/STM32H745XG.json @@ -5128,7 +5128,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5282,7 +5282,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5438,7 +5438,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5519,7 +5519,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15105,7 +15105,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15259,7 +15259,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15415,7 +15415,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15496,7 +15496,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745XI.json b/data/chips/STM32H745XI.json index 6563e04..7175177 100644 --- a/data/chips/STM32H745XI.json +++ b/data/chips/STM32H745XI.json @@ -5139,7 +5139,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5293,7 +5293,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5449,7 +5449,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5530,7 +5530,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15116,7 +15116,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15270,7 +15270,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15426,7 +15426,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15507,7 +15507,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745ZG.json b/data/chips/STM32H745ZG.json index be3c655..24ee17c 100644 --- a/data/chips/STM32H745ZG.json +++ b/data/chips/STM32H745ZG.json @@ -4299,7 +4299,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4453,7 +4453,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4579,7 +4579,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4660,7 +4660,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13042,7 +13042,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13196,7 +13196,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13322,7 +13322,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13403,7 +13403,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H745ZI.json b/data/chips/STM32H745ZI.json index 411a936..d8e07d2 100644 --- a/data/chips/STM32H745ZI.json +++ b/data/chips/STM32H745ZI.json @@ -4310,7 +4310,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4464,7 +4464,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4590,7 +4590,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4671,7 +4671,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13053,7 +13053,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13207,7 +13207,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13333,7 +13333,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13414,7 +13414,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747AG.json b/data/chips/STM32H747AG.json index e20586a..a9ffaf8 100644 --- a/data/chips/STM32H747AG.json +++ b/data/chips/STM32H747AG.json @@ -4460,7 +4460,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4614,7 +4614,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4740,7 +4740,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4821,7 +4821,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13422,7 +13422,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13576,7 +13576,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13702,7 +13702,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13783,7 +13783,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747AI.json b/data/chips/STM32H747AI.json index 627f96f..aa4b6ea 100644 --- a/data/chips/STM32H747AI.json +++ b/data/chips/STM32H747AI.json @@ -4471,7 +4471,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4625,7 +4625,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4751,7 +4751,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4832,7 +4832,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13433,7 +13433,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13587,7 +13587,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13713,7 +13713,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13794,7 +13794,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747BG.json b/data/chips/STM32H747BG.json index 6c098f5..8c0960b 100644 --- a/data/chips/STM32H747BG.json +++ b/data/chips/STM32H747BG.json @@ -4920,7 +4920,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5074,7 +5074,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5230,7 +5230,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5311,7 +5311,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14557,7 +14557,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14711,7 +14711,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14867,7 +14867,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14948,7 +14948,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747BI.json b/data/chips/STM32H747BI.json index 1cebfc1..bd7a346 100644 --- a/data/chips/STM32H747BI.json +++ b/data/chips/STM32H747BI.json @@ -4931,7 +4931,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5085,7 +5085,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5241,7 +5241,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5322,7 +5322,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14568,7 +14568,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14722,7 +14722,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14878,7 +14878,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14959,7 +14959,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747IG.json b/data/chips/STM32H747IG.json index 4779d18..cc4c5e8 100644 --- a/data/chips/STM32H747IG.json +++ b/data/chips/STM32H747IG.json @@ -4460,7 +4460,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4614,7 +4614,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4740,7 +4740,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4821,7 +4821,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13422,7 +13422,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13576,7 +13576,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13702,7 +13702,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13783,7 +13783,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747II.json b/data/chips/STM32H747II.json index 9ff1cdb..b51bb1f 100644 --- a/data/chips/STM32H747II.json +++ b/data/chips/STM32H747II.json @@ -4471,7 +4471,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4625,7 +4625,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4751,7 +4751,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4832,7 +4832,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13433,7 +13433,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13587,7 +13587,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13713,7 +13713,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13794,7 +13794,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747XG.json b/data/chips/STM32H747XG.json index 121ee0e..37c4483 100644 --- a/data/chips/STM32H747XG.json +++ b/data/chips/STM32H747XG.json @@ -5134,7 +5134,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5288,7 +5288,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5444,7 +5444,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5525,7 +5525,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15115,7 +15115,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15269,7 +15269,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15425,7 +15425,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15506,7 +15506,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747XI.json b/data/chips/STM32H747XI.json index 4acc4f1..4ae3dc4 100644 --- a/data/chips/STM32H747XI.json +++ b/data/chips/STM32H747XI.json @@ -5145,7 +5145,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5299,7 +5299,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5455,7 +5455,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5536,7 +5536,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15126,7 +15126,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15280,7 +15280,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15436,7 +15436,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15517,7 +15517,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H747ZI.json b/data/chips/STM32H747ZI.json index dcbf619..6a0d865 100644 --- a/data/chips/STM32H747ZI.json +++ b/data/chips/STM32H747ZI.json @@ -4209,7 +4209,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4333,7 +4333,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4449,7 +4449,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4530,7 +4530,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12628,7 +12628,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12752,7 +12752,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12868,7 +12868,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12949,7 +12949,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H750IB.json b/data/chips/STM32H750IB.json index 5d50c2a..73b859b 100644 --- a/data/chips/STM32H750IB.json +++ b/data/chips/STM32H750IB.json @@ -4966,7 +4966,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5120,7 +5120,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5276,7 +5276,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5357,7 +5357,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H750VB.json b/data/chips/STM32H750VB.json index d2d804c..15087a6 100644 --- a/data/chips/STM32H750VB.json +++ b/data/chips/STM32H750VB.json @@ -4037,7 +4037,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4161,7 +4161,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4272,7 +4272,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4353,7 +4353,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H750XB.json b/data/chips/STM32H750XB.json index b965aa0..17911de 100644 --- a/data/chips/STM32H750XB.json +++ b/data/chips/STM32H750XB.json @@ -5186,7 +5186,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5340,7 +5340,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5496,7 +5496,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5577,7 +5577,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H750ZB.json b/data/chips/STM32H750ZB.json index 9dff204..d654468 100644 --- a/data/chips/STM32H750ZB.json +++ b/data/chips/STM32H750ZB.json @@ -4500,7 +4500,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4654,7 +4654,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4780,7 +4780,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4861,7 +4861,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753AI.json b/data/chips/STM32H753AI.json index c079313..04e76bf 100644 --- a/data/chips/STM32H753AI.json +++ b/data/chips/STM32H753AI.json @@ -4818,7 +4818,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4972,7 +4972,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5118,7 +5118,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5199,7 +5199,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753BI.json b/data/chips/STM32H753BI.json index 7f0b096..1d4bfb4 100644 --- a/data/chips/STM32H753BI.json +++ b/data/chips/STM32H753BI.json @@ -5151,7 +5151,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5305,7 +5305,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5461,7 +5461,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5542,7 +5542,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753II.json b/data/chips/STM32H753II.json index a176607..70ebb15 100644 --- a/data/chips/STM32H753II.json +++ b/data/chips/STM32H753II.json @@ -4995,7 +4995,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5149,7 +5149,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5305,7 +5305,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5386,7 +5386,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753VI.json b/data/chips/STM32H753VI.json index ec1b896..897c4f4 100644 --- a/data/chips/STM32H753VI.json +++ b/data/chips/STM32H753VI.json @@ -4070,7 +4070,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4194,7 +4194,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4305,7 +4305,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4386,7 +4386,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753XI.json b/data/chips/STM32H753XI.json index 65e2dde..d0ce8ee 100644 --- a/data/chips/STM32H753XI.json +++ b/data/chips/STM32H753XI.json @@ -5215,7 +5215,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5369,7 +5369,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5525,7 +5525,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5606,7 +5606,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H753ZI.json b/data/chips/STM32H753ZI.json index 9364351..9a7138a 100644 --- a/data/chips/STM32H753ZI.json +++ b/data/chips/STM32H753ZI.json @@ -4541,7 +4541,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4695,7 +4695,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4821,7 +4821,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4902,7 +4902,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H755BI.json b/data/chips/STM32H755BI.json index a71f895..2743bfe 100644 --- a/data/chips/STM32H755BI.json +++ b/data/chips/STM32H755BI.json @@ -5049,7 +5049,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5203,7 +5203,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5359,7 +5359,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5440,7 +5440,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14934,7 +14934,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15088,7 +15088,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15244,7 +15244,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15325,7 +15325,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H755II.json b/data/chips/STM32H755II.json index 791a297..9b3a1e5 100644 --- a/data/chips/STM32H755II.json +++ b/data/chips/STM32H755II.json @@ -4935,7 +4935,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5089,7 +5089,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5225,7 +5225,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5306,7 +5306,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14562,7 +14562,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14716,7 +14716,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14852,7 +14852,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14933,7 +14933,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H755XI.json b/data/chips/STM32H755XI.json index 3f10166..3b2e44f 100644 --- a/data/chips/STM32H755XI.json +++ b/data/chips/STM32H755XI.json @@ -5218,7 +5218,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5372,7 +5372,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5528,7 +5528,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5609,7 +5609,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15272,7 +15272,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15426,7 +15426,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15582,7 +15582,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15663,7 +15663,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H755ZI.json b/data/chips/STM32H755ZI.json index 2016c65..e36fa63 100644 --- a/data/chips/STM32H755ZI.json +++ b/data/chips/STM32H755ZI.json @@ -4389,7 +4389,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4543,7 +4543,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4669,7 +4669,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4750,7 +4750,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13209,7 +13209,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13363,7 +13363,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13489,7 +13489,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13570,7 +13570,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H757AI.json b/data/chips/STM32H757AI.json index 513ee3f..30123ad 100644 --- a/data/chips/STM32H757AI.json +++ b/data/chips/STM32H757AI.json @@ -4550,7 +4550,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4704,7 +4704,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4830,7 +4830,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4911,7 +4911,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13589,7 +13589,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13743,7 +13743,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13869,7 +13869,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13950,7 +13950,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H757BI.json b/data/chips/STM32H757BI.json index ac698d8..8505a8f 100644 --- a/data/chips/STM32H757BI.json +++ b/data/chips/STM32H757BI.json @@ -5010,7 +5010,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5164,7 +5164,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5320,7 +5320,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5401,7 +5401,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14724,7 +14724,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -14878,7 +14878,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15034,7 +15034,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15115,7 +15115,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H757II.json b/data/chips/STM32H757II.json index 9da3d0b..29324e0 100644 --- a/data/chips/STM32H757II.json +++ b/data/chips/STM32H757II.json @@ -4550,7 +4550,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4704,7 +4704,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4830,7 +4830,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4911,7 +4911,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13589,7 +13589,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13743,7 +13743,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13869,7 +13869,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13950,7 +13950,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H757XI.json b/data/chips/STM32H757XI.json index 911b121..e0db0b6 100644 --- a/data/chips/STM32H757XI.json +++ b/data/chips/STM32H757XI.json @@ -5224,7 +5224,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5378,7 +5378,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5534,7 +5534,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -5615,7 +5615,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15282,7 +15282,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15436,7 +15436,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15592,7 +15592,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -15673,7 +15673,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H757ZI.json b/data/chips/STM32H757ZI.json index 4abb693..6592b3c 100644 --- a/data/chips/STM32H757ZI.json +++ b/data/chips/STM32H757ZI.json @@ -4288,7 +4288,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4412,7 +4412,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4528,7 +4528,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -4609,7 +4609,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12784,7 +12784,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -12908,7 +12908,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13024,7 +13024,7 @@ "address": 1073831936, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { @@ -13105,7 +13105,7 @@ "address": 1476416512, "registers": { "kind": "sai", - "version": "v3", + "version": "v3_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3AG.json b/data/chips/STM32H7A3AG.json index 6eea03a..a24ef30 100644 --- a/data/chips/STM32H7A3AG.json +++ b/data/chips/STM32H7A3AG.json @@ -4776,7 +4776,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4930,7 +4930,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3AI.json b/data/chips/STM32H7A3AI.json index 8f1dba1..ba08fa0 100644 --- a/data/chips/STM32H7A3AI.json +++ b/data/chips/STM32H7A3AI.json @@ -4787,7 +4787,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4941,7 +4941,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3IG.json b/data/chips/STM32H7A3IG.json index 272e8d9..578c27e 100644 --- a/data/chips/STM32H7A3IG.json +++ b/data/chips/STM32H7A3IG.json @@ -5189,7 +5189,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5343,7 +5343,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3II.json b/data/chips/STM32H7A3II.json index 7ded080..ea3f74f 100644 --- a/data/chips/STM32H7A3II.json +++ b/data/chips/STM32H7A3II.json @@ -5200,7 +5200,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5354,7 +5354,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3LG.json b/data/chips/STM32H7A3LG.json index 93d59d1..b91f936 100644 --- a/data/chips/STM32H7A3LG.json +++ b/data/chips/STM32H7A3LG.json @@ -5341,7 +5341,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5495,7 +5495,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3LI.json b/data/chips/STM32H7A3LI.json index d741a0a..0775217 100644 --- a/data/chips/STM32H7A3LI.json +++ b/data/chips/STM32H7A3LI.json @@ -5358,7 +5358,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5512,7 +5512,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3NG.json b/data/chips/STM32H7A3NG.json index b17b96f..f064dea 100644 --- a/data/chips/STM32H7A3NG.json +++ b/data/chips/STM32H7A3NG.json @@ -5303,7 +5303,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5457,7 +5457,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3NI.json b/data/chips/STM32H7A3NI.json index d0d821a..16ece5a 100644 --- a/data/chips/STM32H7A3NI.json +++ b/data/chips/STM32H7A3NI.json @@ -5314,7 +5314,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5468,7 +5468,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3QI.json b/data/chips/STM32H7A3QI.json index f17a388..db4ffb8 100644 --- a/data/chips/STM32H7A3QI.json +++ b/data/chips/STM32H7A3QI.json @@ -4253,7 +4253,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4367,7 +4367,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3RG.json b/data/chips/STM32H7A3RG.json index 8e94281..ec3bf7c 100644 --- a/data/chips/STM32H7A3RG.json +++ b/data/chips/STM32H7A3RG.json @@ -3220,7 +3220,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3RI.json b/data/chips/STM32H7A3RI.json index 337fbba..fca5ece 100644 --- a/data/chips/STM32H7A3RI.json +++ b/data/chips/STM32H7A3RI.json @@ -3231,7 +3231,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3VG.json b/data/chips/STM32H7A3VG.json index 427af0d..6b3d600 100644 --- a/data/chips/STM32H7A3VG.json +++ b/data/chips/STM32H7A3VG.json @@ -4106,7 +4106,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4230,7 +4230,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3VI.json b/data/chips/STM32H7A3VI.json index 6714597..57d4aa3 100644 --- a/data/chips/STM32H7A3VI.json +++ b/data/chips/STM32H7A3VI.json @@ -4117,7 +4117,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4241,7 +4241,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3ZG.json b/data/chips/STM32H7A3ZG.json index 7e31c7e..f8fad01 100644 --- a/data/chips/STM32H7A3ZG.json +++ b/data/chips/STM32H7A3ZG.json @@ -4586,7 +4586,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4740,7 +4740,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7A3ZI.json b/data/chips/STM32H7A3ZI.json index 322cc96..14039de 100644 --- a/data/chips/STM32H7A3ZI.json +++ b/data/chips/STM32H7A3ZI.json @@ -4597,7 +4597,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4751,7 +4751,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index d8e2b3f..8ecc6a5 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -4863,7 +4863,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5017,7 +5017,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index cee7e7f..bd2ca0d 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -5233,7 +5233,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5387,7 +5387,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index 90b29c3..a25f13e 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -3297,7 +3297,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index 0f7fbc5..4586e5d 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -4171,7 +4171,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4295,7 +4295,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index f5b2de5..153bd7b 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -4669,7 +4669,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4823,7 +4823,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index 85307b4..73b426f 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -4880,7 +4880,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5034,7 +5034,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index 1f53c0d..5645e93 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -5293,7 +5293,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5447,7 +5447,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index 4f7f3df..29fba1d 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -5451,7 +5451,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5605,7 +5605,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index a5c8ecf..d5d8bd5 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -5407,7 +5407,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -5561,7 +5561,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index f0e6edb..6160c5c 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -4336,7 +4336,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4450,7 +4450,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 6257459..64db75f 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -3314,7 +3314,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index f879c70..1335cc1 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -4200,7 +4200,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4324,7 +4324,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index 017f7e6..35c732c 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -4690,7 +4690,7 @@ "address": 1073829888, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { @@ -4844,7 +4844,7 @@ "address": 1073830912, "registers": { "kind": "sai", - "version": "v4", + "version": "v4_4pdm", "block": "SAI" }, "rcc": { diff --git a/data/chips/STM32L552CC.json b/data/chips/STM32L552CC.json index 40e0567..e3d8218 100644 --- a/data/chips/STM32L552CC.json +++ b/data/chips/STM32L552CC.json @@ -2005,6 +2005,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2146,6 +2151,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552CE.json b/data/chips/STM32L552CE.json index b510b36..87df37f 100644 --- a/data/chips/STM32L552CE.json +++ b/data/chips/STM32L552CE.json @@ -2013,6 +2013,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2154,6 +2159,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552ME.json b/data/chips/STM32L552ME.json index 32eb9fb..4449f8d 100644 --- a/data/chips/STM32L552ME.json +++ b/data/chips/STM32L552ME.json @@ -2199,6 +2199,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2355,6 +2360,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552QC.json b/data/chips/STM32L552QC.json index 4d5e9d9..7aa1604 100644 --- a/data/chips/STM32L552QC.json +++ b/data/chips/STM32L552QC.json @@ -2787,6 +2787,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3033,6 +3038,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552QE.json b/data/chips/STM32L552QE.json index 67a8c95..0f416da 100644 --- a/data/chips/STM32L552QE.json +++ b/data/chips/STM32L552QE.json @@ -2795,6 +2795,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3041,6 +3046,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552RC.json b/data/chips/STM32L552RC.json index 2a214f3..76fd8e9 100644 --- a/data/chips/STM32L552RC.json +++ b/data/chips/STM32L552RC.json @@ -2156,6 +2156,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2317,6 +2322,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552RE.json b/data/chips/STM32L552RE.json index b97d0c5..81a018a 100644 --- a/data/chips/STM32L552RE.json +++ b/data/chips/STM32L552RE.json @@ -2164,6 +2164,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2325,6 +2330,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552VC.json b/data/chips/STM32L552VC.json index 08e0445..5dcc5ae 100644 --- a/data/chips/STM32L552VC.json +++ b/data/chips/STM32L552VC.json @@ -2537,6 +2537,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2773,6 +2778,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552VE.json b/data/chips/STM32L552VE.json index 8d7f192..fc2d6fc 100644 --- a/data/chips/STM32L552VE.json +++ b/data/chips/STM32L552VE.json @@ -2541,6 +2541,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2777,6 +2782,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552ZC.json b/data/chips/STM32L552ZC.json index 441f58c..a5b93aa 100644 --- a/data/chips/STM32L552ZC.json +++ b/data/chips/STM32L552ZC.json @@ -2812,6 +2812,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3083,6 +3088,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L552ZE.json b/data/chips/STM32L552ZE.json index 7a27b09..98b4d80 100644 --- a/data/chips/STM32L552ZE.json +++ b/data/chips/STM32L552ZE.json @@ -2816,6 +2816,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3087,6 +3092,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index 47a6b2e..bb958c0 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -2096,6 +2096,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2237,6 +2242,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index 45f4c0f..a739fcf 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -2282,6 +2282,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2438,6 +2443,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index d249767..fbf723f 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -2878,6 +2878,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3124,6 +3129,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index 70b024b..43f905f 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -2247,6 +2247,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2408,6 +2413,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index bde9507..36047eb 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -2624,6 +2624,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -2860,6 +2865,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index d074e2e..2f6f917 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -2899,6 +2899,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", @@ -3170,6 +3175,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v3_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": "PCLK2", diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index 5867fcf..1b67849 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -2165,6 +2165,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index 3234097..4e759eb 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -2165,6 +2165,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index f02a670..0c4e270 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -2165,6 +2165,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index 8e2f9e5..bbb39fa 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -2266,6 +2266,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index 58edf68..750baea 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -2132,6 +2132,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index 6f5f86d..df2c268 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -2132,6 +2132,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index 36f0fff..68f11cd 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -2372,6 +2372,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index ae37652..130cd3b 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -2372,6 +2372,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index 5226e54..88a7c01 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -2372,6 +2372,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index fa68a87..c27784e 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -2947,6 +2947,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index 0e0b4ef..bcf6168 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -2947,6 +2947,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index 9c2fb25..d6b938f 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -2285,6 +2285,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index 759f151..17bedc0 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -2386,6 +2386,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 3dee2cc..3f53cdb 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -2252,6 +2252,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index 40b54db..fa7b87e 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -2492,6 +2492,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index af45e04..25ecbab 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -3067,6 +3067,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575AG.json b/data/chips/STM32U575AG.json index e4e5ed4..4dd82b3 100644 --- a/data/chips/STM32U575AG.json +++ b/data/chips/STM32U575AG.json @@ -4649,6 +4649,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4913,6 +4918,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575AI.json b/data/chips/STM32U575AI.json index c8090d8..76d3bcf 100644 --- a/data/chips/STM32U575AI.json +++ b/data/chips/STM32U575AI.json @@ -4649,6 +4649,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4913,6 +4918,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575CG.json b/data/chips/STM32U575CG.json index c353376..0c5dc45 100644 --- a/data/chips/STM32U575CG.json +++ b/data/chips/STM32U575CG.json @@ -2758,6 +2758,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575CI.json b/data/chips/STM32U575CI.json index 12c458b..fd44b2e 100644 --- a/data/chips/STM32U575CI.json +++ b/data/chips/STM32U575CI.json @@ -2758,6 +2758,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575OG.json b/data/chips/STM32U575OG.json index 46e2bfa..a0b7856 100644 --- a/data/chips/STM32U575OG.json +++ b/data/chips/STM32U575OG.json @@ -3536,6 +3536,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575OI.json b/data/chips/STM32U575OI.json index a09b31d..d1ae860 100644 --- a/data/chips/STM32U575OI.json +++ b/data/chips/STM32U575OI.json @@ -3536,6 +3536,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575QG.json b/data/chips/STM32U575QG.json index 6a3f52f..776077d 100644 --- a/data/chips/STM32U575QG.json +++ b/data/chips/STM32U575QG.json @@ -4259,6 +4259,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4498,6 +4503,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575QI.json b/data/chips/STM32U575QI.json index e955eb6..4444703 100644 --- a/data/chips/STM32U575QI.json +++ b/data/chips/STM32U575QI.json @@ -4259,6 +4259,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4498,6 +4503,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575RG.json b/data/chips/STM32U575RG.json index e9fabec..4f21a38 100644 --- a/data/chips/STM32U575RG.json +++ b/data/chips/STM32U575RG.json @@ -3230,6 +3230,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575RI.json b/data/chips/STM32U575RI.json index bc1a26d..c2f163b 100644 --- a/data/chips/STM32U575RI.json +++ b/data/chips/STM32U575RI.json @@ -3230,6 +3230,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575VG.json b/data/chips/STM32U575VG.json index a998b6e..79cc6d5 100644 --- a/data/chips/STM32U575VG.json +++ b/data/chips/STM32U575VG.json @@ -3869,6 +3869,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4098,6 +4103,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575VI.json b/data/chips/STM32U575VI.json index 6153f80..5a7aa6a 100644 --- a/data/chips/STM32U575VI.json +++ b/data/chips/STM32U575VI.json @@ -3869,6 +3869,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4098,6 +4103,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575ZG.json b/data/chips/STM32U575ZG.json index 69b5616..b7be1cb 100644 --- a/data/chips/STM32U575ZG.json +++ b/data/chips/STM32U575ZG.json @@ -4339,6 +4339,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4603,6 +4608,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U575ZI.json b/data/chips/STM32U575ZI.json index 3a69cab..0daed7b 100644 --- a/data/chips/STM32U575ZI.json +++ b/data/chips/STM32U575ZI.json @@ -4339,6 +4339,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4603,6 +4608,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index a2323ef..be0e368 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -4797,6 +4797,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5061,6 +5066,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index c023cae..26ad2c3 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -2906,6 +2906,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index 49b999d..1c1b246 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -3684,6 +3684,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index b6d389d..d7ccf51 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -4407,6 +4407,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4646,6 +4651,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index 453389a..7e0659f 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -3378,6 +3378,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index e4b7ca7..132ef8b 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -4017,6 +4017,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4246,6 +4251,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index 75b0995..8268dc5 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -4487,6 +4487,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4751,6 +4756,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index acdb52b..f8209e5 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -4562,6 +4562,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4826,6 +4831,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index eafe06b..46fbec3 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -4562,6 +4562,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4826,6 +4831,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index c41e1b8..51077a3 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -4157,6 +4157,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4396,6 +4401,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index 5b014e9..d28b63d 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -4157,6 +4157,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4396,6 +4401,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index 89367ae..5216351 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -2976,6 +2976,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index 09c9015..ea5b542 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -2976,6 +2976,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index 511cf06..95b2fb9 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -3732,6 +3732,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3961,6 +3966,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index fd4525b..15615e9 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -3732,6 +3732,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -3961,6 +3966,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index d2b4bdb..2132c67 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -4241,6 +4241,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4505,6 +4510,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index b2da2bd..8556a05 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -4241,6 +4241,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4505,6 +4510,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index 81ba33e..372aa5d 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -5003,6 +5003,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5267,6 +5272,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index b3e89d9..60f952e 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -5028,6 +5028,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5292,6 +5297,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index 5077bc0..779b435 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -5028,6 +5028,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5292,6 +5297,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index 5f8f1c2..e135f19 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -3895,6 +3895,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4119,6 +4124,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index ed2495e..1107e09 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -4000,6 +4000,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4229,6 +4234,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index 6e6496b..faed05a 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -4535,6 +4535,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4799,6 +4804,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index acec42b..ad0fd3d 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -4535,6 +4535,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4799,6 +4804,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index db2f4bf..08adde2 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -4704,6 +4704,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4968,6 +4973,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index c9b35b0..1811804 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -4299,6 +4299,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4538,6 +4543,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index 9997ab1..3754cfb 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -3118,6 +3118,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index ed5cb14..282b816 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -3874,6 +3874,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4103,6 +4108,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 6db0dbd..cc60c35 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -4383,6 +4383,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4647,6 +4652,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 8b47aa0..8fbb762 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -5145,6 +5145,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5409,6 +5414,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index 41b5f6a..7e74a62 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -5170,6 +5170,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -5434,6 +5439,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 9e6503d..4e2c415 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -4037,6 +4037,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4261,6 +4266,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index 2967d3b..3a36c7d 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -4677,6 +4677,11 @@ { "name": "SAI1", "address": 1073828864, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { @@ -4941,6 +4946,11 @@ { "name": "SAI2", "address": 1073829888, + "registers": { + "kind": "sai", + "version": "v4_2pdm", + "block": "SAI" + }, "rcc": { "bus_clock": "PCLK2", "kernel_clock": { diff --git a/data/registers/sai_v3_2pdm.json b/data/registers/sai_v3_2pdm.json new file mode 100644 index 0000000..dbe4698 --- /dev/null +++ b/data/registers/sai_v3_2pdm.json @@ -0,0 +1,916 @@ +{ + "block/CH": { + "description": "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR", + "items": [ + { + "name": "CR1", + "description": "Configuration register 1", + "byte_offset": 0, + "fieldset": "CR1" + }, + { + "name": "CR2", + "description": "Configuration register 2", + "byte_offset": 4, + "fieldset": "CR2" + }, + { + "name": "FRCR", + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "byte_offset": 8, + "fieldset": "FRCR" + }, + { + "name": "SLOTR", + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "byte_offset": 12, + "fieldset": "SLOTR" + }, + { + "name": "IM", + "description": "Interrupt mask register 2", + "byte_offset": 16, + "fieldset": "IM" + }, + { + "name": "SR", + "description": "Status register", + "byte_offset": 20, + "access": "Read", + "fieldset": "SR" + }, + { + "name": "CLRFR", + "description": "Clear flag register", + "byte_offset": 24, + "access": "Write", + "fieldset": "CLRFR" + }, + { + "name": "DR", + "description": "Data register", + "byte_offset": 28, + "fieldset": "DR" + } + ] + }, + "block/SAI": { + "description": "Serial audio interface", + "items": [ + { + "name": "GCR", + "description": "Global configuration register", + "byte_offset": 0, + "fieldset": "GCR" + }, + { + "name": "CH", + "description": "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR", + "array": { + "len": 2, + "stride": 32 + }, + "byte_offset": 4, + "block": "CH" + }, + { + "name": "PDMCR", + "description": "PDM control register", + "byte_offset": 68, + "fieldset": "PDMCR" + }, + { + "name": "PDMDLY", + "description": "PDM delay register", + "byte_offset": 72, + "fieldset": "PDMDLY" + } + ] + }, + "fieldset/CLRFR": { + "description": "Clear flag register", + "fields": [ + { + "name": "COVRUDR", + "description": "Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CMUTEDET", + "description": "Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CWCKCFG", + "description": "Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CCNRDY", + "description": "Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "CAFSDET", + "description": "Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CLFSDET", + "description": "Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/CR1": { + "description": "Configuration register 1", + "fields": [ + { + "name": "MODE", + "description": "SAIx audio block mode immediately", + "bit_offset": 0, + "bit_size": 2, + "enum": "MODE" + }, + { + "name": "PRTCFG", + "description": "Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled.", + "bit_offset": 2, + "bit_size": 2, + "enum": "PRTCFG" + }, + { + "name": "DS", + "description": "Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled.", + "bit_offset": 5, + "bit_size": 3, + "enum": "DS" + }, + { + "name": "LSBFIRST", + "description": "Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first.", + "bit_offset": 8, + "bit_size": 1, + "enum": "LSBFIRST" + }, + { + "name": "CKSTR", + "description": "Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol.", + "bit_offset": 9, + "bit_size": 1, + "enum": "CKSTR" + }, + { + "name": "SYNCEN", + "description": "Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.", + "bit_offset": 10, + "bit_size": 2, + "enum": "SYNCEN" + }, + { + "name": "MONO", + "description": "Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details.", + "bit_offset": 12, + "bit_size": 1, + "enum": "MONO" + }, + { + "name": "OUTDRIV", + "description": "Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration.", + "bit_offset": 13, + "bit_size": 1, + "enum": "OUTDRIV" + }, + { + "name": "SAIEN", + "description": "Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "DMAEN", + "description": "DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "NODIV", + "description": "No fixed divider between MCLK and FS", + "bit_offset": 19, + "bit_size": 1, + "enum": "NODIV" + }, + { + "name": "MCKDIV", + "description": "Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:", + "bit_offset": 20, + "bit_size": 6 + }, + { + "name": "OSR", + "description": "Oversampling ratio for master clock", + "bit_offset": 26, + "bit_size": 1 + } + ] + }, + "fieldset/CR2": { + "description": "Configuration register 2", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold. This bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 3, + "enum": "FTH" + }, + { + "name": "FFLUSH", + "description": "FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TRIS", + "description": "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "MUTE", + "description": "Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "MUTEVAL", + "description": "Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.", + "bit_offset": 6, + "bit_size": 1, + "enum": "MUTEVAL" + }, + { + "name": "MUTECNT", + "description": "Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details.", + "bit_offset": 7, + "bit_size": 6 + }, + { + "name": "CPL", + "description": "Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm.", + "bit_offset": 13, + "bit_size": 1, + "enum": "CPL" + }, + { + "name": "COMP", + "description": "Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected.", + "bit_offset": 14, + "bit_size": 2, + "enum": "COMP" + } + ] + }, + "fieldset/DR": { + "description": "Data register", + "fields": [ + { + "name": "DATA", + "description": "Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/FRCR": { + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "fields": [ + { + "name": "FRL", + "description": "Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "FSALL", + "description": "Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled.", + "bit_offset": 8, + "bit_size": 7 + }, + { + "name": "FSDEF", + "description": "Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "FSPOL", + "description": "Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.", + "bit_offset": 17, + "bit_size": 1, + "enum": "FSPOL" + }, + { + "name": "FSOFF", + "description": "Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.", + "bit_offset": 18, + "bit_size": 1, + "enum": "FSOFF" + } + ] + }, + "fieldset/GCR": { + "description": "Global configuration register", + "fields": [ + { + "name": "SYNCIN", + "description": "Synchronization inputs", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "SYNCOUT", + "description": "Synchronization outputs These bits are set and cleared by software.", + "bit_offset": 4, + "bit_size": 2 + } + ] + }, + "fieldset/IM": { + "description": "Interrupt mask register 2", + "fields": [ + { + "name": "OVRUDRIE", + "description": "Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MUTEDETIE", + "description": "Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "WCKCFGIE", + "description": "Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "FREQIE", + "description": "FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CNRDYIE", + "description": "Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AFSDETIE", + "description": "Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LFSDETIE", + "description": "Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/PDMCR": { + "description": "PDM control register", + "fields": [ + { + "name": "PDMEN", + "description": "PDM enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MICNBR", + "description": "Number of microphones", + "bit_offset": 4, + "bit_size": 2 + }, + { + "name": "CKEN", + "description": "Clock enable of bitstream clock number 1", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + } + ] + }, + "fieldset/PDMDLY": { + "description": "PDM delay register", + "fields": [ + { + "name": "DLYML", + "description": "Delay line adjust for first microphone of pair 1", + "bit_offset": 0, + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } + }, + { + "name": "DLYMR", + "description": "Delay line adjust for second microphone of pair 1", + "bit_offset": 4, + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } + } + ] + }, + "fieldset/SLOTR": { + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "fields": [ + { + "name": "FBOFF", + "description": "First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 0, + "bit_size": 5 + }, + { + "name": "SLOTSZ", + "description": "Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 6, + "bit_size": 2, + "enum": "SLOTSZ" + }, + { + "name": "NBSLOT", + "description": "Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SLOTEN", + "description": "Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 16, + "bit_size": 16, + "enum": "SLOTEN" + } + ] + }, + "fieldset/SR": { + "description": "Status register", + "fields": [ + { + "name": "OVRUDR", + "description": "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MUTEDET", + "description": "Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register.", + "bit_offset": 2, + "bit_size": 1, + "enum": "WCKCFG" + }, + { + "name": "FREQ", + "description": "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CNRDY", + "description": "Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register.", + "bit_offset": 4, + "bit_size": 1, + "enum": "CNRDY" + }, + { + "name": "AFSDET", + "description": "Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LFSDET", + "description": "Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "FLVL", + "description": "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:", + "bit_offset": 16, + "bit_size": 3, + "enum": "FLVL" + } + ] + }, + "enum/CKSTR": { + "bit_size": 1, + "variants": [ + { + "name": "FallingEdge", + "description": "Data strobing edge is falling edge of SCK", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "Data strobing edge is rising edge of SCK", + "value": 1 + } + ] + }, + "enum/CNRDY": { + "bit_size": 1, + "variants": [ + { + "name": "Ready", + "description": "External AC’97 Codec is ready", + "value": 0 + }, + { + "name": "NotReady", + "description": "External AC’97 Codec is not ready", + "value": 1 + } + ] + }, + "enum/COMP": { + "bit_size": 2, + "variants": [ + { + "name": "NoCompanding", + "description": "No companding algorithm", + "value": 0 + }, + { + "name": "MuLaw", + "description": "μ-Law algorithm", + "value": 2 + }, + { + "name": "ALaw", + "description": "A-Law algorithm", + "value": 3 + } + ] + }, + "enum/CPL": { + "bit_size": 1, + "variants": [ + { + "name": "OnesComplement", + "description": "1’s complement representation", + "value": 0 + }, + { + "name": "TwosComplement", + "description": "2’s complement representation", + "value": 1 + } + ] + }, + "enum/DS": { + "bit_size": 3, + "variants": [ + { + "name": "Bit8", + "description": "8 bits", + "value": 2 + }, + { + "name": "Bit10", + "description": "10 bits", + "value": 3 + }, + { + "name": "Bit16", + "description": "16 bits", + "value": 4 + }, + { + "name": "Bit20", + "description": "20 bits", + "value": 5 + }, + { + "name": "Bit24", + "description": "24 bits", + "value": 6 + }, + { + "name": "Bit32", + "description": "32 bits", + "value": 7 + } + ] + }, + "enum/FLVL": { + "bit_size": 3, + "variants": [ + { + "name": "Empty", + "description": "FIFO empty", + "value": 0 + }, + { + "name": "Quarter1", + "description": "FIFO <= 1⁄4 but not empty", + "value": 1 + }, + { + "name": "Quarter2", + "description": "1⁄4 < FIFO <= 1⁄2", + "value": 2 + }, + { + "name": "Quarter3", + "description": "1⁄2 < FIFO <= 3⁄4", + "value": 3 + }, + { + "name": "Quarter4", + "description": "3⁄4 < FIFO but not full", + "value": 4 + }, + { + "name": "Full", + "description": "FIFO full", + "value": 5 + } + ] + }, + "enum/FSOFF": { + "bit_size": 1, + "variants": [ + { + "name": "OnFirst", + "description": "FS is asserted on the first bit of the slot 0", + "value": 0 + }, + { + "name": "BeforeFirst", + "description": "FS is asserted one bit before the first bit of the slot 0", + "value": 1 + } + ] + }, + "enum/FSPOL": { + "bit_size": 1, + "variants": [ + { + "name": "FallingEdge", + "description": "FS is active low (falling edge)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "FS is active high (rising edge)", + "value": 1 + } + ] + }, + "enum/FTH": { + "bit_size": 3, + "variants": [ + { + "name": "Empty", + "description": "FIFO empty", + "value": 0 + }, + { + "name": "Quarter1", + "description": "1⁄4 FIFO", + "value": 1 + }, + { + "name": "Quarter2", + "description": "1⁄2 FIFO", + "value": 2 + }, + { + "name": "Quarter3", + "description": "3⁄4 FIFO", + "value": 3 + }, + { + "name": "Full", + "description": "FIFO full", + "value": 4 + } + ] + }, + "enum/LSBFIRST": { + "bit_size": 1, + "variants": [ + { + "name": "MsbFirst", + "description": "Data are transferred with MSB first", + "value": 0 + }, + { + "name": "LsbFirst", + "description": "Data are transferred with LSB first", + "value": 1 + } + ] + }, + "enum/MODE": { + "bit_size": 2, + "variants": [ + { + "name": "MasterTx", + "description": "Master transmitter", + "value": 0 + }, + { + "name": "MasterRx", + "description": "Master receiver", + "value": 1 + }, + { + "name": "SlaveTx", + "description": "Slave transmitter", + "value": 2 + }, + { + "name": "SlaveRx", + "description": "Slave receiver", + "value": 3 + } + ] + }, + "enum/MONO": { + "bit_size": 1, + "variants": [ + { + "name": "Stereo", + "description": "Stereo mode", + "value": 0 + }, + { + "name": "Mono", + "description": "Mono mode", + "value": 1 + } + ] + }, + "enum/MUTEVAL": { + "bit_size": 1, + "variants": [ + { + "name": "SendZero", + "description": "Bit value 0 is sent during the mute mode", + "value": 0 + }, + { + "name": "SendLast", + "description": "Last values are sent during the mute mode", + "value": 1 + } + ] + }, + "enum/NODIV": { + "bit_size": 1, + "variants": [ + { + "name": "MasterClock", + "description": "MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value", + "value": 0 + }, + { + "name": "NoDiv", + "description": "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.", + "value": 1 + } + ] + }, + "enum/OUTDRIV": { + "bit_size": 1, + "variants": [ + { + "name": "OnStart", + "description": "Audio block output driven when SAIEN is set", + "value": 0 + }, + { + "name": "Immediately", + "description": "Audio block output driven immediately after the setting of this bit", + "value": 1 + } + ] + }, + "enum/PRTCFG": { + "bit_size": 2, + "variants": [ + { + "name": "Free", + "description": "Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol", + "value": 0 + }, + { + "name": "Spdif", + "description": "SPDIF protocol", + "value": 1 + }, + { + "name": "Ac97", + "description": "AC’97 protocol", + "value": 2 + } + ] + }, + "enum/SLOTEN": { + "bit_size": 16, + "variants": [ + { + "name": "Inactive", + "description": "Inactive slot", + "value": 0 + }, + { + "name": "Active", + "description": "Active slot", + "value": 1 + } + ] + }, + "enum/SLOTSZ": { + "bit_size": 2, + "variants": [ + { + "name": "DataSize", + "description": "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)", + "value": 0 + }, + { + "name": "Bit16", + "description": "16-bit", + "value": 1 + }, + { + "name": "Bit32", + "description": "32-bit", + "value": 2 + } + ] + }, + "enum/SYNCEN": { + "bit_size": 2, + "variants": [ + { + "name": "Asynchronous", + "description": "audio sub-block in asynchronous mode", + "value": 0 + }, + { + "name": "Internal", + "description": "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode", + "value": 1 + }, + { + "name": "External", + "description": "audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode", + "value": 2 + } + ] + }, + "enum/WCKCFG": { + "bit_size": 1, + "variants": [ + { + "name": "Correct", + "description": "Clock configuration is correct", + "value": 0 + }, + { + "name": "Wrong", + "description": "Clock configuration does not respect the rule concerning the frame length specification", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/sai_v3_4pdm.json b/data/registers/sai_v3_4pdm.json new file mode 100644 index 0000000..cf40008 --- /dev/null +++ b/data/registers/sai_v3_4pdm.json @@ -0,0 +1,916 @@ +{ + "block/CH": { + "description": "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR", + "items": [ + { + "name": "CR1", + "description": "Configuration register 1", + "byte_offset": 0, + "fieldset": "CR1" + }, + { + "name": "CR2", + "description": "Configuration register 2", + "byte_offset": 4, + "fieldset": "CR2" + }, + { + "name": "FRCR", + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "byte_offset": 8, + "fieldset": "FRCR" + }, + { + "name": "SLOTR", + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "byte_offset": 12, + "fieldset": "SLOTR" + }, + { + "name": "IM", + "description": "Interrupt mask register 2", + "byte_offset": 16, + "fieldset": "IM" + }, + { + "name": "SR", + "description": "Status register", + "byte_offset": 20, + "access": "Read", + "fieldset": "SR" + }, + { + "name": "CLRFR", + "description": "Clear flag register", + "byte_offset": 24, + "access": "Write", + "fieldset": "CLRFR" + }, + { + "name": "DR", + "description": "Data register", + "byte_offset": 28, + "fieldset": "DR" + } + ] + }, + "block/SAI": { + "description": "Serial audio interface", + "items": [ + { + "name": "GCR", + "description": "Global configuration register", + "byte_offset": 0, + "fieldset": "GCR" + }, + { + "name": "CH", + "description": "Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR", + "array": { + "len": 2, + "stride": 32 + }, + "byte_offset": 4, + "block": "CH" + }, + { + "name": "PDMCR", + "description": "PDM control register", + "byte_offset": 68, + "fieldset": "PDMCR" + }, + { + "name": "PDMDLY", + "description": "PDM delay register", + "byte_offset": 72, + "fieldset": "PDMDLY" + } + ] + }, + "fieldset/CLRFR": { + "description": "Clear flag register", + "fields": [ + { + "name": "COVRUDR", + "description": "Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CMUTEDET", + "description": "Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CWCKCFG", + "description": "Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CCNRDY", + "description": "Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "CAFSDET", + "description": "Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "CLFSDET", + "description": "Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/CR1": { + "description": "Configuration register 1", + "fields": [ + { + "name": "MODE", + "description": "SAIx audio block mode immediately", + "bit_offset": 0, + "bit_size": 2, + "enum": "MODE" + }, + { + "name": "PRTCFG", + "description": "Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled.", + "bit_offset": 2, + "bit_size": 2, + "enum": "PRTCFG" + }, + { + "name": "DS", + "description": "Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled.", + "bit_offset": 5, + "bit_size": 3, + "enum": "DS" + }, + { + "name": "LSBFIRST", + "description": "Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first.", + "bit_offset": 8, + "bit_size": 1, + "enum": "LSBFIRST" + }, + { + "name": "CKSTR", + "description": "Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol.", + "bit_offset": 9, + "bit_size": 1, + "enum": "CKSTR" + }, + { + "name": "SYNCEN", + "description": "Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled.", + "bit_offset": 10, + "bit_size": 2, + "enum": "SYNCEN" + }, + { + "name": "MONO", + "description": "Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details.", + "bit_offset": 12, + "bit_size": 1, + "enum": "MONO" + }, + { + "name": "OUTDRIV", + "description": "Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration.", + "bit_offset": 13, + "bit_size": 1, + "enum": "OUTDRIV" + }, + { + "name": "SAIEN", + "description": "Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "DMAEN", + "description": "DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "NODIV", + "description": "No fixed divider between MCLK and FS", + "bit_offset": 19, + "bit_size": 1, + "enum": "NODIV" + }, + { + "name": "MCKDIV", + "description": "Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:", + "bit_offset": 20, + "bit_size": 6 + }, + { + "name": "OSR", + "description": "Oversampling ratio for master clock", + "bit_offset": 26, + "bit_size": 1 + } + ] + }, + "fieldset/CR2": { + "description": "Configuration register 2", + "fields": [ + { + "name": "FTH", + "description": "FIFO threshold. This bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 3, + "enum": "FTH" + }, + { + "name": "FFLUSH", + "description": "FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "TRIS", + "description": "Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "MUTE", + "description": "Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "MUTEVAL", + "description": "Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks.", + "bit_offset": 6, + "bit_size": 1, + "enum": "MUTEVAL" + }, + { + "name": "MUTECNT", + "description": "Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details.", + "bit_offset": 7, + "bit_size": 6 + }, + { + "name": "CPL", + "description": "Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm.", + "bit_offset": 13, + "bit_size": 1, + "enum": "CPL" + }, + { + "name": "COMP", + "description": "Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected.", + "bit_offset": 14, + "bit_size": 2, + "enum": "COMP" + } + ] + }, + "fieldset/DR": { + "description": "Data register", + "fields": [ + { + "name": "DATA", + "description": "Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/FRCR": { + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "fields": [ + { + "name": "FRL", + "description": "Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "FSALL", + "description": "Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled.", + "bit_offset": 8, + "bit_size": 7 + }, + { + "name": "FSDEF", + "description": "Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "FSPOL", + "description": "Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.", + "bit_offset": 17, + "bit_size": 1, + "enum": "FSPOL" + }, + { + "name": "FSOFF", + "description": "Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled.", + "bit_offset": 18, + "bit_size": 1, + "enum": "FSOFF" + } + ] + }, + "fieldset/GCR": { + "description": "Global configuration register", + "fields": [ + { + "name": "SYNCIN", + "description": "Synchronization inputs", + "bit_offset": 0, + "bit_size": 2 + }, + { + "name": "SYNCOUT", + "description": "Synchronization outputs These bits are set and cleared by software.", + "bit_offset": 4, + "bit_size": 2 + } + ] + }, + "fieldset/IM": { + "description": "Interrupt mask register 2", + "fields": [ + { + "name": "OVRUDRIE", + "description": "Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MUTEDETIE", + "description": "Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "WCKCFGIE", + "description": "Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "FREQIE", + "description": "FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode,", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CNRDYIE", + "description": "Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AFSDETIE", + "description": "Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LFSDETIE", + "description": "Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master.", + "bit_offset": 6, + "bit_size": 1 + } + ] + }, + "fieldset/PDMCR": { + "description": "PDM control register", + "fields": [ + { + "name": "PDMEN", + "description": "PDM enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MICNBR", + "description": "Number of microphones", + "bit_offset": 4, + "bit_size": 2 + }, + { + "name": "CKEN", + "description": "Clock enable of bitstream clock number 1", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } + } + ] + }, + "fieldset/PDMDLY": { + "description": "PDM delay register", + "fields": [ + { + "name": "DLYML", + "description": "Delay line adjust for first microphone of pair 1", + "bit_offset": 0, + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } + }, + { + "name": "DLYMR", + "description": "Delay line adjust for second microphone of pair 1", + "bit_offset": 4, + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } + } + ] + }, + "fieldset/SLOTR": { + "description": "This register has no meaning in AC97 and SPDIF audio protocol", + "fields": [ + { + "name": "FBOFF", + "description": "First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 0, + "bit_size": 5 + }, + { + "name": "SLOTSZ", + "description": "Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 6, + "bit_size": 2, + "enum": "SLOTSZ" + }, + { + "name": "NBSLOT", + "description": "Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SLOTEN", + "description": "Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode.", + "bit_offset": 16, + "bit_size": 16, + "enum": "SLOTEN" + } + ] + }, + "fieldset/SR": { + "description": "Status register", + "fields": [ + { + "name": "OVRUDR", + "description": "Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "MUTEDET", + "description": "Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "WCKCFG", + "description": "Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register.", + "bit_offset": 2, + "bit_size": 1, + "enum": "WCKCFG" + }, + { + "name": "FREQ", + "description": "FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "CNRDY", + "description": "Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register.", + "bit_offset": 4, + "bit_size": 1, + "enum": "CNRDY" + }, + { + "name": "AFSDET", + "description": "Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "LFSDET", + "description": "Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "FLVL", + "description": "FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:", + "bit_offset": 16, + "bit_size": 3, + "enum": "FLVL" + } + ] + }, + "enum/CKSTR": { + "bit_size": 1, + "variants": [ + { + "name": "FallingEdge", + "description": "Data strobing edge is falling edge of SCK", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "Data strobing edge is rising edge of SCK", + "value": 1 + } + ] + }, + "enum/CNRDY": { + "bit_size": 1, + "variants": [ + { + "name": "Ready", + "description": "External AC’97 Codec is ready", + "value": 0 + }, + { + "name": "NotReady", + "description": "External AC’97 Codec is not ready", + "value": 1 + } + ] + }, + "enum/COMP": { + "bit_size": 2, + "variants": [ + { + "name": "NoCompanding", + "description": "No companding algorithm", + "value": 0 + }, + { + "name": "MuLaw", + "description": "μ-Law algorithm", + "value": 2 + }, + { + "name": "ALaw", + "description": "A-Law algorithm", + "value": 3 + } + ] + }, + "enum/CPL": { + "bit_size": 1, + "variants": [ + { + "name": "OnesComplement", + "description": "1’s complement representation", + "value": 0 + }, + { + "name": "TwosComplement", + "description": "2’s complement representation", + "value": 1 + } + ] + }, + "enum/DS": { + "bit_size": 3, + "variants": [ + { + "name": "Bit8", + "description": "8 bits", + "value": 2 + }, + { + "name": "Bit10", + "description": "10 bits", + "value": 3 + }, + { + "name": "Bit16", + "description": "16 bits", + "value": 4 + }, + { + "name": "Bit20", + "description": "20 bits", + "value": 5 + }, + { + "name": "Bit24", + "description": "24 bits", + "value": 6 + }, + { + "name": "Bit32", + "description": "32 bits", + "value": 7 + } + ] + }, + "enum/FLVL": { + "bit_size": 3, + "variants": [ + { + "name": "Empty", + "description": "FIFO empty", + "value": 0 + }, + { + "name": "Quarter1", + "description": "FIFO <= 1⁄4 but not empty", + "value": 1 + }, + { + "name": "Quarter2", + "description": "1⁄4 < FIFO <= 1⁄2", + "value": 2 + }, + { + "name": "Quarter3", + "description": "1⁄2 < FIFO <= 3⁄4", + "value": 3 + }, + { + "name": "Quarter4", + "description": "3⁄4 < FIFO but not full", + "value": 4 + }, + { + "name": "Full", + "description": "FIFO full", + "value": 5 + } + ] + }, + "enum/FSOFF": { + "bit_size": 1, + "variants": [ + { + "name": "OnFirst", + "description": "FS is asserted on the first bit of the slot 0", + "value": 0 + }, + { + "name": "BeforeFirst", + "description": "FS is asserted one bit before the first bit of the slot 0", + "value": 1 + } + ] + }, + "enum/FSPOL": { + "bit_size": 1, + "variants": [ + { + "name": "FallingEdge", + "description": "FS is active low (falling edge)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "FS is active high (rising edge)", + "value": 1 + } + ] + }, + "enum/FTH": { + "bit_size": 3, + "variants": [ + { + "name": "Empty", + "description": "FIFO empty", + "value": 0 + }, + { + "name": "Quarter1", + "description": "1⁄4 FIFO", + "value": 1 + }, + { + "name": "Quarter2", + "description": "1⁄2 FIFO", + "value": 2 + }, + { + "name": "Quarter3", + "description": "3⁄4 FIFO", + "value": 3 + }, + { + "name": "Full", + "description": "FIFO full", + "value": 4 + } + ] + }, + "enum/LSBFIRST": { + "bit_size": 1, + "variants": [ + { + "name": "MsbFirst", + "description": "Data are transferred with MSB first", + "value": 0 + }, + { + "name": "LsbFirst", + "description": "Data are transferred with LSB first", + "value": 1 + } + ] + }, + "enum/MODE": { + "bit_size": 2, + "variants": [ + { + "name": "MasterTx", + "description": "Master transmitter", + "value": 0 + }, + { + "name": "MasterRx", + "description": "Master receiver", + "value": 1 + }, + { + "name": "SlaveTx", + "description": "Slave transmitter", + "value": 2 + }, + { + "name": "SlaveRx", + "description": "Slave receiver", + "value": 3 + } + ] + }, + "enum/MONO": { + "bit_size": 1, + "variants": [ + { + "name": "Stereo", + "description": "Stereo mode", + "value": 0 + }, + { + "name": "Mono", + "description": "Mono mode", + "value": 1 + } + ] + }, + "enum/MUTEVAL": { + "bit_size": 1, + "variants": [ + { + "name": "SendZero", + "description": "Bit value 0 is sent during the mute mode", + "value": 0 + }, + { + "name": "SendLast", + "description": "Last values are sent during the mute mode", + "value": 1 + } + ] + }, + "enum/NODIV": { + "bit_size": 1, + "variants": [ + { + "name": "MasterClock", + "description": "MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value", + "value": 0 + }, + { + "name": "NoDiv", + "description": "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.", + "value": 1 + } + ] + }, + "enum/OUTDRIV": { + "bit_size": 1, + "variants": [ + { + "name": "OnStart", + "description": "Audio block output driven when SAIEN is set", + "value": 0 + }, + { + "name": "Immediately", + "description": "Audio block output driven immediately after the setting of this bit", + "value": 1 + } + ] + }, + "enum/PRTCFG": { + "bit_size": 2, + "variants": [ + { + "name": "Free", + "description": "Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol", + "value": 0 + }, + { + "name": "Spdif", + "description": "SPDIF protocol", + "value": 1 + }, + { + "name": "Ac97", + "description": "AC’97 protocol", + "value": 2 + } + ] + }, + "enum/SLOTEN": { + "bit_size": 16, + "variants": [ + { + "name": "Inactive", + "description": "Inactive slot", + "value": 0 + }, + { + "name": "Active", + "description": "Active slot", + "value": 1 + } + ] + }, + "enum/SLOTSZ": { + "bit_size": 2, + "variants": [ + { + "name": "DataSize", + "description": "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)", + "value": 0 + }, + { + "name": "Bit16", + "description": "16-bit", + "value": 1 + }, + { + "name": "Bit32", + "description": "32-bit", + "value": 2 + } + ] + }, + "enum/SYNCEN": { + "bit_size": 2, + "variants": [ + { + "name": "Asynchronous", + "description": "audio sub-block in asynchronous mode", + "value": 0 + }, + { + "name": "Internal", + "description": "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode", + "value": 1 + }, + { + "name": "External", + "description": "audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode", + "value": 2 + } + ] + }, + "enum/WCKCFG": { + "bit_size": 1, + "variants": [ + { + "name": "Correct", + "description": "Clock configuration is correct", + "value": 0 + }, + { + "name": "Wrong", + "description": "Clock configuration does not respect the rule concerning the frame length specification", + "value": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/sai_v3.json b/data/registers/sai_v4_2pdm.json similarity index 95% rename from data/registers/sai_v3.json rename to data/registers/sai_v4_2pdm.json index 16f3967..a6ad251 100644 --- a/data/registers/sai_v3.json +++ b/data/registers/sai_v4_2pdm.json @@ -217,6 +217,12 @@ "description": "Oversampling ratio for master clock", "bit_offset": 26, "bit_size": 1 + }, + { + "name": "MCKEN", + "description": "Master clock generation enable", + "bit_offset": 27, + "bit_size": 1 } ] }, @@ -405,28 +411,14 @@ "bit_size": 2 }, { - "name": "CKEN1", + "name": "CKEN", "description": "Clock enable of bitstream clock number 1", "bit_offset": 8, - "bit_size": 1 - }, - { - "name": "CKEN2", - "description": "Clock enable of bitstream clock number 2", - "bit_offset": 9, - "bit_size": 1 - }, - { - "name": "CKEN3", - "description": "Clock enable of bitstream clock number 3", - "bit_offset": 10, - "bit_size": 1 - }, - { - "name": "CKEN4", - "description": "Clock enable of bitstream clock number 4", - "bit_offset": 11, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } } ] }, @@ -434,52 +426,24 @@ "description": "PDM delay register", "fields": [ { - "name": "DLYM1L", + "name": "DLYML", "description": "Delay line adjust for first microphone of pair 1", "bit_offset": 0, - "bit_size": 3 + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } }, { - "name": "DLYM1R", + "name": "DLYMR", "description": "Delay line adjust for second microphone of pair 1", "bit_offset": 4, - "bit_size": 3 - }, - { - "name": "DLYM2L", - "description": "Delay line for first microphone of pair 2", - "bit_offset": 8, - "bit_size": 3 - }, - { - "name": "DLYM2R", - "description": "Delay line for second microphone of pair 2", - "bit_offset": 12, - "bit_size": 3 - }, - { - "name": "DLYM3L", - "description": "Delay line for first microphone of pair 3", - "bit_offset": 16, - "bit_size": 3 - }, - { - "name": "DLYM3R", - "description": "Delay line for second microphone of pair 3", - "bit_offset": 20, - "bit_size": 3 - }, - { - "name": "DLYM4L", - "description": "Delay line for first microphone of pair 4", - "bit_offset": 24, - "bit_size": 3 - }, - { - "name": "DLYM4R", - "description": "Delay line for second microphone of pair 4", - "bit_offset": 28, - "bit_size": 3 + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } } ] }, diff --git a/data/registers/sai_v4.json b/data/registers/sai_v4_4pdm.json similarity index 95% rename from data/registers/sai_v4.json rename to data/registers/sai_v4_4pdm.json index c8731e6..26f6f1a 100644 --- a/data/registers/sai_v4.json +++ b/data/registers/sai_v4_4pdm.json @@ -411,28 +411,14 @@ "bit_size": 2 }, { - "name": "CKEN1", + "name": "CKEN", "description": "Clock enable of bitstream clock number 1", "bit_offset": 8, - "bit_size": 1 - }, - { - "name": "CKEN2", - "description": "Clock enable of bitstream clock number 2", - "bit_offset": 9, - "bit_size": 1 - }, - { - "name": "CKEN3", - "description": "Clock enable of bitstream clock number 3", - "bit_offset": 10, - "bit_size": 1 - }, - { - "name": "CKEN4", - "description": "Clock enable of bitstream clock number 4", - "bit_offset": 11, - "bit_size": 1 + "bit_size": 1, + "array": { + "len": 4, + "stride": 1 + } } ] }, @@ -440,52 +426,24 @@ "description": "PDM delay register", "fields": [ { - "name": "DLYM1L", + "name": "DLYML", "description": "Delay line adjust for first microphone of pair 1", "bit_offset": 0, - "bit_size": 3 + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } }, { - "name": "DLYM1R", + "name": "DLYMR", "description": "Delay line adjust for second microphone of pair 1", "bit_offset": 4, - "bit_size": 3 - }, - { - "name": "DLYM2L", - "description": "Delay line for first microphone of pair 2", - "bit_offset": 8, - "bit_size": 3 - }, - { - "name": "DLYM2R", - "description": "Delay line for second microphone of pair 2", - "bit_offset": 12, - "bit_size": 3 - }, - { - "name": "DLYM3L", - "description": "Delay line for first microphone of pair 3", - "bit_offset": 16, - "bit_size": 3 - }, - { - "name": "DLYM3R", - "description": "Delay line for second microphone of pair 3", - "bit_offset": 20, - "bit_size": 3 - }, - { - "name": "DLYM4L", - "description": "Delay line for first microphone of pair 4", - "bit_offset": 24, - "bit_size": 3 - }, - { - "name": "DLYM4R", - "description": "Delay line for second microphone of pair 4", - "bit_offset": 28, - "bit_size": 3 + "bit_size": 3, + "array": { + "len": 4, + "stride": 8 + } } ] },