diff --git a/data/chips/STM32H503CB.json b/data/chips/STM32H503CB.json index fbefc3c..956d368 100644 --- a/data/chips/STM32H503CB.json +++ b/data/chips/STM32H503CB.json @@ -1255,8 +1255,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1415,8 +1415,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32H503EB.json b/data/chips/STM32H503EB.json index a181494..66a1213 100644 --- a/data/chips/STM32H503EB.json +++ b/data/chips/STM32H503EB.json @@ -1143,8 +1143,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1268,8 +1268,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32H503KB.json b/data/chips/STM32H503KB.json index 2646762..ef5375f 100644 --- a/data/chips/STM32H503KB.json +++ b/data/chips/STM32H503KB.json @@ -1192,8 +1192,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1337,8 +1337,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32H503RB.json b/data/chips/STM32H503RB.json index a7abe33..ea19f4b 100644 --- a/data/chips/STM32H503RB.json +++ b/data/chips/STM32H503RB.json @@ -1405,8 +1405,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1575,8 +1575,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32H562AG.json b/data/chips/STM32H562AG.json index 19e7bf8..95fb1e3 100644 --- a/data/chips/STM32H562AG.json +++ b/data/chips/STM32H562AG.json @@ -2659,8 +2659,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2804,8 +2804,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2929,8 +2929,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3069,8 +3069,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3127,8 +3127,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3257,8 +3257,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562AI.json b/data/chips/STM32H562AI.json index 8091019..44bcf6f 100644 --- a/data/chips/STM32H562AI.json +++ b/data/chips/STM32H562AI.json @@ -2670,8 +2670,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2815,8 +2815,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2940,8 +2940,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3080,8 +3080,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3138,8 +3138,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3268,8 +3268,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562IG.json b/data/chips/STM32H562IG.json index 23a5abc..041763c 100644 --- a/data/chips/STM32H562IG.json +++ b/data/chips/STM32H562IG.json @@ -2688,8 +2688,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2833,8 +2833,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2958,8 +2958,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3098,8 +3098,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3156,8 +3156,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3286,8 +3286,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562II.json b/data/chips/STM32H562II.json index ba0c379..434c564 100644 --- a/data/chips/STM32H562II.json +++ b/data/chips/STM32H562II.json @@ -2699,8 +2699,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2844,8 +2844,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2969,8 +2969,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3109,8 +3109,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3167,8 +3167,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3297,8 +3297,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562RG.json b/data/chips/STM32H562RG.json index 781f923..9f2ec9e 100644 --- a/data/chips/STM32H562RG.json +++ b/data/chips/STM32H562RG.json @@ -1765,8 +1765,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1860,8 +1860,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1975,8 +1975,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2085,8 +2085,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2123,8 +2123,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2193,8 +2193,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562RI.json b/data/chips/STM32H562RI.json index d6f922a..129cb78 100644 --- a/data/chips/STM32H562RI.json +++ b/data/chips/STM32H562RI.json @@ -1776,8 +1776,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1871,8 +1871,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1986,8 +1986,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2096,8 +2096,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2134,8 +2134,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2204,8 +2204,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562VG.json b/data/chips/STM32H562VG.json index ebde387..7c5d587 100644 --- a/data/chips/STM32H562VG.json +++ b/data/chips/STM32H562VG.json @@ -2195,8 +2195,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2300,8 +2300,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2420,8 +2420,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2530,8 +2530,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2578,8 +2578,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2648,8 +2648,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562VI.json b/data/chips/STM32H562VI.json index f619f19..7d9810a 100644 --- a/data/chips/STM32H562VI.json +++ b/data/chips/STM32H562VI.json @@ -2206,8 +2206,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2311,8 +2311,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2431,8 +2431,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2541,8 +2541,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2589,8 +2589,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2659,8 +2659,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562ZG.json b/data/chips/STM32H562ZG.json index 44536a8..3d19e96 100644 --- a/data/chips/STM32H562ZG.json +++ b/data/chips/STM32H562ZG.json @@ -2469,8 +2469,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2599,8 +2599,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2719,8 +2719,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2859,8 +2859,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2917,8 +2917,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3047,8 +3047,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H562ZI.json b/data/chips/STM32H562ZI.json index 3337199..8e1c0c5 100644 --- a/data/chips/STM32H562ZI.json +++ b/data/chips/STM32H562ZI.json @@ -2480,8 +2480,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2610,8 +2610,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2730,8 +2730,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2870,8 +2870,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2928,8 +2928,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3058,8 +3058,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563AG.json b/data/chips/STM32H563AG.json index a591b7d..36f0aa0 100644 --- a/data/chips/STM32H563AG.json +++ b/data/chips/STM32H563AG.json @@ -2932,8 +2932,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3077,8 +3077,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3202,8 +3202,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3342,8 +3342,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3400,8 +3400,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3530,8 +3530,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563AI.json b/data/chips/STM32H563AI.json index 6092598..bcc01bc 100644 --- a/data/chips/STM32H563AI.json +++ b/data/chips/STM32H563AI.json @@ -2962,8 +2962,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3107,8 +3107,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3232,8 +3232,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3372,8 +3372,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3430,8 +3430,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3560,8 +3560,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563IG.json b/data/chips/STM32H563IG.json index 88f8d00..46066b1 100644 --- a/data/chips/STM32H563IG.json +++ b/data/chips/STM32H563IG.json @@ -2966,8 +2966,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3111,8 +3111,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3236,8 +3236,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3376,8 +3376,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3434,8 +3434,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3564,8 +3564,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563II.json b/data/chips/STM32H563II.json index 9f26c10..856e280 100644 --- a/data/chips/STM32H563II.json +++ b/data/chips/STM32H563II.json @@ -2985,8 +2985,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3130,8 +3130,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3255,8 +3255,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3395,8 +3395,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3453,8 +3453,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3583,8 +3583,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563MI.json b/data/chips/STM32H563MI.json index e93d8fd..77ce238 100644 --- a/data/chips/STM32H563MI.json +++ b/data/chips/STM32H563MI.json @@ -2149,8 +2149,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2234,8 +2234,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2324,8 +2324,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2434,8 +2434,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2472,8 +2472,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2542,8 +2542,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563RG.json b/data/chips/STM32H563RG.json index 445c61b..a29458e 100644 --- a/data/chips/STM32H563RG.json +++ b/data/chips/STM32H563RG.json @@ -1983,8 +1983,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2078,8 +2078,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2193,8 +2193,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2303,8 +2303,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2341,8 +2341,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2411,8 +2411,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563RI.json b/data/chips/STM32H563RI.json index de93dd1..9040b21 100644 --- a/data/chips/STM32H563RI.json +++ b/data/chips/STM32H563RI.json @@ -1994,8 +1994,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2089,8 +2089,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2204,8 +2204,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2314,8 +2314,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2352,8 +2352,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2422,8 +2422,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563VG.json b/data/chips/STM32H563VG.json index 8597be5..eb7b782 100644 --- a/data/chips/STM32H563VG.json +++ b/data/chips/STM32H563VG.json @@ -2418,8 +2418,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2523,8 +2523,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2643,8 +2643,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2753,8 +2753,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2801,8 +2801,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2871,8 +2871,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563VI.json b/data/chips/STM32H563VI.json index cf791fb..639c002 100644 --- a/data/chips/STM32H563VI.json +++ b/data/chips/STM32H563VI.json @@ -2443,8 +2443,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2548,8 +2548,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2673,8 +2673,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2783,8 +2783,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2831,8 +2831,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2901,8 +2901,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563ZG.json b/data/chips/STM32H563ZG.json index 59c3032..966dc47 100644 --- a/data/chips/STM32H563ZG.json +++ b/data/chips/STM32H563ZG.json @@ -2717,8 +2717,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2847,8 +2847,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2967,8 +2967,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3107,8 +3107,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3165,8 +3165,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3295,8 +3295,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H563ZI.json b/data/chips/STM32H563ZI.json index 4a54094..b326d3a 100644 --- a/data/chips/STM32H563ZI.json +++ b/data/chips/STM32H563ZI.json @@ -2757,8 +2757,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2892,8 +2892,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3017,8 +3017,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3157,8 +3157,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3215,8 +3215,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3345,8 +3345,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 6d8bd7b..0bba33e 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -3021,8 +3021,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3166,8 +3166,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3291,8 +3291,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3431,8 +3431,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3489,8 +3489,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3619,8 +3619,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index 9494755..da94f30 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -3044,8 +3044,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3189,8 +3189,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3314,8 +3314,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3454,8 +3454,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3512,8 +3512,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3642,8 +3642,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index 8a03d19..f1bd971 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -2208,8 +2208,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2293,8 +2293,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2383,8 +2383,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2493,8 +2493,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2531,8 +2531,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2601,8 +2601,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index 3386f3b..96e5bfa 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -2053,8 +2053,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2148,8 +2148,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2263,8 +2263,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2373,8 +2373,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2411,8 +2411,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2481,8 +2481,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index 69a5bb5..68c7e8a 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -2502,8 +2502,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2607,8 +2607,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2732,8 +2732,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2842,8 +2842,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -2890,8 +2890,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2960,8 +2960,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index c3105bb..75117e6 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -2816,8 +2816,8 @@ "address": 1140868096, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2951,8 +2951,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3076,8 +3076,8 @@ "address": 1140869120, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3216,8 +3216,8 @@ "address": 1140870144, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", @@ -3274,8 +3274,8 @@ "address": 1140871168, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3404,8 +3404,8 @@ "address": 1140872192, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32L552CC.json b/data/chips/STM32L552CC.json index 1c0db36..2dd0aa8 100644 --- a/data/chips/STM32L552CC.json +++ b/data/chips/STM32L552CC.json @@ -1445,7 +1445,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1500,7 +1500,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1550,7 +1550,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552CE.json b/data/chips/STM32L552CE.json index 3ad4252..a3c0d44 100644 --- a/data/chips/STM32L552CE.json +++ b/data/chips/STM32L552CE.json @@ -1453,7 +1453,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1508,7 +1508,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1558,7 +1558,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552ME.json b/data/chips/STM32L552ME.json index dc29b69..efbe5ff 100644 --- a/data/chips/STM32L552ME.json +++ b/data/chips/STM32L552ME.json @@ -1514,7 +1514,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1609,7 +1609,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1669,7 +1669,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552QC.json b/data/chips/STM32L552QC.json index 3e5c751..d86558c 100644 --- a/data/chips/STM32L552QC.json +++ b/data/chips/STM32L552QC.json @@ -1984,7 +1984,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2079,7 +2079,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2154,7 +2154,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552QE.json b/data/chips/STM32L552QE.json index d5a15ed..6844408 100644 --- a/data/chips/STM32L552QE.json +++ b/data/chips/STM32L552QE.json @@ -1992,7 +1992,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2087,7 +2087,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2162,7 +2162,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552RC.json b/data/chips/STM32L552RC.json index ae6c28e..4229ebe 100644 --- a/data/chips/STM32L552RC.json +++ b/data/chips/STM32L552RC.json @@ -1507,7 +1507,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1582,7 +1582,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1642,7 +1642,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552RE.json b/data/chips/STM32L552RE.json index df662b4..7b9a19b 100644 --- a/data/chips/STM32L552RE.json +++ b/data/chips/STM32L552RE.json @@ -1515,7 +1515,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1590,7 +1590,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1650,7 +1650,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552VC.json b/data/chips/STM32L552VC.json index d4d3ef7..5a073e7 100644 --- a/data/chips/STM32L552VC.json +++ b/data/chips/STM32L552VC.json @@ -1809,7 +1809,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1884,7 +1884,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1959,7 +1959,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552VE.json b/data/chips/STM32L552VE.json index 382ca36..215f9b4 100644 --- a/data/chips/STM32L552VE.json +++ b/data/chips/STM32L552VE.json @@ -1813,7 +1813,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1888,7 +1888,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1963,7 +1963,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552ZC.json b/data/chips/STM32L552ZC.json index 3a50c10..1bb35e9 100644 --- a/data/chips/STM32L552ZC.json +++ b/data/chips/STM32L552ZC.json @@ -1984,7 +1984,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2079,7 +2079,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2154,7 +2154,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L552ZE.json b/data/chips/STM32L552ZE.json index 56174f4..d325df9 100644 --- a/data/chips/STM32L552ZE.json +++ b/data/chips/STM32L552ZE.json @@ -1988,7 +1988,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2083,7 +2083,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2158,7 +2158,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index f1e3b7a..48f8a4a 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -1492,7 +1492,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1547,7 +1547,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1597,7 +1597,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index a16421d..b3fe12a 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -1553,7 +1553,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1648,7 +1648,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1708,7 +1708,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index b9bfd37..65fbbb0 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -2031,7 +2031,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2126,7 +2126,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2201,7 +2201,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index 951b4ef..6f8f7b6 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -1554,7 +1554,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1629,7 +1629,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1689,7 +1689,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index 80a5c25..3c7d829 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -1852,7 +1852,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1927,7 +1927,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2002,7 +2002,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index ffe82f3..c9cdfb2 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -2027,7 +2027,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2122,7 +2122,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -2197,7 +2197,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index 0a4f668..b5493d1 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -1334,8 +1334,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1424,8 +1424,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1509,8 +1509,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1581,8 +1581,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index 2dfff7f..6040d83 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -1334,8 +1334,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1424,8 +1424,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1509,8 +1509,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1581,8 +1581,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index 46f028b..2112c71 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -1334,8 +1334,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1424,8 +1424,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1509,8 +1509,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1581,8 +1581,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index f07371c..5b5d720 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -1350,8 +1350,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1470,8 +1470,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1555,8 +1555,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1627,8 +1627,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index 9f2331d..f24d0e6 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -1307,8 +1307,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1397,8 +1397,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1482,8 +1482,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1549,8 +1549,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index 599cf78..16b5f1d 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -1307,8 +1307,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1397,8 +1397,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1482,8 +1482,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1549,8 +1549,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index 6f0269e..8158549 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -1410,8 +1410,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1520,8 +1520,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1620,8 +1620,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1717,8 +1717,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index 36748a6..118fdba 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -1410,8 +1410,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1520,8 +1520,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1620,8 +1620,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1717,8 +1717,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index 332d5c1..8d58258 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -1410,8 +1410,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1520,8 +1520,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1620,8 +1620,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1717,8 +1717,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index 0b2cff5..ccdb925 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -1643,8 +1643,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1753,8 +1753,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1878,8 +1878,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1995,8 +1995,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index 1a94e6a..9e7af51 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -1643,8 +1643,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1753,8 +1753,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1878,8 +1878,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1995,8 +1995,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index ff17a20..cbb404c 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -1373,8 +1373,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1463,8 +1463,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1548,8 +1548,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1620,8 +1620,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index d4dea65..afd55e6 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -1389,8 +1389,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1509,8 +1509,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1594,8 +1594,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1666,8 +1666,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index cb40780..720e19a 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -1346,8 +1346,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1436,8 +1436,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1521,8 +1521,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1588,8 +1588,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index 02cff9f..f2d6213 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -1449,8 +1449,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1559,8 +1559,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1659,8 +1659,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1756,8 +1756,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index e8dbe29..35ced3b 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -1682,8 +1682,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1792,8 +1792,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1917,8 +1917,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2034,8 +2034,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575AG.json b/data/chips/STM32U575AG.json index b73a092..cde80d0 100644 --- a/data/chips/STM32U575AG.json +++ b/data/chips/STM32U575AG.json @@ -2732,8 +2732,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2867,8 +2867,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2992,8 +2992,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3129,8 +3129,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575AI.json b/data/chips/STM32U575AI.json index 9d4f070..f44a3bf 100644 --- a/data/chips/STM32U575AI.json +++ b/data/chips/STM32U575AI.json @@ -2732,8 +2732,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2867,8 +2867,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2992,8 +2992,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3129,8 +3129,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575CG.json b/data/chips/STM32U575CG.json index 568bee9..d36293b 100644 --- a/data/chips/STM32U575CG.json +++ b/data/chips/STM32U575CG.json @@ -1803,8 +1803,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1893,8 +1893,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1978,8 +1978,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2050,8 +2050,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575CI.json b/data/chips/STM32U575CI.json index 47a152d..c26e1f9 100644 --- a/data/chips/STM32U575CI.json +++ b/data/chips/STM32U575CI.json @@ -1803,8 +1803,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1893,8 +1893,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1978,8 +1978,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2050,8 +2050,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575OG.json b/data/chips/STM32U575OG.json index acdd6ee..b367f04 100644 --- a/data/chips/STM32U575OG.json +++ b/data/chips/STM32U575OG.json @@ -2188,8 +2188,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2318,8 +2318,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2418,8 +2418,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2525,8 +2525,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575OI.json b/data/chips/STM32U575OI.json index ae95df5..b2f575f 100644 --- a/data/chips/STM32U575OI.json +++ b/data/chips/STM32U575OI.json @@ -2188,8 +2188,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2318,8 +2318,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2418,8 +2418,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2525,8 +2525,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575QG.json b/data/chips/STM32U575QG.json index 3a0fab2..3cbe4e2 100644 --- a/data/chips/STM32U575QG.json +++ b/data/chips/STM32U575QG.json @@ -2582,8 +2582,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2717,8 +2717,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2842,8 +2842,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2979,8 +2979,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575QI.json b/data/chips/STM32U575QI.json index 009db96..31a4cd9 100644 --- a/data/chips/STM32U575QI.json +++ b/data/chips/STM32U575QI.json @@ -2582,8 +2582,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2717,8 +2717,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2842,8 +2842,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2979,8 +2979,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575RG.json b/data/chips/STM32U575RG.json index e050919..c09e390 100644 --- a/data/chips/STM32U575RG.json +++ b/data/chips/STM32U575RG.json @@ -2002,8 +2002,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2112,8 +2112,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2212,8 +2212,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2309,8 +2309,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575RI.json b/data/chips/STM32U575RI.json index 86e02fe..df7314f 100644 --- a/data/chips/STM32U575RI.json +++ b/data/chips/STM32U575RI.json @@ -2002,8 +2002,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2112,8 +2112,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2212,8 +2212,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2309,8 +2309,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575VG.json b/data/chips/STM32U575VG.json index cb04404..62c80c6 100644 --- a/data/chips/STM32U575VG.json +++ b/data/chips/STM32U575VG.json @@ -2381,8 +2381,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2491,8 +2491,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2616,8 +2616,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2733,8 +2733,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575VI.json b/data/chips/STM32U575VI.json index ae3cd9f..e123cb3 100644 --- a/data/chips/STM32U575VI.json +++ b/data/chips/STM32U575VI.json @@ -2381,8 +2381,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2491,8 +2491,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2616,8 +2616,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2733,8 +2733,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575ZG.json b/data/chips/STM32U575ZG.json index fb4f7a9..d4b2820 100644 --- a/data/chips/STM32U575ZG.json +++ b/data/chips/STM32U575ZG.json @@ -2602,8 +2602,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2737,8 +2737,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2862,8 +2862,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2999,8 +2999,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U575ZI.json b/data/chips/STM32U575ZI.json index 7823604..27f6626 100644 --- a/data/chips/STM32U575ZI.json +++ b/data/chips/STM32U575ZI.json @@ -2602,8 +2602,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2737,8 +2737,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2862,8 +2862,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2999,8 +2999,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index ea630c2..2d8f357 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -2777,8 +2777,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2912,8 +2912,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3037,8 +3037,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3174,8 +3174,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index b73922b..71d8241 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -1848,8 +1848,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1938,8 +1938,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2023,8 +2023,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2095,8 +2095,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index 9d9e09f..aca36ce 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -2233,8 +2233,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2363,8 +2363,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2463,8 +2463,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2570,8 +2570,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index 81e1856..97586b2 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -2627,8 +2627,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2762,8 +2762,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2887,8 +2887,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3024,8 +3024,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index 682e89c..dcd8769 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -2047,8 +2047,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2157,8 +2157,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2257,8 +2257,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2354,8 +2354,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index cbf51ff..9d6017b 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -2426,8 +2426,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2536,8 +2536,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2661,8 +2661,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2778,8 +2778,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index d5ab318..f36815d 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -2647,8 +2647,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2782,8 +2782,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2907,8 +2907,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3044,8 +3044,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index aa9e326..4e030c8 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -2633,8 +2633,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2768,8 +2768,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2893,8 +2893,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3030,8 +3030,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index 671335b..3dc1e6c 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -2633,8 +2633,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2768,8 +2768,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2893,8 +2893,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3030,8 +3030,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index e555bc3..b0bcfa5 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -2468,8 +2468,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2603,8 +2603,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2728,8 +2728,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2865,8 +2865,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index a5575ed..a077985 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -2468,8 +2468,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2603,8 +2603,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2728,8 +2728,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2865,8 +2865,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index 14a0e29..461b143 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -1751,8 +1751,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1861,8 +1861,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1961,8 +1961,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2058,8 +2058,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index 996dc26..8544dfd 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -1751,8 +1751,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1861,8 +1861,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -1961,8 +1961,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2058,8 +2058,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index 3637f2d..513754d 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -2247,8 +2247,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2357,8 +2357,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2482,8 +2482,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2599,8 +2599,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index 416ced9..2b121ce 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -2247,8 +2247,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2357,8 +2357,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2482,8 +2482,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2599,8 +2599,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index 1d6babb..f47f907 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -2492,8 +2492,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2627,8 +2627,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2752,8 +2752,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2889,8 +2889,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index 1558964..342e2ba 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -2492,8 +2492,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2627,8 +2627,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2752,8 +2752,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2889,8 +2889,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index fd58ebe..d94e25c 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -2838,8 +2838,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2973,8 +2973,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3098,8 +3098,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3235,8 +3235,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index 6f02592..40342e8 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -2863,8 +2863,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2998,8 +2998,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3123,8 +3123,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3260,8 +3260,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index 8530431..f74a705 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -2863,8 +2863,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2998,8 +2998,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3123,8 +3123,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3260,8 +3260,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index e64241f..ea4926b 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -2258,8 +2258,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2368,8 +2368,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2493,8 +2493,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2610,8 +2610,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index e47fadd..360afad 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -2319,8 +2319,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2429,8 +2429,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2554,8 +2554,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2671,8 +2671,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index 069d80c..acd596d 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -2560,8 +2560,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2690,8 +2690,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2815,8 +2815,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2952,8 +2952,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index 73c528d..aa50195 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -2560,8 +2560,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2690,8 +2690,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2815,8 +2815,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2952,8 +2952,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index 1e2ad61..90c4f4d 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -2672,8 +2672,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2807,8 +2807,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2932,8 +2932,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3069,8 +3069,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index b4b53ae..e7f6a21 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -2507,8 +2507,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2642,8 +2642,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2767,8 +2767,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2904,8 +2904,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index a25fef8..35f8e5a 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -1790,8 +1790,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -1900,8 +1900,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2000,8 +2000,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2097,8 +2097,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index bfc3fb1..0cd5629 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -2286,8 +2286,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2396,8 +2396,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2521,8 +2521,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2638,8 +2638,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 082b4b8..01b09f6 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -2531,8 +2531,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2666,8 +2666,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2791,8 +2791,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2928,8 +2928,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 194e883..70fe072 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -2877,8 +2877,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3012,8 +3012,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3137,8 +3137,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3274,8 +3274,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index 21ee0eb..3070243 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -2902,8 +2902,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3037,8 +3037,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -3162,8 +3162,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -3299,8 +3299,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index df5e26b..61a608b 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -2297,8 +2297,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2407,8 +2407,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2532,8 +2532,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2649,8 +2649,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index 14c743b..d267611 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -2599,8 +2599,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2729,8 +2729,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", @@ -2854,8 +2854,8 @@ "address": 1174423552, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK3", @@ -2991,8 +2991,8 @@ "address": 1174424576, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_BASIC" }, "rcc": { "bus_clock": "PCLK3", diff --git a/data/chips/STM32WBA52CE.json b/data/chips/STM32WBA52CE.json index 2c3e069..eb5ef3a 100644 --- a/data/chips/STM32WBA52CE.json +++ b/data/chips/STM32WBA52CE.json @@ -674,8 +674,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK7", @@ -759,8 +759,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32WBA52CG.json b/data/chips/STM32WBA52CG.json index bc6bbec..162ead1 100644 --- a/data/chips/STM32WBA52CG.json +++ b/data/chips/STM32WBA52CG.json @@ -674,8 +674,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK7", @@ -759,8 +759,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32WBA52KE.json b/data/chips/STM32WBA52KE.json index 1784d48..c6dbd29 100644 --- a/data/chips/STM32WBA52KE.json +++ b/data/chips/STM32WBA52KE.json @@ -650,8 +650,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK7", @@ -725,8 +725,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32WBA52KG.json b/data/chips/STM32WBA52KG.json index 4762d50..d72eb91 100644 --- a/data/chips/STM32WBA52KG.json +++ b/data/chips/STM32WBA52KG.json @@ -650,8 +650,8 @@ "address": 1174422528, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK7", @@ -725,8 +725,8 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", - "block": "LPTIM" + "version": "v2b", + "block": "LPTIM_ADV" }, "rcc": { "bus_clock": "PCLK1", diff --git a/data/chips/STM32WL54CC.json b/data/chips/STM32WL54CC.json index ee32326..a9c1f94 100644 --- a/data/chips/STM32WL54CC.json +++ b/data/chips/STM32WL54CC.json @@ -1128,7 +1128,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1188,7 +1188,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1233,7 +1233,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -3696,7 +3696,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -3756,7 +3756,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -3801,7 +3801,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WL54JC.json b/data/chips/STM32WL54JC.json index f9f992b..f7d07a2 100644 --- a/data/chips/STM32WL54JC.json +++ b/data/chips/STM32WL54JC.json @@ -1194,7 +1194,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1274,7 +1274,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1334,7 +1334,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -4013,7 +4013,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -4093,7 +4093,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -4153,7 +4153,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WL55CC.json b/data/chips/STM32WL55CC.json index 0b1bb45..28607e0 100644 --- a/data/chips/STM32WL55CC.json +++ b/data/chips/STM32WL55CC.json @@ -1134,7 +1134,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1194,7 +1194,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1239,7 +1239,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -3702,7 +3702,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -3762,7 +3762,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -3807,7 +3807,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WL55JC.json b/data/chips/STM32WL55JC.json index 4a51103..9768ad4 100644 --- a/data/chips/STM32WL55JC.json +++ b/data/chips/STM32WL55JC.json @@ -1200,7 +1200,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1280,7 +1280,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1340,7 +1340,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -4019,7 +4019,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -4099,7 +4099,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -4159,7 +4159,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4C8.json b/data/chips/STM32WLE4C8.json index ff39e34..afc011a 100644 --- a/data/chips/STM32WLE4C8.json +++ b/data/chips/STM32WLE4C8.json @@ -916,7 +916,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -976,7 +976,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1021,7 +1021,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4CB.json b/data/chips/STM32WLE4CB.json index 81d2aaa..fe22475 100644 --- a/data/chips/STM32WLE4CB.json +++ b/data/chips/STM32WLE4CB.json @@ -916,7 +916,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -976,7 +976,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1021,7 +1021,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4CC.json b/data/chips/STM32WLE4CC.json index 9348975..cd45c21 100644 --- a/data/chips/STM32WLE4CC.json +++ b/data/chips/STM32WLE4CC.json @@ -1091,7 +1091,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1151,7 +1151,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1196,7 +1196,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4J8.json b/data/chips/STM32WLE4J8.json index 8e58638..112430f 100644 --- a/data/chips/STM32WLE4J8.json +++ b/data/chips/STM32WLE4J8.json @@ -982,7 +982,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1062,7 +1062,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1122,7 +1122,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4JB.json b/data/chips/STM32WLE4JB.json index fc4d02e..6cda994 100644 --- a/data/chips/STM32WLE4JB.json +++ b/data/chips/STM32WLE4JB.json @@ -982,7 +982,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1062,7 +1062,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1122,7 +1122,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE4JC.json b/data/chips/STM32WLE4JC.json index 2c05737..cee029f 100644 --- a/data/chips/STM32WLE4JC.json +++ b/data/chips/STM32WLE4JC.json @@ -1157,7 +1157,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1237,7 +1237,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1297,7 +1297,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5C8.json b/data/chips/STM32WLE5C8.json index ca4457e..3452885 100644 --- a/data/chips/STM32WLE5C8.json +++ b/data/chips/STM32WLE5C8.json @@ -1091,7 +1091,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1151,7 +1151,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1196,7 +1196,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5CB.json b/data/chips/STM32WLE5CB.json index ea4330d..7871ac2 100644 --- a/data/chips/STM32WLE5CB.json +++ b/data/chips/STM32WLE5CB.json @@ -1091,7 +1091,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1151,7 +1151,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1196,7 +1196,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5CC.json b/data/chips/STM32WLE5CC.json index 75b9924..1d87b02 100644 --- a/data/chips/STM32WLE5CC.json +++ b/data/chips/STM32WLE5CC.json @@ -1091,7 +1091,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1151,7 +1151,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1196,7 +1196,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5J8.json b/data/chips/STM32WLE5J8.json index 14afe21..42a7b91 100644 --- a/data/chips/STM32WLE5J8.json +++ b/data/chips/STM32WLE5J8.json @@ -1157,7 +1157,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1237,7 +1237,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1297,7 +1297,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5JB.json b/data/chips/STM32WLE5JB.json index d061aa8..e19af1f 100644 --- a/data/chips/STM32WLE5JB.json +++ b/data/chips/STM32WLE5JB.json @@ -1157,7 +1157,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1237,7 +1237,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1297,7 +1297,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/chips/STM32WLE5JC.json b/data/chips/STM32WLE5JC.json index 5601efc..c963a86 100644 --- a/data/chips/STM32WLE5JC.json +++ b/data/chips/STM32WLE5JC.json @@ -1157,7 +1157,7 @@ "address": 1073773568, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1237,7 +1237,7 @@ "address": 1073779712, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { @@ -1297,7 +1297,7 @@ "address": 1073780736, "registers": { "kind": "lptim", - "version": "v1", + "version": "v2a", "block": "LPTIM" }, "rcc": { diff --git a/data/registers/lptim_v2a.json b/data/registers/lptim_v2a.json new file mode 100644 index 0000000..32d58c6 --- /dev/null +++ b/data/registers/lptim_v2a.json @@ -0,0 +1,506 @@ +{ + "block/LPTIM": { + "description": "Low power timer.", + "items": [ + { + "name": "ISR", + "description": "Interrupt and Status Register.", + "byte_offset": 0, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "Interrupt Clear Register.", + "byte_offset": 4, + "access": "Write", + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "Interrupt Enable Register.", + "byte_offset": 8, + "fieldset": "IER" + }, + { + "name": "CFGR", + "description": "Configuration Register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "Control Register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CMP", + "description": "Compare Register.", + "byte_offset": 20, + "fieldset": "CMP" + }, + { + "name": "ARR", + "description": "Autoreload Register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "Counter Register.", + "byte_offset": 28, + "access": "Read", + "fieldset": "CNT" + }, + { + "name": "OR", + "description": "LPTIM option register.", + "byte_offset": 32 + }, + { + "name": "RCR", + "description": "LPTIM repetition register.", + "byte_offset": 40, + "fieldset": "RCR" + } + ] + }, + "fieldset/ARR": { + "description": "Autoreload Register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "Configuration Register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector.", + "bit_offset": 0, + "bit_size": 1, + "enum": "CKSEL" + }, + { + "name": "CKPOL", + "description": "Clock Polarity.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector.", + "bit_offset": 13, + "bit_size": 3 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity.", + "bit_offset": 17, + "bit_size": 2 + }, + { + "name": "TIMOUT", + "description": "Timeout enable.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "PRELOAD", + "description": "Registers update mode.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ENC", + "description": "Encoder mode enable.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CMP": { + "description": "Compare Register.", + "fields": [ + { + "name": "CMP", + "description": "Compare value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CNT": { + "description": "Counter Register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "Control Register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM Enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in single mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in continuous mode.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "RSTARE", + "description": "Reset after read enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "COUNTRST", + "description": "Counter reset.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/ICR": { + "description": "Interrupt Clear Register.", + "fields": [ + { + "name": "CMPMCF", + "description": "compare match Clear Flag.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ARRMCF", + "description": "Autoreload match Clear Flag.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge Clear Flag.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register update OK Clear Flag.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK Clear Flag.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP Clear Flag.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down Clear Flag.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UECF", + "description": "Update event clear flag.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKCF", + "description": "Repetition register update OK clear flag.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "Interrupt Enable Register.", + "fields": [ + { + "name": "CMPMIE", + "description": "Compare match Interrupt Enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register update OK Interrupt Enable.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UEIE", + "description": "Update event interrupt enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKIE", + "description": "REPOKIE.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "Interrupt and Status Register.", + "fields": [ + { + "name": "CMPM", + "description": "Compare match.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ARRM", + "description": "Autoreload match.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register update OK.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "ARROK", + "description": "Autoreload register update OK.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UE", + "description": "LPTIM update event occurred.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOK", + "description": "Repetition register update Ok.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/RCR": { + "description": "LPTIM repetition register.", + "fields": [ + { + "name": "REP", + "description": "Repetition register value.", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/CKSEL": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "LPTIM is clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/lptim_v2b.json b/data/registers/lptim_v2b.json new file mode 100644 index 0000000..ffd93ef --- /dev/null +++ b/data/registers/lptim_v2b.json @@ -0,0 +1,1111 @@ +{ + "block/IC": { + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR_IC" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR_IC" + }, + { + "name": "DIER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "DIER_IC" + } + ] + }, + "block/LPTIM_ADV": { + "extends": "LPTIM_BASIC", + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "InputCapture", + "byte_offset": 0, + "block": "IC" + }, + { + "name": "OutputCompare", + "byte_offset": 0, + "block": "OC_ADV" + }, + { + "name": "CCR", + "description": "LPTIM compare register 1.", + "array": { + "len": 2, + "stride": 32 + }, + "byte_offset": 20, + "fieldset": "CCR" + }, + { + "name": "CCMR_IC", + "description": "LPTIM capture/compare mode register 1.", + "byte_offset": 44, + "fieldset": "CCMR_IC" + }, + { + "name": "CCMR_OC", + "description": "LPTIM capture/compare mode register 1.", + "byte_offset": 44, + "fieldset": "CCMR_OC" + } + ] + }, + "block/LPTIM_BASIC": { + "description": "Low power timer with Output Compare", + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR_BASIC" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR_BASIC" + }, + { + "name": "DIER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "DIER_BASIC" + }, + { + "name": "CFGR", + "description": "LPTIM configuration register.", + "byte_offset": 12, + "fieldset": "CFGR" + }, + { + "name": "CR", + "description": "LPTIM control register.", + "byte_offset": 16, + "fieldset": "CR" + }, + { + "name": "CCR", + "description": "LPTIM compare register 1.", + "array": { + "len": 1, + "stride": 32 + }, + "byte_offset": 20, + "fieldset": "CCR" + }, + { + "name": "ARR", + "description": "LPTIM autoreload register.", + "byte_offset": 24, + "fieldset": "ARR" + }, + { + "name": "CNT", + "description": "LPTIM counter register.", + "byte_offset": 28, + "fieldset": "CNT" + }, + { + "name": "CFGR2", + "description": "LPTIM configuration register 2.", + "byte_offset": 36, + "fieldset": "CFGR2" + }, + { + "name": "RCR", + "description": "LPTIM repetition register.", + "byte_offset": 40, + "fieldset": "RCR" + } + ] + }, + "block/OC_ADV": { + "items": [ + { + "name": "ISR", + "description": "LPTIM interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR_OC_ADV" + }, + { + "name": "ICR", + "description": "LPTIM interrupt clear register.", + "byte_offset": 4, + "fieldset": "ICR_OC_ADV" + }, + { + "name": "DIER", + "description": "LPTIM interrupt enable register.", + "byte_offset": 8, + "fieldset": "DIER_OC_ADV" + } + ] + }, + "fieldset/ARR": { + "description": "LPTIM autoreload register.", + "fields": [ + { + "name": "ARR", + "description": "Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CCMR_IC": { + "extends": "CCMR_partial", + "description": "LPTIM input capture mode register 1.", + "fields": [ + { + "name": "CCP", + "description": "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.", + "bit_offset": 2, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "CCP_IC" + } + ] + }, + "fieldset/CCMR_OC": { + "extends": "CCMR_partial", + "description": "LPTIM output compare mode register 1.", + "fields": [ + { + "name": "CCP", + "description": "Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations.", + "bit_offset": 2, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "CCP_OC" + } + ] + }, + "fieldset/CCMR_partial": { + "description": "internal use only - common fields between CCMR input mode and output mode", + "fields": [ + { + "name": "CCSEL", + "description": "Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "CCSEL" + }, + { + "name": "CCE", + "description": "Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not.", + "bit_offset": 1, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + }, + { + "name": "ICPSC", + "description": "Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).", + "bit_offset": 8, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "Filter" + }, + { + "name": "ICF", + "description": "Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 12, + "bit_size": 2, + "array": { + "len": 2, + "stride": 16 + }, + "enum": "Filter" + } + ] + }, + "fieldset/CCR": { + "description": "LPTIM compare register 1.", + "fields": [ + { + "name": "CCR", + "description": "Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CFGR": { + "description": "LPTIM configuration register.", + "fields": [ + { + "name": "CKSEL", + "description": "Clock selector The CKSEL bit selects which clock source the LPTIM uses:.", + "bit_offset": 0, + "bit_size": 1, + "enum": "CKSEL" + }, + { + "name": "CKPOL", + "description": "Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.", + "bit_offset": 1, + "bit_size": 2, + "enum": "CKPOL" + }, + { + "name": "CKFLT", + "description": "Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 3, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "TRGFLT", + "description": "Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.", + "bit_offset": 6, + "bit_size": 2, + "enum": "Filter" + }, + { + "name": "PRESC", + "description": "Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:.", + "bit_offset": 9, + "bit_size": 3, + "enum": "PRESC" + }, + { + "name": "TRIGSEL", + "description": "Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.", + "bit_offset": 13, + "bit_size": 3 + }, + { + "name": "TRIGEN", + "description": "Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.", + "bit_offset": 17, + "bit_size": 2, + "enum": "TRIGEN" + }, + { + "name": "TIMOUT", + "description": "Timeout enable The TIMOUT bit controls the Timeout feature.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "WAVE", + "description": "Waveform shape The WAVE bit controls the output shape.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "WAVPOL", + "description": "Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "PRELOAD", + "description": "Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "COUNTMODE", + "description": "counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "ENC", + "description": "Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR2": { + "description": "LPTIM configuration register 2.", + "fields": [ + { + "name": "INSEL", + "description": "LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to.", + "bit_offset": 0, + "bit_size": 2, + "array": { + "len": 2, + "stride": 4 + } + }, + { + "name": "ICSEL", + "description": "LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to.", + "bit_offset": 16, + "bit_size": 2, + "array": { + "len": 2, + "stride": 4 + } + } + ] + }, + "fieldset/CNT": { + "description": "LPTIM counter register.", + "fields": [ + { + "name": "CNT", + "description": "Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/CR": { + "description": "LPTIM control register.", + "fields": [ + { + "name": "ENABLE", + "description": "LPTIM enable The ENABLE bit is set and cleared by software.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "SNGSTRT", + "description": "LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "CNTSTRT", + "description": "Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "COUNTRST", + "description": "Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "RSTARE", + "description": "Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.", + "bit_offset": 4, + "bit_size": 1 + } + ] + }, + "fieldset/DIER_BASIC": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UEIE", + "description": "Update event interrupt enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKIE", + "description": "Repetition register update OK interrupt Enable.", + "bit_offset": 8, + "bit_size": 1 + } + ] + }, + "fieldset/DIER_IC": { + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "ARRMIE", + "description": "Autoreload match Interrupt Enable.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGIE", + "description": "External trigger valid edge Interrupt Enable.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ARROKIE", + "description": "Autoreload register update OK Interrupt Enable.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPIE", + "description": "Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNIE", + "description": "Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UEIE", + "description": "Update event interrupt enable.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKIE", + "description": "Repetition register update OK interrupt Enable.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "CCOIE", + "description": "Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 12, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, + { + "name": "CCDE", + "description": "Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 16, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "UEDE", + "description": "Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 23, + "bit_size": 1 + } + ] + }, + "fieldset/DIER_OC_ADV": { + "extends": "DIER_BASIC", + "description": "LPTIM interrupt enable register.", + "fields": [ + { + "name": "CCIE", + "description": "Capture/compare 1 interrupt enable.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "CMPOKIE", + "description": "Compare register 1 update OK interrupt enable.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + } + ] + }, + "fieldset/ICR_BASIC": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UECF", + "description": "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKCF", + "description": "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "DIEROKCF", + "description": "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/ICR_IC": { + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "ARRMCF", + "description": "Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIGCF", + "description": "External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ARROKCF", + "description": "Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UPCF", + "description": "Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWNCF", + "description": "Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UECF", + "description": "Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOKCF", + "description": "Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "CCOCF", + "description": "Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 12, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, + { + "name": "DIEROKCF", + "description": "Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/ICR_OC_ADV": { + "extends": "ICR_BASIC", + "description": "LPTIM interrupt clear register.", + "fields": [ + { + "name": "CCCF", + "description": "Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "CMPOKCF", + "description": "Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + } + ] + }, + "fieldset/ISR_BASIC": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 1, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 1, + "stride": 16 + } + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UE", + "description": "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOK", + "description": "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "DIEROK", + "description": "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/ISR_IC": { + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "capture 1 interrupt flag If channel CC1 is configured as input: CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "ARRM", + "description": "Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EXTTRIG", + "description": "External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ARROK", + "description": "Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "UP", + "description": "Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DOWN", + "description": "Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "UE", + "description": "LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "REPOK", + "description": "Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "CCOF", + "description": "Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.", + "bit_offset": 12, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, + { + "name": "DIEROK", + "description": "Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/ISR_OC_ADV": { + "extends": "ISR_BASIC", + "description": "LPTIM interrupt and status register.", + "fields": [ + { + "name": "CCIF", + "description": "Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 9 + } + }, + { + "name": "CMPOK", + "description": "Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.", + "bit_offset": 3, + "bit_size": 1, + "array": { + "len": 2, + "stride": 16 + } + } + ] + }, + "fieldset/RCR": { + "description": "LPTIM repetition register.", + "fields": [ + { + "name": "REP", + "description": "Repetition register value REP is the repetition value for the LPTIM.", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "enum/CCP_IC": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "value": 0 + }, + { + "name": "Falling", + "value": 1 + }, + { + "name": "Both", + "value": 3 + } + ] + }, + "enum/CCP_OC": { + "bit_size": 2, + "variants": [ + { + "name": "ActiveHigh", + "value": 0 + }, + { + "name": "ActiveLow", + "value": 1 + } + ] + }, + "enum/CCSEL": { + "bit_size": 1, + "variants": [ + { + "name": "OutputCompare", + "description": "channel is configured in output PWM mode", + "value": 0 + }, + { + "name": "InputCapture", + "description": "channel is configured in input capture mode", + "value": 1 + } + ] + }, + "enum/CKPOL": { + "bit_size": 2, + "variants": [ + { + "name": "Rising", + "description": "the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.", + "value": 0 + }, + { + "name": "Falling", + "description": "the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.", + "value": 1 + }, + { + "name": "Both", + "description": "both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.", + "value": 2 + } + ] + }, + "enum/CKSEL": { + "bit_size": 1, + "variants": [ + { + "name": "Internal", + "description": "LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)", + "value": 0 + }, + { + "name": "External", + "description": "LPTIM is clocked by an external clock source through the LPTIM external Input1", + "value": 1 + } + ] + }, + "enum/Filter": { + "bit_size": 2, + "variants": [ + { + "name": "Count1", + "value": 0 + }, + { + "name": "Count2", + "value": 1 + }, + { + "name": "Count4", + "value": 2 + }, + { + "name": "Count8", + "value": 3 + } + ] + }, + "enum/PRESC": { + "bit_size": 3, + "variants": [ + { + "name": "Div1", + "value": 0 + }, + { + "name": "Div2", + "value": 1 + }, + { + "name": "Div4", + "value": 2 + }, + { + "name": "Div8", + "value": 3 + }, + { + "name": "Div16", + "value": 4 + }, + { + "name": "Div32", + "value": 5 + }, + { + "name": "Div64", + "value": 6 + }, + { + "name": "Div128", + "value": 7 + } + ] + }, + "enum/TRIGEN": { + "bit_size": 2, + "variants": [ + { + "name": "Software", + "description": "software trigger (counting start is initiated by software)", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "rising edge is the active edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "falling edge is the active edge", + "value": 2 + }, + { + "name": "BothEdge", + "description": "both edges are active edges", + "value": 3 + } + ] + } +} \ No newline at end of file