diff --git a/data/chips/STM32WLE4C8.json b/data/chips/STM32WLE4C8.json index bdcdc69..957d3ce 100644 --- a/data/chips/STM32WLE4C8.json +++ b/data/chips/STM32WLE4C8.json @@ -165,6 +165,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -211,6 +216,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/chips/STM32WLE4CB.json b/data/chips/STM32WLE4CB.json index 136e785..a841314 100644 --- a/data/chips/STM32WLE4CB.json +++ b/data/chips/STM32WLE4CB.json @@ -165,6 +165,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -211,6 +216,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/chips/STM32WLE4CC.json b/data/chips/STM32WLE4CC.json index 62e7e07..53fe605 100644 --- a/data/chips/STM32WLE4CC.json +++ b/data/chips/STM32WLE4CC.json @@ -340,6 +340,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -386,6 +391,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/chips/STM32WLE4J8.json b/data/chips/STM32WLE4J8.json index b167774..59b2ce4 100644 --- a/data/chips/STM32WLE4J8.json +++ b/data/chips/STM32WLE4J8.json @@ -177,6 +177,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -228,6 +233,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/chips/STM32WLE4JB.json b/data/chips/STM32WLE4JB.json index 5294bea..b6a8e25 100644 --- a/data/chips/STM32WLE4JB.json +++ b/data/chips/STM32WLE4JB.json @@ -177,6 +177,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -228,6 +233,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/chips/STM32WLE4JC.json b/data/chips/STM32WLE4JC.json index dd1519e..60f51e6 100644 --- a/data/chips/STM32WLE4JC.json +++ b/data/chips/STM32WLE4JC.json @@ -352,6 +352,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -403,6 +408,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/chips/STM32WLE5C8.json b/data/chips/STM32WLE5C8.json index 1b75247..b555968 100644 --- a/data/chips/STM32WLE5C8.json +++ b/data/chips/STM32WLE5C8.json @@ -340,6 +340,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -386,6 +391,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/chips/STM32WLE5CB.json b/data/chips/STM32WLE5CB.json index 935e9a1..432910e 100644 --- a/data/chips/STM32WLE5CB.json +++ b/data/chips/STM32WLE5CB.json @@ -340,6 +340,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -386,6 +391,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/chips/STM32WLE5CC.json b/data/chips/STM32WLE5CC.json index e8c1eaa..8f9490f 100644 --- a/data/chips/STM32WLE5CC.json +++ b/data/chips/STM32WLE5CC.json @@ -340,6 +340,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -386,6 +391,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/chips/STM32WLE5J8.json b/data/chips/STM32WLE5J8.json index 028485c..03de0eb 100644 --- a/data/chips/STM32WLE5J8.json +++ b/data/chips/STM32WLE5J8.json @@ -352,6 +352,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -403,6 +408,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/chips/STM32WLE5JB.json b/data/chips/STM32WLE5JB.json index 43031c8..2e66a43 100644 --- a/data/chips/STM32WLE5JB.json +++ b/data/chips/STM32WLE5JB.json @@ -352,6 +352,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -403,6 +408,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/chips/STM32WLE5JC.json b/data/chips/STM32WLE5JC.json index 0388cb5..131a2d8 100644 --- a/data/chips/STM32WLE5JC.json +++ b/data/chips/STM32WLE5JC.json @@ -352,6 +352,11 @@ { "name": "COMP1", "address": 1073807872, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA0", @@ -403,6 +408,11 @@ { "name": "COMP2", "address": 1073807876, + "registers": { + "kind": "comp", + "version": "v3", + "block": "COMP" + }, "pins": [ { "pin": "PA10", diff --git a/data/registers/comp_v3.json b/data/registers/comp_v3.json new file mode 100644 index 0000000..306f776 --- /dev/null +++ b/data/registers/comp_v3.json @@ -0,0 +1,175 @@ +{ + "block/COMP": { + "description": "Comparator.", + "items": [ + { + "name": "CSR", + "description": "Comparator control and status register.", + "byte_offset": 0, + "fieldset": "CSR" + } + ] + }, + "fieldset/CSR": { + "description": "control and status register.", + "fields": [ + { + "name": "EN", + "description": "Enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "PWRMODE", + "description": "Power Mode.", + "bit_offset": 2, + "bit_size": 2, + "enum": "PWRMODE" + }, + { + "name": "INMSEL", + "description": "Input minus selection bits.", + "bit_offset": 4, + "bit_size": 3 + }, + { + "name": "INPSEL", + "description": "Input plus selection bit.", + "bit_offset": 7, + "bit_size": 2 + }, + { + "name": "POLARITY", + "description": "Polarity selection bit.", + "bit_offset": 15, + "bit_size": 1, + "enum": "POLARITY" + }, + { + "name": "HYST", + "description": "Hysteresis selection bits.", + "bit_offset": 16, + "bit_size": 2, + "enum": "HYST" + }, + { + "name": "BLANKING", + "description": "Blanking source selection bits.", + "bit_offset": 18, + "bit_size": 3, + "enum": "BLANKING" + }, + { + "name": "BRGEN", + "description": "Scaler bridge enable.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "SCALEN", + "description": "Voltage scaler enable bit.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "INMESEL", + "description": "Input minus extended selection bits.", + "bit_offset": 25, + "bit_size": 2 + }, + { + "name": "VALUE", + "description": "Output status bit.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "LOCK", + "description": "Register lock bit.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "enum/BLANKING": { + "bit_size": 3, + "variants": [ + { + "name": "NoBlanking", + "description": "No blanking.", + "value": 0 + }, + { + "name": "TIM1OC5", + "description": "TIM1 OC5 selected as blanking source.", + "value": 1 + }, + { + "name": "TIM2OC3", + "description": "TIM2 OC3 selected as blanking source.", + "value": 2 + } + ] + }, + "enum/HYST": { + "bit_size": 2, + "variants": [ + { + "name": "None", + "value": 0 + }, + { + "name": "Low", + "value": 1 + }, + { + "name": "Medium", + "value": 2 + }, + { + "name": "High", + "value": 3 + } + ] + }, + "enum/POLARITY": { + "bit_size": 1, + "variants": [ + { + "name": "NotInverted", + "description": "Output is not inverted.", + "value": 0 + }, + { + "name": "Inverted", + "description": "Output is inverted.", + "value": 1 + } + ] + }, + "enum/PWRMODE": { + "bit_size": 2, + "variants": [ + { + "name": "HighSpeed", + "description": "High speed / full power.", + "value": 0 + }, + { + "name": "MediumSpeed", + "description": "Medium speed / medium power.", + "value": 1 + }, + { + "name": "LowSpeed", + "description": "Low speed / low power.", + "value": 2 + }, + { + "name": "VeryLowSpeed", + "description": "Very-low speed / ultra-low power.", + "value": 3 + } + ] + } +} \ No newline at end of file