diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index 7e9603a..c682a5f 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -1226,6 +1226,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1308,6 +1313,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index 1f28d7c..196913d 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -1226,6 +1226,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1308,6 +1313,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index 635c135..3dff013 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -1226,6 +1226,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1308,6 +1313,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index 1d7a1fa..429b39f 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -488,6 +488,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -574,6 +579,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index e17a0cb..d564427 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -392,6 +392,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -474,6 +479,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index 4aa2da5..27e8df1 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -392,6 +392,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -474,6 +479,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index 4217c26..4984825 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -1610,6 +1610,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1716,6 +1721,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index ffd3706..7f04aa3 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -1610,6 +1610,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1716,6 +1721,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index fcfd897..31da5ad 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -1610,6 +1610,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1716,6 +1721,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index 86d3a6b..c1889be 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -2474,6 +2474,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2580,6 +2585,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index e6741c5..ae29b61 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -2474,6 +2474,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2580,6 +2585,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index cb8243d..46ec68f 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -1226,6 +1226,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1308,6 +1313,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index 4d4f9a4..e4eb990 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -488,6 +488,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -574,6 +579,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 3e98601..9e59e88 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -392,6 +392,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -474,6 +479,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index dc65bad..01714dc 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -1610,6 +1610,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1716,6 +1721,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index 37bbfac..08bc4fc 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -2474,6 +2474,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2580,6 +2585,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575AG.json b/data/chips/STM32U575AG.json index 51e8d61..493b52d 100644 --- a/data/chips/STM32U575AG.json +++ b/data/chips/STM32U575AG.json @@ -2463,6 +2463,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2569,6 +2574,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575AI.json b/data/chips/STM32U575AI.json index 687adc3..888b185 100644 --- a/data/chips/STM32U575AI.json +++ b/data/chips/STM32U575AI.json @@ -2463,6 +2463,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2569,6 +2574,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575CG.json b/data/chips/STM32U575CG.json index bc3dc9b..aafd4ba 100644 --- a/data/chips/STM32U575CG.json +++ b/data/chips/STM32U575CG.json @@ -1599,6 +1599,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1681,6 +1686,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575CI.json b/data/chips/STM32U575CI.json index e24469a..23fc11a 100644 --- a/data/chips/STM32U575CI.json +++ b/data/chips/STM32U575CI.json @@ -1599,6 +1599,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1681,6 +1686,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575OG.json b/data/chips/STM32U575OG.json index b8eb4d9..b0bdc5f 100644 --- a/data/chips/STM32U575OG.json +++ b/data/chips/STM32U575OG.json @@ -969,6 +969,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1071,6 +1076,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575OI.json b/data/chips/STM32U575OI.json index 262e774..aff3c84 100644 --- a/data/chips/STM32U575OI.json +++ b/data/chips/STM32U575OI.json @@ -969,6 +969,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1071,6 +1076,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575QG.json b/data/chips/STM32U575QG.json index c2ec64d..b9deff9 100644 --- a/data/chips/STM32U575QG.json +++ b/data/chips/STM32U575QG.json @@ -2019,6 +2019,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2125,6 +2130,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575QI.json b/data/chips/STM32U575QI.json index 38f9f06..3c38206 100644 --- a/data/chips/STM32U575QI.json +++ b/data/chips/STM32U575QI.json @@ -2019,6 +2019,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2125,6 +2130,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575RG.json b/data/chips/STM32U575RG.json index d2fb272..9383433 100644 --- a/data/chips/STM32U575RG.json +++ b/data/chips/STM32U575RG.json @@ -1203,6 +1203,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1309,6 +1314,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575RI.json b/data/chips/STM32U575RI.json index 1cadcb4..1a62210 100644 --- a/data/chips/STM32U575RI.json +++ b/data/chips/STM32U575RI.json @@ -1203,6 +1203,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1309,6 +1314,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575VG.json b/data/chips/STM32U575VG.json index d4f7756..71b958e 100644 --- a/data/chips/STM32U575VG.json +++ b/data/chips/STM32U575VG.json @@ -1635,6 +1635,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1741,6 +1746,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575VI.json b/data/chips/STM32U575VI.json index d5c18cc..136cc9c 100644 --- a/data/chips/STM32U575VI.json +++ b/data/chips/STM32U575VI.json @@ -1635,6 +1635,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1741,6 +1746,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575ZG.json b/data/chips/STM32U575ZG.json index 75527a7..404958b 100644 --- a/data/chips/STM32U575ZG.json +++ b/data/chips/STM32U575ZG.json @@ -2163,6 +2163,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2269,6 +2274,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U575ZI.json b/data/chips/STM32U575ZI.json index 8326c0b..283194f 100644 --- a/data/chips/STM32U575ZI.json +++ b/data/chips/STM32U575ZI.json @@ -2163,6 +2163,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2269,6 +2274,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index c02ad32..496bf13 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -2469,6 +2469,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2575,6 +2580,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index 268a22f..59768e2 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -1605,6 +1605,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1687,6 +1692,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index 58ee8aa..943a834 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -975,6 +975,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1077,6 +1082,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index eb74954..bf45705 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -2025,6 +2025,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2131,6 +2136,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index ac60570..4fa9ccb 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -1209,6 +1209,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1315,6 +1320,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index d2b0dbf..020aafa 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -1641,6 +1641,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1747,6 +1752,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index 10203d3..4c12d3d 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -2169,6 +2169,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2275,6 +2280,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index fb7b415..a4cb63a 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -2102,6 +2102,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2208,6 +2213,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2303,6 +2313,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index d99fa09..340d8a8 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -2102,6 +2102,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2208,6 +2213,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2303,6 +2313,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index 38935e8..f648bb3 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -1658,6 +1658,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1764,6 +1769,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1859,6 +1869,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index ec070b9..0c2babb 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -1658,6 +1658,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1764,6 +1769,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1859,6 +1869,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index 7021ffc..f530119 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -842,6 +842,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -948,6 +953,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1043,6 +1053,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index e73c4c7..37fa1c9 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -842,6 +842,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -948,6 +953,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1043,6 +1053,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index 58a858f..ebeb28c 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -1274,6 +1274,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1380,6 +1385,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1475,6 +1485,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index 8333dbe..be3bf3d 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -1274,6 +1274,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1380,6 +1385,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1475,6 +1485,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index 34f7d1e..ceef69e 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -2708,6 +2708,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2814,6 +2819,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2909,6 +2919,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index ef5f47b..8202f91 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -2708,6 +2708,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2814,6 +2819,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2909,6 +2919,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index 8156252..15f4844 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -1316,6 +1316,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1422,6 +1427,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1517,6 +1527,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index 9f4b15e..8abcc6e 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -1364,6 +1364,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1470,6 +1475,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1565,6 +1575,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index 7003364..890c08b 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -1364,6 +1364,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1470,6 +1475,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1565,6 +1575,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index 9e14047..83a4333 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -668,6 +668,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -766,6 +771,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -853,6 +863,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index b54afe6..e737ed8 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -1274,6 +1274,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1380,6 +1385,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1475,6 +1485,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index 55ebab5..c6a0e8e 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -1838,6 +1838,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1944,6 +1949,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2039,6 +2049,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index def327c..13738c5 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -1838,6 +1838,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1944,6 +1949,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2039,6 +2049,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index 3c67452..d601ab3 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -2102,6 +2102,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2208,6 +2213,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2303,6 +2313,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5A5QI.json b/data/chips/STM32U5A5QI.json index 12a6dc2..b08f293 100644 --- a/data/chips/STM32U5A5QI.json +++ b/data/chips/STM32U5A5QI.json @@ -860,6 +860,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -966,6 +971,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1061,6 +1071,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index 3b8033e..7a93c9e 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -1658,6 +1658,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1764,6 +1769,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1859,6 +1869,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index f0de58b..7241e45 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -842,6 +842,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -948,6 +953,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1043,6 +1053,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index ae377a6..6c86526 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -1274,6 +1274,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1380,6 +1385,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1475,6 +1485,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 389c939..025a592 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -2708,6 +2708,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2814,6 +2819,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2909,6 +2919,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index bef84bb..1acd576 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -1316,6 +1316,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1422,6 +1427,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1517,6 +1527,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index d6121cf..cbc2b69 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -1364,6 +1364,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1470,6 +1475,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1565,6 +1575,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index cc37f15..1b45b71 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -668,6 +668,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -766,6 +771,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -853,6 +863,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index a741449..a22e4ab 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -1838,6 +1838,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1944,6 +1949,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -2039,6 +2049,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5F7VI.json b/data/chips/STM32U5F7VI.json index 00e86b9..78110ac 100644 --- a/data/chips/STM32U5F7VI.json +++ b/data/chips/STM32U5F7VI.json @@ -1280,6 +1280,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1386,6 +1391,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1481,6 +1491,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5F7VJ.json b/data/chips/STM32U5F7VJ.json index 52668c9..13c5ada 100644 --- a/data/chips/STM32U5F7VJ.json +++ b/data/chips/STM32U5F7VJ.json @@ -1280,6 +1280,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1386,6 +1391,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1481,6 +1491,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5F9BJ.json b/data/chips/STM32U5F9BJ.json index 9731a87..d47c04f 100644 --- a/data/chips/STM32U5F9BJ.json +++ b/data/chips/STM32U5F9BJ.json @@ -1322,6 +1322,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1428,6 +1433,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1523,6 +1533,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5F9NJ.json b/data/chips/STM32U5F9NJ.json index f2e77f2..e6bf487 100644 --- a/data/chips/STM32U5F9NJ.json +++ b/data/chips/STM32U5F9NJ.json @@ -1370,6 +1370,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1476,6 +1481,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1571,6 +1581,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5F9VI.json b/data/chips/STM32U5F9VI.json index 3c7e361..9cd9960 100644 --- a/data/chips/STM32U5F9VI.json +++ b/data/chips/STM32U5F9VI.json @@ -674,6 +674,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -772,6 +777,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -859,6 +869,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5F9VJ.json b/data/chips/STM32U5F9VJ.json index 1a4dc3e..0206730 100644 --- a/data/chips/STM32U5F9VJ.json +++ b/data/chips/STM32U5F9VJ.json @@ -674,6 +674,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -772,6 +777,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -859,6 +869,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5F9ZI.json b/data/chips/STM32U5F9ZI.json index e808c56..9af9ff1 100644 --- a/data/chips/STM32U5F9ZI.json +++ b/data/chips/STM32U5F9ZI.json @@ -1796,6 +1796,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1894,6 +1899,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1981,6 +1991,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5F9ZJ.json b/data/chips/STM32U5F9ZJ.json index 676dd3f..1f87480 100644 --- a/data/chips/STM32U5F9ZJ.json +++ b/data/chips/STM32U5F9ZJ.json @@ -1796,6 +1796,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1894,6 +1899,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1981,6 +1991,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5G7VJ.json b/data/chips/STM32U5G7VJ.json index f7be066..ce87bf9 100644 --- a/data/chips/STM32U5G7VJ.json +++ b/data/chips/STM32U5G7VJ.json @@ -1280,6 +1280,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1386,6 +1391,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1481,6 +1491,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5G9BJ.json b/data/chips/STM32U5G9BJ.json index 52b1310..00e9c4a 100644 --- a/data/chips/STM32U5G9BJ.json +++ b/data/chips/STM32U5G9BJ.json @@ -1322,6 +1322,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1428,6 +1433,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1523,6 +1533,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5G9NJ.json b/data/chips/STM32U5G9NJ.json index ade3068..2c04e9f 100644 --- a/data/chips/STM32U5G9NJ.json +++ b/data/chips/STM32U5G9NJ.json @@ -1370,6 +1370,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1476,6 +1481,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1571,6 +1581,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5G9VJ.json b/data/chips/STM32U5G9VJ.json index 94d5e40..88da611 100644 --- a/data/chips/STM32U5G9VJ.json +++ b/data/chips/STM32U5G9VJ.json @@ -674,6 +674,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -772,6 +777,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -859,6 +869,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/chips/STM32U5G9ZJ.json b/data/chips/STM32U5G9ZJ.json index 79fd956..cf3902a 100644 --- a/data/chips/STM32U5G9ZJ.json +++ b/data/chips/STM32U5G9ZJ.json @@ -1796,6 +1796,11 @@ { "name": "ADC1", "address": 1107460096, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1894,6 +1899,11 @@ { "name": "ADC2", "address": 1107460352, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { @@ -1981,6 +1991,11 @@ { "name": "ADC4", "address": 1174540288, + "registers": { + "kind": "adc", + "version": "u5", + "block": "ADC" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": { diff --git a/data/registers/adc_u5.json b/data/registers/adc_u5.json new file mode 100644 index 0000000..44ccf53 --- /dev/null +++ b/data/registers/adc_u5.json @@ -0,0 +1,1082 @@ +{ + "block/ADC": { + "description": "ADC.", + "items": [ + { + "name": "ISR", + "description": "ADC interrupt and status register.", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "IER", + "description": "ADC interrupt enable register.", + "byte_offset": 4, + "fieldset": "IER" + }, + { + "name": "CR", + "description": "ADC control register.", + "byte_offset": 8, + "fieldset": "CR" + }, + { + "name": "CFGR1", + "description": "ADC configuration register.", + "byte_offset": 12, + "fieldset": "CFGR1" + }, + { + "name": "CFGR2", + "description": "ADC configuration register 2.", + "byte_offset": 16, + "fieldset": "CFGR2" + }, + { + "name": "SMPR", + "description": "ADC sample time register.", + "byte_offset": 20, + "fieldset": "SMPR" + }, + { + "name": "AWD1TR", + "description": "ADC watchdog threshold register.", + "byte_offset": 32, + "fieldset": "AWD1TR" + }, + { + "name": "AWD2TR", + "description": "ADC watchdog threshold register.", + "byte_offset": 36, + "fieldset": "AWD2TR" + }, + { + "name": "CHSELRMOD0", + "description": "ADC channel selection register [alternate].", + "byte_offset": 40, + "fieldset": "CHSELRMOD0" + }, + { + "name": "CHSELRMOD1", + "description": "ADC channel selection register [alternate].", + "byte_offset": 40, + "fieldset": "CHSELRMOD1" + }, + { + "name": "AWD3TR", + "description": "ADC watchdog threshold register.", + "byte_offset": 44, + "fieldset": "AWD3TR" + }, + { + "name": "DR", + "description": "ADC data register.", + "byte_offset": 64, + "access": "Read", + "fieldset": "DR" + }, + { + "name": "PWRR", + "description": "ADC data register.", + "byte_offset": 68, + "fieldset": "PWRR" + }, + { + "name": "AWD2CR", + "description": "ADC Analog Watchdog 2 Configuration register.", + "byte_offset": 160, + "fieldset": "AWD2CR" + }, + { + "name": "AWD3CR", + "description": "ADC Analog Watchdog 3 Configuration register.", + "byte_offset": 164, + "fieldset": "AWD3CR" + }, + { + "name": "CALFACT", + "description": "ADC Calibration factor.", + "byte_offset": 196, + "fieldset": "CALFACT" + }, + { + "name": "OR", + "description": "ADC option register.", + "byte_offset": 208, + "fieldset": "OR" + }, + { + "name": "CCR", + "description": "ADC common configuration register.", + "byte_offset": 776, + "fieldset": "CCR" + } + ] + }, + "fieldset/AWD1TR": { + "description": "ADC watchdog threshold register.", + "fields": [ + { + "name": "LT1", + "description": "LT1.", + "bit_offset": 0, + "bit_size": 12 + }, + { + "name": "HT1", + "description": "HT1.", + "bit_offset": 16, + "bit_size": 12 + } + ] + }, + "fieldset/AWD2CR": { + "description": "ADC Analog Watchdog 2 Configuration register.", + "fields": [ + { + "name": "AWD2CH0", + "description": "AWD2CH0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AWD2CH1", + "description": "AWD2CH1.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AWD2CH2", + "description": "AWD2CH2.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AWD2CH3", + "description": "AWD2CH3.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AWD2CH4", + "description": "AWD2CH4.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AWD2CH5", + "description": "AWD2CH5.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AWD2CH6", + "description": "AWD2CH6.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AWD2CH7", + "description": "AWD2CH7.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AWD2CH8", + "description": "AWD2CH8.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AWD2CH9", + "description": "AWD2CH9.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "AWD2CH10", + "description": "AWD2CH10.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "AWD2CH11", + "description": "AWD2CH11.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "AWD2CH12", + "description": "AWD2CH12.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "AWD2CH13", + "description": "AWD2CH13.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "AWD2CH14", + "description": "AWD2CH14.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "AWD2CH15", + "description": "AWD2CH15.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "AWD2CH16", + "description": "AWD2CH16.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "AWD2CH17", + "description": "AWD2CH17.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "AWD2CH18", + "description": "AWD2CH18.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "AWD2CH19", + "description": "AWD2CH19.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "AWD2CH20", + "description": "AWD2CH20.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "AWD2CH21", + "description": "AWD2CH21.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "AWD2CH22", + "description": "AWD2CH22.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "AWD2CH23", + "description": "AWD2CH23.", + "bit_offset": 23, + "bit_size": 1 + } + ] + }, + "fieldset/AWD2TR": { + "description": "ADC watchdog threshold register.", + "fields": [ + { + "name": "LT2", + "description": "LT2.", + "bit_offset": 0, + "bit_size": 12 + }, + { + "name": "HT2", + "description": "HT2.", + "bit_offset": 16, + "bit_size": 12 + } + ] + }, + "fieldset/AWD3CR": { + "description": "ADC Analog Watchdog 3 Configuration register.", + "fields": [ + { + "name": "AWD3CH0", + "description": "AWD3CH0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AWD3CH1", + "description": "AWD3CH1.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AWD3CH2", + "description": "AWD3CH2.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "AWD3CH3", + "description": "AWD3CH3.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "AWD3CH4", + "description": "AWD3CH4.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AWD3CH5", + "description": "AWD3CH5.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "AWD3CH6", + "description": "AWD3CH6.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AWD3CH7", + "description": "AWD3CH7.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AWD3CH8", + "description": "AWD3CH8.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AWD3CH9", + "description": "AWD3CH9.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "AWD3CH10", + "description": "AWD3CH10.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "AWD3CH11", + "description": "AWD3CH11.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "AWD3CH12", + "description": "AWD3CH12.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "AWD3CH13", + "description": "AWD3CH13.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "AWD3CH14", + "description": "AWD3CH14.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "AWD3CH15", + "description": "AWD3CH15.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "AWD3CH16", + "description": "AWD3CH16.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "AWD3CH17", + "description": "AWD3CH17.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "AWD3CH18", + "description": "AWD3CH18.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "AWD3CH19", + "description": "AWD3CH19.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "AWD3CH20", + "description": "AWD3CH20.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "AWD3CH21", + "description": "AWD3CH21.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "AWD3CH22", + "description": "AWD3CH22.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "AWD3CH23", + "description": "AWD3CH23.", + "bit_offset": 23, + "bit_size": 1 + } + ] + }, + "fieldset/AWD3TR": { + "description": "ADC watchdog threshold register.", + "fields": [ + { + "name": "LT3", + "description": "LT3.", + "bit_offset": 0, + "bit_size": 12 + }, + { + "name": "HT3", + "description": "HT3.", + "bit_offset": 16, + "bit_size": 12 + } + ] + }, + "fieldset/CALFACT": { + "description": "ADC Calibration factor.", + "fields": [ + { + "name": "CALFACT", + "description": "CALFACT.", + "bit_offset": 0, + "bit_size": 7 + } + ] + }, + "fieldset/CCR": { + "description": "ADC common configuration register.", + "fields": [ + { + "name": "PRESC", + "description": "PRESC.", + "bit_offset": 18, + "bit_size": 4 + }, + { + "name": "VREFEN", + "description": "VREFEN.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "VSENSESEL", + "description": "VSENSESEL.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "VBATEN", + "description": "VBATEN.", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR1": { + "description": "ADC configuration register.", + "fields": [ + { + "name": "DMAEN", + "description": "DMAEN.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMACFG", + "description": "DMACFG.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "RES", + "description": "RES.", + "bit_offset": 2, + "bit_size": 2 + }, + { + "name": "SCANDIR", + "description": "SCANDIR.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ALIGN", + "description": "ALIGN.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "EXTSEL", + "description": "EXTSEL.", + "bit_offset": 6, + "bit_size": 3 + }, + { + "name": "EXTEN", + "description": "EXTEN.", + "bit_offset": 10, + "bit_size": 2 + }, + { + "name": "OVRMOD", + "description": "OVRMOD.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "CONT", + "description": "CONT.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "WAIT", + "description": "WAIT.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "DISCEN", + "description": "DISCEN.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "CHSELRMOD", + "description": "CHSELRMOD.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "AWD1SGL", + "description": "AWD1SGL.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "AWD1EN", + "description": "AWD1EN.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "AWD1CH", + "description": "AWD1CH.", + "bit_offset": 26, + "bit_size": 5 + } + ] + }, + "fieldset/CFGR2": { + "description": "ADC configuration register 2.", + "fields": [ + { + "name": "OVSE", + "description": "OVSE.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "OVSR", + "description": "OVSR.", + "bit_offset": 2, + "bit_size": 3 + }, + { + "name": "OVSS", + "description": "OVSS.", + "bit_offset": 5, + "bit_size": 4 + }, + { + "name": "TOVS", + "description": "TOVS.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "LFTRIG", + "description": "LFTRIG.", + "bit_offset": 29, + "bit_size": 1 + } + ] + }, + "fieldset/CHSELRMOD0": { + "description": "ADC channel selection register [alternate].", + "fields": [ + { + "name": "CHSEL", + "description": "CHSEL.", + "bit_offset": 0, + "bit_size": 24 + } + ] + }, + "fieldset/CHSELRMOD1": { + "description": "ADC channel selection register [alternate].", + "fields": [ + { + "name": "SQ1", + "description": "SQ1.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "SQ2", + "description": "SQ2.", + "bit_offset": 4, + "bit_size": 4 + }, + { + "name": "SQ3", + "description": "SQ3.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "SQ4", + "description": "SQ4.", + "bit_offset": 12, + "bit_size": 4 + }, + { + "name": "SQ5", + "description": "SQ5.", + "bit_offset": 16, + "bit_size": 4 + }, + { + "name": "SQ6", + "description": "SQ6.", + "bit_offset": 20, + "bit_size": 4 + }, + { + "name": "SQ7", + "description": "SQ7.", + "bit_offset": 24, + "bit_size": 4 + }, + { + "name": "SQ8", + "description": "SQ8.", + "bit_offset": 28, + "bit_size": 4 + } + ] + }, + "fieldset/CR": { + "description": "ADC control register.", + "fields": [ + { + "name": "ADEN", + "description": "ADEN.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ADDIS", + "description": "ADDIS.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ADSTART", + "description": "ADSTART.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ADSTP", + "description": "ADSTP.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADVREGEN", + "description": "ADVREGEN.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ADCAL", + "description": "ADCAL.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/DR": { + "description": "ADC data register.", + "fields": [ + { + "name": "DATA", + "description": "DATA.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/IER": { + "description": "ADC interrupt enable register.", + "fields": [ + { + "name": "ADRDYIE", + "description": "ADRDYIE.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "EOSMPIE", + "description": "EOSMPIE.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EOCIE", + "description": "EOCIE.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "EOSIE", + "description": "EOSIE.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "OVRIE", + "description": "OVRIE.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AWD1IE", + "description": "AWD1IE.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AWD2IE", + "description": "AWD2IE.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AWD3IE", + "description": "AWD3IE.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "EOCALIE", + "description": "EOCALIE.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LDORDYIE", + "description": "LDORDYIE.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "ADC interrupt and status register.", + "fields": [ + { + "name": "ADRDY", + "description": "ADRDY.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "EOSMP", + "description": "EOSMP.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EOC", + "description": "EOC.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "EOS", + "description": "EOS.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "OVR", + "description": "OVR.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AWD1", + "description": "AWD1.", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "AWD2", + "description": "AWD2.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "AWD3", + "description": "AWD3.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "EOCAL", + "description": "EOCAL.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "LDORDY", + "description": "LDORDY.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/OR": { + "description": "ADC option register.", + "fields": [ + { + "name": "CHN21SEL", + "description": "CHN21SEL.", + "bit_offset": 0, + "bit_size": 1 + } + ] + }, + "fieldset/PWRR": { + "description": "ADC data register.", + "fields": [ + { + "name": "AUTOFF", + "description": "AUTOFF.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DPD", + "description": "DPD.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "VREFPROT", + "description": "VREFPROT.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "VREFSECSMP", + "description": "VREFSECSMP.", + "bit_offset": 3, + "bit_size": 1 + } + ] + }, + "fieldset/SMPR": { + "description": "ADC sample time register.", + "fields": [ + { + "name": "SMP1", + "description": "SMP1.", + "bit_offset": 0, + "bit_size": 3 + }, + { + "name": "SMP2", + "description": "SMP2.", + "bit_offset": 4, + "bit_size": 3 + }, + { + "name": "SMPSEL0", + "description": "SMPSEL0.", + "bit_offset": 8, + "bit_size": 1 + }, + { + "name": "SMPSEL1", + "description": "SMPSEL1.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "SMPSEL2", + "description": "SMPSEL2.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "SMPSEL3", + "description": "SMPSEL3.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "SMPSEL4", + "description": "SMPSEL4.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "SMPSEL5", + "description": "SMPSEL5.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SMPSEL6", + "description": "SMPSEL6.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "SMPSEL7", + "description": "SMPSEL7.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "SMPSEL8", + "description": "SMPSEL8.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "SMPSEL9", + "description": "SMPSEL9.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "SMPSEL10", + "description": "SMPSEL10.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "SMPSEL11", + "description": "SMPSEL11.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "SMPSEL12", + "description": "SMPSEL12.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "SMPSEL13", + "description": "SMPSEL13.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "SMPSEL14", + "description": "SMPSEL14.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "SMPSEL15", + "description": "SMPSEL15.", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "SMPSEL16", + "description": "SMPSEL16.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "SMPSEL17", + "description": "SMPSEL17.", + "bit_offset": 25, + "bit_size": 1 + }, + { + "name": "SMPSEL18", + "description": "SMPSEL18.", + "bit_offset": 26, + "bit_size": 1 + }, + { + "name": "SMPSEL19", + "description": "SMPSEL19.", + "bit_offset": 27, + "bit_size": 1 + }, + { + "name": "SMPSEL20", + "description": "SMPSEL20.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "SMPSEL21", + "description": "SMPSEL21.", + "bit_offset": 29, + "bit_size": 1 + }, + { + "name": "SMPSEL22", + "description": "SMPSEL22.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "SMPSEL23", + "description": "SMPSEL23.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file