diff --git a/data/chips/STM32WB55CC.json b/data/chips/STM32WB55CC.json index f9fb718..0627fcf 100644 --- a/data/chips/STM32WB55CC.json +++ b/data/chips/STM32WB55CC.json @@ -1050,6 +1050,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55CE.json b/data/chips/STM32WB55CE.json index ef58a8f..5ee4735 100644 --- a/data/chips/STM32WB55CE.json +++ b/data/chips/STM32WB55CE.json @@ -1050,6 +1050,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55CG.json b/data/chips/STM32WB55CG.json index 105179e..bfc7032 100644 --- a/data/chips/STM32WB55CG.json +++ b/data/chips/STM32WB55CG.json @@ -1050,6 +1050,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55RC.json b/data/chips/STM32WB55RC.json index 6f2e2d8..e9dec3f 100644 --- a/data/chips/STM32WB55RC.json +++ b/data/chips/STM32WB55RC.json @@ -1092,6 +1092,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55RE.json b/data/chips/STM32WB55RE.json index 6c2c0a1..59e2a8c 100644 --- a/data/chips/STM32WB55RE.json +++ b/data/chips/STM32WB55RE.json @@ -1092,6 +1092,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55RG.json b/data/chips/STM32WB55RG.json index b7cadc5..a891b01 100644 --- a/data/chips/STM32WB55RG.json +++ b/data/chips/STM32WB55RG.json @@ -1092,6 +1092,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VC.json b/data/chips/STM32WB55VC.json index 7f3493a..abb5fce 100644 --- a/data/chips/STM32WB55VC.json +++ b/data/chips/STM32WB55VC.json @@ -1096,6 +1096,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VE.json b/data/chips/STM32WB55VE.json index 2a5d0a5..5b13cd0 100644 --- a/data/chips/STM32WB55VE.json +++ b/data/chips/STM32WB55VE.json @@ -1096,6 +1096,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VG.json b/data/chips/STM32WB55VG.json index 18adc90..f8cf8a6 100644 --- a/data/chips/STM32WB55VG.json +++ b/data/chips/STM32WB55VG.json @@ -1096,6 +1096,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WB55VY.json b/data/chips/STM32WB55VY.json index c24fa37..a41eef4 100644 --- a/data/chips/STM32WB55VY.json +++ b/data/chips/STM32WB55VY.json @@ -1074,6 +1074,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v1", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WL54CC.json b/data/chips/STM32WL54CC.json index a9c1f94..ca1c3e1 100644 --- a/data/chips/STM32WL54CC.json +++ b/data/chips/STM32WL54CC.json @@ -839,6 +839,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -3407,6 +3412,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WL54JC.json b/data/chips/STM32WL54JC.json index f7d07a2..b96aca6 100644 --- a/data/chips/STM32WL54JC.json +++ b/data/chips/STM32WL54JC.json @@ -865,6 +865,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -3684,6 +3689,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WL55CC.json b/data/chips/STM32WL55CC.json index 28607e0..80bc21c 100644 --- a/data/chips/STM32WL55CC.json +++ b/data/chips/STM32WL55CC.json @@ -845,6 +845,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -3413,6 +3418,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WL55JC.json b/data/chips/STM32WL55JC.json index 9768ad4..4c69486 100644 --- a/data/chips/STM32WL55JC.json +++ b/data/chips/STM32WL55JC.json @@ -871,6 +871,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", @@ -3690,6 +3695,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v3", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4C8.json b/data/chips/STM32WLE4C8.json index afc011a..df8c152 100644 --- a/data/chips/STM32WLE4C8.json +++ b/data/chips/STM32WLE4C8.json @@ -658,6 +658,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4CB.json b/data/chips/STM32WLE4CB.json index fe22475..7db9768 100644 --- a/data/chips/STM32WLE4CB.json +++ b/data/chips/STM32WLE4CB.json @@ -658,6 +658,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4CC.json b/data/chips/STM32WLE4CC.json index cd45c21..7ab9146 100644 --- a/data/chips/STM32WLE4CC.json +++ b/data/chips/STM32WLE4CC.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4J8.json b/data/chips/STM32WLE4J8.json index 112430f..a170f62 100644 --- a/data/chips/STM32WLE4J8.json +++ b/data/chips/STM32WLE4J8.json @@ -684,6 +684,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4JB.json b/data/chips/STM32WLE4JB.json index 6cda994..9a1fac0 100644 --- a/data/chips/STM32WLE4JB.json +++ b/data/chips/STM32WLE4JB.json @@ -684,6 +684,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE4JC.json b/data/chips/STM32WLE4JC.json index cee029f..768f83f 100644 --- a/data/chips/STM32WLE4JC.json +++ b/data/chips/STM32WLE4JC.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5C8.json b/data/chips/STM32WLE5C8.json index 3452885..e342b6a 100644 --- a/data/chips/STM32WLE5C8.json +++ b/data/chips/STM32WLE5C8.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5CB.json b/data/chips/STM32WLE5CB.json index 7871ac2..c3144f9 100644 --- a/data/chips/STM32WLE5CB.json +++ b/data/chips/STM32WLE5CB.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5CC.json b/data/chips/STM32WLE5CC.json index 1d87b02..09c3ce1 100644 --- a/data/chips/STM32WLE5CC.json +++ b/data/chips/STM32WLE5CC.json @@ -833,6 +833,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5J8.json b/data/chips/STM32WLE5J8.json index 42a7b91..4a9bc89 100644 --- a/data/chips/STM32WLE5J8.json +++ b/data/chips/STM32WLE5J8.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5JB.json b/data/chips/STM32WLE5JB.json index e19af1f..ab18672 100644 --- a/data/chips/STM32WLE5JB.json +++ b/data/chips/STM32WLE5JB.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/chips/STM32WLE5JC.json b/data/chips/STM32WLE5JC.json index c963a86..44d1587 100644 --- a/data/chips/STM32WLE5JC.json +++ b/data/chips/STM32WLE5JC.json @@ -859,6 +859,11 @@ { "name": "HSEM", "address": 1476400128, + "registers": { + "kind": "hsem", + "version": "v4", + "block": "HSEM" + }, "rcc": { "bus_clock": "HCLK3", "kernel_clock": "HCLK3", diff --git a/data/registers/hsem_v1.json b/data/registers/hsem_v1.json new file mode 100644 index 0000000..ae2734b --- /dev/null +++ b/data/registers/hsem_v1.json @@ -0,0 +1,226 @@ +{ + "block/HSEM": { + "description": "Hardware semaphore (HSEM).", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "C1IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 256, + "fieldset": "IER" + }, + { + "name": "C1ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 260, + "fieldset": "ICR" + }, + { + "name": "C1ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 264, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "C1MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "C2IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 272, + "fieldset": "IER" + }, + { + "name": "C2ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 276, + "fieldset": "ICR" + }, + { + "name": "C2ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 280, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "C2MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 284, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "COREID of semaphores to be cleared.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "Interrupt semaphore x clear bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "Interrupt semaphore x enable bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "Interrupt semaphore x status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "masked interrupt semaphore x status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v2.json b/data/registers/hsem_v2.json new file mode 100644 index 0000000..23d186c --- /dev/null +++ b/data/registers/hsem_v2.json @@ -0,0 +1,201 @@ +{ + "block/HSEM": { + "description": "HSEM.", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 32, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 256, + "fieldset": "IER" + }, + { + "name": "ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 260, + "access": "Read", + "fieldset": "ICR" + }, + { + "name": "ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 264, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "COREID of semaphores to be cleared.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "Interrupt semaphore x clear bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "Interrupt semaphore x enable bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "Interrupt semaphore x status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "masked interrupt semaphore x status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 32, + "stride": 1 + } + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "MASTERID", + "description": "Semaphore COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v3.json b/data/registers/hsem_v3.json new file mode 100644 index 0000000..e1812ee --- /dev/null +++ b/data/registers/hsem_v3.json @@ -0,0 +1,227 @@ +{ + "block/HSEM": { + "description": "Hardware semaphore.", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "C1IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 256, + "fieldset": "IER" + }, + { + "name": "C1ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 260, + "fieldset": "ICR" + }, + { + "name": "C1ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 264, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "C1MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "C2IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 272, + "fieldset": "IER" + }, + { + "name": "C2ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 276, + "fieldset": "ICR" + }, + { + "name": "C2ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 280, + "access": "Read", + "fieldset": "ISR" + }, + { + "name": "C2MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 284, + "access": "Read", + "fieldset": "MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "access": "Write", + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "Interrupt semaphore x clear bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "Interrupt semaphore x enable bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "Interrupt semaphore x status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "masked interrupt semaphore x status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "COREID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file diff --git a/data/registers/hsem_v4.json b/data/registers/hsem_v4.json new file mode 100644 index 0000000..2399ca1 --- /dev/null +++ b/data/registers/hsem_v4.json @@ -0,0 +1,201 @@ +{ + "block/HSEM": { + "description": "Hardware semaphore.", + "items": [ + { + "name": "R", + "description": "HSEM register HSEM_R%s HSEM_R31.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 0, + "fieldset": "R" + }, + { + "name": "RLR", + "description": "HSEM Read lock register.", + "array": { + "len": 16, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "RLR" + }, + { + "name": "C1IER", + "description": "HSEM Interrupt enable register.", + "byte_offset": 256, + "fieldset": "C1IER" + }, + { + "name": "C1ICR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 260, + "fieldset": "C1ICR" + }, + { + "name": "C1ISR", + "description": "HSEM Interrupt status register.", + "byte_offset": 264, + "access": "Read", + "fieldset": "C1ISR" + }, + { + "name": "C1MISR", + "description": "HSEM Masked interrupt status register.", + "byte_offset": 268, + "access": "Read", + "fieldset": "C1MISR" + }, + { + "name": "CR", + "description": "HSEM Clear register.", + "byte_offset": 320, + "access": "Write", + "fieldset": "CR" + }, + { + "name": "KEYR", + "description": "HSEM Interrupt clear register.", + "byte_offset": 324, + "fieldset": "KEYR" + } + ] + }, + "fieldset/C1ICR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "ISC", + "description": "Interrupt(N) semaphore n clear bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/C1IER": { + "description": "HSEM Interrupt enable register.", + "fields": [ + { + "name": "ISE", + "description": "Interrupt semaphore n enable bit.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/C1ISR": { + "description": "HSEM Interrupt status register.", + "fields": [ + { + "name": "ISF", + "description": "Interrupt(N) semaphore n status bit before enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/C1MISR": { + "description": "HSEM Masked interrupt status register.", + "fields": [ + { + "name": "MISF", + "description": "masked interrupt(N) semaphore n status bit after enable (mask).", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 16, + "stride": 1 + } + } + ] + }, + "fieldset/CR": { + "description": "HSEM Clear register.", + "fields": [ + { + "name": "COREID", + "description": "MASTERID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "KEY", + "description": "Semaphore clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/KEYR": { + "description": "HSEM Interrupt clear register.", + "fields": [ + { + "name": "KEY", + "description": "Semaphore Clear Key.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/R": { + "description": "HSEM register HSEM_R%s HSEM_R31.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore MASTERID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/RLR": { + "description": "HSEM Read lock register.", + "fields": [ + { + "name": "PROCID", + "description": "Semaphore ProcessID.", + "bit_offset": 0, + "bit_size": 8 + }, + { + "name": "COREID", + "description": "Semaphore MASTERID.", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "LOCK", + "description": "Lock indication.", + "bit_offset": 31, + "bit_size": 1 + } + ] + } +} \ No newline at end of file