diff --git a/data/chips/STM32H573AI.json b/data/chips/STM32H573AI.json index 45f3990..0a02b71 100644 --- a/data/chips/STM32H573AI.json +++ b/data/chips/STM32H573AI.json @@ -4075,6 +4075,11 @@ { "name": "OTFDEC1", "address": 1174425600, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK4", "kernel_clock": "HCLK4", diff --git a/data/chips/STM32H573II.json b/data/chips/STM32H573II.json index ffac227..c5cc10e 100644 --- a/data/chips/STM32H573II.json +++ b/data/chips/STM32H573II.json @@ -4098,6 +4098,11 @@ { "name": "OTFDEC1", "address": 1174425600, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK4", "kernel_clock": "HCLK4", diff --git a/data/chips/STM32H573MI.json b/data/chips/STM32H573MI.json index 19a93f2..728d662 100644 --- a/data/chips/STM32H573MI.json +++ b/data/chips/STM32H573MI.json @@ -2932,6 +2932,11 @@ { "name": "OTFDEC1", "address": 1174425600, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK4", "kernel_clock": "HCLK4", diff --git a/data/chips/STM32H573RI.json b/data/chips/STM32H573RI.json index 20276b0..c378f36 100644 --- a/data/chips/STM32H573RI.json +++ b/data/chips/STM32H573RI.json @@ -2802,6 +2802,11 @@ { "name": "OTFDEC1", "address": 1174425600, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK4", "kernel_clock": "HCLK4", diff --git a/data/chips/STM32H573VI.json b/data/chips/STM32H573VI.json index 255ec15..9bb5ee2 100644 --- a/data/chips/STM32H573VI.json +++ b/data/chips/STM32H573VI.json @@ -3336,6 +3336,11 @@ { "name": "OTFDEC1", "address": 1174425600, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK4", "kernel_clock": "HCLK4", diff --git a/data/chips/STM32H573ZI.json b/data/chips/STM32H573ZI.json index 3ce1e14..b30aaa5 100644 --- a/data/chips/STM32H573ZI.json +++ b/data/chips/STM32H573ZI.json @@ -3850,6 +3850,11 @@ { "name": "OTFDEC1", "address": 1174425600, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK4", "kernel_clock": "HCLK4", diff --git a/data/chips/STM32H730AB.json b/data/chips/STM32H730AB.json index b88d2bb..d02d6a2 100644 --- a/data/chips/STM32H730AB.json +++ b/data/chips/STM32H730AB.json @@ -4927,6 +4927,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4937,6 +4942,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H730IB.json b/data/chips/STM32H730IB.json index c39a06c..40a5e04 100644 --- a/data/chips/STM32H730IB.json +++ b/data/chips/STM32H730IB.json @@ -5102,6 +5102,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -5112,6 +5117,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H730VB.json b/data/chips/STM32H730VB.json index c4d15b2..48dc9d4 100644 --- a/data/chips/STM32H730VB.json +++ b/data/chips/STM32H730VB.json @@ -4164,6 +4164,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4174,6 +4179,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H730ZB.json b/data/chips/STM32H730ZB.json index 1be144b..8bcaf39 100644 --- a/data/chips/STM32H730ZB.json +++ b/data/chips/STM32H730ZB.json @@ -4755,6 +4755,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4765,6 +4770,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H733VG.json b/data/chips/STM32H733VG.json index 1d177a0..6338927 100644 --- a/data/chips/STM32H733VG.json +++ b/data/chips/STM32H733VG.json @@ -4164,6 +4164,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4174,6 +4179,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H733ZG.json b/data/chips/STM32H733ZG.json index b11fc5b..c69ec2e 100644 --- a/data/chips/STM32H733ZG.json +++ b/data/chips/STM32H733ZG.json @@ -4755,6 +4755,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4765,6 +4770,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H735AG.json b/data/chips/STM32H735AG.json index b29de6a..4e25ec6 100644 --- a/data/chips/STM32H735AG.json +++ b/data/chips/STM32H735AG.json @@ -4927,6 +4927,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4937,6 +4942,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H735IG.json b/data/chips/STM32H735IG.json index 3b9633a..f67c69a 100644 --- a/data/chips/STM32H735IG.json +++ b/data/chips/STM32H735IG.json @@ -5102,6 +5102,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -5112,6 +5117,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H735RG.json b/data/chips/STM32H735RG.json index a75d9d2..deecb09 100644 --- a/data/chips/STM32H735RG.json +++ b/data/chips/STM32H735RG.json @@ -2984,6 +2984,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -2994,6 +2999,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H735VG.json b/data/chips/STM32H735VG.json index 7e52f33..63585e0 100644 --- a/data/chips/STM32H735VG.json +++ b/data/chips/STM32H735VG.json @@ -4059,6 +4059,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4069,6 +4074,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H735ZG.json b/data/chips/STM32H735ZG.json index 36768f0..6284e49 100644 --- a/data/chips/STM32H735ZG.json +++ b/data/chips/STM32H735ZG.json @@ -4499,6 +4499,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4509,6 +4514,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B0AB.json b/data/chips/STM32H7B0AB.json index b46a9e4..19e54d2 100644 --- a/data/chips/STM32H7B0AB.json +++ b/data/chips/STM32H7B0AB.json @@ -4419,6 +4419,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4429,6 +4434,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B0IB.json b/data/chips/STM32H7B0IB.json index 9b1dca4..bc797ff 100644 --- a/data/chips/STM32H7B0IB.json +++ b/data/chips/STM32H7B0IB.json @@ -4693,6 +4693,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4703,6 +4708,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B0RB.json b/data/chips/STM32H7B0RB.json index 0eee9e6..c0e5a3a 100644 --- a/data/chips/STM32H7B0RB.json +++ b/data/chips/STM32H7B0RB.json @@ -2978,6 +2978,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B0VB.json b/data/chips/STM32H7B0VB.json index aebc527..e8bdcf3 100644 --- a/data/chips/STM32H7B0VB.json +++ b/data/chips/STM32H7B0VB.json @@ -3802,6 +3802,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B0ZB.json b/data/chips/STM32H7B0ZB.json index 6635ae3..07aeed0 100644 --- a/data/chips/STM32H7B0ZB.json +++ b/data/chips/STM32H7B0ZB.json @@ -4245,6 +4245,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4255,6 +4260,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3AI.json b/data/chips/STM32H7B3AI.json index 9bfd9b7..82228ca 100644 --- a/data/chips/STM32H7B3AI.json +++ b/data/chips/STM32H7B3AI.json @@ -4436,6 +4436,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4446,6 +4451,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3II.json b/data/chips/STM32H7B3II.json index 6a9d861..fe90aa3 100644 --- a/data/chips/STM32H7B3II.json +++ b/data/chips/STM32H7B3II.json @@ -4753,6 +4753,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4763,6 +4768,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3LI.json b/data/chips/STM32H7B3LI.json index 1b11a0b..6557ac1 100644 --- a/data/chips/STM32H7B3LI.json +++ b/data/chips/STM32H7B3LI.json @@ -4911,6 +4911,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4921,6 +4926,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3NI.json b/data/chips/STM32H7B3NI.json index c3d7fc1..76ba4df 100644 --- a/data/chips/STM32H7B3NI.json +++ b/data/chips/STM32H7B3NI.json @@ -4867,6 +4867,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4877,6 +4882,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3QI.json b/data/chips/STM32H7B3QI.json index d5f8865..ef060c8 100644 --- a/data/chips/STM32H7B3QI.json +++ b/data/chips/STM32H7B3QI.json @@ -3957,6 +3957,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3RI.json b/data/chips/STM32H7B3RI.json index 18e3c50..645fbe4 100644 --- a/data/chips/STM32H7B3RI.json +++ b/data/chips/STM32H7B3RI.json @@ -2995,6 +2995,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3VI.json b/data/chips/STM32H7B3VI.json index 511f28c..eb53252 100644 --- a/data/chips/STM32H7B3VI.json +++ b/data/chips/STM32H7B3VI.json @@ -3831,6 +3831,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32H7B3ZI.json b/data/chips/STM32H7B3ZI.json index 10e6cd5..f37312e 100644 --- a/data/chips/STM32H7B3ZI.json +++ b/data/chips/STM32H7B3ZI.json @@ -4266,6 +4266,11 @@ { "name": "OTFDEC1", "address": 1375778816, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", @@ -4276,6 +4281,11 @@ { "name": "OTFDEC2", "address": 1375779840, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "interrupts": [ { "signal": "GLOBAL", diff --git a/data/chips/STM32L562CE.json b/data/chips/STM32L562CE.json index 4f934f6..59bcb0a 100644 --- a/data/chips/STM32L562CE.json +++ b/data/chips/STM32L562CE.json @@ -1881,6 +1881,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32L562ME.json b/data/chips/STM32L562ME.json index a052c14..b3b7d1a 100644 --- a/data/chips/STM32L562ME.json +++ b/data/chips/STM32L562ME.json @@ -2067,6 +2067,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32L562QE.json b/data/chips/STM32L562QE.json index 4027192..302917f 100644 --- a/data/chips/STM32L562QE.json +++ b/data/chips/STM32L562QE.json @@ -2655,6 +2655,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32L562RE.json b/data/chips/STM32L562RE.json index 9f11ec2..770d307 100644 --- a/data/chips/STM32L562RE.json +++ b/data/chips/STM32L562RE.json @@ -2028,6 +2028,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32L562VE.json b/data/chips/STM32L562VE.json index 1d876f9..05a4dfa 100644 --- a/data/chips/STM32L562VE.json +++ b/data/chips/STM32L562VE.json @@ -2401,6 +2401,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32L562ZE.json b/data/chips/STM32L562ZE.json index a5af50f..638085e 100644 --- a/data/chips/STM32L562ZE.json +++ b/data/chips/STM32L562ZE.json @@ -2676,6 +2676,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index 23ef814..c81f11b 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -1957,6 +1957,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index d5119d9..a3d648e 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -2058,6 +2058,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 0aea2df..500b5e0 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -1920,6 +1920,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index 3fe01e8..becf437 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -2145,6 +2145,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index 7a8ba04..d0726a4 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -2533,6 +2533,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index 84ece1f..7c49eb0 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -4107,6 +4107,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -4129,6 +4134,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index 948888f..8c40404 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -2556,6 +2556,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -2578,6 +2583,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index e6f6a50..db6707c 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -3158,6 +3158,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -3180,6 +3185,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index e7847f1..0510515 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -3837,6 +3837,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -3859,6 +3864,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index ab71df0..dd8ea02 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -2887,6 +2887,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -2909,6 +2914,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index b5b3cd7..3df7592 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -3461,6 +3461,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -3483,6 +3488,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index 8054593..8ea655b 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -3892,6 +3892,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -3914,6 +3919,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index 504b2c5..958f6f5 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -4014,6 +4014,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -4036,6 +4041,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index d06f239..82c3202 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -3729,6 +3729,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -3751,6 +3756,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index 370ece0..1952075 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -2627,6 +2627,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -2649,6 +2654,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index b158cfe..d60a78b 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -3318,6 +3318,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -3340,6 +3345,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 03e7d15..d9422ba 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -3788,6 +3788,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -3810,6 +3815,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 10772c5..fc18f2a 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -4455,6 +4455,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -4477,6 +4482,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index 070a4d8..fd3307f 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -4480,6 +4480,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -4502,6 +4507,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index fa98a4f..981c90b 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -3495,6 +3495,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -3517,6 +3522,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index 228ec08..81bcd65 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -4082,6 +4082,11 @@ { "name": "OTFDEC1", "address": 1108103168, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", @@ -4104,6 +4109,11 @@ { "name": "OTFDEC2", "address": 1108104192, + "registers": { + "kind": "otfdec", + "version": "v1", + "block": "OTFDEC" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": "HCLK2", diff --git a/data/registers/otfdec_v1.json b/data/registers/otfdec_v1.json new file mode 100644 index 0000000..8c22a56 --- /dev/null +++ b/data/registers/otfdec_v1.json @@ -0,0 +1,248 @@ +{ + "block/OTFDEC": { + "description": "On-The-Fly Decryption engine.", + "items": [ + { + "name": "CR", + "description": "OTFDEC control register.", + "byte_offset": 0, + "fieldset": "CR" + }, + { + "name": "PRIVCFGR", + "description": "OTFDEC_PRIVCFGR.", + "byte_offset": 16, + "fieldset": "PRIVCFGR" + }, + { + "name": "Region", + "array": { + "len": 4, + "stride": 48 + }, + "byte_offset": 32, + "block": "Region" + }, + { + "name": "ISR", + "description": "OTFDEC interrupt status register.", + "byte_offset": 768, + "fieldset": "ISR" + }, + { + "name": "ICR", + "description": "OTFDEC interrupt clear register.", + "byte_offset": 772, + "fieldset": "ICR" + }, + { + "name": "IER", + "description": "OTFDEC interrupt enable register.", + "byte_offset": 776, + "fieldset": "IER" + } + ] + }, + "block/Region": { + "items": [ + { + "name": "CFGR", + "description": "OTFDEC region 3 configuration register.", + "byte_offset": 0, + "fieldset": "RegionCFGR" + }, + { + "name": "STARTADDR", + "description": "OTFDEC region 3 start address register.", + "byte_offset": 4 + }, + { + "name": "ENDADDR", + "description": "OTFDEC region 3 end address register.", + "byte_offset": 8 + }, + { + "name": "NONCER", + "description": "OTFDEC region 3 nonce register 0.", + "array": { + "len": 2, + "stride": 4 + }, + "byte_offset": 12 + }, + { + "name": "KEYR", + "description": "OTFDEC region 3 key register 0.", + "array": { + "len": 4, + "stride": 4 + }, + "byte_offset": 20 + } + ] + }, + "fieldset/CR": { + "description": "OTFDEC control register.", + "fields": [ + { + "name": "ENC", + "description": "Encryption mode bit When this bit is set, OTFDEC is used in encryption mode, during which application can write clear text data then read back encrypted data. When this bit is cleared (default), OTFDEC is used in decryption mode, during which application only read back decrypted data. For both modes, cryptographic context (keys, nonces, firmware versions) must be properly initialized. When this bit is set, only data accesses are allowed (zeros are returned otherwise, and XONEIF is set). When MODE = 11, enhanced encryption mode is automatically selected. Note: When ENC bit is set, no access to OCTOSPI must be done (registers and Memory‑mapped region).", + "bit_offset": 0, + "bit_size": 1, + "enum": "ENC" + } + ] + }, + "fieldset/ICR": { + "description": "OTFDEC interrupt clear register.", + "fields": [ + { + "name": "SEIF", + "description": "Security error interrupt flag clear This bit is written by application, and always read as 0.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "XONEIF", + "description": "Execute-only execute-never error interrupt flag clear This bit is written by application, and always read as 0.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "KEIF", + "description": "Key error interrupt flag clear This bit is written by application, and always read as 0. Note: Clearing KEIF does not solve the source of the problem (bad key registers). To be able to access again any encrypted region, OTFDEC key registers must be properly initialized again.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/IER": { + "description": "OTFDEC interrupt enable register.", + "fields": [ + { + "name": "SEIE", + "description": "Security error interrupt enable This bit is read and written by application. It controls the OTFDEC interrupt generation when SEIF flag status is set.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "XONEIE", + "description": "Execute-only execute-never error interrupt enable This bit is read and written by application. It controls the OTFDEC interrupt generation when XONEIF flag status is set.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "KEIE", + "description": "Key error interrupt enable This bit is read and written by application. It controls the OTFDEC interrupt generation when KEIF flag status is set.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "OTFDEC interrupt status register.", + "fields": [ + { + "name": "SEIF", + "description": "Security error interrupt flag status This bit is set by hardware and read only by application. This bit is set when at least one security error has been detected. This bit is cleared when application sets in OTFDEC_ICR the corresponding bit to 1.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "XONEIF", + "description": "Execute-only execute-never error interrupt flag status This bit is set by hardware and read only by application. This bit is set when a read access and not an instruction fetch is detected on any encrypted region with MODE bits set to 11. Lastly, XONEIF is also set when an execute access is detected while encryption mode is enabled. This bit is cleared when application sets in OTFDEC_ICR the corresponding bit to 1.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "KEIF", + "description": "Key error interrupt flag status This bit is set by hardware and read only by application. The bit is set when a read access occurs on an encrypted region, while its key registers is null or not properly initialized (KEYCRC = 0x0). This bit is cleared when the application sets in OTFDEC_ICR the corresponding bit to 1. After KEIF is set any subsequent read to the region with bad key registers returns a zeroed value. This state remains until those key registers are properly initialized (KEYCRC not zero).", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/PRIVCFGR": { + "description": "OTFDEC_PRIVCFGR.", + "fields": [ + { + "name": "PRIV", + "description": "Privileged access protection. Unprivileged read accesses to registers return zeros Unprivileged write accesses to registers are ignored. Note: This bit can only be written in privileged mode. There is no limitations on reads.", + "bit_offset": 0, + "bit_size": 1 + } + ] + }, + "fieldset/RegionCFGR": { + "description": "OTFDEC region 3 configuration register.", + "fields": [ + { + "name": "REG_EN", + "description": "region on-the-fly decryption enable Note: Garbage is decrypted if region context (version, key, nonce) is not valid when this bit is set.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "CONFIGLOCK", + "description": "region config lock Note: This bit is set once. If this bit is set, it can only be reset to 0 if OTFDEC is reset. Setting this bit forces KEYLOCK bit to 1.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "KEYLOCK", + "description": "region key lock Note: This bit is set once: if this bit is set, it can only be reset to 0 if the OTFDEC is reset.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "MODE", + "description": "operating mode This bitfield selects the OTFDEC operating mode for this region: Others: Reserved When MODE ≠ 11, the standard AES encryption mode is activated. When either of the MODE bits are changed, the region key and associated CRC are zeroed.", + "bit_offset": 4, + "bit_size": 2, + "enum": "MODE" + }, + { + "name": "KEYCRC", + "description": "region key 8-bit CRC When KEYLOCK = 0, KEYCRC bitfield is automatically computed by hardware while loading the key of this region in this exact sequence: KEYR0 then KEYR1 then KEYR2 then finally KEYR3 (all written once). A new computation starts as soon as a new valid sequence is initiated, and KEYCRC is read as zero until a valid sequence is completed. When KEYLOCK = 1, KEYCRC remains unchanged until the next reset. CRC computation is an 8-bit checksum using the standard CRC-8-CCITT algorithm X8 + X2 + X + 1 (according the convention). Source code is available in . This field is read only. Note: CRC information is updated only after the last bit of the key has been written.", + "bit_offset": 8, + "bit_size": 8 + }, + { + "name": "REG_VERSION", + "description": "region firmware version This 16-bit bitfield must be correctly initialized before the region corresponding REG_EN bit is set in OTFDEC_RxCFGR.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "enum/ENC": { + "bit_size": 1, + "variants": [ + { + "name": "Decryption", + "description": "OTFDEC working in decryption mode", + "value": 0 + }, + { + "name": "Encryption", + "description": "OTFDEC working in encryption mode", + "value": 1 + } + ] + }, + "enum/MODE": { + "bit_size": 2, + "variants": [ + { + "name": "Standard", + "description": "All read accesses are decrypted (instruction or data).", + "value": 2 + }, + { + "name": "Enhanced", + "description": "Enhanced encryption mode is activated, and only instruction accesses are decrypted", + "value": 3 + } + ] + } +} \ No newline at end of file