diff --git a/data/chips/STM32L010C6.json b/data/chips/STM32L010C6.json index bedf4e4..0105683 100644 --- a/data/chips/STM32L010C6.json +++ b/data/chips/STM32L010C6.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L010F4.json b/data/chips/STM32L010F4.json index 50a6c04..5287e57 100644 --- a/data/chips/STM32L010F4.json +++ b/data/chips/STM32L010F4.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L010K4.json b/data/chips/STM32L010K4.json index 0135a76..5153f8b 100644 --- a/data/chips/STM32L010K4.json +++ b/data/chips/STM32L010K4.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L010K8.json b/data/chips/STM32L010K8.json index eb7299e..1cac844 100644 --- a/data/chips/STM32L010K8.json +++ b/data/chips/STM32L010K8.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L010R8.json b/data/chips/STM32L010R8.json index a0248f2..b5d7bda 100644 --- a/data/chips/STM32L010R8.json +++ b/data/chips/STM32L010R8.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L010RB.json b/data/chips/STM32L010RB.json index ad22a99..bca9022 100644 --- a/data/chips/STM32L010RB.json +++ b/data/chips/STM32L010RB.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L011D3.json b/data/chips/STM32L011D3.json index e9b6a7b..350dac8 100644 --- a/data/chips/STM32L011D3.json +++ b/data/chips/STM32L011D3.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L011D4.json b/data/chips/STM32L011D4.json index ac58cd9..d2a8836 100644 --- a/data/chips/STM32L011D4.json +++ b/data/chips/STM32L011D4.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L011E3.json b/data/chips/STM32L011E3.json index 9805d03..80234e7 100644 --- a/data/chips/STM32L011E3.json +++ b/data/chips/STM32L011E3.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L011E4.json b/data/chips/STM32L011E4.json index b770371..db8e902 100644 --- a/data/chips/STM32L011E4.json +++ b/data/chips/STM32L011E4.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L011F3.json b/data/chips/STM32L011F3.json index 7cfaa4d..50bce8d 100644 --- a/data/chips/STM32L011F3.json +++ b/data/chips/STM32L011F3.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L011F4.json b/data/chips/STM32L011F4.json index df71102..5f42ac6 100644 --- a/data/chips/STM32L011F4.json +++ b/data/chips/STM32L011F4.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L011G3.json b/data/chips/STM32L011G3.json index 7fd8edd..e1e2ec6 100644 --- a/data/chips/STM32L011G3.json +++ b/data/chips/STM32L011G3.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L011G4.json b/data/chips/STM32L011G4.json index 6b1d543..789ed1d 100644 --- a/data/chips/STM32L011G4.json +++ b/data/chips/STM32L011G4.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L011K3.json b/data/chips/STM32L011K3.json index 3625f16..b609787 100644 --- a/data/chips/STM32L011K3.json +++ b/data/chips/STM32L011K3.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L011K4.json b/data/chips/STM32L011K4.json index 696781b..8ad6c1e 100644 --- a/data/chips/STM32L011K4.json +++ b/data/chips/STM32L011K4.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L021D4.json b/data/chips/STM32L021D4.json index 4a7cc86..3181980 100644 --- a/data/chips/STM32L021D4.json +++ b/data/chips/STM32L021D4.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L021F4.json b/data/chips/STM32L021F4.json index 8456e2f..e349f93 100644 --- a/data/chips/STM32L021F4.json +++ b/data/chips/STM32L021F4.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L021G4.json b/data/chips/STM32L021G4.json index 4d52008..8ea2bf5 100644 --- a/data/chips/STM32L021G4.json +++ b/data/chips/STM32L021G4.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L021K4.json b/data/chips/STM32L021K4.json index ac75203..aab53fe 100644 --- a/data/chips/STM32L021K4.json +++ b/data/chips/STM32L021K4.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L031C4.json b/data/chips/STM32L031C4.json index 66f26ff..9b3d5c1 100644 --- a/data/chips/STM32L031C4.json +++ b/data/chips/STM32L031C4.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L031C6.json b/data/chips/STM32L031C6.json index 61f9446..473ab19 100644 --- a/data/chips/STM32L031C6.json +++ b/data/chips/STM32L031C6.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L031E4.json b/data/chips/STM32L031E4.json index e479761..4e0e5b9 100644 --- a/data/chips/STM32L031E4.json +++ b/data/chips/STM32L031E4.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L031E6.json b/data/chips/STM32L031E6.json index 250026d..2bc10e2 100644 --- a/data/chips/STM32L031E6.json +++ b/data/chips/STM32L031E6.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L031F4.json b/data/chips/STM32L031F4.json index 77a5d9a..ed01afc 100644 --- a/data/chips/STM32L031F4.json +++ b/data/chips/STM32L031F4.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L031F6.json b/data/chips/STM32L031F6.json index bb92f3e..1c7f2c6 100644 --- a/data/chips/STM32L031F6.json +++ b/data/chips/STM32L031F6.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L031G4.json b/data/chips/STM32L031G4.json index 06061ee..569cc31 100644 --- a/data/chips/STM32L031G4.json +++ b/data/chips/STM32L031G4.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L031G6.json b/data/chips/STM32L031G6.json index d25cde1..2d5ce11 100644 --- a/data/chips/STM32L031G6.json +++ b/data/chips/STM32L031G6.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L031K4.json b/data/chips/STM32L031K4.json index a7d36ae..5b03d64 100644 --- a/data/chips/STM32L031K4.json +++ b/data/chips/STM32L031K4.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L031K6.json b/data/chips/STM32L031K6.json index 10eb847..13119d6 100644 --- a/data/chips/STM32L031K6.json +++ b/data/chips/STM32L031K6.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L041C4.json b/data/chips/STM32L041C4.json index 5416be5..afcddf8 100644 --- a/data/chips/STM32L041C4.json +++ b/data/chips/STM32L041C4.json @@ -36,7 +36,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L041C6.json b/data/chips/STM32L041C6.json index addbbe6..d060a15 100644 --- a/data/chips/STM32L041C6.json +++ b/data/chips/STM32L041C6.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L041E6.json b/data/chips/STM32L041E6.json index e620e1b..400a554 100644 --- a/data/chips/STM32L041E6.json +++ b/data/chips/STM32L041E6.json @@ -313,7 +313,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L041F6.json b/data/chips/STM32L041F6.json index d26f1b7..3720e6a 100644 --- a/data/chips/STM32L041F6.json +++ b/data/chips/STM32L041F6.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L041G6.json b/data/chips/STM32L041G6.json index 1b797c2..91cc4de 100644 --- a/data/chips/STM32L041G6.json +++ b/data/chips/STM32L041G6.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L041K6.json b/data/chips/STM32L041K6.json index 3ad607f..721135c 100644 --- a/data/chips/STM32L041K6.json +++ b/data/chips/STM32L041K6.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L051C6.json b/data/chips/STM32L051C6.json index 9dad791..21eabd8 100644 --- a/data/chips/STM32L051C6.json +++ b/data/chips/STM32L051C6.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L051C8.json b/data/chips/STM32L051C8.json index 4629422..96a5239 100644 --- a/data/chips/STM32L051C8.json +++ b/data/chips/STM32L051C8.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L051K6.json b/data/chips/STM32L051K6.json index 0dbb47c..8994745 100644 --- a/data/chips/STM32L051K6.json +++ b/data/chips/STM32L051K6.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L051K8.json b/data/chips/STM32L051K8.json index 609fe35..216f990 100644 --- a/data/chips/STM32L051K8.json +++ b/data/chips/STM32L051K8.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L051R6.json b/data/chips/STM32L051R6.json index ba422be..7686ab1 100644 --- a/data/chips/STM32L051R6.json +++ b/data/chips/STM32L051R6.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L051R8.json b/data/chips/STM32L051R8.json index 88b79e4..c4aca91 100644 --- a/data/chips/STM32L051R8.json +++ b/data/chips/STM32L051R8.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L051T6.json b/data/chips/STM32L051T6.json index 4022a4b..11580a3 100644 --- a/data/chips/STM32L051T6.json +++ b/data/chips/STM32L051T6.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L051T8.json b/data/chips/STM32L051T8.json index f0247cc..14451e4 100644 --- a/data/chips/STM32L051T8.json +++ b/data/chips/STM32L051T8.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L052C6.json b/data/chips/STM32L052C6.json index 86c6379..a456bb8 100644 --- a/data/chips/STM32L052C6.json +++ b/data/chips/STM32L052C6.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L052C8.json b/data/chips/STM32L052C8.json index c54e66d..27ef145 100644 --- a/data/chips/STM32L052C8.json +++ b/data/chips/STM32L052C8.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L052K6.json b/data/chips/STM32L052K6.json index 22b2b35..70b7f52 100644 --- a/data/chips/STM32L052K6.json +++ b/data/chips/STM32L052K6.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L052K8.json b/data/chips/STM32L052K8.json index d9f87b0..2ad48e5 100644 --- a/data/chips/STM32L052K8.json +++ b/data/chips/STM32L052K8.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L052R6.json b/data/chips/STM32L052R6.json index 611bafb..d809378 100644 --- a/data/chips/STM32L052R6.json +++ b/data/chips/STM32L052R6.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L052R8.json b/data/chips/STM32L052R8.json index 38129d0..ebb37d2 100644 --- a/data/chips/STM32L052R8.json +++ b/data/chips/STM32L052R8.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L052T6.json b/data/chips/STM32L052T6.json index f7e5fdc..80a03df 100644 --- a/data/chips/STM32L052T6.json +++ b/data/chips/STM32L052T6.json @@ -331,7 +331,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L052T8.json b/data/chips/STM32L052T8.json index a4d45f2..075522b 100644 --- a/data/chips/STM32L052T8.json +++ b/data/chips/STM32L052T8.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L053C6.json b/data/chips/STM32L053C6.json index a2cc158..b9187ac 100644 --- a/data/chips/STM32L053C6.json +++ b/data/chips/STM32L053C6.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L053C8.json b/data/chips/STM32L053C8.json index e8499e8..b7a971f 100644 --- a/data/chips/STM32L053C8.json +++ b/data/chips/STM32L053C8.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L053R6.json b/data/chips/STM32L053R6.json index 739bca4..f1c5ad7 100644 --- a/data/chips/STM32L053R6.json +++ b/data/chips/STM32L053R6.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L053R8.json b/data/chips/STM32L053R8.json index eb8d065..424e4c9 100644 --- a/data/chips/STM32L053R8.json +++ b/data/chips/STM32L053R8.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L062C8.json b/data/chips/STM32L062C8.json index 8c02835..75c51e8 100644 --- a/data/chips/STM32L062C8.json +++ b/data/chips/STM32L062C8.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L062K8.json b/data/chips/STM32L062K8.json index 3a07b1c..537d012 100644 --- a/data/chips/STM32L062K8.json +++ b/data/chips/STM32L062K8.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L063C8.json b/data/chips/STM32L063C8.json index ea81cc0..ffb6de2 100644 --- a/data/chips/STM32L063C8.json +++ b/data/chips/STM32L063C8.json @@ -335,7 +335,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L063R8.json b/data/chips/STM32L063R8.json index 1d57121..68f2f55 100644 --- a/data/chips/STM32L063R8.json +++ b/data/chips/STM32L063R8.json @@ -331,7 +331,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L071C8.json b/data/chips/STM32L071C8.json index 906dca1..4800e7a 100644 --- a/data/chips/STM32L071C8.json +++ b/data/chips/STM32L071C8.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L071CB.json b/data/chips/STM32L071CB.json index 691113d..4f9a812 100644 --- a/data/chips/STM32L071CB.json +++ b/data/chips/STM32L071CB.json @@ -327,7 +327,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L071CZ.json b/data/chips/STM32L071CZ.json index bce2247..ace9969 100644 --- a/data/chips/STM32L071CZ.json +++ b/data/chips/STM32L071CZ.json @@ -327,7 +327,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L071K8.json b/data/chips/STM32L071K8.json index 30075c5..76fbc0b 100644 --- a/data/chips/STM32L071K8.json +++ b/data/chips/STM32L071K8.json @@ -319,7 +319,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L071KB.json b/data/chips/STM32L071KB.json index 4137249..7eaff71 100644 --- a/data/chips/STM32L071KB.json +++ b/data/chips/STM32L071KB.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L071KZ.json b/data/chips/STM32L071KZ.json index 53021c5..f3c947b 100644 --- a/data/chips/STM32L071KZ.json +++ b/data/chips/STM32L071KZ.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L071RB.json b/data/chips/STM32L071RB.json index f9989f1..fef162b 100644 --- a/data/chips/STM32L071RB.json +++ b/data/chips/STM32L071RB.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L071RZ.json b/data/chips/STM32L071RZ.json index 5d6e07e..8153ae1 100644 --- a/data/chips/STM32L071RZ.json +++ b/data/chips/STM32L071RZ.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L071V8.json b/data/chips/STM32L071V8.json index cb73daa..f489ab6 100644 --- a/data/chips/STM32L071V8.json +++ b/data/chips/STM32L071V8.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L071VB.json b/data/chips/STM32L071VB.json index 7a6a453..789a3d1 100644 --- a/data/chips/STM32L071VB.json +++ b/data/chips/STM32L071VB.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L071VZ.json b/data/chips/STM32L071VZ.json index 6f30946..151392c 100644 --- a/data/chips/STM32L071VZ.json +++ b/data/chips/STM32L071VZ.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L072CB.json b/data/chips/STM32L072CB.json index a4a8288..974e482 100644 --- a/data/chips/STM32L072CB.json +++ b/data/chips/STM32L072CB.json @@ -333,7 +333,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L072CZ.json b/data/chips/STM32L072CZ.json index 85dd391..12f4313 100644 --- a/data/chips/STM32L072CZ.json +++ b/data/chips/STM32L072CZ.json @@ -337,7 +337,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L072KB.json b/data/chips/STM32L072KB.json index 3fd555d..399c02b 100644 --- a/data/chips/STM32L072KB.json +++ b/data/chips/STM32L072KB.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L072KZ.json b/data/chips/STM32L072KZ.json index c763437..bbd1187 100644 --- a/data/chips/STM32L072KZ.json +++ b/data/chips/STM32L072KZ.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L072RB.json b/data/chips/STM32L072RB.json index fe62d9c..55e4743 100644 --- a/data/chips/STM32L072RB.json +++ b/data/chips/STM32L072RB.json @@ -333,7 +333,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L072RZ.json b/data/chips/STM32L072RZ.json index f41007e..cf45f40 100644 --- a/data/chips/STM32L072RZ.json +++ b/data/chips/STM32L072RZ.json @@ -333,7 +333,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L072V8.json b/data/chips/STM32L072V8.json index 746ef56..c17a356 100644 --- a/data/chips/STM32L072V8.json +++ b/data/chips/STM32L072V8.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L072VB.json b/data/chips/STM32L072VB.json index e48d7a9..564b5fe 100644 --- a/data/chips/STM32L072VB.json +++ b/data/chips/STM32L072VB.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L072VZ.json b/data/chips/STM32L072VZ.json index a096499..999c8c7 100644 --- a/data/chips/STM32L072VZ.json +++ b/data/chips/STM32L072VZ.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L073CB.json b/data/chips/STM32L073CB.json index c5d2a4a..b289250 100644 --- a/data/chips/STM32L073CB.json +++ b/data/chips/STM32L073CB.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L073CZ.json b/data/chips/STM32L073CZ.json index 2d45639..1d93805 100644 --- a/data/chips/STM32L073CZ.json +++ b/data/chips/STM32L073CZ.json @@ -333,7 +333,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L073RB.json b/data/chips/STM32L073RB.json index ad9d0bc..82117c9 100644 --- a/data/chips/STM32L073RB.json +++ b/data/chips/STM32L073RB.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L073RZ.json b/data/chips/STM32L073RZ.json index 1ec47a2..cbc86d0 100644 --- a/data/chips/STM32L073RZ.json +++ b/data/chips/STM32L073RZ.json @@ -333,7 +333,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L073V8.json b/data/chips/STM32L073V8.json index a29deab..2d8cc38 100644 --- a/data/chips/STM32L073V8.json +++ b/data/chips/STM32L073V8.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L073VB.json b/data/chips/STM32L073VB.json index 247d380..14b0549 100644 --- a/data/chips/STM32L073VB.json +++ b/data/chips/STM32L073VB.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L073VZ.json b/data/chips/STM32L073VZ.json index a1dab80..9e599a6 100644 --- a/data/chips/STM32L073VZ.json +++ b/data/chips/STM32L073VZ.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L081CB.json b/data/chips/STM32L081CB.json index 00e829d..94179ea 100644 --- a/data/chips/STM32L081CB.json +++ b/data/chips/STM32L081CB.json @@ -313,7 +313,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L081CZ.json b/data/chips/STM32L081CZ.json index 269d801..aa19614 100644 --- a/data/chips/STM32L081CZ.json +++ b/data/chips/STM32L081CZ.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L081KZ.json b/data/chips/STM32L081KZ.json index d0c3b1c..53af166 100644 --- a/data/chips/STM32L081KZ.json +++ b/data/chips/STM32L081KZ.json @@ -323,7 +323,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L082CZ.json b/data/chips/STM32L082CZ.json index f4a853c..7077201 100644 --- a/data/chips/STM32L082CZ.json +++ b/data/chips/STM32L082CZ.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L082KB.json b/data/chips/STM32L082KB.json index afa253d..01c3e88 100644 --- a/data/chips/STM32L082KB.json +++ b/data/chips/STM32L082KB.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L082KZ.json b/data/chips/STM32L082KZ.json index b87ef9c..9fa89b4 100644 --- a/data/chips/STM32L082KZ.json +++ b/data/chips/STM32L082KZ.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L083CB.json b/data/chips/STM32L083CB.json index ee43799..96516e2 100644 --- a/data/chips/STM32L083CB.json +++ b/data/chips/STM32L083CB.json @@ -325,7 +325,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L083CZ.json b/data/chips/STM32L083CZ.json index 5d9a196..406dca6 100644 --- a/data/chips/STM32L083CZ.json +++ b/data/chips/STM32L083CZ.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L083RB.json b/data/chips/STM32L083RB.json index 7bcece2..fefa5ad 100644 --- a/data/chips/STM32L083RB.json +++ b/data/chips/STM32L083RB.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L083RZ.json b/data/chips/STM32L083RZ.json index 7853080..8bb7a46 100644 --- a/data/chips/STM32L083RZ.json +++ b/data/chips/STM32L083RZ.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L083V8.json b/data/chips/STM32L083V8.json index 73af6c5..e81bd47 100644 --- a/data/chips/STM32L083V8.json +++ b/data/chips/STM32L083V8.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L083VB.json b/data/chips/STM32L083VB.json index 76ed4b2..72cb96b 100644 --- a/data/chips/STM32L083VB.json +++ b/data/chips/STM32L083VB.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/chips/STM32L083VZ.json b/data/chips/STM32L083VZ.json index 91c39fe..f2ada12 100644 --- a/data/chips/STM32L083VZ.json +++ b/data/chips/STM32L083VZ.json @@ -329,7 +329,12 @@ "peripherals": [ { "name": "ADC", - "address": 1073817352, + "address": 1073816576, + "registers": { + "kind": "adc", + "version": "l0", + "block": "ADC" + }, "rcc": { "clock": "pclk2", "enable": { diff --git a/data/registers/adc_l0.json b/data/registers/adc_l0.json new file mode 100644 index 0000000..5dafa88 --- /dev/null +++ b/data/registers/adc_l0.json @@ -0,0 +1,703 @@ +{ + "block/ADC": { + "description": "Analog-to-digital converter", + "items": [ + { + "name": "ISR", + "description": "interrupt and status register", + "byte_offset": 0, + "fieldset": "ISR" + }, + { + "name": "IER", + "description": "interrupt enable register", + "byte_offset": 4, + "fieldset": "IER" + }, + { + "name": "CR", + "description": "control register", + "byte_offset": 8, + "fieldset": "CR" + }, + { + "name": "CFGR1", + "description": "configuration register 1", + "byte_offset": 12, + "fieldset": "CFGR1" + }, + { + "name": "CFGR2", + "description": "configuration register 2", + "byte_offset": 16, + "fieldset": "CFGR2" + }, + { + "name": "SMPR", + "description": "sampling time register", + "byte_offset": 20, + "fieldset": "SMPR" + }, + { + "name": "TR", + "description": "watchdog threshold register", + "byte_offset": 32, + "fieldset": "TR" + }, + { + "name": "CHSELR", + "description": "channel selection register", + "byte_offset": 40, + "fieldset": "CHSELR" + }, + { + "name": "DR", + "description": "data register", + "byte_offset": 64, + "access": "Read", + "fieldset": "DR" + }, + { + "name": "CALFACT", + "description": "ADC Calibration factor.", + "byte_offset": 180, + "fieldset": "CALFACT" + }, + { + "name": "CCR", + "description": "common configuration register", + "byte_offset": 776, + "fieldset": "CCR" + } + ] + }, + "fieldset/CALFACT": { + "description": "ADC Calibration factor.", + "fields": [ + { + "name": "CALFACT", + "description": "Calibration factor.", + "bit_offset": 0, + "bit_size": 7 + } + ] + }, + "fieldset/CCR": { + "description": "common configuration register", + "fields": [ + { + "name": "PRESC", + "description": "ADC prescaler.", + "bit_offset": 18, + "bit_size": 4, + "enum": "PRESC" + }, + { + "name": "VREFEN", + "description": "VREFINT enable", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "TSEN", + "description": "Temperature sensor enable", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "LFMEN", + "description": "Low Frequency Mode enable", + "bit_offset": 25, + "bit_size": 1 + } + ] + }, + "fieldset/CFGR1": { + "description": "configuration register 1", + "fields": [ + { + "name": "DMAEN", + "description": "Direct memory access enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DMACFG", + "description": "Direct memery access configuration", + "bit_offset": 1, + "bit_size": 1, + "enum": "DMACFG" + }, + { + "name": "SCANDIR", + "description": "Scan sequence direction", + "bit_offset": 2, + "bit_size": 1, + "enum": "SCANDIR" + }, + { + "name": "RES", + "description": "Data resolution", + "bit_offset": 3, + "bit_size": 2, + "enum": "RES" + }, + { + "name": "ALIGN", + "description": "Data alignment", + "bit_offset": 5, + "bit_size": 1, + "enum": "ALIGN" + }, + { + "name": "EXTSEL", + "description": "External trigger selection", + "bit_offset": 6, + "bit_size": 3 + }, + { + "name": "EXTEN", + "description": "External trigger enable and polarity selection", + "bit_offset": 10, + "bit_size": 2, + "enum": "EXTEN" + }, + { + "name": "OVRMOD", + "description": "Overrun management mode", + "bit_offset": 12, + "bit_size": 1, + "enum": "OVRMOD" + }, + { + "name": "CONT", + "description": "Single / continuous conversion mode", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "WAIT", + "description": "Wait conversion mode", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "AUTOFF", + "description": "Auto-off mode", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "DISCEN", + "description": "Discontinuous mode", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "AWDSGL", + "description": "Enable the watchdog on a single channel or on all channels", + "bit_offset": 22, + "bit_size": 1, + "enum": "AWDSGL" + }, + { + "name": "AWDEN", + "description": "Analog watchdog enable", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "AWDCH", + "description": "Analog watchdog channel selection", + "bit_offset": 26, + "bit_size": 5 + } + ] + }, + "fieldset/CFGR2": { + "description": "configuration register 2", + "fields": [ + { + "name": "OVSE", + "description": "Oversampler Enable.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "OVSR", + "description": "Oversampling ratio.", + "bit_offset": 2, + "bit_size": 3 + }, + { + "name": "OVSS", + "description": "Oversampling shift.", + "bit_offset": 5, + "bit_size": 4 + }, + { + "name": "TOVS", + "description": "Triggered Oversampling.", + "bit_offset": 9, + "bit_size": 1 + }, + { + "name": "CKMODE", + "description": "ADC clock mode", + "bit_offset": 30, + "bit_size": 2, + "enum": "CKMODE" + } + ] + }, + "fieldset/CHSELR": { + "description": "channel selection register", + "fields": [ + { + "name": "CHSEL x", + "description": "Channel-x selection", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 19, + "stride": 1 + } + } + ] + }, + "fieldset/CR": { + "description": "control register", + "fields": [ + { + "name": "ADEN", + "description": "ADC enable command", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "ADDIS", + "description": "ADC disable command", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "ADSTART", + "description": "ADC start conversion command", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "ADSTP", + "description": "ADC stop conversion command", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "ADVREGEN", + "description": "ADC Voltage Regulator Enable.", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "ADCAL", + "description": "ADC calibration", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/DR": { + "description": "data register", + "fields": [ + { + "name": "DATA", + "description": "Converted data", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/IER": { + "description": "interrupt enable register", + "fields": [ + { + "name": "ADRDYIE", + "description": "ADC ready interrupt enable", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "EOSMPIE", + "description": "End of sampling flag interrupt enable", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EOCIE", + "description": "End of conversion interrupt enable", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "EOSIE", + "description": "End of conversion sequence interrupt enable", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "OVRIE", + "description": "Overrun interrupt enable", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AWDIE", + "description": "Analog watchdog interrupt enable", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "EOCALIE", + "description": "End of calibration interrupt enable.", + "bit_offset": 11, + "bit_size": 1 + } + ] + }, + "fieldset/ISR": { + "description": "interrupt and status register", + "fields": [ + { + "name": "ADRDY", + "description": "ADC ready", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "EOSMP", + "description": "End of sampling flag", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EOC", + "description": "End of conversion flag", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "EOS", + "description": "End of sequence flag", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "OVR", + "description": "ADC overrun", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "AWD", + "description": "Analog watchdog flag", + "bit_offset": 7, + "bit_size": 1 + }, + { + "name": "EOCAL", + "description": "End Of Calibration flag", + "bit_offset": 11, + "bit_size": 1 + } + ] + }, + "fieldset/SMPR": { + "description": "sampling time register", + "fields": [ + { + "name": "SMP", + "description": "Sampling time selection", + "bit_offset": 0, + "bit_size": 3, + "enum": "SAMPLE_TIME" + } + ] + }, + "fieldset/TR": { + "description": "watchdog threshold register", + "fields": [ + { + "name": "LT", + "description": "Analog watchdog lower threshold", + "bit_offset": 0, + "bit_size": 12 + }, + { + "name": "HT", + "description": "Analog watchdog higher threshold", + "bit_offset": 16, + "bit_size": 12 + } + ] + }, + "enum/ALIGN": { + "bit_size": 1, + "variants": [ + { + "name": "Right", + "description": "Right alignment", + "value": 0 + }, + { + "name": "Left", + "description": "Left alignment", + "value": 1 + } + ] + }, + "enum/AWDSGL": { + "bit_size": 1, + "variants": [ + { + "name": "AllChannels", + "description": "Analog watchdog enabled on all channels", + "value": 0 + }, + { + "name": "SingleChannel", + "description": "Analog watchdog enabled on a single channel", + "value": 1 + } + ] + }, + "enum/CKMODE": { + "bit_size": 2, + "variants": [ + { + "name": "ADCCLK", + "description": "Asynchronous clock mode", + "value": 0 + }, + { + "name": "PCLK_Div2", + "description": "Synchronous clock mode (PCLK/2)", + "value": 1 + }, + { + "name": "PCLK_Div4", + "description": "Sychronous clock mode (PCLK/4)", + "value": 2 + }, + { + "name": "PCLK", + "description": "Synchronous clock mode (PCLK)", + "value": 3 + } + ] + }, + "enum/DMACFG": { + "bit_size": 1, + "variants": [ + { + "name": "OneShot", + "description": "DMA one shot mode", + "value": 0 + }, + { + "name": "Circular", + "description": "DMA circular mode", + "value": 1 + } + ] + }, + "enum/EXTEN": { + "bit_size": 2, + "variants": [ + { + "name": "Disabled", + "description": "Trigger detection disabled", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "Trigger detection on the rising edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "Trigger detection on the falling edge", + "value": 2 + }, + { + "name": "BothEdges", + "description": "Trigger detection on both the rising and falling edges", + "value": 3 + } + ] + }, + "enum/OVRMOD": { + "bit_size": 1, + "variants": [ + { + "name": "Preserved", + "description": "ADC_DR register is preserved with the old data when an overrun is detected", + "value": 0 + }, + { + "name": "Overwritten", + "description": "ADC_DR register is overwritten with the last conversion result when an overrun is detected", + "value": 1 + } + ] + }, + "enum/PRESC": { + "bit_size": 4, + "variants": [ + { + "name": "Div1", + "description": "Input ADC clock not divided.", + "value": 0 + }, + { + "name": "Div2", + "description": "Input ADC clock divided by 2.", + "value": 1 + }, + { + "name": "Div4", + "description": "Input ADC clock divided by 4.", + "value": 2 + }, + { + "name": "Div6", + "description": "Input ADC clock divided by 6.", + "value": 3 + }, + { + "name": "Div8", + "description": "Input ADC clock divided by 8.", + "value": 4 + }, + { + "name": "Div10", + "description": "Input ADC clock divided by 10.", + "value": 5 + }, + { + "name": "Div12", + "description": "Input ADC clock divided by 12.", + "value": 6 + }, + { + "name": "Div16", + "description": "Input ADC clock divided by 16.", + "value": 7 + }, + { + "name": "Div32", + "description": "Input ADC clock divided by 32.", + "value": 8 + }, + { + "name": "Div64", + "description": "Input ADC clock divided by 64.", + "value": 9 + }, + { + "name": "Div128", + "description": "Input ADC clock divided by 128.", + "value": 10 + }, + { + "name": "Div256", + "description": "Input ADC clock divided by 256.", + "value": 11 + } + ] + }, + "enum/RES": { + "bit_size": 2, + "variants": [ + { + "name": "TwelveBit", + "description": "12-bit (14 ADCCLK cycles)", + "value": 0 + }, + { + "name": "TenBit", + "description": "10-bit (13 ADCCLK cycles)", + "value": 1 + }, + { + "name": "EightBit", + "description": "8-bit (11 ADCCLK cycles)", + "value": 2 + }, + { + "name": "SixBit", + "description": "6-bit (9 ADCCLK cycles)", + "value": 3 + } + ] + }, + "enum/SAMPLE_TIME": { + "bit_size": 3, + "variants": [ + { + "name": "Cycles1_5", + "description": "1.5 cycles", + "value": 0 + }, + { + "name": "Cycles3_5", + "description": "3.5 cycles", + "value": 1 + }, + { + "name": "Cycles7_5", + "description": "7.5 cycles", + "value": 2 + }, + { + "name": "Cycles12_5", + "description": "12.5 cycles", + "value": 3 + }, + { + "name": "Cycles19_5", + "description": "19.5 cycles", + "value": 4 + }, + { + "name": "Cycles39_5", + "description": "39.5 cycles", + "value": 5 + }, + { + "name": "Cycles79_5", + "description": "79.5 cycles", + "value": 6 + }, + { + "name": "Cycles160_5", + "description": "160.5 cycles", + "value": 7 + } + ] + }, + "enum/SCANDIR": { + "bit_size": 1, + "variants": [ + { + "name": "Upward", + "description": "Upward scan (from CHSEL0 to CHSEL18)", + "value": 0 + }, + { + "name": "Backward", + "description": "Backward scan (from CHSEL18 to CHSEL0)", + "value": 1 + } + ] + } +} \ No newline at end of file