diff --git a/data/registers/can_fdcan_h7.json b/data/registers/can_fdcan_h7.json index 25315cc..d99b35e 100644 --- a/data/registers/can_fdcan_h7.json +++ b/data/registers/can_fdcan_h7.json @@ -2434,7 +2434,8 @@ "name": "TFQM", "description": "Tx FIFO/Queue Mode", "bit_offset": 30, - "bit_size": 1 + "bit_size": 1, + "enum": "TFQM" } ] }, @@ -2664,5 +2665,20 @@ "bit_size": 8 } ] + }, + "enum/TFQM": { + "bit_size": 1, + "variants": [ + { + "name": "FIFO", + "description": "Tx FIFO operation", + "value": 0 + }, + { + "name": "QUEUE", + "description": "Tx queue operation", + "value": 1 + } + ] } } \ No newline at end of file diff --git a/data/registers/can_fdcan_v1.json b/data/registers/can_fdcan_v1.json index b044751..a10f7f3 100644 --- a/data/registers/can_fdcan_v1.json +++ b/data/registers/can_fdcan_v1.json @@ -1180,7 +1180,8 @@ "name": "TFQM", "description": "Tx FIFO/queue mode. This is a protected write (P) bit, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1", "bit_offset": 24, - "bit_size": 1 + "bit_size": 1, + "enum": "TFQM" } ] }, @@ -1580,6 +1581,21 @@ } ] }, + "enum/TFQM": { + "bit_size": 1, + "variants": [ + { + "name": "FIFO", + "description": "Tx FIFO operation", + "value": 0 + }, + { + "name": "QUEUE", + "description": "Tx queue operation", + "value": 1 + } + ] + }, "enum/TOS": { "bit_size": 2, "variants": [