diff --git a/data/chips/STM32U031C6.json b/data/chips/STM32U031C6.json index e9b9ead..bf361a1 100644 --- a/data/chips/STM32U031C6.json +++ b/data/chips/STM32U031C6.json @@ -839,7 +839,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U031C8.json b/data/chips/STM32U031C8.json index 457d135..8adefcc 100644 --- a/data/chips/STM32U031C8.json +++ b/data/chips/STM32U031C8.json @@ -839,7 +839,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U031F4.json b/data/chips/STM32U031F4.json index 08215f2..4c2096c 100644 --- a/data/chips/STM32U031F4.json +++ b/data/chips/STM32U031F4.json @@ -378,7 +378,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U031F6.json b/data/chips/STM32U031F6.json index 3f03302..15e2e3e 100644 --- a/data/chips/STM32U031F6.json +++ b/data/chips/STM32U031F6.json @@ -378,7 +378,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U031F8.json b/data/chips/STM32U031F8.json index 4735975..e9ebfa9 100644 --- a/data/chips/STM32U031F8.json +++ b/data/chips/STM32U031F8.json @@ -378,7 +378,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U031G6.json b/data/chips/STM32U031G6.json index 419ad81..99224f2 100644 --- a/data/chips/STM32U031G6.json +++ b/data/chips/STM32U031G6.json @@ -410,7 +410,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U031G8.json b/data/chips/STM32U031G8.json index 6cbce61..9d07cf0 100644 --- a/data/chips/STM32U031G8.json +++ b/data/chips/STM32U031G8.json @@ -410,7 +410,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U031K4.json b/data/chips/STM32U031K4.json index 09e71f1..5aeb3aa 100644 --- a/data/chips/STM32U031K4.json +++ b/data/chips/STM32U031K4.json @@ -440,7 +440,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U031K6.json b/data/chips/STM32U031K6.json index f470376..f0f32f6 100644 --- a/data/chips/STM32U031K6.json +++ b/data/chips/STM32U031K6.json @@ -440,7 +440,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U031K8.json b/data/chips/STM32U031K8.json index 46567ef..8a4f86c 100644 --- a/data/chips/STM32U031K8.json +++ b/data/chips/STM32U031K8.json @@ -440,7 +440,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U031R6.json b/data/chips/STM32U031R6.json index 2e99aee..51fd970 100644 --- a/data/chips/STM32U031R6.json +++ b/data/chips/STM32U031R6.json @@ -1067,7 +1067,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U031R8.json b/data/chips/STM32U031R8.json index e87eb91..e97dc7c 100644 --- a/data/chips/STM32U031R8.json +++ b/data/chips/STM32U031R8.json @@ -1067,7 +1067,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073C8.json b/data/chips/STM32U073C8.json index c1b8389..2f4bcfb 100644 --- a/data/chips/STM32U073C8.json +++ b/data/chips/STM32U073C8.json @@ -936,7 +936,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073CB.json b/data/chips/STM32U073CB.json index 87eb4cd..56acc9d 100644 --- a/data/chips/STM32U073CB.json +++ b/data/chips/STM32U073CB.json @@ -936,7 +936,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073CC.json b/data/chips/STM32U073CC.json index 1e56b52..1bcc9c4 100644 --- a/data/chips/STM32U073CC.json +++ b/data/chips/STM32U073CC.json @@ -936,7 +936,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073H8.json b/data/chips/STM32U073H8.json index a60abda..5d67571 100644 --- a/data/chips/STM32U073H8.json +++ b/data/chips/STM32U073H8.json @@ -601,7 +601,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073HB.json b/data/chips/STM32U073HB.json index 2977882..0946e3a 100644 --- a/data/chips/STM32U073HB.json +++ b/data/chips/STM32U073HB.json @@ -601,7 +601,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073HC.json b/data/chips/STM32U073HC.json index 95cc737..05d6682 100644 --- a/data/chips/STM32U073HC.json +++ b/data/chips/STM32U073HC.json @@ -601,7 +601,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073K8.json b/data/chips/STM32U073K8.json index d157ca5..08eed3c 100644 --- a/data/chips/STM32U073K8.json +++ b/data/chips/STM32U073K8.json @@ -532,7 +532,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073KB.json b/data/chips/STM32U073KB.json index 75319bd..2c92385 100644 --- a/data/chips/STM32U073KB.json +++ b/data/chips/STM32U073KB.json @@ -532,7 +532,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073KC.json b/data/chips/STM32U073KC.json index 55ae4ad..c376263 100644 --- a/data/chips/STM32U073KC.json +++ b/data/chips/STM32U073KC.json @@ -532,7 +532,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073M8.json b/data/chips/STM32U073M8.json index 9aca59f..a0172ff 100644 --- a/data/chips/STM32U073M8.json +++ b/data/chips/STM32U073M8.json @@ -1366,7 +1366,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073MB.json b/data/chips/STM32U073MB.json index eeb57cb..537b6ca 100644 --- a/data/chips/STM32U073MB.json +++ b/data/chips/STM32U073MB.json @@ -1366,7 +1366,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073MC.json b/data/chips/STM32U073MC.json index f7c038a..cfd7f99 100644 --- a/data/chips/STM32U073MC.json +++ b/data/chips/STM32U073MC.json @@ -1366,7 +1366,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073R8.json b/data/chips/STM32U073R8.json index 5b4bec8..5848dda 100644 --- a/data/chips/STM32U073R8.json +++ b/data/chips/STM32U073R8.json @@ -1164,7 +1164,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073RB.json b/data/chips/STM32U073RB.json index 8644da1..a4bf746 100644 --- a/data/chips/STM32U073RB.json +++ b/data/chips/STM32U073RB.json @@ -1164,7 +1164,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U073RC.json b/data/chips/STM32U073RC.json index 14bab76..281ff09 100644 --- a/data/chips/STM32U073RC.json +++ b/data/chips/STM32U073RC.json @@ -1164,7 +1164,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U083CC.json b/data/chips/STM32U083CC.json index 811b472..f3498de 100644 --- a/data/chips/STM32U083CC.json +++ b/data/chips/STM32U083CC.json @@ -969,7 +969,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U083HC.json b/data/chips/STM32U083HC.json index 6f878e3..34eebfc 100644 --- a/data/chips/STM32U083HC.json +++ b/data/chips/STM32U083HC.json @@ -634,7 +634,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U083KC.json b/data/chips/STM32U083KC.json index 1de550b..9903442 100644 --- a/data/chips/STM32U083KC.json +++ b/data/chips/STM32U083KC.json @@ -565,7 +565,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U083MC.json b/data/chips/STM32U083MC.json index 92d2e69..873b3b3 100644 --- a/data/chips/STM32U083MC.json +++ b/data/chips/STM32U083MC.json @@ -1399,7 +1399,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/chips/STM32U083RC.json b/data/chips/STM32U083RC.json index a1f7a2b..ecd2a1c 100644 --- a/data/chips/STM32U083RC.json +++ b/data/chips/STM32U083RC.json @@ -1197,7 +1197,12 @@ }, { "name": "DBGMCU", - "address": 1073829888 + "address": 1073829888, + "registers": { + "kind": "dbgmcu", + "version": "u0", + "block": "DBGMCU" + } }, { "name": "DMA1", diff --git a/data/registers/dbgmcu_u0.json b/data/registers/dbgmcu_u0.json new file mode 100644 index 0000000..9ba0716 --- /dev/null +++ b/data/registers/dbgmcu_u0.json @@ -0,0 +1,411 @@ +{ + "block/DBGMCU": { + "description": "DBGMCU register block.", + "items": [ + { + "name": "IDCODE", + "description": "DBGMCU device ID code register.", + "byte_offset": 0, + "fieldset": "IDCODE" + }, + { + "name": "CR", + "description": "DBGMCU configuration register.", + "byte_offset": 4, + "fieldset": "CR" + }, + { + "name": "APB1FZR", + "description": "DBGMCU APB1 freeze register.", + "byte_offset": 8, + "fieldset": "APB1FZR" + }, + { + "name": "APB2FZR", + "description": "DBG APB2 freeze register.", + "byte_offset": 12, + "fieldset": "APB2FZR" + }, + { + "name": "SR", + "description": "DBGMCU status register.", + "byte_offset": 252, + "fieldset": "SR" + }, + { + "name": "DBG_AUTH_HOST", + "description": "DBGMCU debug authentication mailbox host register.", + "byte_offset": 256, + "fieldset": "DBG_AUTH_HOST" + }, + { + "name": "DBG_AUTH_DEVICE", + "description": "DBGMCU debug authentication mailbox device register.", + "byte_offset": 260, + "fieldset": "DBG_AUTH_DEVICE" + }, + { + "name": "PIDR4", + "description": "DBGMCU CoreSight peripheral identity register 4.", + "byte_offset": 4048, + "fieldset": "PIDR4" + }, + { + "name": "PIDR0", + "description": "DBGMCU CoreSight peripheral identity register 0.", + "byte_offset": 4064, + "fieldset": "PIDR0" + }, + { + "name": "PIDR1", + "description": "DBGMCU CoreSight peripheral identity register 1.", + "byte_offset": 4068, + "fieldset": "PIDR1" + }, + { + "name": "PIDR2", + "description": "DBGMCU CoreSight peripheral identity register 2.", + "byte_offset": 4072, + "fieldset": "PIDR2" + }, + { + "name": "PIDR3", + "description": "DBGMCU CoreSight peripheral identity register 3.", + "byte_offset": 4076, + "fieldset": "PIDR3" + }, + { + "name": "CIDR0", + "description": "DBGMCU CoreSight component identity register 0.", + "byte_offset": 4080, + "fieldset": "CIDR0" + }, + { + "name": "CIDR1", + "description": "DBGMCU CoreSight component identity register 1.", + "byte_offset": 4084, + "fieldset": "CIDR1" + }, + { + "name": "CIDR2", + "description": "DBGMCU CoreSight component identity register 2.", + "byte_offset": 4088, + "fieldset": "CIDR2" + }, + { + "name": "CIDR3", + "description": "DBGMCU CoreSight component identity register 3.", + "byte_offset": 4092, + "fieldset": "CIDR3" + } + ] + }, + "fieldset/APB1FZR": { + "description": "DBGMCU APB1 freeze register.", + "fields": [ + { + "name": "DBG_TIM2_STOP", + "description": "TIM2 stop in debug.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "DBG_TIM3_STOP", + "description": "TIM3 stop in debug.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DBG_TIM6_STOP", + "description": "TIM6 stop in debug.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "DBG_TIM7_STOP", + "description": "TIM7 stop in debug.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "DBG_RTC_STOP", + "description": "RTC stop in debug.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "DBG_WWDG_STOP", + "description": "WWDG stop in debug.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "DBG_IWDG_STOP", + "description": "IWDG stop in debug.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "DBG_LPTIM2_STOP", + "description": "LPTIM2 stop in debug.", + "bit_offset": 30, + "bit_size": 1 + }, + { + "name": "DBG_LPTIM1_STOP", + "description": "LPTIM1 stop in debug.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/APB2FZR": { + "description": "DBG APB2 freeze register.", + "fields": [ + { + "name": "DBG_TIM1_STOP", + "description": "TIM1 stop in debug.", + "bit_offset": 11, + "bit_size": 1 + }, + { + "name": "DBG_TIM15_STOP", + "description": "TIM15 stop in debug.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "DBG_TIM16_STOP", + "description": "TIM16 stop in debug.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "DBG_LPTIM3_STOP", + "description": "LPTIM3 stop in debug.", + "bit_offset": 18, + "bit_size": 1 + } + ] + }, + "fieldset/CIDR0": { + "description": "DBGMCU CoreSight component identity register 0.", + "fields": [ + { + "name": "PREAMBLE", + "description": "component identification bits [7:0].", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "fieldset/CIDR1": { + "description": "DBGMCU CoreSight component identity register 1.", + "fields": [ + { + "name": "PREAMBLE", + "description": "component identification bits [11:8].", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "CLASS", + "description": "component identification bits [15:12] - component class.", + "bit_offset": 4, + "bit_size": 4 + } + ] + }, + "fieldset/CIDR2": { + "description": "DBGMCU CoreSight component identity register 2.", + "fields": [ + { + "name": "PREAMBLE", + "description": "component identification bits [23:16].", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "fieldset/CIDR3": { + "description": "DBGMCU CoreSight component identity register 3.", + "fields": [ + { + "name": "PREAMBLE", + "description": "component identification bits [31:24].", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "fieldset/CR": { + "description": "DBGMCU configuration register.", + "fields": [ + { + "name": "DBG_STOP", + "description": "Debug Stop mode Debug options in Stop mode.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "DBG_STANDBY", + "description": "Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode.", + "bit_offset": 2, + "bit_size": 1 + } + ] + }, + "fieldset/DBG_AUTH_DEVICE": { + "description": "DBGMCU debug authentication mailbox device register.", + "fields": [ + { + "name": "MESSAGE", + "description": "Device to debug host mailbox message. During debug authentication the device communicates with the debug host via this register.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/DBG_AUTH_HOST": { + "description": "DBGMCU debug authentication mailbox host register.", + "fields": [ + { + "name": "MESSAGE", + "description": "Debug host to device mailbox message. During debug authentication the debug host communicates with the device via this register.", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/IDCODE": { + "description": "DBGMCU device ID code register.", + "fields": [ + { + "name": "DEV_ID", + "description": "Device identifier This field indicates the device ID.", + "bit_offset": 0, + "bit_size": 12 + }, + { + "name": "REV_ID", + "description": "Revision identifier This field indicates the revision of the device.", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/PIDR0": { + "description": "DBGMCU CoreSight peripheral identity register 0.", + "fields": [ + { + "name": "PARTNUM", + "description": "part number bits [7:0].", + "bit_offset": 0, + "bit_size": 8 + } + ] + }, + "fieldset/PIDR1": { + "description": "DBGMCU CoreSight peripheral identity register 1.", + "fields": [ + { + "name": "PARTNUM", + "description": "part number bits [11:8].", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "JEP106ID", + "description": "JEP106 identity code bits [3:0].", + "bit_offset": 4, + "bit_size": 4 + } + ] + }, + "fieldset/PIDR2": { + "description": "DBGMCU CoreSight peripheral identity register 2.", + "fields": [ + { + "name": "JEP106ID", + "description": "JEP106 identity code bits [6:4].", + "bit_offset": 0, + "bit_size": 3 + }, + { + "name": "JEDEC", + "description": "JEDEC assigned value.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "REVISION", + "description": "component revision number.", + "bit_offset": 4, + "bit_size": 4 + } + ] + }, + "fieldset/PIDR3": { + "description": "DBGMCU CoreSight peripheral identity register 3.", + "fields": [ + { + "name": "CMOD", + "description": "customer modified.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "REVAND", + "description": "metal fix version.", + "bit_offset": 4, + "bit_size": 4 + } + ] + }, + "fieldset/PIDR4": { + "description": "DBGMCU CoreSight peripheral identity register 4.", + "fields": [ + { + "name": "JEP106CON", + "description": "JEP106 continuation code.", + "bit_offset": 0, + "bit_size": 4 + }, + { + "name": "SIZE", + "description": "register file size.", + "bit_offset": 4, + "bit_size": 4 + } + ] + }, + "fieldset/SR": { + "description": "DBGMCU status register.", + "fields": [ + { + "name": "AP1_PRESENT", + "description": "Identifies whether access port AP1 is present in device.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "AP0_PRESENT", + "description": "Identifies whether access port AP0 is present in device.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "AP1_ENABLED", + "description": "Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked).", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "AP0_ENABLED", + "description": "Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked).", + "bit_offset": 17, + "bit_size": 1 + } + ] + } +} \ No newline at end of file