diff --git a/data/chips/STM32U535CB.json b/data/chips/STM32U535CB.json index c682a5f..68a0046 100644 --- a/data/chips/STM32U535CB.json +++ b/data/chips/STM32U535CB.json @@ -1308,7 +1308,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1316,7 +1321,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1380,7 +1385,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U535CC.json b/data/chips/STM32U535CC.json index 196913d..3e6dd63 100644 --- a/data/chips/STM32U535CC.json +++ b/data/chips/STM32U535CC.json @@ -1308,7 +1308,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1316,7 +1321,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1380,7 +1385,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U535CE.json b/data/chips/STM32U535CE.json index 3dff013..9cbf459 100644 --- a/data/chips/STM32U535CE.json +++ b/data/chips/STM32U535CE.json @@ -1308,7 +1308,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1316,7 +1321,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1380,7 +1385,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U535JE.json b/data/chips/STM32U535JE.json index 429b39f..97e5eb8 100644 --- a/data/chips/STM32U535JE.json +++ b/data/chips/STM32U535JE.json @@ -574,7 +574,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -582,7 +587,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -650,7 +655,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U535NC.json b/data/chips/STM32U535NC.json index d564427..121da63 100644 --- a/data/chips/STM32U535NC.json +++ b/data/chips/STM32U535NC.json @@ -474,7 +474,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -482,7 +487,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -546,7 +551,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U535NE.json b/data/chips/STM32U535NE.json index 27e8df1..537f67f 100644 --- a/data/chips/STM32U535NE.json +++ b/data/chips/STM32U535NE.json @@ -474,7 +474,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -482,7 +487,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -546,7 +551,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U535RB.json b/data/chips/STM32U535RB.json index 4984825..2f24709 100644 --- a/data/chips/STM32U535RB.json +++ b/data/chips/STM32U535RB.json @@ -1716,7 +1716,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1724,7 +1729,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1812,7 +1817,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U535RC.json b/data/chips/STM32U535RC.json index 7f04aa3..49e72e7 100644 --- a/data/chips/STM32U535RC.json +++ b/data/chips/STM32U535RC.json @@ -1716,7 +1716,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1724,7 +1729,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1812,7 +1817,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U535RE.json b/data/chips/STM32U535RE.json index 31da5ad..a76a51f 100644 --- a/data/chips/STM32U535RE.json +++ b/data/chips/STM32U535RE.json @@ -1716,7 +1716,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1724,7 +1729,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1812,7 +1817,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U535VC.json b/data/chips/STM32U535VC.json index c1889be..eb7cd48 100644 --- a/data/chips/STM32U535VC.json +++ b/data/chips/STM32U535VC.json @@ -2580,7 +2580,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2588,7 +2593,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2688,7 +2693,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U535VE.json b/data/chips/STM32U535VE.json index ae29b61..6e9b64b 100644 --- a/data/chips/STM32U535VE.json +++ b/data/chips/STM32U535VE.json @@ -2580,7 +2580,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2588,7 +2593,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2688,7 +2693,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U545CE.json b/data/chips/STM32U545CE.json index 46ec68f..eb98a96 100644 --- a/data/chips/STM32U545CE.json +++ b/data/chips/STM32U545CE.json @@ -1308,7 +1308,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1316,7 +1321,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1380,7 +1385,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U545JE.json b/data/chips/STM32U545JE.json index e4eb990..e426016 100644 --- a/data/chips/STM32U545JE.json +++ b/data/chips/STM32U545JE.json @@ -574,7 +574,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -582,7 +587,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -650,7 +655,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U545NE.json b/data/chips/STM32U545NE.json index 9e59e88..04336a0 100644 --- a/data/chips/STM32U545NE.json +++ b/data/chips/STM32U545NE.json @@ -474,7 +474,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -482,7 +487,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -546,7 +551,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U545RE.json b/data/chips/STM32U545RE.json index 01714dc..f2dbb73 100644 --- a/data/chips/STM32U545RE.json +++ b/data/chips/STM32U545RE.json @@ -1716,7 +1716,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1724,7 +1729,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1812,7 +1817,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U545VE.json b/data/chips/STM32U545VE.json index 08bc4fc..1b1d36b 100644 --- a/data/chips/STM32U545VE.json +++ b/data/chips/STM32U545VE.json @@ -2580,7 +2580,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2588,7 +2593,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2688,7 +2693,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575AG.json b/data/chips/STM32U575AG.json index 493b52d..b60aebc 100644 --- a/data/chips/STM32U575AG.json +++ b/data/chips/STM32U575AG.json @@ -2569,7 +2569,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2577,7 +2582,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2693,7 +2698,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575AI.json b/data/chips/STM32U575AI.json index 888b185..83e492a 100644 --- a/data/chips/STM32U575AI.json +++ b/data/chips/STM32U575AI.json @@ -2569,7 +2569,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2577,7 +2582,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2693,7 +2698,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575CG.json b/data/chips/STM32U575CG.json index aafd4ba..dc1b2ad 100644 --- a/data/chips/STM32U575CG.json +++ b/data/chips/STM32U575CG.json @@ -1681,7 +1681,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1689,7 +1694,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1753,7 +1758,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575CI.json b/data/chips/STM32U575CI.json index 23fc11a..d40a0d5 100644 --- a/data/chips/STM32U575CI.json +++ b/data/chips/STM32U575CI.json @@ -1681,7 +1681,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1689,7 +1694,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1753,7 +1758,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575OG.json b/data/chips/STM32U575OG.json index b0bdc5f..dd36185 100644 --- a/data/chips/STM32U575OG.json +++ b/data/chips/STM32U575OG.json @@ -1071,7 +1071,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1079,7 +1084,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1163,7 +1168,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575OI.json b/data/chips/STM32U575OI.json index aff3c84..7f16e91 100644 --- a/data/chips/STM32U575OI.json +++ b/data/chips/STM32U575OI.json @@ -1071,7 +1071,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1079,7 +1084,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1163,7 +1168,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575QG.json b/data/chips/STM32U575QG.json index b9deff9..641bd88 100644 --- a/data/chips/STM32U575QG.json +++ b/data/chips/STM32U575QG.json @@ -2125,7 +2125,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2133,7 +2138,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2249,7 +2254,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575QI.json b/data/chips/STM32U575QI.json index 3c38206..0e10cbe 100644 --- a/data/chips/STM32U575QI.json +++ b/data/chips/STM32U575QI.json @@ -2125,7 +2125,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2133,7 +2138,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2249,7 +2254,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575RG.json b/data/chips/STM32U575RG.json index 9383433..38c8d09 100644 --- a/data/chips/STM32U575RG.json +++ b/data/chips/STM32U575RG.json @@ -1309,7 +1309,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1317,7 +1322,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1405,7 +1410,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575RI.json b/data/chips/STM32U575RI.json index 1a62210..9471cd3 100644 --- a/data/chips/STM32U575RI.json +++ b/data/chips/STM32U575RI.json @@ -1309,7 +1309,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1317,7 +1322,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1405,7 +1410,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575VG.json b/data/chips/STM32U575VG.json index 71b958e..c619a8c 100644 --- a/data/chips/STM32U575VG.json +++ b/data/chips/STM32U575VG.json @@ -1741,7 +1741,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1749,7 +1754,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1849,7 +1854,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575VI.json b/data/chips/STM32U575VI.json index 136cc9c..5507475 100644 --- a/data/chips/STM32U575VI.json +++ b/data/chips/STM32U575VI.json @@ -1741,7 +1741,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1749,7 +1754,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1849,7 +1854,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575ZG.json b/data/chips/STM32U575ZG.json index 404958b..5c710fd 100644 --- a/data/chips/STM32U575ZG.json +++ b/data/chips/STM32U575ZG.json @@ -2269,7 +2269,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2277,7 +2282,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2393,7 +2398,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U575ZI.json b/data/chips/STM32U575ZI.json index 283194f..e503b73 100644 --- a/data/chips/STM32U575ZI.json +++ b/data/chips/STM32U575ZI.json @@ -2269,7 +2269,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2277,7 +2282,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2393,7 +2398,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U585AI.json b/data/chips/STM32U585AI.json index 496bf13..3ead06b 100644 --- a/data/chips/STM32U585AI.json +++ b/data/chips/STM32U585AI.json @@ -2575,7 +2575,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2583,7 +2588,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2699,7 +2704,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U585CI.json b/data/chips/STM32U585CI.json index 59768e2..a949b7a 100644 --- a/data/chips/STM32U585CI.json +++ b/data/chips/STM32U585CI.json @@ -1687,7 +1687,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1695,7 +1700,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1759,7 +1764,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U585OI.json b/data/chips/STM32U585OI.json index 943a834..7f23e15 100644 --- a/data/chips/STM32U585OI.json +++ b/data/chips/STM32U585OI.json @@ -1077,7 +1077,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1085,7 +1090,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1169,7 +1174,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U585QI.json b/data/chips/STM32U585QI.json index bf45705..c33be32 100644 --- a/data/chips/STM32U585QI.json +++ b/data/chips/STM32U585QI.json @@ -2131,7 +2131,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2139,7 +2144,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2255,7 +2260,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U585RI.json b/data/chips/STM32U585RI.json index 4fa9ccb..e864078 100644 --- a/data/chips/STM32U585RI.json +++ b/data/chips/STM32U585RI.json @@ -1315,7 +1315,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1323,7 +1328,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1411,7 +1416,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U585VI.json b/data/chips/STM32U585VI.json index 020aafa..1b72f2c 100644 --- a/data/chips/STM32U585VI.json +++ b/data/chips/STM32U585VI.json @@ -1747,7 +1747,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -1755,7 +1760,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1855,7 +1860,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U585ZI.json b/data/chips/STM32U585ZI.json index 4c12d3d..2e3ed8f 100644 --- a/data/chips/STM32U585ZI.json +++ b/data/chips/STM32U585ZI.json @@ -2275,7 +2275,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460872 + "address": 1107460872, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC4", @@ -2283,7 +2288,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2399,7 +2404,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541064 + "address": 1174541064, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U595AI.json b/data/chips/STM32U595AI.json index a4cb63a..5a083a4 100644 --- a/data/chips/STM32U595AI.json +++ b/data/chips/STM32U595AI.json @@ -2208,7 +2208,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -2316,7 +2321,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2432,7 +2437,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U595AJ.json b/data/chips/STM32U595AJ.json index 340d8a8..3997db9 100644 --- a/data/chips/STM32U595AJ.json +++ b/data/chips/STM32U595AJ.json @@ -2208,7 +2208,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -2316,7 +2321,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2432,7 +2437,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U595QI.json b/data/chips/STM32U595QI.json index f648bb3..a22905a 100644 --- a/data/chips/STM32U595QI.json +++ b/data/chips/STM32U595QI.json @@ -1764,7 +1764,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1872,7 +1877,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1988,7 +1993,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U595QJ.json b/data/chips/STM32U595QJ.json index 0c2babb..5c27929 100644 --- a/data/chips/STM32U595QJ.json +++ b/data/chips/STM32U595QJ.json @@ -1764,7 +1764,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1872,7 +1877,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1988,7 +1993,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U595RI.json b/data/chips/STM32U595RI.json index f530119..be8846f 100644 --- a/data/chips/STM32U595RI.json +++ b/data/chips/STM32U595RI.json @@ -948,7 +948,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1056,7 +1061,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1144,7 +1149,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U595RJ.json b/data/chips/STM32U595RJ.json index 37fa1c9..784e432 100644 --- a/data/chips/STM32U595RJ.json +++ b/data/chips/STM32U595RJ.json @@ -948,7 +948,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1056,7 +1061,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1144,7 +1149,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U595VI.json b/data/chips/STM32U595VI.json index ebeb28c..8968c54 100644 --- a/data/chips/STM32U595VI.json +++ b/data/chips/STM32U595VI.json @@ -1380,7 +1380,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1488,7 +1493,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1588,7 +1593,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U595VJ.json b/data/chips/STM32U595VJ.json index be3bf3d..eef5d01 100644 --- a/data/chips/STM32U595VJ.json +++ b/data/chips/STM32U595VJ.json @@ -1380,7 +1380,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1488,7 +1493,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1588,7 +1593,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U595ZI.json b/data/chips/STM32U595ZI.json index ceef69e..910fc8e 100644 --- a/data/chips/STM32U595ZI.json +++ b/data/chips/STM32U595ZI.json @@ -2814,7 +2814,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -2922,7 +2927,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -3038,7 +3043,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U595ZJ.json b/data/chips/STM32U595ZJ.json index 8202f91..7e9577f 100644 --- a/data/chips/STM32U595ZJ.json +++ b/data/chips/STM32U595ZJ.json @@ -2814,7 +2814,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -2922,7 +2927,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -3038,7 +3043,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U599BJ.json b/data/chips/STM32U599BJ.json index 15f4844..d30ab0a 100644 --- a/data/chips/STM32U599BJ.json +++ b/data/chips/STM32U599BJ.json @@ -1422,7 +1422,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1530,7 +1535,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1646,7 +1651,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U599NI.json b/data/chips/STM32U599NI.json index 8abcc6e..6ac7343 100644 --- a/data/chips/STM32U599NI.json +++ b/data/chips/STM32U599NI.json @@ -1470,7 +1470,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1578,7 +1583,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1694,7 +1699,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U599NJ.json b/data/chips/STM32U599NJ.json index 890c08b..7cb82df 100644 --- a/data/chips/STM32U599NJ.json +++ b/data/chips/STM32U599NJ.json @@ -1470,7 +1470,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1578,7 +1583,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1694,7 +1699,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U599VI.json b/data/chips/STM32U599VI.json index 83a4333..92f0ac9 100644 --- a/data/chips/STM32U599VI.json +++ b/data/chips/STM32U599VI.json @@ -766,7 +766,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -866,7 +871,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -958,7 +963,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U599VJ.json b/data/chips/STM32U599VJ.json index e737ed8..f99937f 100644 --- a/data/chips/STM32U599VJ.json +++ b/data/chips/STM32U599VJ.json @@ -1380,7 +1380,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1488,7 +1493,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1588,7 +1593,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U599ZI.json b/data/chips/STM32U599ZI.json index c6a0e8e..3f90b33 100644 --- a/data/chips/STM32U599ZI.json +++ b/data/chips/STM32U599ZI.json @@ -1944,7 +1944,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -2052,7 +2057,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2168,7 +2173,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U599ZJ.json b/data/chips/STM32U599ZJ.json index 13738c5..8b5b606 100644 --- a/data/chips/STM32U599ZJ.json +++ b/data/chips/STM32U599ZJ.json @@ -1944,7 +1944,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -2052,7 +2057,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2168,7 +2173,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index d601ab3..fe6b2a0 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -2208,7 +2208,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -2316,7 +2321,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2432,7 +2437,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5A5QI.json b/data/chips/STM32U5A5QI.json index b08f293..da69a59 100644 --- a/data/chips/STM32U5A5QI.json +++ b/data/chips/STM32U5A5QI.json @@ -966,7 +966,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1074,7 +1079,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1190,7 +1195,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index 7a93c9e..f32ef8f 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -1764,7 +1764,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1872,7 +1877,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1988,7 +1993,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index 7241e45..62f07a6 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -948,7 +948,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1056,7 +1061,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1144,7 +1149,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index 6c86526..b86e46d 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -1380,7 +1380,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1488,7 +1493,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1588,7 +1593,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 025a592..93567be 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -2814,7 +2814,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -2922,7 +2927,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -3038,7 +3043,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 1acd576..75d3230 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -1422,7 +1422,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1530,7 +1535,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1646,7 +1651,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index cbc2b69..eb7e0b9 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -1470,7 +1470,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1578,7 +1583,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1694,7 +1699,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 1b45b71..3565fce 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -766,7 +766,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -866,7 +871,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -958,7 +963,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index a22e4ab..52b6695 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -1944,7 +1944,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -2052,7 +2057,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2168,7 +2173,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5F7VI.json b/data/chips/STM32U5F7VI.json index 78110ac..55df54a 100644 --- a/data/chips/STM32U5F7VI.json +++ b/data/chips/STM32U5F7VI.json @@ -1386,7 +1386,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1494,7 +1499,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1594,7 +1599,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5F7VJ.json b/data/chips/STM32U5F7VJ.json index 13c5ada..32b80e8 100644 --- a/data/chips/STM32U5F7VJ.json +++ b/data/chips/STM32U5F7VJ.json @@ -1386,7 +1386,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1494,7 +1499,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1594,7 +1599,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5F9BJ.json b/data/chips/STM32U5F9BJ.json index d47c04f..1bf87b0 100644 --- a/data/chips/STM32U5F9BJ.json +++ b/data/chips/STM32U5F9BJ.json @@ -1428,7 +1428,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1536,7 +1541,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1652,7 +1657,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5F9NJ.json b/data/chips/STM32U5F9NJ.json index e6bf487..512fb3a 100644 --- a/data/chips/STM32U5F9NJ.json +++ b/data/chips/STM32U5F9NJ.json @@ -1476,7 +1476,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1584,7 +1589,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1700,7 +1705,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5F9VI.json b/data/chips/STM32U5F9VI.json index 9cd9960..204f22b 100644 --- a/data/chips/STM32U5F9VI.json +++ b/data/chips/STM32U5F9VI.json @@ -772,7 +772,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -872,7 +877,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -952,7 +957,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5F9VJ.json b/data/chips/STM32U5F9VJ.json index 0206730..c449594 100644 --- a/data/chips/STM32U5F9VJ.json +++ b/data/chips/STM32U5F9VJ.json @@ -772,7 +772,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -872,7 +877,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -952,7 +957,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5F9ZI.json b/data/chips/STM32U5F9ZI.json index 9af9ff1..8108f40 100644 --- a/data/chips/STM32U5F9ZI.json +++ b/data/chips/STM32U5F9ZI.json @@ -1894,7 +1894,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1994,7 +1999,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2094,7 +2099,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5F9ZJ.json b/data/chips/STM32U5F9ZJ.json index 1f87480..61c2122 100644 --- a/data/chips/STM32U5F9ZJ.json +++ b/data/chips/STM32U5F9ZJ.json @@ -1894,7 +1894,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1994,7 +1999,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2094,7 +2099,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5G7VJ.json b/data/chips/STM32U5G7VJ.json index ce87bf9..29f3228 100644 --- a/data/chips/STM32U5G7VJ.json +++ b/data/chips/STM32U5G7VJ.json @@ -1386,7 +1386,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1494,7 +1499,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1594,7 +1599,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5G9BJ.json b/data/chips/STM32U5G9BJ.json index 00e9c4a..c9fd162 100644 --- a/data/chips/STM32U5G9BJ.json +++ b/data/chips/STM32U5G9BJ.json @@ -1428,7 +1428,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1536,7 +1541,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1652,7 +1657,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5G9NJ.json b/data/chips/STM32U5G9NJ.json index 2c04e9f..2769b39 100644 --- a/data/chips/STM32U5G9NJ.json +++ b/data/chips/STM32U5G9NJ.json @@ -1476,7 +1476,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1584,7 +1589,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -1700,7 +1705,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5G9VJ.json b/data/chips/STM32U5G9VJ.json index 88da611..96c7d3f 100644 --- a/data/chips/STM32U5G9VJ.json +++ b/data/chips/STM32U5G9VJ.json @@ -772,7 +772,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -872,7 +877,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -952,7 +957,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/chips/STM32U5G9ZJ.json b/data/chips/STM32U5G9ZJ.json index cf3902a..60511a3 100644 --- a/data/chips/STM32U5G9ZJ.json +++ b/data/chips/STM32U5G9ZJ.json @@ -1894,7 +1894,12 @@ }, { "name": "ADC12_COMMON", - "address": 1107460864 + "address": 1107460864, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADC2", @@ -1994,7 +1999,7 @@ "registers": { "kind": "adc", "version": "u5", - "block": "ADC" + "block": "ADC4" }, "rcc": { "bus_clock": "HCLK3", @@ -2094,7 +2099,12 @@ }, { "name": "ADC4_COMMON", - "address": 1174541056 + "address": 1174541056, + "registers": { + "kind": "adccommon", + "version": "u5", + "block": "ADC_COMMON" + } }, { "name": "ADF1", diff --git a/data/registers/adc_u5.json b/data/registers/adc_u5.json index 44ccf53..4276505 100644 --- a/data/registers/adc_u5.json +++ b/data/registers/adc_u5.json @@ -1,6 +1,6 @@ { "block/ADC": { - "description": "ADC.", + "description": "ADC1.", "items": [ { "name": "ISR", @@ -21,10 +21,10 @@ "fieldset": "CR" }, { - "name": "CFGR1", + "name": "CFGR", "description": "ADC configuration register.", "byte_offset": 12, - "fieldset": "CFGR1" + "fieldset": "CFGR" }, { "name": "CFGR2", @@ -34,518 +34,840 @@ }, { "name": "SMPR", - "description": "ADC sample time register.", + "description": "sampling time register 1-2", + "array": { + "len": 2, + "stride": 4 + }, "byte_offset": 20, "fieldset": "SMPR" }, + { + "name": "PCSEL", + "description": "ADC channel preselection register.", + "byte_offset": 28, + "fieldset": "PCSEL" + }, + { + "name": "SQR1", + "description": "ADC regular sequence register 1.", + "byte_offset": 48, + "fieldset": "SQR1" + }, + { + "name": "SQR2", + "description": "ADC regular sequence register 2.", + "byte_offset": 52, + "fieldset": "SQR2" + }, + { + "name": "SQR3", + "description": "ADC regular sequence register 3.", + "byte_offset": 56, + "fieldset": "SQR3" + }, + { + "name": "SQR4", + "description": "ADC regular sequence register 4.", + "byte_offset": 60, + "fieldset": "SQR4" + }, + { + "name": "DR", + "description": "ADC regular Data Register.", + "byte_offset": 64, + "access": "Read", + "fieldset": "DR" + }, + { + "name": "JSQR", + "description": "ADC injected sequence register.", + "byte_offset": 76, + "fieldset": "JSQR" + }, + { + "name": "OFR", + "description": "ADC offset register.", + "array": { + "len": 4, + "stride": 4 + }, + "byte_offset": 96, + "fieldset": "OFR" + }, + { + "name": "GCOMP", + "description": "ADC gain compensation register.", + "byte_offset": 112, + "fieldset": "GCOMP" + }, + { + "name": "JDR", + "description": "ADC injected data register.", + "array": { + "len": 4, + "stride": 4 + }, + "byte_offset": 128, + "access": "Read", + "fieldset": "JDR" + }, + { + "name": "AWD2CR", + "description": "ADC analog watchdog 2 configuration register.", + "byte_offset": 160, + "fieldset": "AWD2CR" + }, + { + "name": "AWD3CR", + "description": "ADC analog watchdog 3 configuration register.", + "byte_offset": 164, + "fieldset": "AWD3CR" + }, + { + "name": "LTR1", + "description": "ADC watchdog threshold register 1.", + "byte_offset": 168, + "fieldset": "LTR1" + }, + { + "name": "HTR1", + "description": "ADC watchdog threshold register 1.", + "byte_offset": 172, + "fieldset": "HTR1" + }, + { + "name": "LTR2", + "description": "ADC watchdog lower threshold register 2.", + "byte_offset": 176, + "fieldset": "LTR2" + }, + { + "name": "HTR2", + "description": "ADC watchdog higher threshold register 2.", + "byte_offset": 180, + "fieldset": "HTR2" + }, + { + "name": "LTR3", + "description": "ADC watchdog lower threshold register 3.", + "byte_offset": 184, + "fieldset": "LTR3" + }, + { + "name": "HTR3", + "description": "ADC watchdog higher threshold register 3.", + "byte_offset": 188, + "fieldset": "HTR3" + }, + { + "name": "DIFSEL", + "description": "ADC differential mode selection register.", + "byte_offset": 192, + "fieldset": "DIFSEL" + }, + { + "name": "CALFACT", + "description": "ADC user control register.", + "byte_offset": 196, + "fieldset": "CALFACT" + }, + { + "name": "CALFACT2", + "description": "ADC calibration factor register.", + "byte_offset": 200, + "fieldset": "CALFACT2" + } + ] + }, + "block/ADC4": { + "description": "ADC4.", + "items": [ + { + "name": "ISR", + "description": "ADC interrupt and status register.", + "byte_offset": 0, + "fieldset": "ADC4_ISR" + }, + { + "name": "IER", + "description": "ADC interrupt enable register.", + "byte_offset": 4, + "fieldset": "ADC4_IER" + }, + { + "name": "CR", + "description": "ADC control register.", + "byte_offset": 8, + "fieldset": "ADC4_CR" + }, + { + "name": "CFGR1", + "description": "ADC configuration register.", + "byte_offset": 12, + "fieldset": "ADC4_CFGR1" + }, + { + "name": "CFGR2", + "description": "ADC configuration register 2.", + "byte_offset": 16, + "fieldset": "ADC4_CFGR2" + }, + { + "name": "SMPR", + "description": "ADC sample time register.", + "byte_offset": 20, + "fieldset": "ADC4_SMPR" + }, { "name": "AWD1TR", "description": "ADC watchdog threshold register.", "byte_offset": 32, - "fieldset": "AWD1TR" + "fieldset": "ADC4_AWDTR" }, { "name": "AWD2TR", "description": "ADC watchdog threshold register.", "byte_offset": 36, - "fieldset": "AWD2TR" + "fieldset": "ADC4_AWDTR" }, { "name": "CHSELRMOD0", "description": "ADC channel selection register [alternate].", "byte_offset": 40, - "fieldset": "CHSELRMOD0" + "fieldset": "ADC4_CHSELRMOD0" }, { "name": "CHSELRMOD1", "description": "ADC channel selection register [alternate].", "byte_offset": 40, - "fieldset": "CHSELRMOD1" + "fieldset": "ADC4_CHSELRMOD1" }, { "name": "AWD3TR", "description": "ADC watchdog threshold register.", "byte_offset": 44, - "fieldset": "AWD3TR" + "fieldset": "ADC4_AWDTR" }, { "name": "DR", "description": "ADC data register.", "byte_offset": 64, "access": "Read", - "fieldset": "DR" + "fieldset": "ADC4_DR" }, { "name": "PWRR", - "description": "ADC data register.", + "description": "ADC power register.", "byte_offset": 68, - "fieldset": "PWRR" + "fieldset": "ADC4_PWRR" }, { "name": "AWD2CR", "description": "ADC Analog Watchdog 2 Configuration register.", "byte_offset": 160, - "fieldset": "AWD2CR" + "fieldset": "ADC4_AWDCR" }, { "name": "AWD3CR", "description": "ADC Analog Watchdog 3 Configuration register.", "byte_offset": 164, - "fieldset": "AWD3CR" + "fieldset": "ADC4_AWDCR" }, { "name": "CALFACT", "description": "ADC Calibration factor.", "byte_offset": 196, - "fieldset": "CALFACT" + "fieldset": "ADC4_CALFACT" }, { "name": "OR", "description": "ADC option register.", "byte_offset": 208, - "fieldset": "OR" + "fieldset": "ADC4_OR" }, { "name": "CCR", "description": "ADC common configuration register.", "byte_offset": 776, - "fieldset": "CCR" + "fieldset": "ADC4_CCR" } ] }, - "fieldset/AWD1TR": { + "fieldset/ADC4_AWDCR": { + "description": "ADC Analog Watchdog Configuration register.", + "fields": [ + { + "name": "AWDCH", + "description": "AWDCH0.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 24, + "stride": 1 + } + } + ] + }, + "fieldset/ADC4_AWDTR": { "description": "ADC watchdog threshold register.", "fields": [ { - "name": "LT1", - "description": "LT1.", + "name": "LT3", + "description": "LT3.", "bit_offset": 0, "bit_size": 12 }, { - "name": "HT1", - "description": "HT1.", + "name": "HT3", + "description": "HT3.", "bit_offset": 16, "bit_size": 12 } ] }, - "fieldset/AWD2CR": { - "description": "ADC Analog Watchdog 2 Configuration register.", + "fieldset/ADC4_CALFACT": { + "description": "ADC Calibration factor.", "fields": [ { - "name": "AWD2CH0", - "description": "AWD2CH0.", + "name": "CALFACT", + "description": "CALFACT.", "bit_offset": 0, - "bit_size": 1 - }, + "bit_size": 7 + } + ] + }, + "fieldset/ADC4_CCR": { + "description": "ADC common configuration register.", + "fields": [ { - "name": "AWD2CH1", - "description": "AWD2CH1.", - "bit_offset": 1, - "bit_size": 1 + "name": "PRESC", + "description": "PRESC.", + "bit_offset": 18, + "bit_size": 4, + "enum": "ADC4_PRESC" }, { - "name": "AWD2CH2", - "description": "AWD2CH2.", - "bit_offset": 2, + "name": "VREFEN", + "description": "VREFEN.", + "bit_offset": 22, "bit_size": 1 }, { - "name": "AWD2CH3", - "description": "AWD2CH3.", - "bit_offset": 3, + "name": "VSENSESEL", + "description": "VSENSESEL.", + "bit_offset": 23, "bit_size": 1 }, { - "name": "AWD2CH4", - "description": "AWD2CH4.", - "bit_offset": 4, + "name": "VBATEN", + "description": "VBATEN.", + "bit_offset": 24, "bit_size": 1 - }, + } + ] + }, + "fieldset/ADC4_CFGR1": { + "description": "ADC configuration register.", + "fields": [ { - "name": "AWD2CH5", - "description": "AWD2CH5.", - "bit_offset": 5, + "name": "DMAEN", + "description": "DMAEN.", + "bit_offset": 0, "bit_size": 1 }, { - "name": "AWD2CH6", - "description": "AWD2CH6.", - "bit_offset": 6, - "bit_size": 1 + "name": "DMACFG", + "description": "DMACFG.", + "bit_offset": 1, + "bit_size": 1, + "enum": "ADC4_DMACFG" }, { - "name": "AWD2CH7", - "description": "AWD2CH7.", - "bit_offset": 7, - "bit_size": 1 + "name": "RES", + "description": "RES.", + "bit_offset": 2, + "bit_size": 2, + "enum": "ADC4_RES" }, { - "name": "AWD2CH8", - "description": "AWD2CH8.", - "bit_offset": 8, + "name": "SCANDIR", + "description": "SCANDIR.", + "bit_offset": 4, "bit_size": 1 }, { - "name": "AWD2CH9", - "description": "AWD2CH9.", - "bit_offset": 9, + "name": "ALIGN", + "description": "ALIGN.", + "bit_offset": 5, "bit_size": 1 }, { - "name": "AWD2CH10", - "description": "AWD2CH10.", - "bit_offset": 10, - "bit_size": 1 + "name": "EXTSEL", + "description": "EXTSEL.", + "bit_offset": 6, + "bit_size": 3 }, { - "name": "AWD2CH11", - "description": "AWD2CH11.", - "bit_offset": 11, - "bit_size": 1 + "name": "EXTEN", + "description": "EXTEN.", + "bit_offset": 10, + "bit_size": 2, + "enum": "ADC4_EXTEN" }, { - "name": "AWD2CH12", - "description": "AWD2CH12.", + "name": "OVRMOD", + "description": "OVRMOD.", "bit_offset": 12, "bit_size": 1 }, { - "name": "AWD2CH13", - "description": "AWD2CH13.", + "name": "CONT", + "description": "CONT.", "bit_offset": 13, "bit_size": 1 }, { - "name": "AWD2CH14", - "description": "AWD2CH14.", + "name": "WAIT", + "description": "WAIT.", "bit_offset": 14, "bit_size": 1 }, { - "name": "AWD2CH15", - "description": "AWD2CH15.", - "bit_offset": 15, + "name": "DISCEN", + "description": "DISCEN.", + "bit_offset": 16, "bit_size": 1 }, { - "name": "AWD2CH16", - "description": "AWD2CH16.", - "bit_offset": 16, + "name": "CHSELRMOD", + "description": "CHSELRMOD.", + "bit_offset": 21, "bit_size": 1 }, { - "name": "AWD2CH17", - "description": "AWD2CH17.", - "bit_offset": 17, + "name": "AWD1SGL", + "description": "AWD1SGL.", + "bit_offset": 22, "bit_size": 1 }, { - "name": "AWD2CH18", - "description": "AWD2CH18.", - "bit_offset": 18, + "name": "AWD1EN", + "description": "AWD1EN.", + "bit_offset": 23, "bit_size": 1 }, { - "name": "AWD2CH19", - "description": "AWD2CH19.", - "bit_offset": 19, + "name": "AWD1CH", + "description": "AWD1CH.", + "bit_offset": 26, + "bit_size": 5 + } + ] + }, + "fieldset/ADC4_CFGR2": { + "description": "ADC configuration register 2.", + "fields": [ + { + "name": "OVSE", + "description": "OVSE.", + "bit_offset": 0, "bit_size": 1 }, { - "name": "AWD2CH20", - "description": "AWD2CH20.", - "bit_offset": 20, - "bit_size": 1 + "name": "OVSR", + "description": "OVSR.", + "bit_offset": 2, + "bit_size": 3, + "enum": "ADC4_OVERSAMPLING_RATIO" }, { - "name": "AWD2CH21", - "description": "AWD2CH21.", - "bit_offset": 21, - "bit_size": 1 + "name": "OVSS", + "description": "OVSS.", + "bit_offset": 5, + "bit_size": 4 }, { - "name": "AWD2CH22", - "description": "AWD2CH22.", - "bit_offset": 22, + "name": "TOVS", + "description": "TOVS.", + "bit_offset": 9, "bit_size": 1 }, { - "name": "AWD2CH23", - "description": "AWD2CH23.", - "bit_offset": 23, + "name": "LFTRIG", + "description": "LFTRIG.", + "bit_offset": 29, "bit_size": 1 } ] }, - "fieldset/AWD2TR": { - "description": "ADC watchdog threshold register.", + "fieldset/ADC4_CHSELRMOD0": { + "description": "ADC channel selection register [alternate].", "fields": [ { - "name": "LT2", - "description": "LT2.", + "name": "CHSEL", + "description": "CHSEL.", "bit_offset": 0, - "bit_size": 12 - }, + "bit_size": 1, + "array": { + "len": 24, + "stride": 1 + } + } + ] + }, + "fieldset/ADC4_CHSELRMOD1": { + "description": "ADC channel selection register [alternate].", + "fields": [ { - "name": "HT2", - "description": "HT2.", - "bit_offset": 16, - "bit_size": 12 + "name": "SQ", + "description": "SQ", + "bit_offset": 0, + "bit_size": 4, + "array": { + "len": 8, + "stride": 4 + } } ] }, - "fieldset/AWD3CR": { - "description": "ADC Analog Watchdog 3 Configuration register.", + "fieldset/ADC4_CR": { + "description": "ADC control register.", "fields": [ { - "name": "AWD3CH0", - "description": "AWD3CH0.", + "name": "ADEN", + "description": "ADEN.", "bit_offset": 0, "bit_size": 1 }, { - "name": "AWD3CH1", - "description": "AWD3CH1.", + "name": "ADDIS", + "description": "ADDIS.", "bit_offset": 1, "bit_size": 1 }, { - "name": "AWD3CH2", - "description": "AWD3CH2.", + "name": "ADSTART", + "description": "ADSTART.", "bit_offset": 2, "bit_size": 1 }, { - "name": "AWD3CH3", - "description": "AWD3CH3.", - "bit_offset": 3, - "bit_size": 1 - }, - { - "name": "AWD3CH4", - "description": "AWD3CH4.", + "name": "ADSTP", + "description": "ADSTP.", "bit_offset": 4, "bit_size": 1 }, { - "name": "AWD3CH5", - "description": "AWD3CH5.", - "bit_offset": 5, + "name": "ADVREGEN", + "description": "ADVREGEN.", + "bit_offset": 28, "bit_size": 1 }, { - "name": "AWD3CH6", - "description": "AWD3CH6.", - "bit_offset": 6, + "name": "ADCAL", + "description": "ADCAL.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/ADC4_DR": { + "description": "ADC data register.", + "fields": [ + { + "name": "DATA", + "description": "DATA.", + "bit_offset": 0, + "bit_size": 16 + } + ] + }, + "fieldset/ADC4_IER": { + "description": "ADC interrupt enable register.", + "fields": [ + { + "name": "ADRDYIE", + "description": "ADRDYIE.", + "bit_offset": 0, "bit_size": 1 }, { - "name": "AWD3CH7", - "description": "AWD3CH7.", - "bit_offset": 7, + "name": "EOSMPIE", + "description": "EOSMPIE.", + "bit_offset": 1, "bit_size": 1 }, { - "name": "AWD3CH8", - "description": "AWD3CH8.", - "bit_offset": 8, + "name": "EOCIE", + "description": "EOCIE.", + "bit_offset": 2, "bit_size": 1 }, { - "name": "AWD3CH9", - "description": "AWD3CH9.", - "bit_offset": 9, + "name": "EOSIE", + "description": "EOSIE.", + "bit_offset": 3, "bit_size": 1 }, { - "name": "AWD3CH10", - "description": "AWD3CH10.", - "bit_offset": 10, + "name": "OVRIE", + "description": "OVRIE.", + "bit_offset": 4, "bit_size": 1 }, { - "name": "AWD3CH11", - "description": "AWD3CH11.", + "name": "AWDIE", + "description": "AWD1IE.", + "bit_offset": 7, + "bit_size": 1, + "array": { + "len": 3, + "stride": 1 + } + }, + { + "name": "EOCALIE", + "description": "EOCALIE.", "bit_offset": 11, "bit_size": 1 }, { - "name": "AWD3CH12", - "description": "AWD3CH12.", + "name": "LDORDYIE", + "description": "LDORDYIE.", "bit_offset": 12, "bit_size": 1 - }, + } + ] + }, + "fieldset/ADC4_ISR": { + "description": "ADC interrupt and status register.", + "fields": [ { - "name": "AWD3CH13", - "description": "AWD3CH13.", - "bit_offset": 13, + "name": "ADRDY", + "description": "ADRDY.", + "bit_offset": 0, "bit_size": 1 }, { - "name": "AWD3CH14", - "description": "AWD3CH14.", - "bit_offset": 14, + "name": "EOSMP", + "description": "EOSMP.", + "bit_offset": 1, "bit_size": 1 }, { - "name": "AWD3CH15", - "description": "AWD3CH15.", - "bit_offset": 15, + "name": "EOC", + "description": "EOC.", + "bit_offset": 2, "bit_size": 1 }, { - "name": "AWD3CH16", - "description": "AWD3CH16.", - "bit_offset": 16, + "name": "EOS", + "description": "EOS.", + "bit_offset": 3, "bit_size": 1 }, { - "name": "AWD3CH17", - "description": "AWD3CH17.", - "bit_offset": 17, + "name": "OVR", + "description": "OVR.", + "bit_offset": 4, "bit_size": 1 }, { - "name": "AWD3CH18", - "description": "AWD3CH18.", - "bit_offset": 18, - "bit_size": 1 + "name": "AWD", + "description": "AWD1.", + "bit_offset": 7, + "bit_size": 1, + "array": { + "len": 3, + "stride": 1 + } }, { - "name": "AWD3CH19", - "description": "AWD3CH19.", - "bit_offset": 19, + "name": "EOCAL", + "description": "EOCAL.", + "bit_offset": 11, "bit_size": 1 }, { - "name": "AWD3CH20", - "description": "AWD3CH20.", - "bit_offset": 20, + "name": "LDORDY", + "description": "LDORDY.", + "bit_offset": 12, + "bit_size": 1 + } + ] + }, + "fieldset/ADC4_OR": { + "description": "ADC option register.", + "fields": [ + { + "name": "CHN21SEL", + "description": "CHN21SEL.", + "bit_offset": 0, + "bit_size": 1 + } + ] + }, + "fieldset/ADC4_PWRR": { + "description": "ADC data register.", + "fields": [ + { + "name": "AUTOFF", + "description": "AUTOFF.", + "bit_offset": 0, "bit_size": 1 }, { - "name": "AWD3CH21", - "description": "AWD3CH21.", - "bit_offset": 21, + "name": "DPD", + "description": "DPD.", + "bit_offset": 1, "bit_size": 1 }, { - "name": "AWD3CH22", - "description": "AWD3CH22.", - "bit_offset": 22, + "name": "VREFPROT", + "description": "VREFPROT.", + "bit_offset": 2, "bit_size": 1 }, { - "name": "AWD3CH23", - "description": "AWD3CH23.", - "bit_offset": 23, + "name": "VREFSECSMP", + "description": "VREFSECSMP.", + "bit_offset": 3, "bit_size": 1 } ] }, - "fieldset/AWD3TR": { - "description": "ADC watchdog threshold register.", + "fieldset/ADC4_SMPR": { + "description": "ADC sample time register.", "fields": [ { - "name": "LT3", - "description": "LT3.", + "name": "SMP", + "description": "SMP1.", "bit_offset": 0, - "bit_size": 12 + "bit_size": 3, + "array": { + "len": 2, + "stride": 4 + }, + "enum": "ADC4_SAMPLE_TIME" }, { - "name": "HT3", - "description": "HT3.", - "bit_offset": 16, - "bit_size": 12 + "name": "SMPSEL", + "description": "SMPSEL0.", + "bit_offset": 8, + "bit_size": 1, + "array": { + "len": 24, + "stride": 1 + } } ] }, - "fieldset/CALFACT": { - "description": "ADC Calibration factor.", + "fieldset/AWD2CR": { + "description": "ADC analog watchdog 2 configuration register.", "fields": [ { - "name": "CALFACT", - "description": "CALFACT.", + "name": "AWD2CH", + "description": "AWD2CH.", "bit_offset": 0, - "bit_size": 7 + "bit_size": 1, + "array": { + "len": 20, + "stride": 1 + } } ] }, - "fieldset/CCR": { - "description": "ADC common configuration register.", + "fieldset/AWD3CR": { + "description": "ADC analog watchdog 3 configuration register.", "fields": [ { - "name": "PRESC", - "description": "PRESC.", - "bit_offset": 18, - "bit_size": 4 + "name": "AWD3CH", + "description": "AWD3CH.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 20, + "stride": 1 + } + } + ] + }, + "fieldset/CALFACT": { + "description": "ADC user control register.", + "fields": [ + { + "name": "I_APB_ADDR", + "description": "I_APB_ADDR.", + "bit_offset": 0, + "bit_size": 8 }, { - "name": "VREFEN", - "description": "VREFEN.", - "bit_offset": 22, - "bit_size": 1 + "name": "I_APB_DATA", + "description": "I_APB_DATA.", + "bit_offset": 8, + "bit_size": 8 }, { - "name": "VSENSESEL", - "description": "VSENSESEL.", - "bit_offset": 23, + "name": "VALIDITY", + "description": "VALIDITY.", + "bit_offset": 16, "bit_size": 1 }, { - "name": "VBATEN", - "description": "VBATEN.", + "name": "LATCH_COEF", + "description": "LATCH_COEF.", "bit_offset": 24, "bit_size": 1 + }, + { + "name": "CAPTURE_COEF", + "description": "CAPTURE_COEF.", + "bit_offset": 25, + "bit_size": 1 } ] }, - "fieldset/CFGR1": { - "description": "ADC configuration register.", + "fieldset/CALFACT2": { + "description": "ADC calibration factor register.", "fields": [ { - "name": "DMAEN", - "description": "DMAEN.", + "name": "CALFACT", + "description": "CALFACT.", "bit_offset": 0, - "bit_size": 1 - }, + "bit_size": 32 + } + ] + }, + "fieldset/CFGR": { + "description": "ADC configuration register.", + "fields": [ { - "name": "DMACFG", - "description": "DMACFG.", - "bit_offset": 1, - "bit_size": 1 + "name": "DMNGT", + "description": "DMNGT.", + "bit_offset": 0, + "bit_size": 2, + "enum": "DMNGT" }, { "name": "RES", "description": "RES.", "bit_offset": 2, - "bit_size": 2 - }, - { - "name": "SCANDIR", - "description": "SCANDIR.", - "bit_offset": 4, - "bit_size": 1 - }, - { - "name": "ALIGN", - "description": "ALIGN.", - "bit_offset": 5, - "bit_size": 1 + "bit_size": 2, + "enum": "RES" }, { "name": "EXTSEL", "description": "EXTSEL.", - "bit_offset": 6, - "bit_size": 3 + "bit_offset": 5, + "bit_size": 5 }, { "name": "EXTEN", "description": "EXTEN.", "bit_offset": 10, - "bit_size": 2 + "bit_size": 2, + "enum": "EXTEN" }, { "name": "OVRMOD", @@ -560,8 +882,8 @@ "bit_size": 1 }, { - "name": "WAIT", - "description": "WAIT.", + "name": "AUTDLY", + "description": "AUTDLY.", "bit_offset": 14, "bit_size": 1 }, @@ -572,9 +894,15 @@ "bit_size": 1 }, { - "name": "CHSELRMOD", - "description": "CHSELRMOD.", - "bit_offset": 21, + "name": "DISCNUM", + "description": "DISCNUM.", + "bit_offset": 17, + "bit_size": 3 + }, + { + "name": "JDISCEN", + "description": "JDISCEN.", + "bit_offset": 20, "bit_size": 1 }, { @@ -589,6 +917,18 @@ "bit_offset": 23, "bit_size": 1 }, + { + "name": "JAWD1EN", + "description": "JAWD1EN.", + "bit_offset": 24, + "bit_size": 1 + }, + { + "name": "JAUTO", + "description": "JAUTO.", + "bit_offset": 25, + "bit_size": 1 + }, { "name": "AWD1CH", "description": "AWD1CH.", @@ -601,16 +941,16 @@ "description": "ADC configuration register 2.", "fields": [ { - "name": "OVSE", - "description": "OVSE.", + "name": "ROVSE", + "description": "ROVSE.", "bit_offset": 0, "bit_size": 1 }, { - "name": "OVSR", - "description": "OVSR.", - "bit_offset": 2, - "bit_size": 3 + "name": "JOVSE", + "description": "JOVSE.", + "bit_offset": 1, + "bit_size": 1 }, { "name": "OVSS", @@ -619,80 +959,52 @@ "bit_size": 4 }, { - "name": "TOVS", - "description": "TOVS.", + "name": "TROVS", + "description": "TROVS.", "bit_offset": 9, "bit_size": 1 }, + { + "name": "ROVSM", + "description": "ROVSM.", + "bit_offset": 10, + "bit_size": 1 + }, + { + "name": "BULB", + "description": "BULB.", + "bit_offset": 13, + "bit_size": 1 + }, + { + "name": "SWTRIG", + "description": "SWTRIG.", + "bit_offset": 14, + "bit_size": 1 + }, + { + "name": "SMPTRIG", + "description": "SMPTRIG.", + "bit_offset": 15, + "bit_size": 1 + }, + { + "name": "OSVR", + "description": "OSVR.", + "bit_offset": 16, + "bit_size": 10 + }, { "name": "LFTRIG", "description": "LFTRIG.", - "bit_offset": 29, + "bit_offset": 27, "bit_size": 1 - } - ] - }, - "fieldset/CHSELRMOD0": { - "description": "ADC channel selection register [alternate].", - "fields": [ - { - "name": "CHSEL", - "description": "CHSEL.", - "bit_offset": 0, - "bit_size": 24 - } - ] - }, - "fieldset/CHSELRMOD1": { - "description": "ADC channel selection register [alternate].", - "fields": [ - { - "name": "SQ1", - "description": "SQ1.", - "bit_offset": 0, - "bit_size": 4 - }, - { - "name": "SQ2", - "description": "SQ2.", - "bit_offset": 4, - "bit_size": 4 - }, - { - "name": "SQ3", - "description": "SQ3.", - "bit_offset": 8, - "bit_size": 4 - }, - { - "name": "SQ4", - "description": "SQ4.", - "bit_offset": 12, - "bit_size": 4 - }, - { - "name": "SQ5", - "description": "SQ5.", - "bit_offset": 16, - "bit_size": 4 - }, - { - "name": "SQ6", - "description": "SQ6.", - "bit_offset": 20, - "bit_size": 4 - }, - { - "name": "SQ7", - "description": "SQ7.", - "bit_offset": 24, - "bit_size": 4 - }, - { - "name": "SQ8", - "description": "SQ8.", - "bit_offset": 28, - "bit_size": 4 + }, + { + "name": "LSHIFT", + "description": "LSHIFT.", + "bit_offset": 28, + "bit_size": 4 } ] }, @@ -717,18 +1029,49 @@ "bit_offset": 2, "bit_size": 1 }, + { + "name": "JADSTART", + "description": "JADSTART.", + "bit_offset": 3, + "bit_size": 1 + }, { "name": "ADSTP", "description": "ADSTP.", "bit_offset": 4, + "bit_size": 1, + "enum": "ADSTP" + }, + { + "name": "JADSTP", + "description": "JADSTP.", + "bit_offset": 5, "bit_size": 1 }, + { + "name": "ADCALLIN", + "description": "ADCALLIN.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "CALINDEX", + "description": "CALINDEX.", + "bit_offset": 24, + "bit_size": 4 + }, { "name": "ADVREGEN", "description": "ADVREGEN.", "bit_offset": 28, "bit_size": 1 }, + { + "name": "DEEPPWD", + "description": "DEEPPWD.", + "bit_offset": 29, + "bit_size": 1 + }, { "name": "ADCAL", "description": "ADCAL.", @@ -737,14 +1080,86 @@ } ] }, + "fieldset/DIFSEL": { + "description": "ADC differential mode selection register.", + "fields": [ + { + "name": "DIFSEL", + "description": "channel differential or single-ended mode for channel", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 20, + "stride": 1 + }, + "enum": "DIFSEL" + } + ] + }, "fieldset/DR": { - "description": "ADC data register.", + "description": "ADC regular Data Register.", "fields": [ { - "name": "DATA", - "description": "DATA.", + "name": "RDATA", + "description": "RDATA.", "bit_offset": 0, - "bit_size": 16 + "bit_size": 32 + } + ] + }, + "fieldset/GCOMP": { + "description": "ADC gain compensation register.", + "fields": [ + { + "name": "GCOMPCOEFF", + "description": "GCOMPCOEFF.", + "bit_offset": 0, + "bit_size": 14 + }, + { + "name": "GCOMP", + "description": "GCOMP.", + "bit_offset": 31, + "bit_size": 1 + } + ] + }, + "fieldset/HTR1": { + "description": "ADC watchdog threshold register 1.", + "fields": [ + { + "name": "HTR1", + "description": "HTR1.", + "bit_offset": 0, + "bit_size": 25 + }, + { + "name": "AWDFILT1", + "description": "AWDFILT1.", + "bit_offset": 29, + "bit_size": 3 + } + ] + }, + "fieldset/HTR2": { + "description": "ADC watchdog higher threshold register 2.", + "fields": [ + { + "name": "HTR2", + "description": "HTR2.", + "bit_offset": 0, + "bit_size": 25 + } + ] + }, + "fieldset/HTR3": { + "description": "ADC watchdog higher threshold register 3.", + "fields": [ + { + "name": "HTR3", + "description": "HTR3.", + "bit_offset": 0, + "bit_size": 25 } ] }, @@ -782,34 +1197,26 @@ "bit_size": 1 }, { - "name": "AWD1IE", - "description": "AWD1IE.", - "bit_offset": 7, - "bit_size": 1 - }, - { - "name": "AWD2IE", - "description": "AWD2IE.", - "bit_offset": 8, - "bit_size": 1 - }, - { - "name": "AWD3IE", - "description": "AWD3IE.", - "bit_offset": 9, + "name": "JEOCIE", + "description": "JEOCIE.", + "bit_offset": 5, "bit_size": 1 }, { - "name": "EOCALIE", - "description": "EOCALIE.", - "bit_offset": 11, + "name": "JEOSIE", + "description": "JEOSIE.", + "bit_offset": 6, "bit_size": 1 }, { - "name": "LDORDYIE", - "description": "LDORDYIE.", - "bit_offset": 12, - "bit_size": 1 + "name": "AWDIE", + "description": "AWD1IE.", + "bit_offset": 7, + "bit_size": 1, + "array": { + "len": 3, + "stride": 1 + } } ] }, @@ -847,28 +1254,26 @@ "bit_size": 1 }, { - "name": "AWD1", - "description": "AWD1.", - "bit_offset": 7, - "bit_size": 1 - }, - { - "name": "AWD2", - "description": "AWD2.", - "bit_offset": 8, + "name": "JEOC", + "description": "JEOC.", + "bit_offset": 5, "bit_size": 1 }, { - "name": "AWD3", - "description": "AWD3.", - "bit_offset": 9, + "name": "JEOS", + "description": "JEOS.", + "bit_offset": 6, "bit_size": 1 }, { - "name": "EOCAL", - "description": "EOCAL.", - "bit_offset": 11, - "bit_size": 1 + "name": "AWD", + "description": "AWD1.", + "bit_offset": 7, + "bit_size": 1, + "array": { + "len": 3, + "stride": 1 + } }, { "name": "LDORDY", @@ -878,204 +1283,593 @@ } ] }, - "fieldset/OR": { - "description": "ADC option register.", + "fieldset/JDR": { + "description": "ADC injected data register.", "fields": [ { - "name": "CHN21SEL", - "description": "CHN21SEL.", + "name": "JDATA", + "description": "JDATA.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 32 } ] }, - "fieldset/PWRR": { - "description": "ADC data register.", + "fieldset/JSQR": { + "description": "ADC injected sequence register.", "fields": [ { - "name": "AUTOFF", - "description": "AUTOFF.", + "name": "JL", + "description": "JL.", "bit_offset": 0, - "bit_size": 1 + "bit_size": 2 }, { - "name": "DPD", - "description": "DPD.", - "bit_offset": 1, + "name": "JEXTSEL", + "description": "JEXTSEL.", + "bit_offset": 2, + "bit_size": 5 + }, + { + "name": "JEXTEN", + "description": "JEXTEN.", + "bit_offset": 7, + "bit_size": 2 + }, + { + "name": "JSQ", + "description": "JSQ1.", + "bit_offset": 9, + "bit_size": 5, + "array": { + "len": 4, + "stride": 6 + } + } + ] + }, + "fieldset/LTR1": { + "description": "ADC watchdog threshold register 1.", + "fields": [ + { + "name": "LTR1", + "description": "LTR1.", + "bit_offset": 0, + "bit_size": 25 + } + ] + }, + "fieldset/LTR2": { + "description": "ADC watchdog lower threshold register 2.", + "fields": [ + { + "name": "LTR2", + "description": "LTR2.", + "bit_offset": 0, + "bit_size": 25 + } + ] + }, + "fieldset/LTR3": { + "description": "ADC watchdog lower threshold register 3.", + "fields": [ + { + "name": "LTR3", + "description": "LTR3.", + "bit_offset": 0, + "bit_size": 25 + } + ] + }, + "fieldset/OFR": { + "description": "ADC offset register.", + "fields": [ + { + "name": "OFFSET", + "description": "OFFSET.", + "bit_offset": 0, + "bit_size": 24 + }, + { + "name": "POSOFF", + "description": "POSOFF.", + "bit_offset": 24, "bit_size": 1 }, { - "name": "VREFPROT", - "description": "VREFPROT.", - "bit_offset": 2, + "name": "USAT", + "description": "USAT.", + "bit_offset": 25, "bit_size": 1 }, { - "name": "VREFSECSMP", - "description": "VREFSECSMP.", - "bit_offset": 3, + "name": "SSAT", + "description": "SSAT.", + "bit_offset": 26, "bit_size": 1 + }, + { + "name": "OFFSET_CH", + "description": "OFFSET_CH.", + "bit_offset": 27, + "bit_size": 5 + } + ] + }, + "fieldset/PCSEL": { + "description": "ADC channel preselection register.", + "fields": [ + { + "name": "PCSEL", + "description": "PCSEL.", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 20, + "stride": 1 + }, + "enum": "PCSEL" } ] }, "fieldset/SMPR": { - "description": "ADC sample time register.", + "description": "ADC sample time register 1.", "fields": [ { - "name": "SMP1", - "description": "SMP1.", + "name": "SMP", + "description": "SMP0.", "bit_offset": 0, - "bit_size": 3 + "bit_size": 3, + "array": { + "len": 10, + "stride": 3 + }, + "enum": "SAMPLE_TIME" + } + ] + }, + "fieldset/SQR1": { + "description": "ADC regular sequence register 1.", + "fields": [ + { + "name": "L", + "description": "L.", + "bit_offset": 0, + "bit_size": 4 }, { - "name": "SMP2", - "description": "SMP2.", - "bit_offset": 4, - "bit_size": 3 + "name": "SQ", + "description": "SQ1.", + "bit_offset": 6, + "bit_size": 5, + "array": { + "len": 4, + "stride": 6 + } + } + ] + }, + "fieldset/SQR2": { + "description": "ADC regular sequence register 2.", + "fields": [ + { + "name": "SQ", + "description": "SQ5.", + "bit_offset": 0, + "bit_size": 5, + "array": { + "len": 5, + "stride": 6 + } + } + ] + }, + "fieldset/SQR3": { + "description": "ADC regular sequence register 3.", + "fields": [ + { + "name": "SQ", + "description": "SQ10.", + "bit_offset": 0, + "bit_size": 5, + "array": { + "len": 5, + "stride": 6 + } + } + ] + }, + "fieldset/SQR4": { + "description": "ADC regular sequence register 4.", + "fields": [ + { + "name": "SQ", + "description": "SQ15.", + "bit_offset": 0, + "bit_size": 5, + "array": { + "len": 2, + "stride": 6 + } + } + ] + }, + "enum/ADC4_DMACFG": { + "bit_size": 1, + "variants": [ + { + "name": "OneShot", + "description": "DMA One Shot mode selected", + "value": 0 }, { - "name": "SMPSEL0", - "description": "SMPSEL0.", - "bit_offset": 8, - "bit_size": 1 + "name": "Circular", + "description": "DMA Circular mode selected", + "value": 1 + } + ] + }, + "enum/ADC4_EXTEN": { + "bit_size": 2, + "variants": [ + { + "name": "Disabled", + "description": "Trigger detection disabled", + "value": 0 }, { - "name": "SMPSEL1", - "description": "SMPSEL1.", - "bit_offset": 9, - "bit_size": 1 + "name": "RisingEdge", + "description": "Trigger detection on the rising edge", + "value": 1 }, { - "name": "SMPSEL2", - "description": "SMPSEL2.", - "bit_offset": 10, - "bit_size": 1 + "name": "FallingEdge", + "description": "Trigger detection on the falling edge", + "value": 2 }, { - "name": "SMPSEL3", - "description": "SMPSEL3.", - "bit_offset": 11, - "bit_size": 1 + "name": "BothEdges", + "description": "Trigger detection on both the rising and falling edges", + "value": 3 + } + ] + }, + "enum/ADC4_OVERSAMPLING_RATIO": { + "bit_size": 3, + "variants": [ + { + "name": "Oversample2x", + "description": "Oversample 2 times", + "value": 0 }, { - "name": "SMPSEL4", - "description": "SMPSEL4.", - "bit_offset": 12, - "bit_size": 1 + "name": "Oversample4x", + "description": "Oversample 4 times", + "value": 1 }, { - "name": "SMPSEL5", - "description": "SMPSEL5.", - "bit_offset": 13, - "bit_size": 1 + "name": "Oversample8x", + "description": "Oversample 8 times", + "value": 2 }, { - "name": "SMPSEL6", - "description": "SMPSEL6.", - "bit_offset": 14, - "bit_size": 1 + "name": "Oversample16x", + "description": "Oversample 16 times", + "value": 3 }, { - "name": "SMPSEL7", - "description": "SMPSEL7.", - "bit_offset": 15, - "bit_size": 1 + "name": "Oversample32x", + "description": "Oversample 32 times", + "value": 4 }, { - "name": "SMPSEL8", - "description": "SMPSEL8.", - "bit_offset": 16, - "bit_size": 1 + "name": "Oversample64x", + "description": "Oversample 64 times", + "value": 5 }, { - "name": "SMPSEL9", - "description": "SMPSEL9.", - "bit_offset": 17, - "bit_size": 1 + "name": "Oversample128x", + "description": "Oversample 128 times", + "value": 6 }, { - "name": "SMPSEL10", - "description": "SMPSEL10.", - "bit_offset": 18, - "bit_size": 1 + "name": "Oversample256x", + "description": "Oversample 256 times", + "value": 7 + } + ] + }, + "enum/ADC4_PRESC": { + "bit_size": 4, + "variants": [ + { + "name": "Div1", + "description": "adc_ker_ck_input not divided", + "value": 0 }, { - "name": "SMPSEL11", - "description": "SMPSEL11.", - "bit_offset": 19, - "bit_size": 1 + "name": "Div2", + "description": "adc_ker_ck_input divided by 2", + "value": 1 }, { - "name": "SMPSEL12", - "description": "SMPSEL12.", - "bit_offset": 20, - "bit_size": 1 + "name": "Div4", + "description": "adc_ker_ck_input divided by 4", + "value": 2 }, { - "name": "SMPSEL13", - "description": "SMPSEL13.", - "bit_offset": 21, - "bit_size": 1 + "name": "Div6", + "description": "adc_ker_ck_input divided by 6", + "value": 3 }, { - "name": "SMPSEL14", - "description": "SMPSEL14.", - "bit_offset": 22, - "bit_size": 1 + "name": "Div8", + "description": "adc_ker_ck_input divided by 8", + "value": 4 }, { - "name": "SMPSEL15", - "description": "SMPSEL15.", - "bit_offset": 23, - "bit_size": 1 + "name": "Div10", + "description": "adc_ker_ck_input divided by 10", + "value": 5 }, { - "name": "SMPSEL16", - "description": "SMPSEL16.", - "bit_offset": 24, - "bit_size": 1 + "name": "Div12", + "description": "adc_ker_ck_input divided by 12", + "value": 6 }, { - "name": "SMPSEL17", - "description": "SMPSEL17.", - "bit_offset": 25, - "bit_size": 1 + "name": "Div16", + "description": "adc_ker_ck_input divided by 16", + "value": 7 }, { - "name": "SMPSEL18", - "description": "SMPSEL18.", - "bit_offset": 26, - "bit_size": 1 + "name": "Div32", + "description": "adc_ker_ck_input divided by 32", + "value": 8 }, { - "name": "SMPSEL19", - "description": "SMPSEL19.", - "bit_offset": 27, - "bit_size": 1 + "name": "Div64", + "description": "adc_ker_ck_input divided by 64", + "value": 9 }, { - "name": "SMPSEL20", - "description": "SMPSEL20.", - "bit_offset": 28, - "bit_size": 1 + "name": "Div128", + "description": "adc_ker_ck_input divided by 128", + "value": 10 }, { - "name": "SMPSEL21", - "description": "SMPSEL21.", - "bit_offset": 29, - "bit_size": 1 + "name": "Div256", + "description": "adc_ker_ck_input divided by 256", + "value": 11 + } + ] + }, + "enum/ADC4_RES": { + "bit_size": 2, + "variants": [ + { + "name": "Bits12", + "description": "12-bit resolution", + "value": 0 }, { - "name": "SMPSEL22", - "description": "SMPSEL22.", - "bit_offset": 30, - "bit_size": 1 + "name": "Bits10", + "description": "10-bit resolution", + "value": 1 }, { - "name": "SMPSEL23", - "description": "SMPSEL23.", - "bit_offset": 31, - "bit_size": 1 + "name": "Bits8", + "description": "8-bit resolution", + "value": 2 + }, + { + "name": "Bits6", + "description": "6-bit resolution", + "value": 3 + } + ] + }, + "enum/ADC4_SAMPLE_TIME": { + "bit_size": 3, + "variants": [ + { + "name": "Cycles1_5", + "description": "1.5 ADC cycles", + "value": 0 + }, + { + "name": "Cycles3_5", + "description": "3.5 ADC cycles", + "value": 1 + }, + { + "name": "Cycles7_5", + "description": "7.5 ADC cycles", + "value": 2 + }, + { + "name": "Cycles12_5", + "description": "12.5 ADC cycles", + "value": 3 + }, + { + "name": "Cycles19_5", + "description": "19.5 ADC cycles", + "value": 4 + }, + { + "name": "Cycles39_5", + "description": "39.5 ADC cycles", + "value": 5 + }, + { + "name": "Cycles79_5", + "description": "79.5 ADC cycles", + "value": 6 + }, + { + "name": "Cycles814_5", + "description": "160.5 ADC cycles", + "value": 7 + } + ] + }, + "enum/ADSTP": { + "bit_size": 1, + "variants": [ + { + "name": "Stop", + "description": "Stop conversion of channel", + "value": 1 + } + ] + }, + "enum/DIFSEL": { + "bit_size": 1, + "variants": [ + { + "name": "SingleEnded", + "description": "Input channel is configured in single-ended mode", + "value": 0 + }, + { + "name": "Differential", + "description": "Input channel is configured in differential mode", + "value": 1 + } + ] + }, + "enum/DMNGT": { + "bit_size": 2, + "variants": [ + { + "name": "DR", + "description": "Store output data in DR only", + "value": 0 + }, + { + "name": "DMA_OneShot", + "description": "DMA One Shot Mode selected", + "value": 1 + }, + { + "name": "MDF", + "description": "MDF mode selected", + "value": 2 + }, + { + "name": "DMA_Circular", + "description": "DMA Circular Mode selected", + "value": 3 + } + ] + }, + "enum/EXTEN": { + "bit_size": 2, + "variants": [ + { + "name": "Disabled", + "description": "Trigger detection disabled", + "value": 0 + }, + { + "name": "RisingEdge", + "description": "Trigger detection on the rising edge", + "value": 1 + }, + { + "name": "FallingEdge", + "description": "Trigger detection on the falling edge", + "value": 2 + }, + { + "name": "BothEdges", + "description": "Trigger detection on both the rising and falling edges", + "value": 3 + } + ] + }, + "enum/PCSEL": { + "bit_size": 1, + "variants": [ + { + "name": "NotPreselected", + "description": "Input channel x is not pre-selected", + "value": 0 + }, + { + "name": "Preselected", + "description": "Pre-select input channel x", + "value": 1 + } + ] + }, + "enum/RES": { + "bit_size": 2, + "variants": [ + { + "name": "Bits14", + "description": "14-bit resolution", + "value": 0 + }, + { + "name": "Bits12", + "description": "12-bit resolution", + "value": 1 + }, + { + "name": "Bits10", + "description": "10-bit resolution", + "value": 2 + }, + { + "name": "Bits8", + "description": "8-bit resolution", + "value": 3 + } + ] + }, + "enum/SAMPLE_TIME": { + "bit_size": 3, + "variants": [ + { + "name": "Cycles1_5", + "description": "1.5 ADC cycles", + "value": 0 + }, + { + "name": "Cycles3_5", + "description": "3.5 ADC cycles", + "value": 1 + }, + { + "name": "Cycles7_5", + "description": "7.5 ADC cycles", + "value": 2 + }, + { + "name": "Cycles12_5", + "description": "12.5 ADC cycles", + "value": 3 + }, + { + "name": "Cycles19_5", + "description": "19.5 ADC cycles", + "value": 4 + }, + { + "name": "Cycles39_5", + "description": "39.5 ADC cycles", + "value": 5 + }, + { + "name": "Cycles79_5", + "description": "79.5 ADC cycles", + "value": 6 + }, + { + "name": "Cycles160_5", + "description": "160.5 ADC cycles", + "value": 7 } ] } diff --git a/data/registers/adccommon_u5.json b/data/registers/adccommon_u5.json new file mode 100644 index 0000000..4f7bfb9 --- /dev/null +++ b/data/registers/adccommon_u5.json @@ -0,0 +1,363 @@ +{ + "block/ADC_COMMON": { + "description": "Analog-to-Digital Converter.", + "items": [ + { + "name": "CSR", + "description": "ADC common status register.", + "byte_offset": 0, + "access": "Read", + "fieldset": "CSR" + }, + { + "name": "CCR", + "description": "ADC_CCR system control register.", + "byte_offset": 8, + "fieldset": "CCR" + }, + { + "name": "CDR", + "description": "ADC common regular data register for dual mode.", + "byte_offset": 12, + "access": "Read", + "fieldset": "CDR" + }, + { + "name": "CDR2", + "description": "ADC common regular data register for 32-bit dual mode.", + "byte_offset": 16, + "access": "Read", + "fieldset": "CDR2" + } + ] + }, + "fieldset/CCR": { + "description": "ADC_CCR system control register.", + "fields": [ + { + "name": "DUAL", + "description": "Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs are independent: The configurations 00001 to 01001 correspond to the following operating modes: Dual mode, master and slave ADCs working together: All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).", + "bit_offset": 0, + "bit_size": 5, + "enum": "DUAL" + }, + { + "name": "DELAY", + "description": "Delay between the end of the master ADC sampling phase and the beginning of the slave ADC sampling phase. These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).", + "bit_offset": 8, + "bit_size": 4 + }, + { + "name": "DAMDF", + "description": "Dual ADC Mode Data Format This bit-field is set and cleared by software. It specifies the data format in the common data register CDR. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).", + "bit_offset": 14, + "bit_size": 2, + "enum": "DAMDF" + }, + { + "name": "PRESC", + "description": "ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).", + "bit_offset": 18, + "bit_size": 4, + "enum": "PRESC" + }, + { + "name": "VREFEN", + "description": "VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "VSENSEEN", + "description": "Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).", + "bit_offset": 23, + "bit_size": 1 + }, + { + "name": "VBATEN", + "description": "VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).", + "bit_offset": 24, + "bit_size": 1 + } + ] + }, + "fieldset/CDR": { + "description": "ADC common regular data register for dual mode.", + "fields": [ + { + "name": "RDATA_MST", + "description": "Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) In DAMDF[1:0] = 11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0].", + "bit_offset": 0, + "bit_size": 16 + }, + { + "name": "RDATA_SLV", + "description": "Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)).", + "bit_offset": 16, + "bit_size": 16 + } + ] + }, + "fieldset/CDR2": { + "description": "ADC common regular data register for 32-bit dual mode.", + "fields": [ + { + "name": "RDATA_ALT", + "description": "Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT).", + "bit_offset": 0, + "bit_size": 32 + } + ] + }, + "fieldset/CSR": { + "description": "ADC common status register.", + "fields": [ + { + "name": "ADRDY_MST", + "description": "Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.", + "bit_offset": 0, + "bit_size": 1 + }, + { + "name": "EOSMP_MST", + "description": "End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.", + "bit_offset": 1, + "bit_size": 1 + }, + { + "name": "EOC_MST", + "description": "End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register.", + "bit_offset": 2, + "bit_size": 1 + }, + { + "name": "EOS_MST", + "description": "End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register.", + "bit_offset": 3, + "bit_size": 1 + }, + { + "name": "OVR_MST", + "description": "Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register.", + "bit_offset": 4, + "bit_size": 1 + }, + { + "name": "JEOC_MST", + "description": "End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.", + "bit_offset": 5, + "bit_size": 1 + }, + { + "name": "JEOS_MST", + "description": "End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.", + "bit_offset": 6, + "bit_size": 1 + }, + { + "name": "AWD_MST", + "description": "Analog watchdog flags of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.", + "bit_offset": 7, + "bit_size": 1, + "array": { + "len": 3, + "stride": 1 + } + }, + { + "name": "LDORDY_MST", + "description": "ADC voltage regulator ready flag of the master ADC This bit is a copy of the LDORDY bit of the corresponding ADC_ISR register.", + "bit_offset": 12, + "bit_size": 1 + }, + { + "name": "ADRDY_SLV", + "description": "Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register.", + "bit_offset": 16, + "bit_size": 1 + }, + { + "name": "EOSMP_SLV", + "description": "End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register.", + "bit_offset": 17, + "bit_size": 1 + }, + { + "name": "EOC_SLV", + "description": "End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register.", + "bit_offset": 18, + "bit_size": 1 + }, + { + "name": "EOS_SLV", + "description": "End of regular sequence flag of the slave ADC This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register.", + "bit_offset": 19, + "bit_size": 1 + }, + { + "name": "OVR_SLV", + "description": "Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register.", + "bit_offset": 20, + "bit_size": 1 + }, + { + "name": "JEOC_SLV", + "description": "End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register.", + "bit_offset": 21, + "bit_size": 1 + }, + { + "name": "JEOS_SLV", + "description": "End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register.", + "bit_offset": 22, + "bit_size": 1 + }, + { + "name": "AWD1_SLV", + "description": "Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register.", + "bit_offset": 23, + "bit_size": 1, + "array": { + "len": 3, + "stride": 1 + } + }, + { + "name": "LDORDY_SLV", + "description": "ADC voltage regulator ready flag of the slave ADC This bit is a copy of the LDORDY bit of the corresponding ADCx+1_ISR register.", + "bit_offset": 28, + "bit_size": 1 + } + ] + }, + "enum/DAMDF": { + "bit_size": 2, + "variants": [ + { + "name": "NoPack", + "description": "Without data packing, CDR/CDR2 not used", + "value": 0 + }, + { + "name": "Format32to10", + "description": "CDR formatted for 32-bit down to 10-bit resolution", + "value": 2 + }, + { + "name": "Format8", + "description": "CDR formatted for 8-bit resolution", + "value": 3 + } + ] + }, + "enum/DUAL": { + "bit_size": 5, + "variants": [ + { + "name": "Independent", + "description": "Independent mode", + "value": 0 + }, + { + "name": "DualRJ", + "description": "Dual, combined regular simultaneous + injected simultaneous mode", + "value": 1 + }, + { + "name": "DualRA", + "description": "Dual, combined regular simultaneous + alternate trigger mode", + "value": 2 + }, + { + "name": "DualIJ", + "description": "Dual, combined interleaved mode + injected simultaneous mode", + "value": 3 + }, + { + "name": "DualJ", + "description": "Dual, injected simultaneous mode only", + "value": 5 + }, + { + "name": "DualR", + "description": "Dual, regular simultaneous mode only", + "value": 6 + }, + { + "name": "DualI", + "description": "Dual, interleaved mode only", + "value": 7 + }, + { + "name": "DualA", + "description": "Dual, alternate trigger mode only", + "value": 9 + } + ] + }, + "enum/PRESC": { + "bit_size": 4, + "variants": [ + { + "name": "Div1", + "description": "adc_ker_ck_input not divided", + "value": 0 + }, + { + "name": "Div2", + "description": "adc_ker_ck_input divided by 2", + "value": 1 + }, + { + "name": "Div4", + "description": "adc_ker_ck_input divided by 4", + "value": 2 + }, + { + "name": "Div6", + "description": "adc_ker_ck_input divided by 6", + "value": 3 + }, + { + "name": "Div8", + "description": "adc_ker_ck_input divided by 8", + "value": 4 + }, + { + "name": "Div10", + "description": "adc_ker_ck_input divided by 10", + "value": 5 + }, + { + "name": "Div12", + "description": "adc_ker_ck_input divided by 12", + "value": 6 + }, + { + "name": "Div16", + "description": "adc_ker_ck_input divided by 16", + "value": 7 + }, + { + "name": "Div32", + "description": "adc_ker_ck_input divided by 32", + "value": 8 + }, + { + "name": "Div64", + "description": "adc_ker_ck_input divided by 64", + "value": 9 + }, + { + "name": "Div128", + "description": "adc_ker_ck_input divided by 128", + "value": 10 + }, + { + "name": "Div256", + "description": "adc_ker_ck_input divided by 256", + "value": 11 + } + ] + } +} \ No newline at end of file