diff --git a/data/registers/timer_l0.json b/data/registers/timer_l0.json
index 9536366..92b61bd 100644
--- a/data/registers/timer_l0.json
+++ b/data/registers/timer_l0.json
@@ -87,7 +87,7 @@
         "name": "SMCR",
         "description": "slave mode control register",
         "byte_offset": 8,
-        "fieldset": "SMCR_2CH"
+        "fieldset": "SMCR_GP16"
       },
       {
         "name": "DIER",
@@ -792,13 +792,6 @@
         "description": "DMA burst length",
         "bit_offset": 8,
         "bit_size": 5
-      },
-      {
-        "name": "DBSS",
-        "description": "DMA burst source selection",
-        "bit_offset": 16,
-        "bit_size": 4,
-        "enum": "DBSS"
       }
     ]
   },
@@ -983,7 +976,7 @@
       }
     ]
   },
-  "fieldset/SMCR_2CH": {
+  "fieldset/SMCR_GP16": {
     "description": "slave mode control register",
     "fields": [
       {
@@ -1036,39 +1029,6 @@
       }
     ]
   },
-  "fieldset/SMCR_GP16": {
-    "extends": "SMCR_2CH",
-    "description": "slave mode control register",
-    "fields": [
-      {
-        "name": "ETF",
-        "description": "External trigger filter",
-        "bit_offset": 8,
-        "bit_size": 4,
-        "enum": "FilterValue"
-      },
-      {
-        "name": "ETPS",
-        "description": "External trigger prescaler",
-        "bit_offset": 12,
-        "bit_size": 2,
-        "enum": "ETPS"
-      },
-      {
-        "name": "ECE",
-        "description": "External clock mode 2 enable",
-        "bit_offset": 14,
-        "bit_size": 1
-      },
-      {
-        "name": "ETP",
-        "description": "External trigger polarity",
-        "bit_offset": 15,
-        "bit_size": 1,
-        "enum": "ETP"
-      }
-    ]
-  },
   "fieldset/SR_1CH": {
     "extends": "SR_CORE",
     "description": "status register",
@@ -1260,46 +1220,6 @@
       }
     ]
   },
-  "enum/DBSS": {
-    "bit_size": 4,
-    "variants": [
-      {
-        "name": "Update",
-        "description": "Update",
-        "value": 1
-      },
-      {
-        "name": "CC1",
-        "description": "CC1",
-        "value": 2
-      },
-      {
-        "name": "CC2",
-        "description": "CC2",
-        "value": 3
-      },
-      {
-        "name": "CC3",
-        "description": "CC3",
-        "value": 4
-      },
-      {
-        "name": "CC4",
-        "description": "CC4",
-        "value": 5
-      },
-      {
-        "name": "COM",
-        "description": "COM",
-        "value": 6
-      },
-      {
-        "name": "Trigger",
-        "description": "Trigger",
-        "value": 7
-      }
-    ]
-  },
   "enum/DIR": {
     "bit_size": 1,
     "variants": [
@@ -1550,7 +1470,7 @@
     "variants": [
       {
         "name": "Disabled",
-        "description": "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.",
+        "description": "Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock.",
         "value": 0
       },
       {
diff --git a/data/registers/timer_v1.json b/data/registers/timer_v1.json
index 07936a7..7c2ea9f 100644
--- a/data/registers/timer_v1.json
+++ b/data/registers/timer_v1.json
@@ -602,6 +602,12 @@
         "byte_offset": 52,
         "fieldset": "CCR_1CH"
       },
+      {
+        "name": "DCR",
+        "description": "DMA control register",
+        "byte_offset": 72,
+        "fieldset": "DCR_1CH_CMP"
+      },
       {
         "name": "DMAR",
         "description": "DMA address for full transfer",
@@ -644,12 +650,6 @@
           "stride": 4
         },
         "byte_offset": 52
-      },
-      {
-        "name": "DCR",
-        "description": "DMA control register",
-        "byte_offset": 72,
-        "fieldset": "DCR_1CH_CMP"
       }
     ]
   },
@@ -1685,6 +1685,12 @@
     "extends": "DIER_1CH_CMP",
     "description": "DMA/Interrupt enable register",
     "fields": [
+      {
+        "name": "TIE",
+        "description": "Trigger interrupt enable",
+        "bit_offset": 6,
+        "bit_size": 1
+      },
       {
         "name": "COMDE",
         "description": "COM DMA request enable",
diff --git a/data/registers/timer_v2.json b/data/registers/timer_v2.json
index effc322..918d05e 100644
--- a/data/registers/timer_v2.json
+++ b/data/registers/timer_v2.json
@@ -2001,6 +2001,12 @@
     "extends": "DIER_1CH_CMP",
     "description": "DMA/Interrupt enable register",
     "fields": [
+      {
+        "name": "TIE",
+        "description": "Trigger interrupt enable",
+        "bit_offset": 6,
+        "bit_size": 1
+      },
       {
         "name": "COMDE",
         "description": "COM DMA request enable",